mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
Move Uboot specific properties to *u-boot.dtsi files. Preparation to sync Arria 10 device tree from Linux. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
parent
8876f89640
commit
f3fccb12c0
6 changed files with 186 additions and 92 deletions
123
arch/arm/dts/socfpga_arria10-u-boot.dtsi
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123
arch/arm/dts/socfpga_arria10-u-boot.dtsi
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@ -0,0 +1,123 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014, 2020, Intel Corporation
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*/
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/ {
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chosen {
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tick-timer = &timer2;
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u-boot,dm-pre-reloc;
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};
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memory@0 {
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u-boot,dm-pre-reloc;
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&clkmgr {
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u-boot,dm-pre-reloc;
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clocks {
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u-boot,dm-pre-reloc;
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};
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};
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&cb_intosc_hs_div2_clk {
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u-boot,dm-pre-reloc;
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};
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&cb_intosc_ls_clk {
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u-boot,dm-pre-reloc;
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};
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&f2s_free_clk {
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u-boot,dm-pre-reloc;
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};
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&i2c0 {
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reset-names = "i2c";
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};
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&i2c1 {
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reset-names = "i2c";
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};
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&i2c2 {
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reset-names = "i2c";
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};
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&i2c3 {
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reset-names = "i2c";
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};
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&i2c4 {
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reset-names = "i2c";
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};
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&l4_mp_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_sp_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_sys_free_clk {
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u-boot,dm-pre-reloc;
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};
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&main_periph_ref_clk {
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u-boot,dm-pre-reloc;
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};
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&main_pll {
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u-boot,dm-pre-reloc;
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};
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&main_noc_base_clk {
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u-boot,dm-pre-reloc;
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};
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&noc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&osc1 {
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u-boot,dm-pre-reloc;
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};
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&peri_noc_base_clk {
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u-boot,dm-pre-reloc;
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};
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&periph_pll {
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u-boot,dm-pre-reloc;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&portc {
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bank-name = "portc";
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};
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&rst {
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u-boot,dm-pre-reloc;
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};
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&sysmgr {
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u-boot,dm-pre-reloc;
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};
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&timer2 {
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u-boot,dm-pre-reloc;
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};
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@ -21,11 +21,6 @@
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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tick-timer = &timer2;
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u-boot,dm-pre-reloc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -60,7 +55,6 @@
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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u-boot,dm-pre-reloc;
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amba {
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compatible = "simple-bus";
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@ -99,35 +93,29 @@
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clkmgr: clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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u-boot,dm-pre-reloc;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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cb_intosc_ls_clk: cb_intosc_ls_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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f2s_free_clk: f2s_free_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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main_pll: main_pll@40 {
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@ -138,7 +126,6 @@
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>;
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reg = <0x40>;
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u-boot,dm-pre-reloc;
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main_mpu_base_clk: main_mpu_base_clk {
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#clock-cells = <0>;
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@ -152,7 +139,6 @@
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x144 0 11>;
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u-boot,dm-pre-reloc;
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};
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main_emaca_clk: main_emaca_clk@68 {
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@ -228,7 +214,6 @@
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>, <&main_periph_ref_clk>;
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reg = <0xC0>;
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u-boot,dm-pre-reloc;
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peri_mpu_base_clk: peri_mpu_base_clk {
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#clock-cells = <0>;
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@ -242,7 +227,6 @@
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x144 16 11>;
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u-boot,dm-pre-reloc;
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};
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peri_emaca_clk: peri_emaca_clk@e8 {
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@ -318,7 +302,6 @@
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x64>;
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u-boot,dm-pre-reloc;
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};
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s2f_user1_free_clk: s2f_user1_free_clk@104 {
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@ -345,7 +328,6 @@
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&noc_free_clk>;
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fixed-divider = <4>;
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u-boot,dm-pre-reloc;
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};
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l4_main_clk: l4_main_clk {
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@ -500,7 +482,6 @@
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "porta";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <29>;
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@ -520,7 +501,6 @@
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portb";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <29>;
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@ -540,7 +520,6 @@
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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bank-name = "portc";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <27>;
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@ -568,7 +547,6 @@
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C0_RESET>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -580,7 +558,6 @@
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C1_RESET>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -592,7 +569,6 @@
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C2_RESET>;
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reset-names = "i2c";
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status = "disabled";
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};
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C3_RESET>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -616,7 +591,6 @@
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interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sp_clk>;
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resets = <&rst I2C4_RESET>;
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reset-names = "i2c";
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status = "disabled";
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};
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@ -767,7 +741,6 @@
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compatible = "altr,rst-mgr";
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reg = <0xffd05000 0x100>;
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altr,modrst-offset = <0x20>;
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u-boot,dm-pre-reloc;
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};
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scu: snoop-control-unit@ffffc000 {
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@ -811,7 +784,6 @@
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reg = <0xffd00000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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u-boot,dm-pre-reloc;
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};
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timer3: timer3@ffd00100 {
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17
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
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17
arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2015, 2020 Intel. All rights reserved.
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*/
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#include "socfpga_arria10-u-boot.dtsi"
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/ {
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aliases {
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bootargs = "console=ttyS0,115200";
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i2c0 = &i2c1;
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};
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};
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&uart1 {
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u-boot,dm-pre-reloc;
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};
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@ -24,7 +24,6 @@
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aliases {
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ethernet0 = &gmac0;
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serial0 = &uart1;
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i2c0 = &i2c1;
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};
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chosen {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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u-boot,dm-pre-reloc;
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};
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a10leds {
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@ -63,9 +61,6 @@
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};
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&gmac0 {
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@ -155,7 +150,6 @@
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};
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&uart1 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&watchdog1 {
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status = "okay";
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};
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/* Clock available early */
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&main_periph_ref_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_mp_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_sp_clk {
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u-boot,dm-pre-reloc;
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};
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&clkmgr {
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u-boot,dm-pre-reloc;
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};
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&sysmgr {
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u-boot,dm-pre-reloc;
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};
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46
arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
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46
arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
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@ -0,0 +1,46 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
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*/
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#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
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#include "socfpga_arria10_handoff_u-boot.dtsi"
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#include "socfpga_arria10_socdk-u-boot.dtsi"
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/ {
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chosen {
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firmware-loader = <&fs_loader0>;
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};
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fs_loader0: fs-loader {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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phandlepart = <&mmc 1>;
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};
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};
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&fpga_mgr {
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u-boot,dm-pre-reloc;
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altr,bitstream = "fit_spl_fpga.itb";
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};
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&mmc {
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u-boot,dm-pre-reloc;
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};
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/* Clock available early */
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&main_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&peri_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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@ -17,28 +17,8 @@
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/dts-v1/;
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#include "socfpga_arria10_socdk.dtsi"
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#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
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#include "socfpga_arria10_handoff_u-boot.dtsi"
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/ {
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chosen {
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firmware-loader = <&fs_loader0>;
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};
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fs_loader0: fs-loader {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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phandlepart = <&mmc 1>;
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};
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};
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&fpga_mgr {
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u-boot,dm-pre-reloc;
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altr,bitstream = "fit_spl_fpga.itb";
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};
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&mmc {
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u-boot,dm-pre-reloc;
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status = "okay";
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num-slots = <1>;
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cap-sd-highspeed;
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@ -57,20 +37,3 @@
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<48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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/* Clock available early */
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&main_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&peri_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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