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Add port initialization for digital I/O on INKA4x0
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commit
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5 changed files with 59 additions and 17 deletions
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@ -2,6 +2,8 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Add port initialization for digital I/O on INKA4x0
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* Patch by Stefan Roese, 01 March 2005:
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Update for esd boards dp405 and hub405
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@ -43,13 +43,11 @@ static void sdram_start (int hi_addr)
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
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hi_addr_bit;
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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@ -63,13 +61,11 @@ static void sdram_start (int hi_addr)
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
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hi_addr_bit;
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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@ -177,27 +173,51 @@ void flash_preinit(void)
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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#define GPIO_PSC3_9 0x04000000UL
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#define GPIO_PSC3_9 0x04000000UL
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int misc_init_f (void)
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{
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/* Initialize GPIO output pins.
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*/
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/* Configure GPT as GPIO output */
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*(vu_long *)MPC5XXX_GPT0_ENABLE =
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*(vu_long *)MPC5XXX_GPT1_ENABLE =
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*(vu_long *)MPC5XXX_GPT2_ENABLE =
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*(vu_long *)MPC5XXX_GPT3_ENABLE =
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*(vu_long *)MPC5XXX_GPT4_ENABLE =
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*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24;
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/* Configure PSC3_6,7 as GPIO output */
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*(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
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*(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
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/* Configure PSC3_8 as GPIO output, no interrupt */
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*(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
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*(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
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*(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
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/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
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*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
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*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
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/*
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* Reset Coral-P graphics controller
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*/
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
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return 0;
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
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return 0;
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}
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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pci_mpc5xxx_init(&hose);
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}
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#endif
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@ -209,7 +229,7 @@ void init_ide_reset (void)
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{
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debug ("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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/* Deassert reset */
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@ -871,7 +871,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
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dbuf+=1;
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}
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}
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#else
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#else
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volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
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ushort *dbuf = (ushort *)sect_buf;
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@ -274,6 +274,11 @@
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#define CFG_CS2_SIZE 0x0001000
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#define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
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/* GPIO in @0x30400000 */
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#define CFG_CS3_START 0x30400000
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#define CFG_CS3_SIZE 0x00100000
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#define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
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#define CFG_CS_BURST 0x00000000
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#define CFG_CS_DEADCYCLE 0x33333333
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@ -233,6 +233,21 @@
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/* General Purpose Timers registers */
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#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
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#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
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#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
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#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
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#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
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#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
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#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
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#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
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#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
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#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
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#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
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#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
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#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
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#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
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#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
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#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
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/* ATA registers */
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#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
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