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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Tom Rini 2014-05-22 14:29:41 -04:00
commit f6ed9d5094
156 changed files with 7641 additions and 6247 deletions
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2
Makefile
View file

@ -893,7 +893,7 @@ MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \
spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE)
OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
$(call if_changed,pad_cat)

254
arch/arm/cpu/arm1136/start.S
View file

@ -15,48 +15,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _start
_start: b reset
#ifdef CONFIG_SPL_BUILD
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_hang:
.word do_hang
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678 /* now 16*4=64 */
#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -70,26 +29,7 @@ _end_vect:
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -152,195 +92,3 @@ cpu_init_crit:
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_bad_stack_swi
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
ldr r0, IRQ_STACK_START_IN @ get data regions start
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
bl hang /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
.align 5
.global arm1136_cache_flush
arm1136_cache_flush:
#if !defined(CONFIG_SYS_ICACHE_OFF)
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF)
mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
#endif
mov pc, lr @ back to caller
#endif /* CONFIG_SPL_BUILD */

198
arch/arm/cpu/arm1176/start.S
View file

@ -22,48 +22,6 @@
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b reset
#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
_irq:
.word irq
_fiq:
.word fiq
_pad:
.word 0x12345678 /* now 16*4=64 */
#else
. = _start + 64
#endif
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -77,14 +35,7 @@ _end_vect:
*************************************************************************
*/
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -182,150 +133,3 @@ skip_tcmdisable:
c_runtime_cpu_setup:
mov pc, lr
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
*/
.macro bad_save_user_regs
/* carve out a frame on current user stack */
sub sp, sp, #S_FRAME_SIZE
/* Save user registers (now in svc mode) r0-r12 */
stmia sp, {r0 - r12}
ldr r2, IRQ_STACK_START_IN
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
add r0, sp, #S_FRAME_SIZE
add r5, sp, #S_SP
mov r1, lr
/* save sp_SVC, lr_SVC, pc, cpsr */
stmia r5, {r0 - r3}
/* save current stack into r0 (param register) */
mov r0, sp
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
/* save caller lr in position 0 of saved stack */
str lr, [r13]
/* get the spsr */
mrs lr, spsr
/* save spsr in position 1 of saved stack */
str lr, [r13, #4]
/* prepare SVC-Mode */
mov r13, #MODE_SVC
@ msr spsr_c, r13
/* switch modes, make sure moves will execute */
msr spsr, r13
/* capture return pc */
mov lr, pc
/* jump to next instruction & switch modes. */
movs pc, lr
.endm
.macro get_bad_stack_swi
/* space on current stack for scratch reg. */
sub r13, r13, #4
/* save R0's value. */
str r0, [r13]
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */
mrs lr, spsr
/* save spsr in position 1 of saved stack */
str lr, [r0, #4]
/* restore lr */
ldr lr, [r0]
/* restore r0 */
ldr r0, [r13]
/* pop stack entry */
add r13, r13, #4
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_SPL_BUILD */

229
arch/arm/cpu/arm720t/start.S
View file

@ -12,48 +12,6 @@
#include <version.h>
#include <asm/hardware.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt: .word _software_interrupt
_prefetch_abort: .word _prefetch_abort
_data_abort: .word _data_abort
_not_used: .word _not_used
_irq: .word _irq
_fiq: .word _fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -67,26 +25,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -139,169 +78,3 @@ cpu_init_crit:
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
ldr r2, IRQ_STACK_START_IN
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
mov r0, sp
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
msr spsr_c, r13
mov lr, pc
movs pc, lr
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
#endif /* CONFIG_SPL_BUILD */

10
arch/arm/cpu/arm720t/tegra-common/cpu.c
View file

@ -82,7 +82,7 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
},
/*
* T30: 1.4 GHz
* T30: 600 MHz
*
* Register Field Bits Width
* ------------------------------
@ -92,10 +92,10 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
* PLLX_MISC cpcon 11: 8 4
*/
{
{ .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
{ .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
{ .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
},
/*
* T114: 700 MHz

23
arch/arm/cpu/arm720t/tegra30/cpu.c
View file

@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config)
writel(config, &reg->cnfg);
}
#define TPS62366A_I2C_ADDR 0xC0
#define TPS62366A_SET1_REG 0x01
#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
#define TPS62361B_I2C_ADDR 0xC0
#define TPS62361B_SET3_REG 0x03
#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
#define TPS65911_I2C_ADDR 0x5A
#define TPS65911_VDDCTRL_OP_REG 0x28
#define TPS65911_VDDCTRL_SR_REG 0x27
#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
#define I2C_SEND_2_BYTES 0x0A02
@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void)
reg |= CPUPWRREQ_OE;
writel(reg, &pmc->pmc_cntrl);
/* Set VDD_CORE to 1.200V. */
#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
#endif
#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
#endif
udelay(1000);
/*
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
* First set VDD to 1.4V, then enable the VDD regulator.
* First set VDD to 1.0125V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);

1
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
View file

@ -16,6 +16,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
*(.vectors)
arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;

216
arch/arm/cpu/arm920t/start.S
View file

@ -12,36 +12,6 @@
#include <common.h>
#include <config.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -55,28 +25,9 @@ _fiq: .word fiq
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
.globl reset
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual start code
*/
start_code:
reset:
/*
* set the cpu to SVC32 mode
*/
@ -196,166 +147,3 @@ cpu_init_crit:
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, IRQ_STACK_START_IN
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r7, sp, #S_PC
stmdb r7, {sp, lr}^ @ Calling SP, LR
str lr, [r7, #0] @ Save calling PC
mrs r6, spsr
str r6, [r7, #4] @ Save CPSR
str r0, [r7, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
/* return & move spsr_svc into cpsr */
subs pc, lr, #4
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13
mov lr, pc
movs pc, lr
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif

92
arch/arm/cpu/arm926ejs/mxs/start.S
View file

@ -24,70 +24,6 @@
#include <common.h>
#include <version.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start:
b reset
b undefined_instruction
b software_interrupt
b prefetch_abort
b data_abort
b not_used
b irq
b fiq
/*
* Vector table, located at address 0x20.
* This table allows the code running AFTER SPL, the U-Boot, to install it's
* interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
* including it's interrupt vectoring table and the table at 0x0 is still the
* SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
* is still used.
*/
_vt_reset:
.word _reset
_vt_undefined_instruction:
.word _hang
_vt_software_interrupt:
.word _hang
_vt_prefetch_abort:
.word _hang
_vt_data_abort:
.word _hang
_vt_not_used:
.word _reset
_vt_irq:
.word _hang
_vt_fiq:
.word _hang
reset:
ldr pc, _vt_reset
undefined_instruction:
ldr pc, _vt_undefined_instruction
software_interrupt:
ldr pc, _vt_software_interrupt
prefetch_abort:
ldr pc, _vt_prefetch_abort
data_abort:
ldr pc, _vt_data_abort
not_used:
ldr pc, _vt_not_used
irq:
ldr pc, _vt_irq
fiq:
ldr pc, _vt_fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -101,28 +37,8 @@ fiq:
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
_reset:
.globl reset
reset:
/*
* If the CPU is configured in "Wait JTAG connection mode", the stack
* pointer is not configured and is zero. This will cause crash when
@ -179,7 +95,3 @@ _reset:
mov r0, #0
bx lr
_hang:
1:
bl 1b /* hang and never return */

27
arch/arm/cpu/arm926ejs/spear/start.S
View file

@ -17,29 +17,6 @@
#include <config.h>
.globl _start
_start:
b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
_software_interrupt:
_prefetch_abort:
_data_abort:
_not_used:
_irq:
_fiq:
.word infinite_loop
infinite_loop:
b infinite_loop
/*
*************************************************************************
*
@ -53,9 +30,7 @@ infinite_loop:
*************************************************************************
*/
/*
* the actual reset code
*/
.globl reset
reset:
/*

1
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
View file

@ -21,6 +21,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
*(.vectors)
arch/arm/cpu/arm926ejs/spear/start.o (.text*)
*(.text*)
}

262
arch/arm/cpu/arm926ejs/start.S
View file

@ -20,75 +20,6 @@
#include <common.h>
#include <version.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.globl _start
_start:
.globl _NOR_BOOT_CFG
_NOR_BOOT_CFG:
.word CONFIG_SYS_DV_NOR_BOOT_CFG
b reset
#else
.globl _start
_start:
b reset
#endif
#ifdef CONFIG_SPL_BUILD
/* No exception handlers in preloader */
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_hang:
.word do_hang
/* pad to 64 byte boundary */
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
_irq:
.word irq
_fiq:
.word fiq
#endif /* CONFIG_SPL_BUILD */
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -102,26 +33,7 @@ _fiq:
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -198,175 +110,3 @@ flush_dcache:
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
1:
bl 1b /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
#endif /* CONFIG_SPL_BUILD */

13
arch/arm/cpu/arm946es/cpu.c
View file

@ -16,6 +16,7 @@
#include <common.h>
#include <command.h>
#include <asm/system.h>
#include <asm/io.h>
static void cache_flush(void);
@ -51,3 +52,15 @@ static void cache_flush (void)
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
}
#ifndef CONFIG_INTEGRATOR
__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
{
writew(0x0, 0xfffece10);
writew(0x8, 0xfffece10);
for (;;)
;
}
#endif /* #ifdef CONFIG_INTEGRATOR */

246
arch/arm/cpu/arm946es/start.S
View file

@ -19,45 +19,6 @@
#include <config.h>
#include <version.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start:
b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
_irq:
.word irq
_fiq:
.word fiq
.balignl 16,0xdeadbeef
_vectors_end:
/*
*************************************************************************
*
@ -71,26 +32,7 @@ _vectors_end:
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -157,189 +99,3 @@ cpu_init_crit:
mov lr, ip /* restore link */
mov pc, lr /* back to my caller */
#endif
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
# ifdef CONFIG_INTEGRATOR
/* Satisfied by general board level routine */
#else
.align 5
.globl reset_cpu
reset_cpu:
ldr r1, rstctl1 /* get clkm1 reset ctl */
mov r3, #0x0
strh r3, [r1] /* clear it */
mov r3, #0x8
strh r3, [r1] /* force dsp+arm reset */
_loop_forever:
b _loop_forever
rstctl1:
.word 0xfffece10
#endif /* #ifdef CONFIG_INTEGRATOR */

228
arch/arm/cpu/arm_intcm/start.S
View file

@ -18,42 +18,6 @@
#include <config.h>
#include <version.h>
/*
*************************************************************************
*
* Jump vector table
*
*************************************************************************
*/
.globl _start
_start:
b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
_irq:
.word irq
_fiq:
.word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -67,26 +31,7 @@ _fiq:
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -132,174 +77,3 @@ cpu_init_crit:
*/
mov pc, lr /* back to my caller */
#endif
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
.globl undefined_instruction
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
.globl software_interrupt
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
.globl prefetch_abort
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
.globl data_abort
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
.globl not_used
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
.globl irq
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
.globl fiq
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
.globl irq
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
.globl fiq
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif

557
arch/arm/cpu/armv7/exynos/pinmux.c
View file

@ -13,30 +13,23 @@
static void exynos5_uart_config(int peripheral)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
start = EXYNOS5_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->d0;
start = 0;
start = EXYNOS5_GPIO_D00;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
start = EXYNOS5_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
start = EXYNOS5_GPIO_A14;
count = 2;
break;
default:
@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral)
return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static void exynos5420_uart_config(int peripheral)
{
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
start = EXYNOS5420_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
start = EXYNOS5420_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
start = EXYNOS5420_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
start = EXYNOS5420_GPIO_A14;
count = 2;
break;
default:
@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral)
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
int i, start = 0, gpio_func = 0;
int i, start, start_ext, gpio_func = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
start = 0;
gpio_func = GPIO_FUNC(0x2);
start = EXYNOS5_GPIO_C00;
start_ext = EXYNOS5_GPIO_C10;
gpio_func = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
bank = &gpio1->c2;
bank_ext = NULL;
start = EXYNOS5_GPIO_C20;
start_ext = 0;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio1->c3;
bank_ext = &gpio1->c4;
start = 3;
gpio_func = GPIO_FUNC(0x3);
start = EXYNOS5_GPIO_C30;
start_ext = EXYNOS5_GPIO_C43;
gpio_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
bank = &gpio1->c4;
bank_ext = NULL;
start = EXYNOS5_GPIO_C40;
start_ext = 0;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
for (i = start_ext; i <= (start_ext + 3); i++) {
gpio_cfg_pin(i, gpio_func);
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
for (i = start; i < (start + 2); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
for (i = (start + 3); i <= (start + 6); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags)
static int exynos5420_mmc_config(int peripheral, int flags)
{
struct exynos5420_gpio_part3 *gpio3 =
(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
int i, start;
int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio3->c0;
bank_ext = &gpio3->c3;
start = 0;
start = EXYNOS5420_GPIO_C00;
start_ext = EXYNOS5420_GPIO_C30;
break;
case PERIPH_ID_SDMMC1:
bank = &gpio3->c1;
bank_ext = &gpio3->d1;
start = 4;
start = EXYNOS5420_GPIO_C10;
start_ext = EXYNOS5420_GPIO_D14;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio3->c2;
bank_ext = NULL;
start = 0;
start = EXYNOS5420_GPIO_C20;
start_ext = 0;
break;
default:
start = 0;
@ -175,41 +150,41 @@ static int exynos5420_mmc_config(int peripheral, int flags)
return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
for (i = start_ext; i <= (start_ext + 3); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
for (i = 0; i < 3; i++) {
for (i = start; i < (start + 3); i++) {
/*
* MMC0 is intended to be used for eMMC. The
* card detect pin is used as a VDDEN signal to
* power on the eMMC. The 5420 iROM makes
* this same assumption.
*/
if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
s5p_gpio_set_value(bank, i, 1);
s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
gpio_set_value(i, 1);
gpio_cfg_pin(i, S5P_GPIO_OUTPUT);
} else {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
for (i = (start + 3); i <= (start + 6); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_UP);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
return 0;
@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags)
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
int i;
/*
@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags)
* GPY1[2] SROM_WAIT(2)
* GPY1[3] EBI_DATA_RDn(2)
*/
s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2));
for (i = 0; i < 4; i++)
s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2));
/*
* EBI: 8 Addrss Lines
@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags)
* GPY6[7] EBI_DATA[15](2)
*/
for (i = 0; i < 8; i++) {
s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2));
gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2));
gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP);
s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2));
gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP);
}
}
static void exynos5_i2c_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
}
}
static void exynos5420_i2c_config(int peripheral)
{
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C8:
s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C9:
s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C10:
s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2));
break;
}
}
@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral)
static void exynos5_i2s_config(int peripheral)
{
int i;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos5_gpio_part4 *gpio4 =
(struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_I2S0:
for (i = 0; i < 5; i++)
s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02));
gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02));
break;
case PERIPH_ID_I2S1:
for (i = 0; i < 5; i++)
s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02));
break;
}
}
@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral)
void exynos5_spi_config(int peripheral)
{
int cfg = 0, pin = 0, i;
struct s5p_gpio_bank *bank = NULL;
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct exynos5_gpio_part2 *gpio2 =
(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
switch (peripheral) {
case PERIPH_ID_SPI0:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 0;
cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_A20;
break;
case PERIPH_ID_SPI1:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 4;
cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_A24;
break;
case PERIPH_ID_SPI2:
bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
pin = 1;
cfg = S5P_GPIO_FUNC(0x5);
pin = EXYNOS5_GPIO_B11;
break;
case PERIPH_ID_SPI3:
bank = &gpio2->f1;
cfg = GPIO_FUNC(0x2);
pin = 0;
cfg = S5P_GPIO_FUNC(0x2);
pin = EXYNOS5_GPIO_F10;
break;
case PERIPH_ID_SPI4:
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4));
}
break;
}
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
s5p_gpio_cfg_pin(bank, i, cfg);
gpio_cfg_pin(i, cfg);
}
}
void exynos5420_spi_config(int peripheral)
{
int cfg, pin, i;
struct s5p_gpio_bank *bank = NULL;
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos5420_gpio_part4 *gpio4 =
(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_SPI0:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 0;
pin = EXYNOS5420_GPIO_A20;
cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI1:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 4;
pin = EXYNOS5420_GPIO_A24;
cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI2:
bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
pin = 1;
pin = EXYNOS5420_GPIO_B11;
cfg = S5P_GPIO_FUNC(0x5);
break;
case PERIPH_ID_SPI3:
bank = &gpio4->f1;
cfg = GPIO_FUNC(0x2);
pin = 0;
pin = EXYNOS5420_GPIO_F10;
cfg = S5P_GPIO_FUNC(0x2);
break;
case PERIPH_ID_SPI4:
cfg = 0;
@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral)
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
s5p_gpio_cfg_pin(bank, i, cfg);
gpio_cfg_pin(i, cfg);
} else {
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i,
S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i,
S5P_GPIO_FUNC(0x4));
}
}
}
@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
static void exynos4_i2c_config(int peripheral, int flags)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3));
break;
}
}
static int exynos4_mmc_config(int peripheral, int flags)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
struct s5p_gpio_bank *bank, *bank_ext;
int i;
int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio2->k0;
bank_ext = &gpio2->k1;
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio2->k2;
bank_ext = &gpio2->k3;
start = EXYNOS4_GPIO_K20;
start_ext = EXYNOS4_GPIO_K33;
break;
default:
return -1;
}
for (i = 0; i < 7; i++) {
if (i == 2)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = 3; i < 7; i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
for (i = start_ext; i < (start_ext + 4); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
@ -666,41 +606,138 @@ static int exynos4_mmc_config(int peripheral, int flags)
static void exynos4_uart_config(int peripheral)
{
struct exynos4_gpio_part1 *gpio1 =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
start = EXYNOS4_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
start = EXYNOS4_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
start = EXYNOS4_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
start = EXYNOS4_GPIO_A14;
count = 2;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
for (i = start; i < (start + count); i++) {
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static void exynos4x12_i2c_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_I2C0:
gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4));
gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3));
break;
}
}
static int exynos4x12_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4X12_GPIO_K00;
start_ext = EXYNOS4X12_GPIO_K13;
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4X12_GPIO_K20;
start_ext = EXYNOS4X12_GPIO_K33;
break;
default:
return -1;
}
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
}
return 0;
}
static void exynos4x12_uart_config(int peripheral)
{
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
start = EXYNOS4X12_GPIO_A00;
count = 4;
break;
case PERIPH_ID_UART1:
start = EXYNOS4X12_GPIO_A04;
count = 4;
break;
case PERIPH_ID_UART2:
start = EXYNOS4X12_GPIO_A10;
count = 4;
break;
case PERIPH_ID_UART3:
start = EXYNOS4X12_GPIO_A14;
count = 2;
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return;
}
for (i = start; i < (start + count); i++) {
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
}
}
static int exynos4_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags)
return 0;
}
static int exynos4x12_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
exynos4x12_uart_config(peripheral);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
exynos4x12_i2c_config(peripheral, flags);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
return exynos4x12_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
return 0;
}
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
@ -744,11 +816,14 @@ int exynos_pinmux_config(int peripheral, int flags)
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
} else if (cpu_is_exynos4()) {
if (proid_is_exynos4412())
return exynos4x12_pinmux_config(peripheral, flags);
else
return exynos4_pinmux_config(peripheral, flags);
} else {
debug("pinmux functionality not supported\n");
}
debug("pinmux functionality not supported\n");
return -1;
}
@ -787,7 +862,7 @@ int pinmux_decode_periph_id(const void *blob, int node)
return exynos5_pinmux_decode_periph_id(blob, node);
else if (cpu_is_exynos4())
return exynos4_pinmux_decode_periph_id(blob, node);
else
return PERIPH_ID_NONE;
}
#endif

4
arch/arm/cpu/armv7/rmobile/Makefile
View file

@ -11,7 +11,7 @@ obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o

29
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
View file

@ -1,29 +0,0 @@
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
u32 rmobile_get_cpu_type(void)
{
u32 product;
product = readl(PRR);
return (u32)((product & 0x00007F00) >> 8);
}
u32 rmobile_get_cpu_rev_integer(void)
{
u32 product;
product = readl(PRR);
return (u32)((product & 0x000000F0) >> 4);
}

12
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c → arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
View file

@ -1,8 +1,7 @@
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
* This file is r8a7790 processor support.
* arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -18,5 +17,10 @@ u32 rmobile_get_cpu_type(void)
u32 rmobile_get_cpu_rev_integer(void)
{
return (readl(PRR) & 0x000000F0) >> 4;
return ((readl(PRR) & 0x000000F0) >> 4) + 1;
}
u32 rmobile_get_cpu_rev_fraction(void)
{
return readl(PRR) & 0x0000000F;
}

43
arch/arm/cpu/armv7/rmobile/cpu_info.c
View file

@ -44,36 +44,31 @@ static u32 __rmobile_get_cpu_rev_fraction(void)
u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
/* CPU infomation table */
static const struct {
u16 cpu_type;
u8 cpu_name[10];
} rmobile_cpuinfo[] = {
{ 0x37, "SH73A0" },
{ 0x40, "R8A7740" },
{ 0x45, "R8A7790" },
{ 0x47, "R8A7791" },
{ 0x0, "CPU" },
};
int print_cpuinfo(void)
{
switch (rmobile_get_cpu_type()) {
case 0x37:
printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
case 0x40:
printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
case 0x45:
printf("CPU: Renesas Electronics R8A7790 rev %d\n",
rmobile_get_cpu_rev_integer());
break;
case 0x47:
printf("CPU: Renesas Electronics R8A7791 rev %d\n",
rmobile_get_cpu_rev_integer());
break;
default:
printf("CPU: Renesas Electronics CPU rev %d.%d\n",
int i = 0;
u32 cpu_type = rmobile_get_cpu_type();
for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) {
if (rmobile_cpuinfo[i].cpu_type == cpu_type) {
printf("CPU: Renesas Electronics %s rev %d.%d\n",
rmobile_cpuinfo[i].cpu_name,
rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
break;
}
}
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

18
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
View file

@ -2,7 +2,7 @@
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -40,12 +40,28 @@ do_lowlevel_init:
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
/* and set l2 latency */
mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
orreq r0, r0, #0x00000800
orreq r0, r0, #0x00000003
mcreq p15, 1, r0, c9, c0, 2
mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
and r0, r0, #0xf00
lsr r0, r0, #8
tst r0, #1 /* only need for cluster 0 */
bne _exit_init_l2_a15
mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
and r1, r0, #7
cmp r1, #3 /* has already been set up */
bicne r0, r0, #0xe7
orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
orrne r0, r0, #0x20 /* L2CTLR[5] */
mcrne p15, 1, r0, c9, c0, 2
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]

15
arch/arm/cpu/armv7/socfpga/lowlevel_init.S
View file

@ -10,20 +10,7 @@
/* Save the parameter pass in by previous boot loader */
.global save_boot_params
save_boot_params:
/* save the parameter here */
/*
* Setup stack for exception, which is located
* at the end of on-chip RAM. We don't expect exception prior to
* relocation and if that happens, we won't worry -- it will overide
* global data region as the code will goto reset. After relocation,
* this region won't be used by other part of program.
* Hence it is safe.
*/
ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
ldr r1, =IRQ_STACK_START_IN
str r0, [r1]
/* no parameter to save */
bx lr

253
arch/arm/cpu/armv7/start.S
View file

@ -19,46 +19,6 @@
#include <asm/system.h>
#include <linux/linkage.h>
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt: .word _software_interrupt
_prefetch_abort: .word _prefetch_abort
_data_abort: .word _data_abort
_not_used: .word _not_used
_irq: .word _irq
_fiq: .word _fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#else
.globl _undefined_instruction
_undefined_instruction: .word undefined_instruction
.globl _software_interrupt
_software_interrupt: .word software_interrupt
.globl _prefetch_abort
_prefetch_abort: .word prefetch_abort
.globl _data_abort
_data_abort: .word data_abort
.globl _not_used
_not_used: .word not_used
.globl _irq
_irq: .word irq
.globl _fiq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
/*************************************************************************
*
* Startup Code (reset vector)
@ -70,26 +30,7 @@ _end_vect:
*
*************************************************************************/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
bl save_boot_params
@ -250,195 +191,3 @@ ENTRY(cpu_init_crit)
b lowlevel_init @ go setup pll,mux,memory
ENDPROC(cpu_init_crit)
#endif
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
@ user stack
stmia sp, {r0 - r12} @ Save user registers (now in
@ svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
@ stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc
@ and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0
@ (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
@ a reserved stack spot would
@ be good.
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into
@ cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
@ in banked mode)
str lr, [r13] @ save caller lr in position 0
@ of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of
@ saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure
@ moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction &
@ switch modes.
.endm
.macro get_bad_stack_swi
sub r13, r13, #4 @ space on current stack for
@ scratch reg.
str r0, [r13] @ save R0's value.
ldr r0, IRQ_STACK_START_IN @ get data regions start
@ spots for abort stack
str lr, [r0] @ save caller lr in position 0
@ of saved stack
mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of
@ saved stack
ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effective fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_USE_IRQ */
#endif /* CONFIG_SPL_BUILD */

2
arch/arm/cpu/armv7/zynq/u-boot.lds
View file

@ -88,7 +88,7 @@ SECTIONS
}
/*
* Zynq needs to discard more sections because the user
* Zynq needs to discard these sections because the user
* is expected to pass this image on to tools for boot.bin
* generation that require them to be dropped.
*/

6
arch/arm/cpu/pxa/cpuinfo.c
View file

@ -11,6 +11,12 @@
#include <errno.h>
#include <linux/compiler.h>
#ifdef CONFIG_CPU_PXA25X
#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
#error "Init SP address must be set to 0xfffff800 for PXA250"
#endif
#endif
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f

253
arch/arm/cpu/pxa/start.S
View file

@ -23,54 +23,6 @@
#include <config.h>
#include <version.h>
#ifdef CONFIG_CPU_PXA25X
#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
#error "Init SP address must be set to 0xfffff800 for PXA250"
#endif
#endif
.globl _start
_start: b reset
#ifdef CONFIG_SPL_BUILD
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_hang:
.word do_hang
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678
.word 0x12345678 /* now 16*4=64 */
#else
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
#endif /* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -84,26 +36,7 @@ _end_vect:
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -174,190 +107,6 @@ cpu_init_crit:
mov pc, lr /* back to my caller */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_bad_stack_swi
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
ldr r0, IRQ_STACK_START_IN @ get data regions start
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack
ldr lr, [r0] @ restore lr
ldr r0, [r13] @ restore r0
add r13, r13, #4 @ pop stack entry
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
bl hang /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
.align 5
#endif /* CONFIG_SPL_BUILD */
/*
* Enable MMU to use DCache as DRAM.
*

14
arch/arm/cpu/sa1100/cpu.c
View file

@ -17,6 +17,7 @@
#include <common.h>
#include <command.h>
#include <asm/system.h>
#include <asm/io.h>
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
@ -52,3 +53,16 @@ static void cache_flush (void)
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
#define RST_BASE 0x90030000
#define RSRR 0x00
#define RCSR 0x04
__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
{
/* repeat endlessly */
while (1) {
writel(0, RST_BASE + RCSR);
writel(1, RST_BASE + RSRR);
}
}

225
arch/arm/cpu/sa1100/start.S
View file

@ -13,36 +13,6 @@
#include <config.h>
#include <version.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
@ -56,26 +26,7 @@ _fiq: .word fiq
*************************************************************************
*/
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
.globl reset
reset:
/*
@ -173,177 +124,3 @@ cpu_init_crit:
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov pc, lr
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
ldr r2, IRQ_STACK_START_IN
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
mov r0, sp
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
msr spsr_c, r13
mov lr, pc
movs pc, lr
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
.align 5
.globl reset_cpu
reset_cpu:
ldr r0, RST_BASE
mov r1, #0x0 @ set bit 3-0 ...
str r1, [r0, #RCSR] @ ... to clear in RCSR
mov r1, #0x1
str r1, [r0, #RSRR] @ and perform reset
b reset_cpu @ silly, but repeat endlessly

19
arch/arm/cpu/tegra-common/pinmux-common.c
View file

@ -86,12 +86,31 @@
#define IO_RESET_SHIFT 8
#define RCV_SEL_SHIFT 9
#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
/* This register/field only exists on Tegra114 and later */
#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
#define CLAMP_INPUTS_WHEN_TRISTATED 1
void pinmux_set_tristate_input_clamping(void)
{
u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
u32 val;
val = readl(reg);
val |= CLAMP_INPUTS_WHEN_TRISTATED;
writel(val, reg);
}
#endif
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
u32 *reg = MUX_REG(pin);
int i, mux = -1;
u32 val;
if (func == PMUX_FUNC_DEFAULT)
return;
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));

1
arch/arm/cpu/u-boot-spl.lds
View file

@ -18,6 +18,7 @@ SECTIONS
.text :
{
__image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}

1
arch/arm/cpu/u-boot.lds
View file

@ -18,6 +18,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}

2
arch/arm/dts/exynos4210-origen.dts
View file

@ -36,7 +36,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x2008002 0>;
cd-gpios = <&gpio 0xA2 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4210-trats.dts
View file

@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x2008002 0>;
pwr-gpios = <&gpio 0xA2 0>;
};
sdhci@12520000 {
@ -111,7 +111,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x20c6004 0>;
cd-gpios = <&gpio 0x39C 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4210-universal_c210.dts
View file

@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x2008002 0>;
pwr-gpios = <&gpio 0xA2 0>;
};
sdhci@12520000 {
@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x20c6004 0>;
cd-gpios = <&gpio 0x39C 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4412-trats2.dts
View file

@ -415,7 +415,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x2004002 0>;
pwr-gpios = <&gpio 0xB2 0>;
};
sdhci@12520000 {
@ -425,7 +425,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x20C6004 0>;
cd-gpios = <&gpio 0x3BC 0>;
};
sdhci@12540000 {

10
arch/arm/dts/imx6q-sabreauto.dts
View file

@ -1,9 +1,9 @@
/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;

1
arch/arm/imx-common/Makefile
View file

@ -19,6 +19,7 @@ obj-y += misc.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o

8
arch/arm/imx-common/iomux-v3.c
View file

@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
#if defined CONFIG_MX6SL
/* Check whether LVE bit needs to be set */
if (pad_ctrl & PAD_CTL_LVE) {
pad_ctrl &= ~PAD_CTL_LVE;
pad_ctrl |= PAD_CTL_LVE_BIT;
}
#endif
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);

65
arch/arm/imx-common/video.c Normal file
View file

@ -0,0 +1,65 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/imx-common/video.h>
extern struct display_info_t const displays[];
extern size_t display_count;
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
for (i = 0; i < display_count; i++) {
struct display_info_t const *dev = displays+i;
if (dev->detect && dev->detect(dev)) {
panel = dev->mode.name;
printf("auto-detected panel %s\n", panel);
break;
}
}
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
i = 0;
}
} else {
for (i = 0; i < display_count; i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < display_count) {
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
} else {
printf("unsupported panel %s\n", panel);
return -EINVAL;
}
return 0;
}
#ifdef CONFIG_IMX_HDMI
#include <asm/arch/mxc_hdmi.h>
#include <asm/io.h>
int detect_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
}
#endif

2
arch/arm/include/asm/arch-am33xx/clock.h
View file

@ -42,6 +42,8 @@
#define MODULE_CLKCTRL_IDLEST_DISABLED 3
/* CM_CLKMODE_DPLL */
#define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12
#define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12)
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10

17
arch/arm/include/asm/arch-exynos/cpu.h
View file

@ -98,7 +98,7 @@
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
#define EXYNOS5_GPIO_PART8_BASE 0x03860000
#define EXYNOS5_PRO_ID 0x10000000
#define EXYNOS5_CLOCK_BASE 0x10010000
#define EXYNOS5_POWER_BASE 0x10040000
@ -108,9 +108,13 @@
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY_BASE 0x10C00000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
#define EXYNOS5_GPIO_PART5_BASE 0x10D10000
#define EXYNOS5_GPIO_PART6_BASE 0x10D10060
#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
#define EXYNOS5_GPIO_PART2_BASE 0x114002E0
#define EXYNOS5_GPIO_PART3_BASE 0x11400C00
#define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
#define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
#define EXYNOS5_USB3PHY_BASE 0x12100000
@ -125,7 +129,7 @@
#define EXYNOS5_I2S_BASE 0x12D60000
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5_SPI_ISP_BASE 0x131A0000
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
#define EXYNOS5_GPIO_PART4_BASE 0x13400000
#define EXYNOS5_FIMD_BASE 0x14400000
#define EXYNOS5_DP_BASE 0x145B0000
@ -135,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
#define EXYNOS5420_GPIO_PART6_BASE 0x03860000
#define EXYNOS5420_PRO_ID 0x10000000
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
@ -158,8 +162,9 @@
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
#define EXYNOS5420_GPIO_PART4_BASE 0x13410000
#define EXYNOS5420_GPIO_PART5_BASE 0x14000000
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
#define EXYNOS5420_DP_BASE 0x145B0000

1787
arch/arm/include/asm/arch-exynos/gpio.h
View file

File diff suppressed because it is too large Load diff

175
arch/arm/include/asm/arch-mx25/imx-regs.h
View file

@ -161,6 +161,126 @@ struct aips_regs {
u32 mpr_0_7;
u32 mpr_8_15;
};
/* LCD controller registers */
struct lcdc_regs {
u32 lssar; /* Screen Start Address */
u32 lsr; /* Size */
u32 lvpwr; /* Virtual Page Width */
u32 lcpr; /* Cursor Position */
u32 lcwhb; /* Cursor Width Height and Blink */
u32 lccmr; /* Color Cursor Mapping */
u32 lpcr; /* Panel Configuration */
u32 lhcr; /* Horizontal Configuration */
u32 lvcr; /* Vertical Configuration */
u32 lpor; /* Panning Offset */
u32 lscr; /* Sharp Configuration */
u32 lpccr; /* PWM Contrast Control */
u32 ldcr; /* DMA Control */
u32 lrmcr; /* Refresh Mode Control */
u32 licr; /* Interrupt Configuration */
u32 lier; /* Interrupt Enable */
u32 lisr; /* Interrupt Status */
u32 res0[3];
u32 lgwsar; /* Graphic Window Start Address */
u32 lgwsr; /* Graphic Window Size */
u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
u32 lgwpor; /* Graphic Window Panning Offset */
u32 lgwpr; /* Graphic Window Position */
u32 lgwcr; /* Graphic Window Control */
u32 lgwdcr; /* Graphic Window DMA Control */
u32 res1[5];
u32 lauscr; /* AUS Mode Control */
u32 lausccr; /* AUS mode Cursor Control */
u32 res2[31 + 64*7];
u32 bglut; /* Background Lookup Table */
u32 gwlut; /* Graphic Window Lookup Table */
};
/* Wireless External Interface Module Registers */
struct weim_regs {
u32 cscr0u; /* Chip Select 0 Upper Register */
u32 cscr0l; /* Chip Select 0 Lower Register */
u32 cscr0a; /* Chip Select 0 Addition Register */
u32 pad0;
u32 cscr1u; /* Chip Select 1 Upper Register */
u32 cscr1l; /* Chip Select 1 Lower Register */
u32 cscr1a; /* Chip Select 1 Addition Register */
u32 pad1;
u32 cscr2u; /* Chip Select 2 Upper Register */
u32 cscr2l; /* Chip Select 2 Lower Register */
u32 cscr2a; /* Chip Select 2 Addition Register */
u32 pad2;
u32 cscr3u; /* Chip Select 3 Upper Register */
u32 cscr3l; /* Chip Select 3 Lower Register */
u32 cscr3a; /* Chip Select 3 Addition Register */
u32 pad3;
u32 cscr4u; /* Chip Select 4 Upper Register */
u32 cscr4l; /* Chip Select 4 Lower Register */
u32 cscr4a; /* Chip Select 4 Addition Register */
u32 pad4;
u32 cscr5u; /* Chip Select 5 Upper Register */
u32 cscr5l; /* Chip Select 5 Lower Register */
u32 cscr5a; /* Chip Select 5 Addition Register */
u32 pad5;
u32 wcr; /* WEIM Configuration Register */
};
/* Multi-Master Memory Interface */
struct m3if_regs {
u32 ctl; /* Control Register */
u32 wcfg0; /* Watermark Configuration Register 0 */
u32 wcfg1; /* Watermark Configuration Register1 */
u32 wcfg2; /* Watermark Configuration Register2 */
u32 wcfg3; /* Watermark Configuration Register 3 */
u32 wcfg4; /* Watermark Configuration Register 4 */
u32 wcfg5; /* Watermark Configuration Register 5 */
u32 wcfg6; /* Watermark Configuration Register 6 */
u32 wcfg7; /* Watermark Configuration Register 7 */
u32 wcsr; /* Watermark Control and Status Register */
u32 scfg0; /* Snooping Configuration Register 0 */
u32 scfg1; /* Snooping Configuration Register 1 */
u32 scfg2; /* Snooping Configuration Register 2 */
u32 ssr0; /* Snooping Status Register 0 */
u32 ssr1; /* Snooping Status Register 1 */
u32 res0;
u32 mlwe0; /* Master Lock WEIM CS0 Register */
u32 mlwe1; /* Master Lock WEIM CS1 Register */
u32 mlwe2; /* Master Lock WEIM CS2 Register */
u32 mlwe3; /* Master Lock WEIM CS3 Register */
u32 mlwe4; /* Master Lock WEIM CS4 Register */
u32 mlwe5; /* Master Lock WEIM CS5 Register */
};
/* Pulse width modulation */
struct pwm_regs {
u32 cr; /* Control Register */
u32 sr; /* Status Register */
u32 ir; /* Interrupt Register */
u32 sar; /* Sample Register */
u32 pr; /* Period Register */
u32 cnr; /* Counter Register */
};
/* Enhanced Periodic Interrupt Timer */
struct epit_regs {
u32 cr; /* Control register */
u32 sr; /* Status register */
u32 lr; /* Load register */
u32 cmpr; /* Compare register */
u32 cnr; /* Counter register */
};
/* CSPI registers */
struct cspi_regs {
u32 rxdata;
u32 txdata;
u32 ctrl;
u32 intr;
u32 dma;
u32 stat;
u32 period;
u32 test;
};
#endif
@ -289,6 +409,8 @@ struct aips_regs {
#define CCM_PERCLK_MASK 0x3f
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
#define CCM_CRDR_BT_UART_SRC_SHIFT 29
#define CCM_CRDR_BT_UART_SRC_MASK 7
/* ESDRAM Controller register bitfields */
#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
@ -345,12 +467,65 @@ struct aips_regs {
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
/* MAX bits */
#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
/* M3IF bits */
#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
/* WEIM bits */
/* 13 fields of the upper CS control register */
#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
cnc, wsc, ew, wws, edc) \
((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
/* 12 fields of the lower CS control register */
#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
csa, ebc, dsz, csn, psr, cre, wrap, csen) \
((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
/* 14 fields of the additional CS control register */
#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
wwu, age, cnc2, fce) \
((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
(age) << 2 | (cnc2) << 1 | (fce) << 0)
/* Names used in GPIO driver */
#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
/*
* CSPI register definitions
*/
#define MXC_CSPI
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_SMC (1 << 3)
#define MXC_CSPICTRL_POL (1 << 4)
#define MXC_CSPICTRL_PHA (1 << 5)
#define MXC_CSPICTRL_SSCTL (1 << 6)
#define MXC_CSPICTRL_SSPOL (1 << 7)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
#define MXC_CSPICTRL_TC (1 << 7)
#define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPICTRL_MAXBITS 0xfff
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
#define MAX_SPI_BYTES 4
#define MXC_SPI_BASE_ADDRESSES \
IMX_CSPI1_BASE, \
IMX_CSPI2_BASE, \
IMX_CSPI3_BASE
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
#define CHIP_REV_1_2 0x12

4
arch/arm/include/asm/arch-mx6/mx6sl_pins.h
View file

@ -10,6 +10,10 @@
#include <asm/imx-common/iomux-v3.h>
enum {
MX6_PAD_ECSPI1_MISO__ECSPI_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),

3
arch/arm/include/asm/arch-omap5/clock.h
View file

@ -322,6 +322,9 @@
#define V_SCLK V_OSCK
/* CKO buffer control */
#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
/* AUXCLKx reg fields */
#define AUXCLK_ENABLE_MASK (1 << 8)
#define AUXCLK_SRCSELECT_SHIFT 1

1
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -50,6 +50,7 @@
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000)
/* General Purpose Timers */
#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)

609
arch/arm/include/asm/arch-rmobile/r8a7790.h
View file

@ -1,615 +1,18 @@
/*
* arch/arm/include/asm/arch-rmobile/r8a7790.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
*/
#ifndef __ASM_ARCH_R8A7790_H
#define __ASM_ARCH_R8A7790_H
/*
* R8A7790 I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define SH_QSPI_BASE 0xE6B10000
#include "rcar-base.h"
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7790_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct r8a7790_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct r8a7790_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct r8a7790_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct r8a7790_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct r8a7790_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 s3carcr11;
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct r8a7790_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct r8a7790_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct r8a7790_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[7]; /* 0x08 .. 0x20 */
u32 mxaxiracr;
u32 mxs3cracr;
u32 dummy1[2]; /* 0x2C .. 0x30 */
u32 mxaxiwacr;
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct r8a7790_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct r8a7790_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7790_H */

626
arch/arm/include/asm/arch-rmobile/r8a7791.h
View file

@ -1,69 +1,18 @@
/*
* arch/arm/include/asm/arch-rmobile/r8a7791.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
*/
#ifndef __ASM_ARCH_R8A7791_H
#define __ASM_ARCH_R8A7791_H
#include "rcar-base.h"
/*
* R8A7791 I/O Addresses
* R-Car (R8A7791) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
@ -97,569 +46,8 @@
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define SYS_AXI_AX2M_BASE 0xFF800380
#define SYS_AXI_CC50_BASE 0xFF8003C0
#define SYS_AXI_CCI_BASE 0xFF800440
#define SYS_AXI_CS_BASE 0xFF800480
#define SYS_AXI_DDM_BASE 0xFF8004C0
#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_SAT0_BASE 0xFF800980
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
#define SYS_AXI_TRAB_BASE 0xFF800B00
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_DBG_BASE 0xFF810140
#define RT_AXI_RDM_BASE 0xFF810180
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define RT_AXI_SY2RT_BASE 0xFF810280
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_MXR_BASE 0xFE960080
#define MEDIA_AXI_MXW_BASE 0xFE9600C0
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7791_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct r8a7791_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct r8a7791_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct r8a7791_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct r8a7791_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct r8a7791_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 dummy0; /* 0x10 */
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct r8a7791_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct r8a7791_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct r8a7791_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[8]; /* 0x08 .. 0x24 */
u32 mxs3cracr;
u32 dummy1[3]; /* 0x2C .. 0x34 */
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct r8a7791_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct r8a7791_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#define R8A7791_CUT_ES2X 2
#define IS_R8A7791_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7791_H */

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arch/arm/include/asm/arch-rmobile/rcar-base.h Normal file
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/*
* arch/arm/include/asm/arch-rmobile/rcar-base.h
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_RCAR_BASE_H
#define __ASM_ARCH_RCAR_BASE_H
/*
* R-Car (R8A7790/R8A7791) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define SYS_AXI_AX2M_BASE 0xFF800380
#define SYS_AXI_CC50_BASE 0xFF8003C0
#define SYS_AXI_CCI_BASE 0xFF800440
#define SYS_AXI_CS_BASE 0xFF800480
#define SYS_AXI_DDM_BASE 0xFF8004C0
#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_SAT0_BASE 0xFF800980
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
#define SYS_AXI_TRAB_BASE 0xFF800B00
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */
#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_BIT 24
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct rcar_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct rcar_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct rcar_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct rcar_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct rcar_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct rcar_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 s3carcr11;
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct rcar_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct rcar_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct rcar_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[7]; /* 0x08 .. 0x20 */
u32 mxaxiracr; /* R8a7790 only */
u32 mxs3cracr;
u32 dummy1[2]; /* 0x2C .. 0x30 */
u32 mxaxiwacr; /* R8a7790 only */
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct rcar_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct rcar_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#endif /* __ASM_ARCH_RCAR_BASE_H */

6
arch/arm/include/asm/arch-rmobile/rmobile.h
View file

@ -15,4 +15,10 @@
#endif
#endif /* CONFIG_RMOBILE */
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_H */

960
arch/arm/include/asm/arch-s5pc1xx/gpio.h
View file

@ -19,170 +19,830 @@ struct s5p_gpio_bank {
unsigned char res1[8];
};
struct s5pc100_gpio {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
struct s5p_gpio_bank c;
struct s5p_gpio_bank d;
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
struct s5p_gpio_bank g0;
struct s5p_gpio_bank g1;
struct s5p_gpio_bank g2;
struct s5p_gpio_bank g3;
struct s5p_gpio_bank i;
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank j2;
struct s5p_gpio_bank j3;
struct s5p_gpio_bank j4;
struct s5p_gpio_bank k0;
struct s5p_gpio_bank k1;
struct s5p_gpio_bank k2;
struct s5p_gpio_bank k3;
struct s5p_gpio_bank l0;
struct s5p_gpio_bank l1;
struct s5p_gpio_bank l2;
struct s5p_gpio_bank l3;
struct s5p_gpio_bank l4;
struct s5p_gpio_bank h0;
struct s5p_gpio_bank h1;
struct s5p_gpio_bank h2;
struct s5p_gpio_bank h3;
/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
enum s5pc100_gpio_pin {
S5PC100_GPIO_A00,
S5PC100_GPIO_A01,
S5PC100_GPIO_A02,
S5PC100_GPIO_A03,
S5PC100_GPIO_A04,
S5PC100_GPIO_A05,
S5PC100_GPIO_A06,
S5PC100_GPIO_A07,
S5PC100_GPIO_A10,
S5PC100_GPIO_A11,
S5PC100_GPIO_A12,
S5PC100_GPIO_A13,
S5PC100_GPIO_A14,
S5PC100_GPIO_A15,
S5PC100_GPIO_A16,
S5PC100_GPIO_A17,
S5PC100_GPIO_B0,
S5PC100_GPIO_B1,
S5PC100_GPIO_B2,
S5PC100_GPIO_B3,
S5PC100_GPIO_B4,
S5PC100_GPIO_B5,
S5PC100_GPIO_B6,
S5PC100_GPIO_B7,
S5PC100_GPIO_C0,
S5PC100_GPIO_C1,
S5PC100_GPIO_C2,
S5PC100_GPIO_C3,
S5PC100_GPIO_C4,
S5PC100_GPIO_C5,
S5PC100_GPIO_C6,
S5PC100_GPIO_C7,
S5PC100_GPIO_D0,
S5PC100_GPIO_D1,
S5PC100_GPIO_D2,
S5PC100_GPIO_D3,
S5PC100_GPIO_D4,
S5PC100_GPIO_D5,
S5PC100_GPIO_D6,
S5PC100_GPIO_D7,
S5PC100_GPIO_E00,
S5PC100_GPIO_E01,
S5PC100_GPIO_E02,
S5PC100_GPIO_E03,
S5PC100_GPIO_E04,
S5PC100_GPIO_E05,
S5PC100_GPIO_E06,
S5PC100_GPIO_E07,
S5PC100_GPIO_E10,
S5PC100_GPIO_E11,
S5PC100_GPIO_E12,
S5PC100_GPIO_E13,
S5PC100_GPIO_E14,
S5PC100_GPIO_E15,
S5PC100_GPIO_E16,
S5PC100_GPIO_E17,
S5PC100_GPIO_F00,
S5PC100_GPIO_F01,
S5PC100_GPIO_F02,
S5PC100_GPIO_F03,
S5PC100_GPIO_F04,
S5PC100_GPIO_F05,
S5PC100_GPIO_F06,
S5PC100_GPIO_F07,
S5PC100_GPIO_F10,
S5PC100_GPIO_F11,
S5PC100_GPIO_F12,
S5PC100_GPIO_F13,
S5PC100_GPIO_F14,
S5PC100_GPIO_F15,
S5PC100_GPIO_F16,
S5PC100_GPIO_F17,
S5PC100_GPIO_F20,
S5PC100_GPIO_F21,
S5PC100_GPIO_F22,
S5PC100_GPIO_F23,
S5PC100_GPIO_F24,
S5PC100_GPIO_F25,
S5PC100_GPIO_F26,
S5PC100_GPIO_F27,
S5PC100_GPIO_F30,
S5PC100_GPIO_F31,
S5PC100_GPIO_F32,
S5PC100_GPIO_F33,
S5PC100_GPIO_F34,
S5PC100_GPIO_F35,
S5PC100_GPIO_F36,
S5PC100_GPIO_F37,
S5PC100_GPIO_G00,
S5PC100_GPIO_G01,
S5PC100_GPIO_G02,
S5PC100_GPIO_G03,
S5PC100_GPIO_G04,
S5PC100_GPIO_G05,
S5PC100_GPIO_G06,
S5PC100_GPIO_G07,
S5PC100_GPIO_G10,
S5PC100_GPIO_G11,
S5PC100_GPIO_G12,
S5PC100_GPIO_G13,
S5PC100_GPIO_G14,
S5PC100_GPIO_G15,
S5PC100_GPIO_G16,
S5PC100_GPIO_G17,
S5PC100_GPIO_G20,
S5PC100_GPIO_G21,
S5PC100_GPIO_G22,
S5PC100_GPIO_G23,
S5PC100_GPIO_G24,
S5PC100_GPIO_G25,
S5PC100_GPIO_G26,
S5PC100_GPIO_G27,
S5PC100_GPIO_G30,
S5PC100_GPIO_G31,
S5PC100_GPIO_G32,
S5PC100_GPIO_G33,
S5PC100_GPIO_G34,
S5PC100_GPIO_G35,
S5PC100_GPIO_G36,
S5PC100_GPIO_G37,
S5PC100_GPIO_I0,
S5PC100_GPIO_I1,
S5PC100_GPIO_I2,
S5PC100_GPIO_I3,
S5PC100_GPIO_I4,
S5PC100_GPIO_I5,
S5PC100_GPIO_I6,
S5PC100_GPIO_I7,
S5PC100_GPIO_J00,
S5PC100_GPIO_J01,
S5PC100_GPIO_J02,
S5PC100_GPIO_J03,
S5PC100_GPIO_J04,
S5PC100_GPIO_J05,
S5PC100_GPIO_J06,
S5PC100_GPIO_J07,
S5PC100_GPIO_J10,
S5PC100_GPIO_J11,
S5PC100_GPIO_J12,
S5PC100_GPIO_J13,
S5PC100_GPIO_J14,
S5PC100_GPIO_J15,
S5PC100_GPIO_J16,
S5PC100_GPIO_J17,
S5PC100_GPIO_J20,
S5PC100_GPIO_J21,
S5PC100_GPIO_J22,
S5PC100_GPIO_J23,
S5PC100_GPIO_J24,
S5PC100_GPIO_J25,
S5PC100_GPIO_J26,
S5PC100_GPIO_J27,
S5PC100_GPIO_J30,
S5PC100_GPIO_J31,
S5PC100_GPIO_J32,
S5PC100_GPIO_J33,
S5PC100_GPIO_J34,
S5PC100_GPIO_J35,
S5PC100_GPIO_J36,
S5PC100_GPIO_J37,
S5PC100_GPIO_J40,
S5PC100_GPIO_J41,
S5PC100_GPIO_J42,
S5PC100_GPIO_J43,
S5PC100_GPIO_J44,
S5PC100_GPIO_J45,
S5PC100_GPIO_J46,
S5PC100_GPIO_J47,
S5PC100_GPIO_K00,
S5PC100_GPIO_K01,
S5PC100_GPIO_K02,
S5PC100_GPIO_K03,
S5PC100_GPIO_K04,
S5PC100_GPIO_K05,
S5PC100_GPIO_K06,
S5PC100_GPIO_K07,
S5PC100_GPIO_K10,
S5PC100_GPIO_K11,
S5PC100_GPIO_K12,
S5PC100_GPIO_K13,
S5PC100_GPIO_K14,
S5PC100_GPIO_K15,
S5PC100_GPIO_K16,
S5PC100_GPIO_K17,
S5PC100_GPIO_K20,
S5PC100_GPIO_K21,
S5PC100_GPIO_K22,
S5PC100_GPIO_K23,
S5PC100_GPIO_K24,
S5PC100_GPIO_K25,
S5PC100_GPIO_K26,
S5PC100_GPIO_K27,
S5PC100_GPIO_K30,
S5PC100_GPIO_K31,
S5PC100_GPIO_K32,
S5PC100_GPIO_K33,
S5PC100_GPIO_K34,
S5PC100_GPIO_K35,
S5PC100_GPIO_K36,
S5PC100_GPIO_K37,
S5PC100_GPIO_L00,
S5PC100_GPIO_L01,
S5PC100_GPIO_L02,
S5PC100_GPIO_L03,
S5PC100_GPIO_L04,
S5PC100_GPIO_L05,
S5PC100_GPIO_L06,
S5PC100_GPIO_L07,
S5PC100_GPIO_L10,
S5PC100_GPIO_L11,
S5PC100_GPIO_L12,
S5PC100_GPIO_L13,
S5PC100_GPIO_L14,
S5PC100_GPIO_L15,
S5PC100_GPIO_L16,
S5PC100_GPIO_L17,
S5PC100_GPIO_L20,
S5PC100_GPIO_L21,
S5PC100_GPIO_L22,
S5PC100_GPIO_L23,
S5PC100_GPIO_L24,
S5PC100_GPIO_L25,
S5PC100_GPIO_L26,
S5PC100_GPIO_L27,
S5PC100_GPIO_L30,
S5PC100_GPIO_L31,
S5PC100_GPIO_L32,
S5PC100_GPIO_L33,
S5PC100_GPIO_L34,
S5PC100_GPIO_L35,
S5PC100_GPIO_L36,
S5PC100_GPIO_L37,
S5PC100_GPIO_L40,
S5PC100_GPIO_L41,
S5PC100_GPIO_L42,
S5PC100_GPIO_L43,
S5PC100_GPIO_L44,
S5PC100_GPIO_L45,
S5PC100_GPIO_L46,
S5PC100_GPIO_L47,
S5PC100_GPIO_H00,
S5PC100_GPIO_H01,
S5PC100_GPIO_H02,
S5PC100_GPIO_H03,
S5PC100_GPIO_H04,
S5PC100_GPIO_H05,
S5PC100_GPIO_H06,
S5PC100_GPIO_H07,
S5PC100_GPIO_H10,
S5PC100_GPIO_H11,
S5PC100_GPIO_H12,
S5PC100_GPIO_H13,
S5PC100_GPIO_H14,
S5PC100_GPIO_H15,
S5PC100_GPIO_H16,
S5PC100_GPIO_H17,
S5PC100_GPIO_H20,
S5PC100_GPIO_H21,
S5PC100_GPIO_H22,
S5PC100_GPIO_H23,
S5PC100_GPIO_H24,
S5PC100_GPIO_H25,
S5PC100_GPIO_H26,
S5PC100_GPIO_H27,
S5PC100_GPIO_H30,
S5PC100_GPIO_H31,
S5PC100_GPIO_H32,
S5PC100_GPIO_H33,
S5PC100_GPIO_H34,
S5PC100_GPIO_H35,
S5PC100_GPIO_H36,
S5PC100_GPIO_H37,
S5PC100_GPIO_MAX_PORT
};
struct s5pc110_gpio {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
struct s5p_gpio_bank c0;
struct s5p_gpio_bank c1;
struct s5p_gpio_bank d0;
struct s5p_gpio_bank d1;
struct s5p_gpio_bank e0;
struct s5p_gpio_bank e1;
struct s5p_gpio_bank f0;
struct s5p_gpio_bank f1;
struct s5p_gpio_bank f2;
struct s5p_gpio_bank f3;
struct s5p_gpio_bank g0;
struct s5p_gpio_bank g1;
struct s5p_gpio_bank g2;
struct s5p_gpio_bank g3;
struct s5p_gpio_bank i;
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank j2;
struct s5p_gpio_bank j3;
struct s5p_gpio_bank j4;
struct s5p_gpio_bank mp0_1;
struct s5p_gpio_bank mp0_2;
struct s5p_gpio_bank mp0_3;
struct s5p_gpio_bank mp0_4;
struct s5p_gpio_bank mp0_5;
struct s5p_gpio_bank mp0_6;
struct s5p_gpio_bank mp0_7;
struct s5p_gpio_bank mp1_0;
struct s5p_gpio_bank mp1_1;
struct s5p_gpio_bank mp1_2;
struct s5p_gpio_bank mp1_3;
struct s5p_gpio_bank mp1_4;
struct s5p_gpio_bank mp1_5;
struct s5p_gpio_bank mp1_6;
struct s5p_gpio_bank mp1_7;
struct s5p_gpio_bank mp1_8;
struct s5p_gpio_bank mp2_0;
struct s5p_gpio_bank mp2_1;
struct s5p_gpio_bank mp2_2;
struct s5p_gpio_bank mp2_3;
struct s5p_gpio_bank mp2_4;
struct s5p_gpio_bank mp2_5;
struct s5p_gpio_bank mp2_6;
struct s5p_gpio_bank mp2_7;
struct s5p_gpio_bank mp2_8;
struct s5p_gpio_bank res1[48];
struct s5p_gpio_bank h0;
struct s5p_gpio_bank h1;
struct s5p_gpio_bank h2;
struct s5p_gpio_bank h3;
enum s5pc110_gpio_pin {
S5PC110_GPIO_A00,
S5PC110_GPIO_A01,
S5PC110_GPIO_A02,
S5PC110_GPIO_A03,
S5PC110_GPIO_A04,
S5PC110_GPIO_A05,
S5PC110_GPIO_A06,
S5PC110_GPIO_A07,
S5PC110_GPIO_A10,
S5PC110_GPIO_A11,
S5PC110_GPIO_A12,
S5PC110_GPIO_A13,
S5PC110_GPIO_A14,
S5PC110_GPIO_A15,
S5PC110_GPIO_A16,
S5PC110_GPIO_A17,
S5PC110_GPIO_B0,
S5PC110_GPIO_B1,
S5PC110_GPIO_B2,
S5PC110_GPIO_B3,
S5PC110_GPIO_B4,
S5PC110_GPIO_B5,
S5PC110_GPIO_B6,
S5PC110_GPIO_B7,
S5PC110_GPIO_C00,
S5PC110_GPIO_C01,
S5PC110_GPIO_C02,
S5PC110_GPIO_C03,
S5PC110_GPIO_C04,
S5PC110_GPIO_C05,
S5PC110_GPIO_C06,
S5PC110_GPIO_C07,
S5PC110_GPIO_C10,
S5PC110_GPIO_C11,
S5PC110_GPIO_C12,
S5PC110_GPIO_C13,
S5PC110_GPIO_C14,
S5PC110_GPIO_C15,
S5PC110_GPIO_C16,
S5PC110_GPIO_C17,
S5PC110_GPIO_D00,
S5PC110_GPIO_D01,
S5PC110_GPIO_D02,
S5PC110_GPIO_D03,
S5PC110_GPIO_D04,
S5PC110_GPIO_D05,
S5PC110_GPIO_D06,
S5PC110_GPIO_D07,
S5PC110_GPIO_D10,
S5PC110_GPIO_D11,
S5PC110_GPIO_D12,
S5PC110_GPIO_D13,
S5PC110_GPIO_D14,
S5PC110_GPIO_D15,
S5PC110_GPIO_D16,
S5PC110_GPIO_D17,
S5PC110_GPIO_E00,
S5PC110_GPIO_E01,
S5PC110_GPIO_E02,
S5PC110_GPIO_E03,
S5PC110_GPIO_E04,
S5PC110_GPIO_E05,
S5PC110_GPIO_E06,
S5PC110_GPIO_E07,
S5PC110_GPIO_E10,
S5PC110_GPIO_E11,
S5PC110_GPIO_E12,
S5PC110_GPIO_E13,
S5PC110_GPIO_E14,
S5PC110_GPIO_E15,
S5PC110_GPIO_E16,
S5PC110_GPIO_E17,
S5PC110_GPIO_F00,
S5PC110_GPIO_F01,
S5PC110_GPIO_F02,
S5PC110_GPIO_F03,
S5PC110_GPIO_F04,
S5PC110_GPIO_F05,
S5PC110_GPIO_F06,
S5PC110_GPIO_F07,
S5PC110_GPIO_F10,
S5PC110_GPIO_F11,
S5PC110_GPIO_F12,
S5PC110_GPIO_F13,
S5PC110_GPIO_F14,
S5PC110_GPIO_F15,
S5PC110_GPIO_F16,
S5PC110_GPIO_F17,
S5PC110_GPIO_F20,
S5PC110_GPIO_F21,
S5PC110_GPIO_F22,
S5PC110_GPIO_F23,
S5PC110_GPIO_F24,
S5PC110_GPIO_F25,
S5PC110_GPIO_F26,
S5PC110_GPIO_F27,
S5PC110_GPIO_F30,
S5PC110_GPIO_F31,
S5PC110_GPIO_F32,
S5PC110_GPIO_F33,
S5PC110_GPIO_F34,
S5PC110_GPIO_F35,
S5PC110_GPIO_F36,
S5PC110_GPIO_F37,
S5PC110_GPIO_G00,
S5PC110_GPIO_G01,
S5PC110_GPIO_G02,
S5PC110_GPIO_G03,
S5PC110_GPIO_G04,
S5PC110_GPIO_G05,
S5PC110_GPIO_G06,
S5PC110_GPIO_G07,
S5PC110_GPIO_G10,
S5PC110_GPIO_G11,
S5PC110_GPIO_G12,
S5PC110_GPIO_G13,
S5PC110_GPIO_G14,
S5PC110_GPIO_G15,
S5PC110_GPIO_G16,
S5PC110_GPIO_G17,
S5PC110_GPIO_G20,
S5PC110_GPIO_G21,
S5PC110_GPIO_G22,
S5PC110_GPIO_G23,
S5PC110_GPIO_G24,
S5PC110_GPIO_G25,
S5PC110_GPIO_G26,
S5PC110_GPIO_G27,
S5PC110_GPIO_G30,
S5PC110_GPIO_G31,
S5PC110_GPIO_G32,
S5PC110_GPIO_G33,
S5PC110_GPIO_G34,
S5PC110_GPIO_G35,
S5PC110_GPIO_G36,
S5PC110_GPIO_G37,
S5PC110_GPIO_I0,
S5PC110_GPIO_I1,
S5PC110_GPIO_I2,
S5PC110_GPIO_I3,
S5PC110_GPIO_I4,
S5PC110_GPIO_I5,
S5PC110_GPIO_I6,
S5PC110_GPIO_I7,
S5PC110_GPIO_J00,
S5PC110_GPIO_J01,
S5PC110_GPIO_J02,
S5PC110_GPIO_J03,
S5PC110_GPIO_J04,
S5PC110_GPIO_J05,
S5PC110_GPIO_J06,
S5PC110_GPIO_J07,
S5PC110_GPIO_J10,
S5PC110_GPIO_J11,
S5PC110_GPIO_J12,
S5PC110_GPIO_J13,
S5PC110_GPIO_J14,
S5PC110_GPIO_J15,
S5PC110_GPIO_J16,
S5PC110_GPIO_J17,
S5PC110_GPIO_J20,
S5PC110_GPIO_J21,
S5PC110_GPIO_J22,
S5PC110_GPIO_J23,
S5PC110_GPIO_J24,
S5PC110_GPIO_J25,
S5PC110_GPIO_J26,
S5PC110_GPIO_J27,
S5PC110_GPIO_J30,
S5PC110_GPIO_J31,
S5PC110_GPIO_J32,
S5PC110_GPIO_J33,
S5PC110_GPIO_J34,
S5PC110_GPIO_J35,
S5PC110_GPIO_J36,
S5PC110_GPIO_J37,
S5PC110_GPIO_J40,
S5PC110_GPIO_J41,
S5PC110_GPIO_J42,
S5PC110_GPIO_J43,
S5PC110_GPIO_J44,
S5PC110_GPIO_J45,
S5PC110_GPIO_J46,
S5PC110_GPIO_J47,
S5PC110_GPIO_MP010,
S5PC110_GPIO_MP011,
S5PC110_GPIO_MP012,
S5PC110_GPIO_MP013,
S5PC110_GPIO_MP014,
S5PC110_GPIO_MP015,
S5PC110_GPIO_MP016,
S5PC110_GPIO_MP017,
S5PC110_GPIO_MP020,
S5PC110_GPIO_MP021,
S5PC110_GPIO_MP022,
S5PC110_GPIO_MP023,
S5PC110_GPIO_MP024,
S5PC110_GPIO_MP025,
S5PC110_GPIO_MP026,
S5PC110_GPIO_MP027,
S5PC110_GPIO_MP030,
S5PC110_GPIO_MP031,
S5PC110_GPIO_MP032,
S5PC110_GPIO_MP033,
S5PC110_GPIO_MP034,
S5PC110_GPIO_MP035,
S5PC110_GPIO_MP036,
S5PC110_GPIO_MP037,
S5PC110_GPIO_MP040,
S5PC110_GPIO_MP041,
S5PC110_GPIO_MP042,
S5PC110_GPIO_MP043,
S5PC110_GPIO_MP044,
S5PC110_GPIO_MP045,
S5PC110_GPIO_MP046,
S5PC110_GPIO_MP047,
S5PC110_GPIO_MP050,
S5PC110_GPIO_MP051,
S5PC110_GPIO_MP052,
S5PC110_GPIO_MP053,
S5PC110_GPIO_MP054,
S5PC110_GPIO_MP055,
S5PC110_GPIO_MP056,
S5PC110_GPIO_MP057,
S5PC110_GPIO_MP060,
S5PC110_GPIO_MP061,
S5PC110_GPIO_MP062,
S5PC110_GPIO_MP063,
S5PC110_GPIO_MP064,
S5PC110_GPIO_MP065,
S5PC110_GPIO_MP066,
S5PC110_GPIO_MP067,
S5PC110_GPIO_MP070,
S5PC110_GPIO_MP071,
S5PC110_GPIO_MP072,
S5PC110_GPIO_MP073,
S5PC110_GPIO_MP074,
S5PC110_GPIO_MP075,
S5PC110_GPIO_MP076,
S5PC110_GPIO_MP077,
S5PC110_GPIO_MP100,
S5PC110_GPIO_MP101,
S5PC110_GPIO_MP102,
S5PC110_GPIO_MP103,
S5PC110_GPIO_MP104,
S5PC110_GPIO_MP105,
S5PC110_GPIO_MP106,
S5PC110_GPIO_MP107,
S5PC110_GPIO_MP110,
S5PC110_GPIO_MP111,
S5PC110_GPIO_MP112,
S5PC110_GPIO_MP113,
S5PC110_GPIO_MP114,
S5PC110_GPIO_MP115,
S5PC110_GPIO_MP116,
S5PC110_GPIO_MP117,
S5PC110_GPIO_MP120,
S5PC110_GPIO_MP121,
S5PC110_GPIO_MP122,
S5PC110_GPIO_MP123,
S5PC110_GPIO_MP124,
S5PC110_GPIO_MP125,
S5PC110_GPIO_MP126,
S5PC110_GPIO_MP127,
S5PC110_GPIO_MP130,
S5PC110_GPIO_MP131,
S5PC110_GPIO_MP132,
S5PC110_GPIO_MP133,
S5PC110_GPIO_MP134,
S5PC110_GPIO_MP135,
S5PC110_GPIO_MP136,
S5PC110_GPIO_MP137,
S5PC110_GPIO_MP140,
S5PC110_GPIO_MP141,
S5PC110_GPIO_MP142,
S5PC110_GPIO_MP143,
S5PC110_GPIO_MP144,
S5PC110_GPIO_MP145,
S5PC110_GPIO_MP146,
S5PC110_GPIO_MP147,
S5PC110_GPIO_MP150,
S5PC110_GPIO_MP151,
S5PC110_GPIO_MP152,
S5PC110_GPIO_MP153,
S5PC110_GPIO_MP154,
S5PC110_GPIO_MP155,
S5PC110_GPIO_MP156,
S5PC110_GPIO_MP157,
S5PC110_GPIO_MP160,
S5PC110_GPIO_MP161,
S5PC110_GPIO_MP162,
S5PC110_GPIO_MP163,
S5PC110_GPIO_MP164,
S5PC110_GPIO_MP165,
S5PC110_GPIO_MP166,
S5PC110_GPIO_MP167,
S5PC110_GPIO_MP170,
S5PC110_GPIO_MP171,
S5PC110_GPIO_MP172,
S5PC110_GPIO_MP173,
S5PC110_GPIO_MP174,
S5PC110_GPIO_MP175,
S5PC110_GPIO_MP176,
S5PC110_GPIO_MP177,
S5PC110_GPIO_MP180,
S5PC110_GPIO_MP181,
S5PC110_GPIO_MP182,
S5PC110_GPIO_MP183,
S5PC110_GPIO_MP184,
S5PC110_GPIO_MP185,
S5PC110_GPIO_MP186,
S5PC110_GPIO_MP187,
S5PC110_GPIO_MP200,
S5PC110_GPIO_MP201,
S5PC110_GPIO_MP202,
S5PC110_GPIO_MP203,
S5PC110_GPIO_MP204,
S5PC110_GPIO_MP205,
S5PC110_GPIO_MP206,
S5PC110_GPIO_MP207,
S5PC110_GPIO_MP210,
S5PC110_GPIO_MP211,
S5PC110_GPIO_MP212,
S5PC110_GPIO_MP213,
S5PC110_GPIO_MP214,
S5PC110_GPIO_MP215,
S5PC110_GPIO_MP216,
S5PC110_GPIO_MP217,
S5PC110_GPIO_MP220,
S5PC110_GPIO_MP221,
S5PC110_GPIO_MP222,
S5PC110_GPIO_MP223,
S5PC110_GPIO_MP224,
S5PC110_GPIO_MP225,
S5PC110_GPIO_MP226,
S5PC110_GPIO_MP227,
S5PC110_GPIO_MP230,
S5PC110_GPIO_MP231,
S5PC110_GPIO_MP232,
S5PC110_GPIO_MP233,
S5PC110_GPIO_MP234,
S5PC110_GPIO_MP235,
S5PC110_GPIO_MP236,
S5PC110_GPIO_MP237,
S5PC110_GPIO_MP240,
S5PC110_GPIO_MP241,
S5PC110_GPIO_MP242,
S5PC110_GPIO_MP243,
S5PC110_GPIO_MP244,
S5PC110_GPIO_MP245,
S5PC110_GPIO_MP246,
S5PC110_GPIO_MP247,
S5PC110_GPIO_MP250,
S5PC110_GPIO_MP251,
S5PC110_GPIO_MP252,
S5PC110_GPIO_MP253,
S5PC110_GPIO_MP254,
S5PC110_GPIO_MP255,
S5PC110_GPIO_MP256,
S5PC110_GPIO_MP257,
S5PC110_GPIO_MP260,
S5PC110_GPIO_MP261,
S5PC110_GPIO_MP262,
S5PC110_GPIO_MP263,
S5PC110_GPIO_MP264,
S5PC110_GPIO_MP265,
S5PC110_GPIO_MP266,
S5PC110_GPIO_MP267,
S5PC110_GPIO_MP270,
S5PC110_GPIO_MP271,
S5PC110_GPIO_MP272,
S5PC110_GPIO_MP273,
S5PC110_GPIO_MP274,
S5PC110_GPIO_MP275,
S5PC110_GPIO_MP276,
S5PC110_GPIO_MP277,
S5PC110_GPIO_MP280,
S5PC110_GPIO_MP281,
S5PC110_GPIO_MP282,
S5PC110_GPIO_MP283,
S5PC110_GPIO_MP284,
S5PC110_GPIO_MP285,
S5PC110_GPIO_MP286,
S5PC110_GPIO_MP287,
S5PC110_GPIO_RES,
S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
S5PC110_GPIO_H01,
S5PC110_GPIO_H02,
S5PC110_GPIO_H03,
S5PC110_GPIO_H04,
S5PC110_GPIO_H05,
S5PC110_GPIO_H06,
S5PC110_GPIO_H07,
S5PC110_GPIO_H10,
S5PC110_GPIO_H11,
S5PC110_GPIO_H12,
S5PC110_GPIO_H13,
S5PC110_GPIO_H14,
S5PC110_GPIO_H15,
S5PC110_GPIO_H16,
S5PC110_GPIO_H17,
S5PC110_GPIO_H20,
S5PC110_GPIO_H21,
S5PC110_GPIO_H22,
S5PC110_GPIO_H23,
S5PC110_GPIO_H24,
S5PC110_GPIO_H25,
S5PC110_GPIO_H26,
S5PC110_GPIO_H27,
S5PC110_GPIO_H30,
S5PC110_GPIO_H31,
S5PC110_GPIO_H32,
S5PC110_GPIO_H33,
S5PC110_GPIO_H34,
S5PC110_GPIO_H35,
S5PC110_GPIO_H36,
S5PC110_GPIO_H37,
S5PC110_GPIO_MAX_PORT
};
struct gpio_info {
unsigned int reg_addr; /* Address of register for this part */
unsigned int max_gpio; /* Maximum GPIO in this part */
};
#define S5PC100_GPIO_NUM_PARTS 1
static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
{ S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
};
#define S5PC110_GPIO_NUM_PARTS 1
static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
{ S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
};
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_s5pc100())
return s5pc100_gpio_data;
else if (cpu_is_s5pc110())
return s5pc110_gpio_data;
return NULL;
}
static inline unsigned int get_bank_num(void)
{
if (cpu_is_s5pc100())
return S5PC100_GPIO_NUM_PARTS;
else if (cpu_is_s5pc110())
return S5PC110_GPIO_NUM_PARTS;
return 0;
}
/*
* This structure helps mapping symbolic GPIO names into indices from
* exynos5_gpio_pin/exynos5420_gpio_pin enums.
*
* By convention, symbolic GPIO name is defined as follows:
*
* g[p]<bank><set><bit>, where
* p is optional
* <bank> - a single character bank name, as defined by the SOC
* <set> - a single digit set number
* <bit> - bit number within the set (in 0..7 range).
*
* <set><bit> essentially form an octal number of the GPIO pin within the bank
* space. On the 5420 architecture some banks' sets do not start not from zero
* ('d' starts from 1 and 'j' starts from 4). To compensate for that and
* maintain flat number space withoout holes, those banks use offsets to be
* deducted from the pin number.
*/
struct gpio_name_num_table {
char bank; /* bank name symbol */
u8 bank_size; /* total number of pins in the bank */
char bank_offset; /* offset of the first bank's pin */
unsigned int base; /* index of the first bank's pin in the enum */
};
#define GPIO_PER_BANK 8
#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
static const struct gpio_name_num_table s5pc100_gpio_table[] = {
GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
{ 0 }
};
static const struct gpio_name_num_table s5pc110_gpio_table[] = {
GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
{ 0 }
};
/* functions */
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
int gpio_direction_output(unsigned gpio, int value);
int gpio_set_value(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
void gpio_set_rate(int gpio, int mode);
struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
int s5p_gpio_get_pin(unsigned gpio);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define S5P_GPIO_PART_SHIFT (24)
#define S5P_GPIO_PART_MASK (0xff)
#define S5P_GPIO_BANK_SHIFT (8)
#define S5P_GPIO_BANK_MASK (0xffff)
#define S5P_GPIO_PIN_MASK (0xff)
#define S5P_GPIO_SET_PART(x) \
(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
#define S5P_GPIO_GET_PART(x) \
(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
#define S5P_GPIO_SET_PIN(x) \
((x) & S5P_GPIO_PIN_MASK)
#define S5PC100_SET_BANK(bank) \
(((unsigned)&(((struct s5pc100_gpio *) \
S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define S5PC110_SET_BANK(bank) \
((((unsigned)&(((struct s5pc110_gpio *) \
S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
#define s5pc100_gpio_get(bank, pin) \
(S5P_GPIO_SET_PART(0) | \
S5PC100_SET_BANK(bank) | \
S5P_GPIO_SET_PIN(pin))
#define s5pc110_gpio_get(bank, pin) \
(S5P_GPIO_SET_PART(0) | \
S5PC110_SET_BANK(bank) | \
S5P_GPIO_SET_PIN(pin))
static inline unsigned int s5p_gpio_base(int nr)
{
return samsung_get_base_gpio();
}
#endif
/* Pin configurations */
#define GPIO_INPUT 0x0
#define GPIO_OUTPUT 0x1
#define GPIO_IRQ 0xf
#define GPIO_FUNC(x) (x)
#define S5P_GPIO_INPUT 0x0
#define S5P_GPIO_OUTPUT 0x1
#define S5P_GPIO_IRQ 0xf
#define S5P_GPIO_FUNC(x) (x)
/* Pull mode */
#define GPIO_PULL_NONE 0x0
#define GPIO_PULL_DOWN 0x1
#define GPIO_PULL_UP 0x2
#define S5P_GPIO_PULL_NONE 0x0
#define S5P_GPIO_PULL_DOWN 0x1
#define S5P_GPIO_PULL_UP 0x2
/* Drive Strength level */
#define GPIO_DRV_1X 0x0
#define GPIO_DRV_3X 0x1
#define GPIO_DRV_2X 0x2
#define GPIO_DRV_4X 0x3
#define GPIO_DRV_FAST 0x0
#define GPIO_DRV_SLOW 0x1
#define S5P_GPIO_DRV_1X 0x0
#define S5P_GPIO_DRV_3X 0x1
#define S5P_GPIO_DRV_2X 0x2
#define S5P_GPIO_DRV_4X 0x3
#define S5P_GPIO_DRV_FAST 0x0
#define S5P_GPIO_DRV_SLOW 0x1
#endif

20
arch/arm/include/asm/arch-tegra/gpio.h
View file

@ -14,11 +14,31 @@
#define GPIO_FULLPORT(x) ((x) >> 3)
#define GPIO_BIT(x) ((x) & 0x7)
enum tegra_gpio_init {
TEGRA_GPIO_INIT_IN,
TEGRA_GPIO_INIT_OUT0,
TEGRA_GPIO_INIT_OUT1,
};
struct tegra_gpio_config {
u32 gpio:16;
u32 init:2;
};
/*
* Tegra-specific GPIO API
*/
/**
* Configure a list of GPIOs
*
* @param config List of GPIO configurations
* @param len Number of config items in list
*/
void gpio_config_table(const struct tegra_gpio_config *config, int len);
void gpio_info(void);
#define gpio_status() gpio_info()
#endif /* TEGRA_GPIO_H_ */

5
arch/arm/include/asm/arch-tegra/pinmux.h
View file

@ -80,6 +80,11 @@ struct pmux_pingrp_config {
#endif
};
#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
void pinmux_set_tristate_input_clamping(void);
#endif
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);

2
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View file

@ -14,8 +14,6 @@
/* for mmc_config definition */
#include <mmc.h>
#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
#ifndef __ASSEMBLY__
struct tegra_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */

1
arch/arm/include/asm/arch-tegra114/pinmux.h
View file

@ -231,6 +231,7 @@ enum pmux_drvgrp {
};
enum pmux_func {
PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLDVFS,

1
arch/arm/include/asm/arch-tegra124/pinmux.h
View file

@ -247,6 +247,7 @@ enum pmux_drvgrp {
};
enum pmux_func {
PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,

1
arch/arm/include/asm/arch-tegra20/pinmux.h
View file

@ -166,6 +166,7 @@ enum pmux_pingrp {
* purely a convenience. The translation is done through a table search.
*/
enum pmux_func {
PMUX_FUNC_DEFAULT,
PMUX_FUNC_AHB_CLK,
PMUX_FUNC_APB_CLK,
PMUX_FUNC_AUDIO_SYNC,

1
arch/arm/include/asm/arch-tegra30/pinmux.h
View file

@ -306,6 +306,7 @@ enum pmux_drvgrp {
};
enum pmux_func {
PMUX_FUNC_DEFAULT,
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLK_12M_OUT,

5
arch/arm/include/asm/imx-common/iomux-v3.h
View file

@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
#if defined CONFIG_MX6SL
#define PAD_CTL_LVE (1 << 1)
#define PAD_CTL_LVE_BIT (1 << 22)
#endif
#elif defined(CONFIG_VF610)
#define PAD_MUX_MODE_SHIFT 20

24
arch/arm/include/asm/imx-common/video.h Normal file
View file

@ -0,0 +1,24 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_VIDEO_H_
#define __IMX_VIDEO_H_
#include <linux/fb.h>
#include <ipu_pixfmt.h>
struct display_info_t {
int bus;
int addr;
int pixfmt;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
};
#ifdef CONFIG_IMX_HDMI
extern int detect_hdmi(struct display_info_t const *dev);
#endif
#endif

2
arch/arm/lib/Makefile
View file

@ -11,7 +11,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
ifdef CONFIG_ARM64
obj-y += crt0_64.o
else
obj-y += crt0.o
obj-y += vectors.o crt0.o
endif
ifndef CONFIG_SPL_BUILD

13
arch/arm/lib/cache.c
View file

@ -12,16 +12,23 @@
void __flush_cache(unsigned long start, unsigned long size)
{
#if defined(CONFIG_ARM1136)
void arm1136_cache_flush(void);
arm1136_cache_flush();
#if !defined(CONFIG_SYS_ICACHE_OFF)
asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
#endif
#if !defined(CONFIG_SYS_DCACHE_OFF)
asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
#endif
#endif /* CONFIG_ARM1136 */
#ifdef CONFIG_ARM926EJS
/* test and clean, page 2-23 of arm926ejs manual */
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
#endif
#endif /* CONFIG_ARM926EJS */
return;
}
void flush_cache(unsigned long start, unsigned long size)

291
arch/arm/lib/vectors.S Normal file
View file

@ -0,0 +1,291 @@
/*
* vectors - Generic ARM exception table code
*
* Copyright (c) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (c) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (c) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
*************************************************************************
*
* Symbol _start is referenced elsewhere, so make it global
*
*************************************************************************
*/
.globl _start
/*
*************************************************************************
*
* Vectors have their own section so linker script can map them easily
*
*************************************************************************
*/
.section ".vectors", "x"
/*
*************************************************************************
*
* Exception vectors as described in ARM reference manuals
*
* Uses indirect branch to allow reaching handlers anywhere in memory.
*
*************************************************************************
*/
_start:
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word CONFIG_SYS_DV_NOR_BOOT_CFG
#endif
_start:
ldr pc, _reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
/*
*************************************************************************
*
* Indirect vectors table
*
* Symbols referenced here must be defined somewhere else
*
*************************************************************************
*/
.globl _undefined_instruction
.globl _software_interrupt
.globl _prefetch_abort
.globl _data_abort
.globl _not_used
.globl _irq
.globl _fiq
_reset: .word reset
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
/* SPL interrupt handling: just hang */
#ifdef CONFIG_SPL_BUILD
.align 5
undefined_instruction:
software_interrupt:
prefetch_abort:
data_abort:
not_used:
irq:
fiq:
1:
bl 1b /* hang and never return */
#else /* !CONFIG_SPL_BUILD */
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif /* CONFIG_USE_IRQ */
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, IRQ_STACK_START_IN
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp @ save current stack into r0 (param register)
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
str lr, [r13, #4] @ save spsr in position 1 of saved stack
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13 @ switch modes, make sure moves will execute
mov lr, pc @ capture return pc
movs pc, lr @ jump to next instruction & switch modes.
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif /* CONFIG_USE_IRQ */
#endif /* CONFIG_SPL_BUILD */

69
board/boundary/nitrogen6x/nitrogen6x.c
View file

@ -19,13 +19,12 @@
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <i2c.h>
@ -331,7 +330,7 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
@ -446,22 +445,6 @@ static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
};
struct display_info_t {
int bus;
int addr;
int pixfmt;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
};
static int detect_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
}
static void do_enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
@ -492,7 +475,7 @@ static void enable_rgb(struct display_info_t const *dev)
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
static struct display_info_t const displays[] = {{
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
@ -573,51 +556,7 @@ static struct display_info_t const displays[] = {{
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
struct display_info_t const *dev = displays+i;
if (dev->detect(dev)) {
panel = dev->mode.name;
printf("auto-detected panel %s\n", panel);
break;
}
}
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
i = 0;
}
} else {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < ARRAY_SIZE(displays)) {
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else {
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
}
} else {
printf("unsupported panel %s\n", panel);
ret = -EINVAL;
}
return (0 != ret);
}
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{

1
board/compulab/cm_t335/u-boot.lds
View file

@ -18,6 +18,7 @@ SECTIONS
.text :
{
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
board/compulab/cm_t335/built-in.o (.text*)
*(.text*)

9
board/embest/mx6boards/Makefile Normal file
View file

@ -0,0 +1,9 @@
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := mx6boards.o

601
board/embest/mx6boards/mx6boards.c Normal file
View file

@ -0,0 +1,601 @@
/*
* Copyright (C) 2014 Eukréa Electromatique
* Author: Eric Bénard <eric@eukrea.com>
* Fabio Estevam <fabio.estevam@freescale.com>
* Jon Nettleton <jon.nettleton@gmail.com>
*
* based on sabresd.c which is :
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* and on hummingboard.c which is :
* Copyright (C) 2013 SolidRun ltd.
* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/video.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
static int board_type = -1;
#define BOARD_IS_MARSBOARD 0
#define BOARD_IS_RIOTBOARD 1
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* GPIO16 -> AR8035 25MHz */
MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* AR8035 PHY Reset */
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* AR8035 PHY Interrupt */
MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset AR8035 PHY */
gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(3, 31), 1);
}
int mx6_rgmii_rework(struct phy_device *phydev)
{
/* from linux/arch/arm/mach-imx/mach-imx6q.c :
* Ar803x phy SmartEEE feature cause link status generates glitch,
* which cause ethernet link down/up issue, so disable SmartEEE
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
mx6_rgmii_rework(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* eMMC RST */
MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC3_BASE_ADDR:
if (board_type == BOARD_IS_RIOTBOARD)
ret = !gpio_get_value(USDHC3_CD_GPIO);
else if (board_type == BOARD_IS_MARSBOARD)
ret = 1; /* eMMC/uSDHC3 is always present */
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int i;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* ** RiOTboard :
* mmc0 SDCard slot (bottom)
* mmc1 uSDCard slot (top)
* mmc2 eMMC
* ** MarSBoard :
* mmc0 uSDCard slot (bottom)
* mmc1 eMMC
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[0].max_bus_width = 4;
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
if (board_type == BOARD_IS_RIOTBOARD) {
imx_iomux_v3_setup_multiple_pads(
riotboard_usdhc3_pads,
ARRAY_SIZE(riotboard_usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
udelay(250);
gpio_set_value(IMX_GPIO_NR(7, 8), 1);
}
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].max_bus_width = 4;
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[2].max_bus_width = 4;
gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
udelay(250);
gpio_set_value(IMX_GPIO_NR(6, 8), 1);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
}
return status;
}
#endif
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(5, 26)
}
};
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(4, 13)
}
};
struct i2c_pads_info i2c_pad_info3 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(1, 6)
}
};
iomux_v3_cfg_t const tft_pads_riot[] = {
/* LCD_PWR_EN */
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* TOUCH_INT */
MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED_PWR_EN */
MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* BL LEVEL */
MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const tft_pads_mars[] = {
/* LCD_PWR_EN */
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* TOUCH_INT */
MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LED_PWR_EN */
MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* BL LEVEL (PWM4) */
MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#if defined(CONFIG_VIDEO_IPUV3)
static void enable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
setbits_le32(&iomux->gpr[2],
IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
/* set backlight level to ON */
if (board_type == BOARD_IS_RIOTBOARD)
gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
else if (board_type == BOARD_IS_MARSBOARD)
gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
}
static void disable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set backlight level to OFF */
if (board_type == BOARD_IS_RIOTBOARD)
gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
else if (board_type == BOARD_IS_MARSBOARD)
gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
clrbits_le32(&iomux->gpr[2],
IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
}
static void do_enable_hdmi(struct display_info_t const *dev)
{
disable_lvds(dev);
imx_enable_hdmi_phy();
}
static int detect_i2c(struct display_info_t const *dev)
{
return (0 == i2c_set_bus_num(dev->bus)) &&
(0 == i2c_probe(dev->addr));
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x1,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = detect_i2c,
.enable = enable_lvds,
.mode = {
.name = "LCD8000-97C",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 100,
.right_margin = 200,
.upper_margin = 10,
.lower_margin = 20,
.hsync_len = 20,
.vsync_len = 8,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0, IPU,IPU DI0 clocks */
setbits_le32(&mxc_ccm->CCGR3,
MXC_CCM_CCGR3_LDB_DI0_MASK);
/* set LDB0 clk select to 011/011 */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
setbits_le32(&mxc_ccm->cscmr2,
MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
setbits_le32(&mxc_ccm->chsccdr,
(CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
| IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
writel(reg, &iomux->gpr[2]);
clrsetbits_le32(&iomux->gpr[3],
IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
}
#endif /* CONFIG_VIDEO_IPUV3 */
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
u32 cputype = cpu_type(get_cpu_rev());
switch (cputype) {
case MXC_CPU_MX6SOLO:
board_type = BOARD_IS_RIOTBOARD;
break;
case MXC_CPU_MX6D:
board_type = BOARD_IS_MARSBOARD;
break;
}
setup_iomux_uart();
if (board_type == BOARD_IS_RIOTBOARD)
imx_iomux_v3_setup_multiple_pads(
tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
else if (board_type == BOARD_IS_MARSBOARD)
imx_iomux_v3_setup_multiple_pads(
tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
#if defined(CONFIG_VIDEO_IPUV3)
/* power ON LCD */
gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
/* touch interrupt is an input */
gpio_direction_input(IMX_GPIO_NR(6, 14));
/* power ON backlight */
gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
/* set backlight level to off */
if (board_type == BOARD_IS_RIOTBOARD)
gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
else if (board_type == BOARD_IS_MARSBOARD)
gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
setup_display();
#endif
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
/* i2c2 : HDMI EDID */
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
/* i2c3 : LVDS, Expansion connector */
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode riotboard_boot_modes[] = {
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
static const struct boot_mode marsboard_boot_modes[] = {
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
if (board_type == BOARD_IS_RIOTBOARD)
add_board_boot_modes(riotboard_boot_modes);
else if (board_type == BOARD_IS_RIOTBOARD)
add_board_boot_modes(marsboard_boot_modes);
#endif
return 0;
}
int checkboard(void)
{
puts("Board: ");
if (board_type == BOARD_IS_MARSBOARD)
puts("MarSBoard\n");
else if (board_type == BOARD_IS_RIOTBOARD)
puts("RIoTboard\n");
else
printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
return 0;
}

1
board/freescale/mx31ads/u-boot.lds
View file

@ -22,6 +22,7 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
* (.vectors)
arch/arm/cpu/arm1136/start.o (.text*)
board/freescale/mx31ads/built-in.o (.text*)
arch/arm/lib/built-in.o (.text*)

67
board/freescale/mx6sabresd/mx6sabresd.c
View file

@ -14,14 +14,13 @@
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@ -265,22 +264,6 @@ int board_phy_config(struct phy_device *phydev)
}
#if defined(CONFIG_VIDEO_IPUV3)
struct display_info_t {
int bus;
int addr;
int pixfmt;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
};
static int detect_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
}
static void disable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -309,7 +292,7 @@ static void enable_lvds(struct display_info_t const *dev)
writel(reg, &iomux->gpr[2]);
}
static struct display_info_t const displays[] = {{
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB666,
@ -350,51 +333,7 @@ static struct display_info_t const displays[] = {{
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
struct display_info_t const *dev = displays+i;
if (dev->detect && dev->detect(dev)) {
panel = dev->mode.name;
printf("auto-detected panel %s\n", panel);
break;
}
}
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
i = 0;
}
} else {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < ARRAY_SIZE(displays)) {
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
} else {
printf("unsupported panel %s\n", panel);
return -EINVAL;
}
return 0;
}
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{

20
board/freescale/mx6slevk/mx6slevk.c
View file

@ -34,6 +34,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
int dram_init(void)
@ -71,6 +74,20 @@ static iomux_v3_cfg_t const fec_pads[] = {
MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_MXC_SPI
static iomux_v3_cfg_t ecspi1_pads[] = {
MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@ -132,6 +149,9 @@ static int setup_fec(void)
int board_early_init_f(void)
{
setup_iomux_uart();
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
return 0;
}

215
board/gateworks/gw_ventana/gw_ventana.c
View file

@ -12,6 +12,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
@ -19,6 +20,7 @@
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/video.h>
#include <jffs2/load_kernel.h>
#include <hwconfig.h>
#include <i2c.h>
@ -30,8 +32,8 @@
#include <mtd_node.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/ltc3676_pmic.h>
#include <power/pfuze100_pmic.h>
#include <i2c.h>
#include <fdt_support.h>
#include <jffs2/load_kernel.h>
#include <spi_flash.h>
@ -369,6 +371,134 @@ int board_eth_init(bd_t *bis)
return 0;
}
#if defined(CONFIG_VIDEO_IPUV3)
static void enable_hdmi(struct display_info_t const *dev)
{
imx_enable_hdmi_phy();
}
static int detect_i2c(struct display_info_t const *dev)
{
return i2c_set_bus_num(dev->bus) == 0 &&
i2c_probe(dev->addr) == 0;
}
static void enable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
MUX_PAD_CTRL(NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
}
struct display_info_t const displays[] = {{
/* HDMI Output */
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
.bus = 2,
.addr = 0x4,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = detect_i2c,
.enable = enable_lvds,
.mode = {
.name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
/* set LDB0, LDB1 clk select to 011/011 */
reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cs2cdr);
reg = readl(&mxc_ccm->cscmr2);
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
writel(reg, &iomux->gpr[2]);
reg = readl(&iomux->gpr[3]);
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
/* Backlight CABEN on LVDS connector */
imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
MUX_PAD_CTRL(NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
/* read ventana EEPROM, check for validity, and return baseboard type */
static int
read_eeprom(void)
@ -733,6 +863,62 @@ struct ventana gpio_cfg[] = {
},
};
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
u32 reg;
/* configure PFUZE100 PMIC */
if (board_type == GW54xx || board_type == GW54proto) {
power_pfuze100_init(I2C_PMIC);
p = pmic_get("PFUZE100_PMIC");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set VGEN1 to 1.5V and enable */
pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
reg &= ~(LDO_VOL_MASK);
reg |= (LDOA_1_50V | LDO_EN);
pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
/* Set SWBST to 5.0V and enable */
pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
}
}
/* configure LTC3676 PMIC */
else {
power_ltc3676_init(I2C_PMIC);
p = pmic_get("LTC3676_PMIC");
if (p && !pmic_probe(p)) {
puts("PMIC: LTC3676\n");
/* set board-specific scalar to 1225mV for IMX6Q@1GHz */
if (is_cpu_type(MXC_CPU_MX6Q)) {
/* mask PGOOD during SW1 transition */
reg = 0x1d | LTC3676_PGOOD_MASK;
pmic_reg_write(p, LTC3676_DVB1B, reg);
/* set SW1 (VDD_SOC) to 1259mV */
reg = 0x1d;
pmic_reg_write(p, LTC3676_DVB1A, reg);
/* mask PGOOD during SW3 transition */
reg = 0x1d | LTC3676_PGOOD_MASK;
pmic_reg_write(p, LTC3676_DVB3B, reg);
/*set SW3 (VDD_ARM) to 1259mV */
reg = 0x1d;
pmic_reg_write(p, LTC3676_DVB3A, reg);
}
}
}
return 0;
}
/* setup GPIO pinmux and default configuration per baseboard */
static void setup_board_gpio(int board)
{
@ -888,6 +1074,9 @@ int board_early_init_f(void)
setup_iomux_uart();
gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
return 0;
}
@ -1076,28 +1265,6 @@ int misc_init_r(void)
setenv("serial#", str);
}
/* configure PFUZE100 PMIC (not used on all Ventana baseboards) */
if ((board_type == GW54xx || board_type == GW54proto) &&
!pmic_init(I2C_PMIC)) {
struct pmic *p = pmic_get("PFUZE100_PMIC");
u32 reg;
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set VGEN1 to 1.5V and enable */
pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
reg &= ~(LDO_VOL_MASK);
reg |= (LDOA_1_50V | LDO_EN);
pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
/* Set SWBST to 5.0V and enable */
pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
}
}
/* setup baseboard specific GPIO pinmux and config */
setup_board_gpio(board_type);
@ -1243,7 +1410,7 @@ void ft_board_setup(void *blob, bd_t *bd)
/* board serial number */
fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
strlen(getenv("serial#") + 1));
strlen(getenv("serial#")) + 1);
/* board (model contains model from device-tree) */
fdt_setprop(blob, 0, "board", info->model,

14
board/gateworks/gw_ventana/ventana_eeprom.h
View file

@ -16,16 +16,16 @@ struct ventana_board_info {
u8 mfgdate[4]; /* 0x20: MFG date (read only) */
u8 res2[7]; /* 0x24 */
/* sdram config */
u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */
u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */
u8 sdram_width; /* 0x2D: enum (32,64) bit */
u8 sdram_size; /* 0x2B: (16 << n) MB */
u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
u8 sdram_width; /* 0x2D: (8 << n) bit */
/* cpu config */
u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */
u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */
u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */
u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */
u8 model[16]; /* 0x30: model string */
/* FLASH config */
u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */
u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */
u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */
u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */
/* Config1: SoC Peripherals */
u8 config[8]; /* 0x42: loading options */

13
board/gumstix/pepper/Makefile Normal file
View file

@ -0,0 +1,13 @@
#
# Makefile
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += mux.o
endif
obj-y += board.o

226
board/gumstix/pepper/board.c Normal file
View file

@ -0,0 +1,226 @@
/*
* Board functions for Gumstix Pepper and AM335x-based boards
*
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
* Based on board/ti/am335x/board.c from Texas Instruments, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <environment.h>
#include <watchdog.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
(MT47H128M16RT25E_RD_DQS<<20) |
(MT47H128M16RT25E_RD_DQS<<10) |
(MT47H128M16RT25E_RD_DQS<<0)),
.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
(MT47H128M16RT25E_WR_DQS<<20) |
(MT47H128M16RT25E_WR_DQS<<10) |
(MT47H128M16RT25E_WR_DQS<<0)),
.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
(MT47H128M16RT25E_PHY_WRLVL<<20) |
(MT47H128M16RT25E_PHY_WRLVL<<10) |
(MT47H128M16RT25E_PHY_WRLVL<<0)),
.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
(MT47H128M16RT25E_PHY_GATELVL<<20) |
(MT47H128M16RT25E_PHY_GATELVL<<10) |
(MT47H128M16RT25E_PHY_GATELVL<<0)),
.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
(MT47H128M16RT25E_PHY_FIFO_WE<<20) |
(MT47H128M16RT25E_PHY_FIFO_WE<<10) |
(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
return serial_tstc() && serial_getc() == 'c';
}
#endif
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr;
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
const struct ctrl_ioregs ioregs = {
.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
};
void sdram_init(void)
{
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;
}
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
const char *devname;
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
/*
*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the KSZ9021 PHY. Since we only support a single ethernet
* device in U-Boot, we only do this for the current instance.
*/
devname = miiphy_get_current_dev();
/* max rx/tx clock delay, min rx/tx control delay */
miiphy_write(devname, 0x0, 0x0b, 0x8104);
miiphy_write(devname, 0x0, 0xc, 0xa0a0);
/* min rx data delay */
miiphy_write(devname, 0x0, 0x0b, 0x8105);
miiphy_write(devname, 0x0, 0x0c, 0x0000);
/* min tx data delay */
miiphy_write(devname, 0x0, 0x0b, 0x8106);
miiphy_write(devname, 0x0, 0x0c, 0x0000);
return n;
}
#endif

19
board/gumstix/pepper/board.h Normal file
View file

@ -0,0 +1,19 @@
/*
* Gumstix Pepper and AM335x-based boards information header
*
* Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* We must be able to enable uart0, for initial output. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
#endif

78
board/gumstix/pepper/mux.c Normal file
View file

@ -0,0 +1,78 @@
/*
* Muxing for Gumstix Pepper and AM335x-based boards
*
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
/* I2C_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
{OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
{OFFSET(xdma_event_intr1), MODE(3)},
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
/*
* Do board-specific muxes.
*/
void enable_board_pin_mux(void)
{
/* I2C0 */
configure_module_pin_mux(i2c0_pin_mux);
/* SD Card */
configure_module_pin_mux(mmc0_pin_mux);
/* Ethernet pinmux. */
configure_module_pin_mux(rgmii1_pin_mux);
}

6
board/nvidia/jetson-tk1/jetson-tk1.c
View file

@ -6,6 +6,7 @@
*/
#include <common.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-jetson-tk1.h"
@ -15,6 +16,11 @@
*/
void pinmux_init(void)
{
pinmux_set_tristate_input_clamping();
gpio_config_table(jetson_tk1_gpio_inits,
ARRAY_SIZE(jetson_tk1_gpio_inits));
pinmux_config_pingrp_table(jetson_tk1_pingrps,
ARRAY_SIZE(jetson_tk1_pingrps));

256
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
View file

@ -7,6 +7,98 @@
#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
#define _PINMUX_CONFIG_JETSON_TK1_H_
#define GPIO_INIT(_gpio, _init) \
{ \
.gpio = GPIO_P##_gpio, \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
/* gpio, init_val */
GPIO_INIT(C7, IN),
GPIO_INIT(G0, OUT0),
GPIO_INIT(G1, OUT0),
GPIO_INIT(G2, IN),
GPIO_INIT(G3, IN),
GPIO_INIT(H2, OUT0),
GPIO_INIT(H3, OUT0),
GPIO_INIT(H4, IN),
GPIO_INIT(H5, OUT0),
GPIO_INIT(H6, IN),
GPIO_INIT(H7, OUT0),
GPIO_INIT(I0, OUT0),
GPIO_INIT(I2, OUT0),
GPIO_INIT(I4, OUT0),
GPIO_INIT(I5, IN),
GPIO_INIT(I6, IN),
GPIO_INIT(J0, IN),
GPIO_INIT(J2, IN),
GPIO_INIT(K1, OUT0),
GPIO_INIT(K2, IN),
GPIO_INIT(K3, IN),
GPIO_INIT(K4, OUT0),
GPIO_INIT(K5, OUT0),
GPIO_INIT(K6, OUT0),
GPIO_INIT(N7, IN),
GPIO_INIT(O0, IN),
GPIO_INIT(O1, IN),
GPIO_INIT(O2, IN),
GPIO_INIT(O3, IN),
GPIO_INIT(O4, IN),
GPIO_INIT(O5, IN),
GPIO_INIT(O6, OUT0),
GPIO_INIT(O7, IN),
GPIO_INIT(P0, OUT0),
GPIO_INIT(P1, OUT0),
GPIO_INIT(P2, OUT0),
GPIO_INIT(Q0, IN),
GPIO_INIT(Q1, IN),
GPIO_INIT(Q2, IN),
GPIO_INIT(Q5, IN),
GPIO_INIT(Q6, IN),
GPIO_INIT(Q7, IN),
GPIO_INIT(R0, OUT0),
GPIO_INIT(R1, OUT0),
GPIO_INIT(R2, OUT0),
GPIO_INIT(R4, IN),
GPIO_INIT(R5, OUT0),
GPIO_INIT(R7, IN),
GPIO_INIT(S0, IN),
GPIO_INIT(S3, OUT0),
GPIO_INIT(S4, OUT0),
GPIO_INIT(S5, IN),
GPIO_INIT(S6, OUT0),
GPIO_INIT(T0, OUT0),
GPIO_INIT(T1, OUT0),
GPIO_INIT(U0, OUT0),
GPIO_INIT(U1, IN),
GPIO_INIT(U2, IN),
GPIO_INIT(U3, OUT0),
GPIO_INIT(U4, OUT0),
GPIO_INIT(U5, IN),
GPIO_INIT(U6, IN),
GPIO_INIT(V0, IN),
GPIO_INIT(V1, IN),
GPIO_INIT(W2, IN),
GPIO_INIT(W3, IN),
GPIO_INIT(X1, OUT0),
GPIO_INIT(X3, IN),
GPIO_INIT(X4, OUT0),
GPIO_INIT(X5, IN),
GPIO_INIT(X6, IN),
GPIO_INIT(X7, OUT0),
GPIO_INIT(BB3, OUT0),
GPIO_INIT(BB5, OUT0),
GPIO_INIT(BB6, OUT0),
GPIO_INIT(BB7, OUT0),
GPIO_INIT(CC1, IN),
GPIO_INIT(CC2, IN),
GPIO_INIT(CC5, OUT0),
GPIO_INIT(EE1, OUT0),
GPIO_INIT(FF1, OUT0),
GPIO_INIT(FF2, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
@ -41,43 +133,43 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PC7, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG1, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG3, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH2, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH4, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH7, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI6, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK1, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK3, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_OUT_PK5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
@ -85,79 +177,79 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA1_PO2, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA2_PO3, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA3_PO4, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA6_PO7, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DOUT_PP2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL0_PQ0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL1_PQ1, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL2_PQ2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL5_PQ5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL6_PQ6, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL7_PQ7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW4_PR4, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW5_PR5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW7_PR7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW8_PS0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW12_PS4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW13_PS5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW14_PS6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU1, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU5, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU6, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV1, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(GPIO_W2_AUD_PW2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X1_AUD_PX1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X3_AUD_PX3, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X4_AUD_PX4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X5_AUD_PX5, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X6_AUD_PX6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X7_AUD_PX7, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
@ -181,25 +273,25 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PCC1, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PCC2, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_REQ_PEE1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PFF2, RSVD2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),

563
board/nvidia/venice2/pinmux-config-venice2.h
View file

@ -1,6 +1,5 @@
/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -8,69 +7,280 @@
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
#define GPIO_INIT(_gpio, _init) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.od = PMUX_PIN_OD_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
.gpio = GPIO_P##_gpio, \
.init = TEGRA_GPIO_INIT_##_init, \
}
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
static const struct tegra_gpio_config venice2_gpio_inits[] = {
/* gpio, init_val */
GPIO_INIT(A0, IN),
GPIO_INIT(C7, IN),
GPIO_INIT(G0, IN),
GPIO_INIT(G1, IN),
GPIO_INIT(G2, IN),
GPIO_INIT(G3, IN),
GPIO_INIT(H2, IN),
GPIO_INIT(H4, IN),
GPIO_INIT(H5, OUT0),
GPIO_INIT(H6, IN),
GPIO_INIT(H7, OUT1),
GPIO_INIT(I0, IN),
GPIO_INIT(I1, IN),
GPIO_INIT(I2, OUT0),
GPIO_INIT(I4, OUT0),
GPIO_INIT(I5, OUT1),
GPIO_INIT(I6, IN),
GPIO_INIT(J0, IN),
GPIO_INIT(J7, IN),
GPIO_INIT(K0, IN),
GPIO_INIT(K1, OUT0),
GPIO_INIT(K2, IN),
GPIO_INIT(K3, IN),
GPIO_INIT(K4, OUT0),
GPIO_INIT(K6, OUT0),
GPIO_INIT(K7, IN),
GPIO_INIT(N7, IN),
GPIO_INIT(O2, IN),
GPIO_INIT(O5, IN),
GPIO_INIT(O6, OUT0),
GPIO_INIT(O7, IN),
GPIO_INIT(P2, OUT0),
GPIO_INIT(Q0, IN),
GPIO_INIT(Q2, IN),
GPIO_INIT(Q3, IN),
GPIO_INIT(Q6, IN),
GPIO_INIT(Q7, IN),
GPIO_INIT(R0, OUT0),
GPIO_INIT(R1, IN),
GPIO_INIT(R4, IN),
GPIO_INIT(S0, IN),
GPIO_INIT(S3, OUT0),
GPIO_INIT(S4, OUT0),
GPIO_INIT(S7, IN),
GPIO_INIT(T1, IN),
GPIO_INIT(U4, IN),
GPIO_INIT(U5, IN),
GPIO_INIT(U6, IN),
GPIO_INIT(V0, IN),
GPIO_INIT(V1, IN),
GPIO_INIT(W3, IN),
GPIO_INIT(X1, IN),
GPIO_INIT(X3, IN),
GPIO_INIT(X4, IN),
GPIO_INIT(X7, OUT0),
GPIO_INIT(CC5, OUT0),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.od = PMUX_PIN_OD_##_od, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.od = PMUX_PIN_OD_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
static const struct pmux_pingrp_config venice2_pingrps[] = {
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
};
#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.od = PMUX_PIN_OD_##_od, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define USB_PINMUX CEC_PINMUX
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
@ -82,258 +292,7 @@
.hsm = PMUX_HSM_##_hsm, \
}
static struct pmux_pingrp_config tegra124_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
/* I2S0 pinmux */
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
/* I2S1 pinmux */
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
/* I2S3 pinmux */
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
/* CLDVFS pinmux */
DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
/* ULPI pinmux */
DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
/* EC KBC/SPI */
DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
/* I2C3 (TPM) pinmux */
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* I2C2 pinmux */
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTD pinmux (UART4 on Servo board, unused) */
DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT),
/* SPI4 (Winbond 'boot ROM') */
DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT),
/* Touch IRQ */
DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT),
/* PWM1 pinmux */
DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT),
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
/* SDMMC4 pinmux */
DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
/* BLINK pinmux */
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
/* KBC pinmux */
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
/* Misc */
DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT),
/* I2CPWR pinmux (I2C5) */
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
/* CLK pinmux */
DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
/* PWRON pinmux */
DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
/* CPU pinmux */
DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
/* PMI pinmux */
DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
/* RESET_OUT_N pinmux */
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
/* EXTPERIPH3 pinmux */
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* UARTB, GPS */
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
/* UARTC (WIFI/BT) */
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
/* CEC pinmux */
CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C4 (HDMI_DDC) pinmux */
DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
/* USB pinmux */
USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* Unused, marked SNN_ on schematic, TRISTATE 'em */
DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT),
static const struct pmux_drvgrp_config venice2_drvgrps[] = {
};
static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
/* EN_VDD_BL */
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
/* MODEM */
DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
/* BOOT_SEL0-3 */
DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
/* TS_SHDN_L */
DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT),
};
static struct pmux_drvgrp_config venice2_padctrl[] = {
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};
#endif /* PINMUX_CONFIG_VENICE2_H */

19
board/nvidia/venice2/venice2.c
View file

@ -6,12 +6,9 @@
*/
#include <common.h>
#include <asm-generic/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-venice2.h"
#include <i2c.h>
/*
* Routine: pinmux_init
@ -19,16 +16,14 @@
*/
void pinmux_init(void)
{
pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
ARRAY_SIZE(tegra124_pinmux_set_nontristate));
pinmux_set_tristate_input_clamping();
pinmux_config_pingrp_table(tegra124_pinmux_common,
ARRAY_SIZE(tegra124_pinmux_common));
gpio_config_table(venice2_gpio_inits,
ARRAY_SIZE(venice2_gpio_inits));
pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
pinmux_config_pingrp_table(venice2_pingrps,
ARRAY_SIZE(venice2_pingrps));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
pinmux_config_drvgrp_table(venice2_padctrl,
ARRAY_SIZE(venice2_padctrl));
pinmux_config_drvgrp_table(venice2_drvgrps,
ARRAY_SIZE(venice2_drvgrps));
}

194
board/renesas/koelsch/koelsch.c
View file

@ -19,186 +19,28 @@
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
#define s_init_wait(cnt) \
({ \
u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
#define dbpdrgd_check(bsc) \
({ \
while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
; \
})
#if defined(CONFIG_NORFLASH)
static void bsc_init(void)
{
struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
/* LBSC */
writel(0x00000020, &lbsc->cs0ctrl);
writel(0x00000020, &lbsc->cs1ctrl);
writel(0x00002020, &lbsc->ecs0ctrl);
writel(0x00002020, &lbsc->ecs1ctrl);
writel(0x077F077F, &lbsc->cswcr0);
writel(0x077F077F, &lbsc->cswcr1);
writel(0x077F077F, &lbsc->ecswcr0);
writel(0x077F077F, &lbsc->ecswcr1);
/* DBSC3 */
s_init_wait(10);
writel(0x0000A55A, &dbsc3_0->dbpdlck);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x80000000, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000006, &dbsc3_0->dbpdrga);
writel(0x0001C000, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FD2480, &dbsc3_0->dbpdrgd);
writel(0x00000010, &dbsc3_0->dbpdrga);
writel(0xF004649B, &dbsc3_0->dbpdrgd);
writel(0x0000000F, &dbsc3_0->dbpdrga);
writel(0x00181EE4, &dbsc3_0->dbpdrgd);
writel(0x0000000E, &dbsc3_0->dbpdrga);
writel(0x33C03812, &dbsc3_0->dbpdrgd);
writel(0x00000003, &dbsc3_0->dbpdrga);
writel(0x0300C481, &dbsc3_0->dbpdrgd);
writel(0x00000007, &dbsc3_0->dbkind);
writel(0x10030A02, &dbsc3_0->dbconf0);
writel(0x00000001, &dbsc3_0->dbphytype);
writel(0x00000000, &dbsc3_0->dbbl);
writel(0x0000000B, &dbsc3_0->dbtr0);
writel(0x00000008, &dbsc3_0->dbtr1);
writel(0x00000000, &dbsc3_0->dbtr2);
writel(0x0000000B, &dbsc3_0->dbtr3);
writel(0x000C000B, &dbsc3_0->dbtr4);
writel(0x00000027, &dbsc3_0->dbtr5);
writel(0x0000001C, &dbsc3_0->dbtr6);
writel(0x00000005, &dbsc3_0->dbtr7);
writel(0x00000018, &dbsc3_0->dbtr8);
writel(0x00000008, &dbsc3_0->dbtr9);
writel(0x0000000C, &dbsc3_0->dbtr10);
writel(0x00000009, &dbsc3_0->dbtr11);
writel(0x00000012, &dbsc3_0->dbtr12);
writel(0x000000D0, &dbsc3_0->dbtr13);
writel(0x00140005, &dbsc3_0->dbtr14);
writel(0x00050004, &dbsc3_0->dbtr15);
writel(0x70233005, &dbsc3_0->dbtr16);
writel(0x000C0000, &dbsc3_0->dbtr17);
writel(0x00000300, &dbsc3_0->dbtr18);
writel(0x00000040, &dbsc3_0->dbtr19);
writel(0x00000001, &dbsc3_0->dbrnk0);
writel(0x00020001, &dbsc3_0->dbadj0);
writel(0x20082008, &dbsc3_0->dbadj2);
writel(0x00020002, &dbsc3_0->dbwt0cnf0);
writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
writel(0x00000015, &dbsc3_0->dbpdrga);
writel(0x00000D70, &dbsc3_0->dbpdrgd);
writel(0x00000016, &dbsc3_0->dbpdrga);
writel(0x00000006, &dbsc3_0->dbpdrgd);
writel(0x00000017, &dbsc3_0->dbpdrga);
writel(0x00000018, &dbsc3_0->dbpdrgd);
writel(0x00000012, &dbsc3_0->dbpdrga);
writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
writel(0x00000013, &dbsc3_0->dbpdrga);
writel(0x1A868300, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
writel(0x00000014, &dbsc3_0->dbpdrga);
writel(0x300214D8, &dbsc3_0->dbpdrgd);
writel(0x0000001A, &dbsc3_0->dbpdrga);
writel(0x930035C7, &dbsc3_0->dbpdrgd);
writel(0x00000060, &dbsc3_0->dbpdrga);
writel(0x330657B2, &dbsc3_0->dbpdrgd);
writel(0x00000011, &dbsc3_0->dbpdrga);
writel(0x1000040B, &dbsc3_0->dbpdrgd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000071, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x2100FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x110000DB, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000181, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x0000FE01, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000000, &dbsc3_0->dbbs0cnt1);
writel(0x01004C20, &dbsc3_0->dbcalcnf);
writel(0x014000AA, &dbsc3_0->dbcaltr);
writel(0x00000140, &dbsc3_0->dbrfcnf0);
writel(0x00081860, &dbsc3_0->dbrfcnf1);
writel(0x00010000, &dbsc3_0->dbrfcnf2);
writel(0x00000001, &dbsc3_0->dbrfen);
writel(0x00000001, &dbsc3_0->dbacen);
}
#else
#define bsc_init() do {} while (0)
#endif /* CONFIG_NORFLASH */
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.5GHz */
stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS */
qos_init();
/* BSC */
bsc_init();
}
#define MSTPSR1 0xE6150038
@ -213,18 +55,6 @@ void s_init(void)
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
#define set_guard_reg(addr, mask, value) \
{ \
u32 val; \
val = (readl(addr) & ~(mask)) | (value); \
writel(~val, PMMR); \
writel(val, addr); \
}
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
@ -238,13 +68,7 @@ int board_early_init_f(void)
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
#if defined(CONFIG_NORFLASH)
/* SCIF0 */
set_guard_reg(GPSR4, 0x34000000, 0x00000000);
set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
set_guard_reg(GPSR4, 0x00000000, 0x34000000);
#endif
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */

452
board/renesas/koelsch/qos.c
View file

File diff suppressed because it is too large Load diff

196
board/renesas/lager/lager.c
View file

@ -24,181 +24,23 @@
DECLARE_GLOBAL_DATA_PTR;
#define s_init_wait(cnt) \
({ \
u32 i = 0x10000 * cnt; \
while (i > 0) \
i--; \
})
#define dbpdrgd_check(bsc) \
({ \
while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
; \
})
#if defined(CONFIG_NORFLASH)
static void bsc_init(void)
{
struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
/* LBSC */
writel(0x00000020, &lbsc->cs0ctrl);
writel(0x00000020, &lbsc->cs1ctrl);
writel(0x00002020, &lbsc->ecs0ctrl);
writel(0x00002020, &lbsc->ecs1ctrl);
writel(0x077F077F, &lbsc->cswcr0);
writel(0x077F077F, &lbsc->cswcr1);
writel(0x077F077F, &lbsc->ecswcr0);
writel(0x077F077F, &lbsc->ecswcr1);
/* DBSC3 */
s_init_wait(10);
writel(0x0000A55A, &dbsc3_0->dbpdlck);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x80000000, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000006, &dbsc3_0->dbpdrga);
writel(0x0001C000, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FD2480, &dbsc3_0->dbpdrgd);
writel(0x00000010, &dbsc3_0->dbpdrga);
writel(0xF004649B, &dbsc3_0->dbpdrgd);
writel(0x0000000F, &dbsc3_0->dbpdrga);
writel(0x00181EE4, &dbsc3_0->dbpdrgd);
writel(0x0000000E, &dbsc3_0->dbpdrga);
writel(0x33C03812, &dbsc3_0->dbpdrgd);
writel(0x00000003, &dbsc3_0->dbpdrga);
writel(0x0300C481, &dbsc3_0->dbpdrgd);
writel(0x00000007, &dbsc3_0->dbkind);
writel(0x10030A02, &dbsc3_0->dbconf0);
writel(0x00000001, &dbsc3_0->dbphytype);
writel(0x00000000, &dbsc3_0->dbbl);
writel(0x0000000B, &dbsc3_0->dbtr0);
writel(0x00000008, &dbsc3_0->dbtr1);
writel(0x00000000, &dbsc3_0->dbtr2);
writel(0x0000000B, &dbsc3_0->dbtr3);
writel(0x000C000B, &dbsc3_0->dbtr4);
writel(0x00000027, &dbsc3_0->dbtr5);
writel(0x0000001C, &dbsc3_0->dbtr6);
writel(0x00000005, &dbsc3_0->dbtr7);
writel(0x00000018, &dbsc3_0->dbtr8);
writel(0x00000008, &dbsc3_0->dbtr9);
writel(0x0000000C, &dbsc3_0->dbtr10);
writel(0x00000009, &dbsc3_0->dbtr11);
writel(0x00000012, &dbsc3_0->dbtr12);
writel(0x000000D0, &dbsc3_0->dbtr13);
writel(0x00140005, &dbsc3_0->dbtr14);
writel(0x00050004, &dbsc3_0->dbtr15);
writel(0x70233005, &dbsc3_0->dbtr16);
writel(0x000C0000, &dbsc3_0->dbtr17);
writel(0x00000300, &dbsc3_0->dbtr18);
writel(0x00000040, &dbsc3_0->dbtr19);
writel(0x00000001, &dbsc3_0->dbrnk0);
writel(0x00020001, &dbsc3_0->dbadj0);
writel(0x20082008, &dbsc3_0->dbadj2);
writel(0x00020002, &dbsc3_0->dbwt0cnf0);
writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
writel(0x00000015, &dbsc3_0->dbpdrga);
writel(0x00000D70, &dbsc3_0->dbpdrgd);
writel(0x00000016, &dbsc3_0->dbpdrga);
writel(0x00000006, &dbsc3_0->dbpdrgd);
writel(0x00000017, &dbsc3_0->dbpdrga);
writel(0x00000018, &dbsc3_0->dbpdrgd);
writel(0x00000012, &dbsc3_0->dbpdrga);
writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
writel(0x00000013, &dbsc3_0->dbpdrga);
writel(0x1A868300, &dbsc3_0->dbpdrgd);
writel(0x00000023, &dbsc3_0->dbpdrga);
writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
writel(0x00000014, &dbsc3_0->dbpdrga);
writel(0x300214D8, &dbsc3_0->dbpdrgd);
writel(0x0000001A, &dbsc3_0->dbpdrga);
writel(0x930035C7, &dbsc3_0->dbpdrgd);
writel(0x00000060, &dbsc3_0->dbpdrga);
writel(0x330657B2, &dbsc3_0->dbpdrgd);
writel(0x00000011, &dbsc3_0->dbpdrga);
writel(0x1000040B, &dbsc3_0->dbpdrgd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000071, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x2100FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x0000FA00, &dbsc3_0->dbcmd);
writel(0x110000DB, &dbsc3_0->dbcmd);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x00000181, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000001, &dbsc3_0->dbpdrga);
writel(0x0000FE01, &dbsc3_0->dbpdrgd);
writel(0x00000004, &dbsc3_0->dbpdrga);
dbpdrgd_check(dbsc3_0);
writel(0x00000000, &dbsc3_0->dbbs0cnt1);
writel(0x01004C20, &dbsc3_0->dbcalcnf);
writel(0x014000AA, &dbsc3_0->dbcaltr);
writel(0x00000140, &dbsc3_0->dbrfcnf0);
writel(0x00081860, &dbsc3_0->dbrfcnf1);
writel(0x00010000, &dbsc3_0->dbrfcnf2);
writel(0x00000001, &dbsc3_0->dbrfen);
writel(0x00000001, &dbsc3_0->dbacen);
}
#else
#define bsc_init() do {} while (0)
#endif /* CONFIG_NORFLASH */
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.4GHz */
stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
/* QoS(Quality-of-Service) Init */
qos_init();
/* BSC init */
bsc_init();
}
#define MSTPSR1 0xE6150038
@ -213,18 +55,6 @@ void s_init(void)
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
#define PMMR 0xE6060000
#define GPSR4 0xE6060014
#define IPSR14 0xE6060058
#define set_guard_reg(addr, mask, value) \
{ \
u32 val; \
val = (readl(addr) & ~(mask)) | (value); \
writel(~val, PMMR); \
writel(val, addr); \
}
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
@ -238,16 +68,8 @@ int board_early_init_f(void)
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
#if defined(CONFIG_NORFLASH)
/* SCIF0 */
set_guard_reg(GPSR4, 0x34000000, 0x00000000);
set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
set_guard_reg(GPSR4, 0x00000000, 0x34000000);
#endif
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
@ -263,8 +85,6 @@ void arch_preboot_os(void)
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_LAGER;
/* adress of boot parameters */
gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;

236
board/renesas/lager/qos.c
View file

@ -1,7 +1,7 @@
/*
* board/renesas/lager/qos.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -12,7 +12,7 @@
#include <asm/io.h>
#include <asm/arch/rmobile.h>
/* QoS version 0.954 */
/* QoS version 0.955 */
enum {
DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
@ -64,24 +64,24 @@ static const u32 dbsc3_qos_addr[DBSC3_NR] = {
void qos_init(void)
{
int i;
struct r8a7790_s3c *s3c;
struct r8a7790_s3c_qos *s3c_qos;
struct r8a7790_dbsc3_qos *qos_addr;
struct r8a7790_mxi *mxi;
struct r8a7790_mxi_qos *mxi_qos;
struct r8a7790_axi_qos *axi_qos;
struct rcar_s3c *s3c;
struct rcar_s3c_qos *s3c_qos;
struct rcar_dbsc3_qos *qos_addr;
struct rcar_mxi *mxi;
struct rcar_mxi_qos *mxi_qos;
struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
s3c = (struct r8a7790_s3c *)S3C_BASE;
s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x80FF1C1E, &s3c->s3cadsplcr);
writel(0x1F060505, &s3c->s3crorr);
writel(0x1F020100, &s3c->s3cworr);
/* QoS Control Registers */
s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00800080, &s3c_qos->s3cqos0);
writel(0x22000010, &s3c_qos->s3cqos1);
writel(0x22002200, &s3c_qos->s3cqos2);
@ -92,7 +92,7 @@ void qos_init(void)
writel(0x2F002200, &s3c_qos->s3cqos7);
writel(0x2F002F00, &s3c_qos->s3cqos8);
s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00800080, &s3c_qos->s3cqos0);
writel(0x22000010, &s3c_qos->s3cqos1);
writel(0x22002200, &s3c_qos->s3cqos2);
@ -103,7 +103,7 @@ void qos_init(void)
writel(0x2F002200, &s3c_qos->s3cqos7);
writel(0x2F002F00, &s3c_qos->s3cqos8);
s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
writel(0x80918099, &s3c_qos->s3cqos0);
writel(0x20410010, &s3c_qos->s3cqos1);
writel(0x200A2023, &s3c_qos->s3cqos2);
@ -114,7 +114,7 @@ void qos_init(void)
writel(0x20502001, &s3c_qos->s3cqos7);
writel(0x20142032, &s3c_qos->s3cqos8);
s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00810089, &s3c_qos->s3cqos0);
writel(0x20410001, &s3c_qos->s3cqos1);
@ -131,7 +131,7 @@ void qos_init(void)
/* DBSC -QoS */
/* DBSC0 - Read/Write */
for (i = DBSC3_R00; i < DBSC3_NR; i++) {
qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i];
writel(0x00000203, &qos_addr->dblgcnt);
writel(0x00002064, &qos_addr->dbtmval0);
writel(0x00002048, &qos_addr->dbtmval1);
@ -151,7 +151,7 @@ void qos_init(void)
/* MXI -QoS */
/* Transaction Control (MXI) */
mxi = (struct r8a7790_mxi *)MXI_BASE;
mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00B800C0, &mxi->mxsaar0);
@ -162,7 +162,7 @@ void qos_init(void)
writel(0x00200000, &mxi->mxaxiwacr);
/* QoS Control (MXI) */
mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE;
mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
writel(0x0000000C, &mxi_qos->vspdu0);
writel(0x0000000C, &mxi_qos->vspdu1);
writel(0x0000000D, &mxi_qos->du0);
@ -170,7 +170,7 @@ void qos_init(void)
/* AXI -QoS */
/* Transaction Control (MXI) */
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -182,7 +182,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -191,7 +191,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -200,7 +200,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -209,7 +209,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -218,7 +218,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -230,7 +230,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -242,7 +242,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -254,7 +254,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -263,7 +263,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -275,7 +275,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -287,7 +287,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -299,7 +299,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -311,7 +311,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -323,7 +323,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -332,7 +332,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -341,7 +341,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -350,7 +350,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -362,7 +362,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -371,7 +371,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -380,7 +380,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -389,7 +389,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -398,7 +398,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -407,7 +407,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -417,7 +417,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (RT-AXI) */
axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -429,7 +429,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -438,7 +438,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -450,7 +450,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002003, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -463,7 +463,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (MP-AXI) */
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -472,34 +472,34 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00001FF0, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -511,7 +511,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -520,7 +520,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200D, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -530,7 +530,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (SYS-AXI256) */
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -542,7 +542,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -554,7 +554,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -566,7 +566,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -579,7 +579,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (CCI-AXI) */
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -591,7 +591,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -603,7 +603,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -615,7 +615,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -627,7 +627,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -639,7 +639,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -651,7 +651,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -663,7 +663,7 @@ void qos_init(void)
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@ -676,7 +676,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (Media-AXI) */
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -685,7 +685,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -694,7 +694,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -703,7 +703,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -712,7 +712,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -721,7 +721,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -730,7 +730,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -739,7 +739,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -748,7 +748,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -757,7 +757,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -766,7 +766,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -775,7 +775,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -784,7 +784,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -793,7 +793,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -802,7 +802,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -811,7 +811,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -820,7 +820,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -829,7 +829,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -838,7 +838,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -847,7 +847,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -856,7 +856,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -865,7 +865,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -874,7 +874,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -883,7 +883,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -892,7 +892,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -901,7 +901,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -910,7 +910,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -919,7 +919,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -928,7 +928,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -937,7 +937,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -946,7 +946,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -955,7 +955,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -964,7 +964,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -973,7 +973,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -982,7 +982,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -991,7 +991,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -1000,7 +1000,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -1009,7 +1009,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -1018,7 +1018,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@ -1027,7 +1027,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1036,7 +1036,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1045,7 +1045,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1054,7 +1054,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1063,7 +1063,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1072,7 +1072,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1081,7 +1081,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1090,7 +1090,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1099,7 +1099,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@ -1108,7 +1108,7 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);

11
board/samsung/arndale/arndale.c
View file

@ -16,17 +16,14 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
int board_usb_init(int index, enum usb_init_type init)
{
struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Configure gpios for usb 3503 hub:
* disconnect, toggle reset and connect
*/
s5p_gpio_direction_output(&gpio->d1, 7, 0);
s5p_gpio_direction_output(&gpio->x3, 5, 0);
gpio_direction_output(EXYNOS5_GPIO_D17, 0);
gpio_direction_output(EXYNOS5_GPIO_X35, 0);
s5p_gpio_direction_output(&gpio->x3, 5, 1);
s5p_gpio_direction_output(&gpio->d1, 7, 1);
gpio_direction_output(EXYNOS5_GPIO_X35, 1);
gpio_direction_output(EXYNOS5_GPIO_D17, 1);
return 0;
}

130
board/samsung/common/misc.c
View file

@ -116,12 +116,14 @@ static int check_keys(void)
* 4 BOOT_MODE_EXIT
*/
static char *
mode_name[BOOT_MODE_EXIT + 1] = {
"DEVICE",
"THOR",
"UMS",
"DFU",
"EXIT"
mode_name[BOOT_MODE_EXIT + 1][2] = {
{"DEVICE", ""},
{"THOR", "thor"},
{"UMS", "ums"},
{"DFU", "dfu"},
{"GPT", "gpt"},
{"ENV", "env"},
{"EXIT", ""},
};
static char *
@ -130,18 +132,20 @@ mode_info[BOOT_MODE_EXIT + 1] = {
"downloader",
"mass storage",
"firmware update",
"restore",
"default",
"and run normal boot"
};
#define MODE_CMD_ARGC 4
static char *
mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = {
{"", "", "", ""},
{"thor", "0", "mmc", "0"},
{"ums", "0", "mmc", "0"},
{"dfu", "0", "mmc", "0"},
{"", "", "", ""},
mode_cmd[BOOT_MODE_EXIT + 1] = {
"",
"thor 0 mmc 0",
"ums 0 mmc 0",
"dfu 0 mmc 0",
"gpt write mmc 0 $partitions",
"env default -a; saveenv",
"",
};
static void display_board_info(void)
@ -182,11 +186,10 @@ static void display_board_info(void)
static int mode_leave_menu(int mode)
{
char *exit_option;
char *exit_boot = "boot";
char *exit_reset = "reset";
char *exit_back = "back";
cmd_tbl_t *cmd;
int cmd_result;
int cmd_repeatable;
int leave;
lcd_clear();
@ -200,31 +203,29 @@ static int mode_leave_menu(int mode)
leave = 0;
break;
default:
cmd = find_cmd(mode_cmd[mode][0]);
cmd = find_cmd(mode_name[mode][1]);
if (cmd) {
printf("Enter: %s %s\n", mode_name[mode],
printf("Enter: %s %s\n", mode_name[mode][0],
mode_info[mode]);
lcd_printf("\n\n\t%s %s\n", mode_name[mode],
lcd_printf("\n\n\t%s %s\n", mode_name[mode][0],
mode_info[mode]);
lcd_puts("\n\tDo not turn off device before finish!\n");
cmd_result = cmd_process(0, MODE_CMD_ARGC,
*(mode_cmd + mode),
&cmd_repeatable, NULL);
cmd_result = run_command(mode_cmd[mode], 0);
if (cmd_result == CMD_RET_SUCCESS) {
printf("Command finished\n");
lcd_clear();
lcd_printf("\n\n\t%s finished\n",
mode_name[mode]);
mode_name[mode][0]);
exit_option = exit_boot;
exit_option = exit_reset;
leave = 1;
} else {
printf("Command error\n");
lcd_clear();
lcd_printf("\n\n\t%s command error\n",
mode_name[mode]);
mode_name[mode][0]);
exit_option = exit_back;
leave = 0;
@ -260,11 +261,11 @@ static void display_download_menu(int mode)
selection[mode] = "[=>]";
lcd_clear();
lcd_printf("\n\t\tDownload Mode Menu\n");
lcd_printf("\n\n\t\tDownload Mode Menu\n\n");
for (i = 0; i <= BOOT_MODE_EXIT; i++)
lcd_printf("\t%s %s - %s\n\n", selection[i],
mode_name[i],
mode_name[i][0],
mode_info[i]);
}
@ -273,10 +274,38 @@ static void download_menu(void)
int mode = 0;
int last_mode = 0;
int run;
int key;
int key = 0;
int timeout = 15; /* sec */
int i;
display_download_menu(mode);
lcd_puts("\n");
/* Start count if no key is pressed */
while (check_keys())
continue;
while (timeout--) {
lcd_printf("\r\tNormal boot will start in: %2.d seconds.",
timeout);
/* about 1000 ms in for loop */
for (i = 0; i < 10; i++) {
mdelay(100);
key = check_keys();
if (key)
break;
}
if (key)
break;
}
if (!key) {
lcd_clear();
return;
}
while (1) {
run = 0;
@ -284,7 +313,7 @@ static void download_menu(void)
display_download_menu(mode);
last_mode = mode;
mdelay(100);
mdelay(200);
key = check_keys();
switch (key) {
@ -305,7 +334,7 @@ static void download_menu(void)
if (run) {
if (mode_leave_menu(mode))
break;
run_command("reset", 0);
display_download_menu(mode);
}
@ -314,45 +343,6 @@ static void download_menu(void)
lcd_clear();
}
static void display_mode_info(void)
{
lcd_position_cursor(4, 4);
lcd_printf("%s\n", U_BOOT_VERSION);
lcd_puts("\nDownload Mode Menu\n");
#ifdef CONFIG_SYS_BOARD
lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD);
#endif
lcd_printf("Press POWER KEY to display MENU options.");
}
static int boot_menu(void)
{
int key = 0;
int timeout = 10;
display_mode_info();
while (timeout--) {
lcd_printf("\rNormal boot will start in: %d seconds.", timeout);
mdelay(1000);
key = key_pressed(KEY_POWER);
if (key)
break;
}
lcd_clear();
/* If PWR pressed - show download menu */
if (key) {
printf("Power pressed - go to download menu\n");
download_menu();
printf("Download mode exit.\n");
}
return 0;
}
void check_boot_mode(void)
{
int pwr_key;
@ -365,7 +355,7 @@ void check_boot_mode(void)
power_key_pressed(KEY_PWR_INTERRUPT_REG);
if (key_pressed(KEY_VOLUMEUP))
boot_menu();
download_menu();
else if (key_pressed(KEY_VOLUMEDOWN))
mode_leave_menu(BOOT_MODE_THOR);
}

32
board/samsung/goni/goni.c
View file

@ -17,8 +17,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct s5pc110_gpio *s5pc110_gpio;
u32 get_board_rev(void)
{
return 0;
@ -27,8 +25,6 @@ u32 get_board_rev(void)
int board_init(void)
{
/* Set Initial global variables */
s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE;
gd->bd->bi_arch_number = MACH_TYPE_GONI;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@ -82,7 +78,7 @@ int board_mmc_init(bd_t *bis)
int i, ret, ret_sd = 0;
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
gpio_direction_output(S5PC110_GPIO_J27, 1);
/*
* MMC0 GPIO
@ -91,15 +87,15 @@ int board_mmc_init(bd_t *bis)
* GPG0[2] SD_0_CDn -> Not used
* GPG0[3:6] SD_0_DATA[0:3]
*/
for (i = 0; i < 7; i++) {
if (i == 2)
for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) {
if (i == S5PC110_GPIO_G02)
continue;
/* GPG0[0:6] special function 2 */
s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2);
gpio_cfg_pin(i, 0x2);
/* GPG0[0:6] pull disable */
s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* GPG0[0:6] drv 4x */
s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
ret = s5p_mmc_init(0, 4);
@ -110,20 +106,20 @@ int board_mmc_init(bd_t *bis)
* SD card (T_FLASH) detect and init
* T_FLASH_DETECT: EINT28: GPH3[4] input mode
*/
s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
for (i = 0; i < 7; i++) {
if (i == 2)
if (!gpio_get_value(S5PC110_GPIO_H34)) {
for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) {
if (i == S5PC110_GPIO_G22)
continue;
/* GPG2[0:6] special function 2 */
s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
gpio_cfg_pin(i, 0x2);
/* GPG2[0:6] pull disable */
s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* GPG2[0:6] drv 4x */
s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
ret_sd = s5p_mmc_init(2, 4);

20
board/samsung/smdk5250/exynos5-dt.c
View file

@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Enable MAX98095 Codec */
s5p_gpio_direction_output(&gpio1->x1, 7, 1);
s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
@ -47,19 +44,16 @@ int exynos_init(void)
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)

19
board/samsung/smdk5250/smdk5250.c
View file

@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Enable MAX98095 Codec */
s5p_gpio_direction_output(&gpio1->x1, 7, 1);
s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
@ -275,19 +272,17 @@ int exynos_power_init(void)
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)

15
board/samsung/smdk5420/smdk5420.c
View file

@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_USB_EHCI_EXYNOS
static int board_usb_vbus_init(void)
{
struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
/* Enable VBUS power switch */
s5p_gpio_direction_output(&gpio1->x2, 6, 1);
gpio_direction_output(EXYNOS5420_GPIO_X26, 1);
/* VBUS turn ON time */
mdelay(3);
@ -49,15 +46,15 @@ void cfg_lcd_gpio(void)
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->b2, 0, 1);
gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5420_GPIO_B20, 1);
/* LCD power on */
s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
s5p_gpio_set_value(&gpio1->x1, 5, 1);
gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5420_GPIO_X15, 1);
/* Set Hotplug detect for DP */
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
vidinfo_t panel_info = {

5
board/samsung/smdkc100/smdkc100.c
View file

@ -21,11 +21,8 @@ static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
struct s5pc100_gpio *const gpio =
(struct s5pc100_gpio *)samsung_get_base_gpio();
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);

19
board/samsung/smdkv310/smdkv310.c
View file

@ -15,15 +15,13 @@
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
/* gpio configuration GPK0CON */
s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
/* Ethernet needs bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
@ -38,9 +36,6 @@ static void smc9115_pre_init(void)
int board_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
smc9115_pre_init();
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
@ -103,21 +98,21 @@ int board_mmc_init(bd_t *bis)
* GPK2[2] SD_2_CDn
* GPK2[3:6] SD_2_DATA[0:3](2)
*/
for (i = 0; i < 7; i++) {
for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
/* GPK2[0:6] special function 2 */
s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
/* GPK2[0:6] drv 4x */
s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
/* GPK2[0:1] pull disable */
if (i == 0 || i == 1) {
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
continue;
}
/* GPK2[2:6] pull up */
s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
gpio_set_pull(i, S5P_GPIO_PULL_UP);
}
err = s5p_mmc_init(2, 4);
return err;

39
board/samsung/trats/trats.c
View file

@ -54,8 +54,6 @@ int exynos_init(void)
void i2c_init_board(void)
{
int err;
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_5 -> PMIC */
err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
@ -65,8 +63,8 @@ void i2c_init_board(void)
}
/* I2C_8 -> FG */
s5p_gpio_direction_output(&gpio2->y4, 0, 1);
s5p_gpio_direction_output(&gpio2->y4, 1, 1);
gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
}
static void trats_low_power_mode(void)
@ -347,21 +345,19 @@ int exynos_power_init(void)
static unsigned int get_hw_revision(void)
{
struct exynos4_gpio_part1 *gpio =
(struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
int hwrev = 0;
int i;
/* hw_rev[3:0] == GPE1[3:0] */
for (i = 0; i < 4; i++) {
s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) {
gpio_cfg_pin(i, S5P_GPIO_INPUT);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
}
udelay(1);
for (i = 0; i < 4; i++)
hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
debug("hwrev 0x%x\n", hwrev);
@ -442,11 +438,8 @@ int g_dnl_board_usb_cable_connected(void)
static void pmic_reset(void)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio->x0, 7, 1);
s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
gpio_direction_output(EXYNOS4_GPIO_X07, 1);
gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
}
static void board_clock_init(void)
@ -523,12 +516,9 @@ static void board_power_init(void)
static void exynos_uart_init(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio2->y4, 7, 1);
gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
}
int exynos_early_init_f(void)
@ -544,14 +534,11 @@ int exynos_early_init_f(void)
void exynos_reset_lcd(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
s5p_gpio_direction_output(&gpio2->y4, 5, 0);
gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
s5p_gpio_direction_output(&gpio2->y4, 5, 1);
gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
}
int lcd_power(void)

74
board/samsung/trats2/trats2.c
View file

@ -25,9 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
static struct exynos4x12_gpio_part1 *gpio1;
static struct exynos4x12_gpio_part2 *gpio2;
static unsigned int board_rev = -1;
static inline u32 get_model_rev(void);
@ -37,26 +34,24 @@ static void check_hw_revision(void)
int modelrev = 0;
int i;
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/*
* GPM1[1:0]: MODEL_REV[1:0]
* Don't set as pull-none for these N/C pin.
* TRM say that it may cause unexcepted state and leakage current.
* and pull-none is only for output function.
*/
for (i = 0; i < 2; i++)
s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++)
gpio_cfg_pin(i, S5P_GPIO_INPUT);
/* GPM1[5:2]: HW_REV[3:0] */
for (i = 2; i < 6; i++) {
s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT);
s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE);
for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) {
gpio_cfg_pin(i, S5P_GPIO_INPUT);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
}
/* GPM1[1:0]: MODEL_REV[1:0] */
for (i = 0; i < 2; i++)
modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i);
modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i);
/* board_rev[15:8] = model */
board_rev = modelrev << 8;
@ -74,26 +69,24 @@ static inline u32 get_model_rev(void)
static void board_external_gpio_init(void)
{
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/*
* some pins which in alive block are connected with external pull-up
* but it's default setting is pull-down.
* if that pin set as input then that floated
*/
s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */
s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */
s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */
s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */
s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */
s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */
s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */
s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */
s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */
s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */
gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */
gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */
gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */
gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */
gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */
gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */
gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */
gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */
gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */
gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
@ -101,9 +94,6 @@ static void board_init_i2c(void)
{
int err;
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_7 */
err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
if (err) {
@ -112,12 +102,12 @@ static void board_init_i2c(void)
}
/* I2C_8 */
s5p_gpio_direction_output(&gpio1->f1, 4, 1);
s5p_gpio_direction_output(&gpio1->f1, 5, 1);
gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
/* I2C_9 */
s5p_gpio_direction_output(&gpio2->m2, 1, 1);
s5p_gpio_direction_output(&gpio2->m2, 0, 1);
gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
}
#endif
@ -125,17 +115,17 @@ static void board_init_i2c(void)
int get_soft_i2c_scl_pin(void)
{
if (I2C_ADAP_HWNR)
return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */
return EXYNOS4X12_GPIO_M21; /* I2C9 */
else
return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */
return EXYNOS4X12_GPIO_F14; /* I2C8 */
}
int get_soft_i2c_sda_pin(void)
{
if (I2C_ADAP_HWNR)
return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */
return EXYNOS4X12_GPIO_M20; /* I2C9 */
else
return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */
return EXYNOS4X12_GPIO_F15; /* I2C8 */
}
#endif
@ -396,11 +386,9 @@ void exynos_lcd_power_on(void)
{
struct pmic *p = pmic_get("MAX77686_PMIC");
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
/* LCD_2.2V_EN: GPC0[1] */
s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
s5p_gpio_direction_output(&gpio1->c0, 1, 1);
gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
/* LDO25 VCC_3.1V_LCD */
pmic_probe(p);
@ -410,12 +398,10 @@ void exynos_lcd_power_on(void)
void exynos_reset_lcd(void)
{
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
/* reset lcd */
s5p_gpio_direction_output(&gpio1->f2, 1, 0);
gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
udelay(10);
s5p_gpio_set_value(&gpio1->f2, 1, 1);
gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
}
void exynos_lcd_misc_init(vidinfo_t *vid)

51
board/samsung/universal_c210/universal.c
View file

@ -27,8 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
unsigned int board_rev;
u32 get_board_rev(void)
@ -305,35 +303,35 @@ void exynos_cfg_lcd_gpio(void)
for (i = 0; i < 8; i++) {
/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
}
for (i = 0; i < f3_end; i++) {
for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
/* pull-up/down disable */
s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
/* drive strength to max (24bit) */
s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
}
/* gpio pad configuration for LCD reset. */
s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
spi_init();
}
@ -345,11 +343,11 @@ int mipi_power(void)
void exynos_reset_lcd(void)
{
s5p_gpio_set_value(&gpio2->y4, 5, 1);
gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(10000);
s5p_gpio_set_value(&gpio2->y4, 5, 0);
gpio_set_value(EXYNOS4_GPIO_Y45, 0);
udelay(10000);
s5p_gpio_set_value(&gpio2->y4, 5, 1);
gpio_set_value(EXYNOS4_GPIO_Y45, 1);
udelay(100);
}
@ -379,9 +377,6 @@ void exynos_enable_ldo(unsigned int onoff)
int exynos_init(void)
{
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
switch (get_hwrev()) {
@ -392,7 +387,7 @@ int exynos_init(void)
* you should set it HIGH since it removes the inverter
*/
/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
s5p_gpio_direction_output(&gpio1->e3, 6, 0);
gpio_direction_output(EXYNOS4_GPIO_E36, 0);
break;
default:
/*
@ -400,7 +395,7 @@ int exynos_init(void)
* But set it as HIGH to ensure
*/
/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
s5p_gpio_direction_output(&gpio1->e1, 3, 1);
gpio_direction_output(EXYNOS4_GPIO_E13, 1);
break;
}

46
board/siemens/common/board.c
View file

@ -128,12 +128,6 @@ do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
button = 0;
gpio_free(gpio);
if (!button) {
/* LED0 - RED=1: GPIO2_0 2*32 = 64 */
gpio_request(BOARD_DFU_BUTTON_LED, "");
gpio_direction_output(BOARD_DFU_BUTTON_LED, 1);
gpio_set_value(BOARD_DFU_BUTTON_LED, 1);
}
return button;
}
@ -144,6 +138,46 @@ U_BOOT_CMD(
""
);
#endif
/*
* This command sets led
* Input - name of led
* value of led
* Returns - 1 if input does not match
* 0 if led was set
*/
static int
do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int gpio = 0;
if (argc != 3)
goto exit;
#if defined(BOARD_STATUS_LED)
if (!strcmp(argv[1], "stat"))
gpio = BOARD_STATUS_LED;
#endif
#if defined(BOARD_DFU_BUTTON_LED)
if (!strcmp(argv[1], "dfu"))
gpio = BOARD_DFU_BUTTON_LED;
#endif
/* If argument does not mach exit */
if (gpio == 0)
goto exit;
gpio_request(gpio, "");
gpio_direction_output(gpio, 1);
if (!strcmp(argv[2], "1"))
gpio_set_value(gpio, 1);
else
gpio_set_value(gpio, 0);
return 0;
exit:
return 1;
}
U_BOOT_CMD(
led, CONFIG_SYS_MAXARGS, 2, do_setled,
"Set led on or off",
"dfu val - set dfu led\nled stat val - set status led"
);
static int
do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

0
board/siemens/dxr2/Makefile → board/siemens/draco/Makefile
View file

106
board/siemens/dxr2/board.c → board/siemens/draco/board.c
View file

@ -1,5 +1,5 @@
/*
* Board functions for TI AM335X based dxr2 board
* Board functions for TI AM335X based draco board
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
@ -37,13 +37,27 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
/* @303MHz-i0 */
static struct draco_baseboard_id __attribute__((section(".data"))) settings;
#if DDR_PLL_FREQ == 303
/* Default@303MHz-i0 */
const struct ddr3_data ddr3_default = {
0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
0x00000618, 0x0000014A,
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
0x0000093B, 0x0000014A,
"default name @303MHz \0",
"default marking \0",
};
#elif DDR_PLL_FREQ == 400
/* Default@400MHz-i0 */
const struct ddr3_data ddr3_default = {
0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
0x00000618, 0x0000014A,
"default name @400MHz \0",
"default marking \0",
};
#endif
static void set_default_ddr3_timings(void)
{
@ -53,8 +67,12 @@ static void set_default_ddr3_timings(void)
static void print_ddr3_timings(void)
{
printf("\n\nDDR3 Timing parameters:\n");
printf("Diff Eeprom Default\n");
printf("\nDDR3\n");
printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
printf("device:\t\t%s\n", settings.ddr3.manu_name);
printf("marking:\t%s\n", settings.ddr3.manu_marking);
printf("timing parameters\n");
printf("diff\teeprom\tdefault\n");
PRINTARGS(magic);
PRINTARGS(version);
PRINTARGS(ddr3_sratio);
@ -78,9 +96,9 @@ static void print_ddr3_timings(void)
static void print_chip_data(void)
{
printf("\n");
printf("Device: '%s'\n", settings.chip.sdevname);
printf("HW version: '%s'\n", settings.chip.shwver);
printf("\nCPU BOARD\n");
printf("device: \t'%s'\n", settings.chip.sdevname);
printf("hw version: \t'%s'\n", settings.chip.shwver);
}
#endif /* CONFIG_SPL_BUILD */
@ -112,20 +130,18 @@ static int read_eeprom(void)
printf("Using DDR3 settings from EEPROM\n");
} else {
if (ddr3_default.magic != settings.ddr3.magic)
printf("Error: No valid DDR3 data in eeprom.\n");
printf("Warning: No valid DDR3 data in eeprom.\n");
if (ddr3_default.version != settings.ddr3.version)
printf("Error: DDR3 data version does not match.\n");
printf("Warning: DDR3 data version does not match.\n");
printf("Using default settings\n");
set_default_ddr3_timings();
}
if (MAGIC_CHIP == settings.chip.magic) {
printf("Valid chip data in eeprom\n");
if (MAGIC_CHIP == settings.chip.magic)
print_chip_data();
} else {
printf("Error: No chip data in eeprom\n");
}
else
printf("Warning: No chip data in eeprom\n");
print_ddr3_timings();
#endif
@ -135,48 +151,48 @@ static int read_eeprom(void)
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs dxr2_ddr3_emif_reg_data = {
struct emif_regs draco_ddr3_emif_reg_data = {
.zq_config = 0x50074BE4,
};
struct ddr_data dxr2_ddr3_data = {
struct ddr_data draco_ddr3_data = {
};
struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
struct cmd_control draco_ddr3_cmd_ctrl_data = {
};
struct ctrl_ioregs dxr2_ddr3_ioregs = {
struct ctrl_ioregs draco_ddr3_ioregs = {
};
/* pass values from eeprom */
dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)

26
board/siemens/dxr2/board.h → board/siemens/draco/board.h
View file

@ -22,24 +22,26 @@
#define MAGIC_CHIP 0x50494843
/* Automatic generated definition */
/* Wed, 18 Sep 2013 18:58:27 +0200 */
/* From file: draco/ddr3-data-micron-v2.txt */
/* Wed, 16 Apr 2014 16:50:41 +0200 */
/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
struct ddr3_data {
unsigned int magic; /* 0x33524444 */
unsigned int version; /* 0x56312e34 */
unsigned short int ddr3_sratio; /* 0x0100 */
unsigned short int iclkout; /* 0x0001 */
unsigned int version; /* 0x56312e35 */
unsigned short int ddr3_sratio; /* 0x0080 */
unsigned short int iclkout; /* 0x0000 */
unsigned short int dt0rdsratio0; /* 0x003A */
unsigned short int dt0wdsratio0; /* 0x008A */
unsigned short int dt0fwsratio0; /* 0x010B */
unsigned short int dt0wrsratio0; /* 0x00C4 */
unsigned short int dt0wdsratio0; /* 0x003F */
unsigned short int dt0fwsratio0; /* 0x009F */
unsigned short int dt0wrsratio0; /* 0x0079 */
unsigned int sdram_tim1; /* 0x0888A39B */
unsigned int sdram_tim2; /* 0x26247FDA */
unsigned int sdram_tim3; /* 0x501F821F */
unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
unsigned int sdram_config; /* 0x61C04AB2 */
unsigned int ref_ctrl; /* 0x00000618 */
unsigned int ioctr_val; /* 0x0000018B */
unsigned int sdram_config; /* 0x61A44A32 */
unsigned int ref_ctrl; /* 0x0000093B */
unsigned int ioctr_val; /* 0x0000014A */
char manu_name[32]; /* "default@303MHz \0" */
char manu_marking[32]; /* "default \0" */
};
struct chip_data {
@ -48,7 +50,7 @@ struct chip_data {
char shwver[7];
};
struct dxr2_baseboard_id {
struct draco_baseboard_id {
struct ddr3_data ddr3;
struct chip_data chip;
};

2
board/siemens/dxr2/mux.c → board/siemens/draco/mux.c
View file

@ -1,5 +1,5 @@
/*
* pinmux setup for siemens dxr2 board
* pinmux setup for siemens draco board
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.

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