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ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot using GPIO0 pin 10 to make sure, the Phy latches the configuration from the input pins correctly. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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2 changed files with 18 additions and 0 deletions
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@ -69,9 +69,12 @@
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#define K2G_GPIO0_BASE 0X02603000
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#define K2G_GPIO1_BASE 0X0260a000
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#define K2G_GPIO0_BANK0_BASE K2G_GPIO0_BASE + 0x10
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#define K2G_GPIO1_BANK2_BASE K2G_GPIO1_BASE + 0x38
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#define K2G_GPIO_DIR_OFFSET 0x0
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#define K2G_GPIO_OUTDATA_OFFSET 0x4
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#define K2G_GPIO_SETDATA_OFFSET 0x8
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#define K2G_GPIO_CLRDATA_OFFSET 0xC
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/* BOOTCFG RESETMUX8 */
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#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
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@ -315,6 +315,21 @@ int embedded_dtb_select(void)
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BIT(9));
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setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
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BIT(9));
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} else if (board_is_k2g_ice()) {
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/* GBE Phy workaround. For Phy to latch the input
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* configuration, a GPIO reset is asserted at the
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* Phy reset pin to latch configuration correctly after SoC
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* reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
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* board. Just do a low to high transition.
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*/
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clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
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BIT(10));
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setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
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BIT(10));
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/* Delay just to get a transition to high */
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udelay(100);
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setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
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BIT(10));
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}
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return 0;
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