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mmc: dcache: allocate cache aligned buffer for scr and switch_status
Currently the sd_change_freq function allocates two buffers on the stack that it passes down to the MMC device driver. These buffers could be unaligned to the L1 dcache line size. This causes problems when using DMA and with caches enabled. This patch correctly cache alignes the buffers used for reading the scr register and switch status values from an MMC device. Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Mike Frysinger <vapier@gentoo.org>
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parent
96d21237ec
commit
f781dd383a
1 changed files with 5 additions and 5 deletions
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@ -702,8 +702,8 @@ int sd_change_freq(struct mmc *mmc)
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{
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int err;
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struct mmc_cmd cmd;
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uint scr[2];
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uint switch_status[16];
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ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
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ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
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struct mmc_data data;
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int timeout;
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@ -731,7 +731,7 @@ int sd_change_freq(struct mmc *mmc)
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timeout = 3;
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retry_scr:
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data.dest = (char *)&scr;
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data.dest = (char *)scr;
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data.blocksize = 8;
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data.blocks = 1;
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data.flags = MMC_DATA_READ;
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@ -773,7 +773,7 @@ retry_scr:
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timeout = 4;
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while (timeout--) {
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err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
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(u8 *)&switch_status);
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(u8 *)switch_status);
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if (err)
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return err;
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@ -787,7 +787,7 @@ retry_scr:
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if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
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return 0;
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err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)&switch_status);
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err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
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if (err)
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return err;
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