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ls102xa: Fix reset hang
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman <sinan@writeme.com> Tested-by: Sinan Akman <sinan@writeme.com> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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parent
f532727d16
commit
f861f51c46
2 changed files with 16 additions and 1 deletions
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@ -13,6 +13,8 @@
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#include <tsec.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#include <config.h>
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#include <fsl_wdog.h>
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#include "fsl_epu.h"
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@ -354,3 +356,16 @@ void smp_kick_all_cpus(void)
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asm volatile("sev");
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}
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#endif
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void reset_cpu(ulong addr)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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clrbits_be16(&wdog->wcr, WCR_SRS);
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while (1) {
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/*
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* Let the watchdog trigger
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*/
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}
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}
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@ -7,7 +7,7 @@
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obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
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obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
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ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 ls102xa))
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ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610))
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obj-y += imx_watchdog.o
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endif
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obj-$(CONFIG_S5P) += s5p_wdt.o
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