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ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

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After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Adam Graham 2008-10-06 10:16:13 -07:00 • committed by Stefan Roese
parent 50a874b3b0
commit f8a00dea84
1 changed files with 21 additions and 0 deletions
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21
cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
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@ -174,6 +174,23 @@ static inline void ecc_clear_status_reg(void)
#endif #endif
} }
/*
* Reset and relock memory DLL after SDRAM_CLKTR change
*/
static inline void relock_memory_DLL(void)
{
u32 reg;
mtsdram(SDRAM_MCOPT2, SDRAM_MCOPT2_IPTR_EXECUTE);
do {
mfsdram(SDRAM_MCSTAT, reg);
} while (!(reg & SDRAM_MCSTAT_MIC_COMP));
mfsdram(SDRAM_MCOPT2, reg);
mtsdram(SDRAM_MCOPT2, reg | SDRAM_MCOPT2_DCEN_ENABLE);
}
static int ecc_check_status_reg(void) static int ecc_check_status_reg(void)
{ {
u32 ecc_status; u32 ecc_status;
@ -981,6 +998,8 @@ u32 DQS_autocalibration(void)
mtsdram(SDRAM_CLKTR, clkp << 30); mtsdram(SDRAM_CLKTR, clkp << 30);
relock_memory_DLL();
putc('\b'); putc('\b');
putc(slash[loopi++ % 8]); putc(slash[loopi++ % 8]);
@ -1170,6 +1189,8 @@ u32 DQS_autocalibration(void)
mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30); mtsdram(SDRAM_CLKTR, tcal.clocks.clktr << 30);
relock_memory_DLL();
mfsdram(SDRAM_RQDC, rqdc_reg); mfsdram(SDRAM_RQDC, rqdc_reg);
rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
mtsdram(SDRAM_RQDC, rqdc_reg | mtsdram(SDRAM_RQDC, rqdc_reg |