GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 06:31:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

common: Drop floppy disk support

Browse source 
This seems pretty old now. It has not been converted to driver model and
is not used by any boards.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2019-12-28 10:44:47 -07:00 • committed by Jagan Teki
parent 0f67fc2328
commit f9aaf98451
10 changed files with 1 additions and 1159 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

26
README
View file

@ -2870,32 +2870,6 @@ Low Level (hardware related) configuration options:
If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
forced to a value that ensures that CCSR is not relocated.
- Floppy Disk Support:
CONFIG_SYS_FDC_DRIVE_NUMBER
the default drive number (default value 0)
CONFIG_SYS_ISA_IO_STRIDE
defines the spacing between FDC chipset registers
(default value 1)
CONFIG_SYS_ISA_IO_OFFSET
defines the offset of register from address. It
depends on which part of the data bus is connected to
the FDC chipset. (default value 0)
If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
default value.
if CONFIG_SYS_FDC_HW_INIT is defined, then the function
fdc_hw_init() is called at the beginning of the FDC
setup. fdc_hw_init() must be provided by the board
source code. It is used to make hardware-dependent
initializations.
- CONFIG_IDE_AHB:
Most IDE controllers were designed to be connected with PCI
interface. Only few of them were designed for AHB interface.

5
cmd/Kconfig
View file

@ -858,11 +858,6 @@ config CMD_FASTBOOT
See doc/android/fastboot.txt for more information.
config CMD_FDC
bool "fdcboot - Boot from floppy device"
help
The 'fdtboot' command allows booting an image from a floppy disk.
config CMD_FLASH
bool "flinfo, erase, protect"
default y

1
cmd/Makefile
View file

@ -58,7 +58,6 @@ obj-$(CONFIG_HUSH_PARSER) += exit.o
obj-$(CONFIG_CMD_EXT4) += ext4.o
obj-$(CONFIG_CMD_EXT2) += ext2.o
obj-$(CONFIG_CMD_FAT) += fat.o
obj-$(CONFIG_CMD_FDC) += fdc.o
obj-$(CONFIG_CMD_FDT) += fdt.o
obj-$(CONFIG_CMD_FITUPD) += fitupd.o
obj-$(CONFIG_CMD_FLASH) += flash.o

752
cmd/fdc.c
View file

@ -1,752 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2001
* Denis Peter, MPL AG, d.peter@mpl.ch.
*/
/*
* Floppy Disk support
*/
#include <common.h>
#include <config.h>
#include <command.h>
#include <image.h>
#include <irq_func.h>
#undef FDC_DEBUG
#ifdef FDC_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/*#if defined(CONFIG_CMD_DATE) */
/*#include <rtc.h> */
/*#endif */
typedef struct {
int flags; /* connected drives ect */
unsigned long blnr; /* Logical block nr */
uchar drive; /* drive no */
uchar cmdlen; /* cmd length */
uchar cmd[16]; /* cmd desc */
uchar dma; /* if > 0 dma enabled */
uchar result[11]; /* status information */
uchar resultlen; /* lenght of result */
} FDC_COMMAND_STRUCT;
/* flags: only the lower 8bit used:
* bit 0 if set drive 0 is present
* bit 1 if set drive 1 is present
* bit 2 if set drive 2 is present
* bit 3 if set drive 3 is present
* bit 4 if set disk in drive 0 is inserted
* bit 5 if set disk in drive 1 is inserted
* bit 6 if set disk in drive 2 is inserted
* bit 7 if set disk in drive 4 is inserted
*/
/* cmd indexes */
#define COMMAND 0
#define DRIVE 1
#define CONFIG0 1
#define SPEC_HUTSRT 1
#define TRACK 2
#define CONFIG1 2
#define SPEC_HLT 2
#define HEAD 3
#define CONFIG2 3
#define SECTOR 4
#define SECTOR_SIZE 5
#define LAST_TRACK 6
#define GAP 7
#define DTL 8
/* result indexes */
#define STATUS_0 0
#define STATUS_PCN 1
#define STATUS_1 1
#define STATUS_2 2
#define STATUS_TRACK 3
#define STATUS_HEAD 4
#define STATUS_SECT 5
#define STATUS_SECT_SIZE 6
/* Register addresses */
#define FDC_BASE 0x3F0
#define FDC_SRA FDC_BASE + 0 /* Status Register A */
#define FDC_SRB FDC_BASE + 1 /* Status Register B */
#define FDC_DOR FDC_BASE + 2 /* Digital Output Register */
#define FDC_TDR FDC_BASE + 3 /* Tape Drive Register */
#define FDC_DSR FDC_BASE + 4 /* Data rate Register */
#define FDC_MSR FDC_BASE + 4 /* Main Status Register */
#define FDC_FIFO FDC_BASE + 5 /* FIFO */
#define FDC_DIR FDC_BASE + 6 /* Digital Input Register */
#define FDC_CCR FDC_BASE + 7 /* Configuration Control */
/* Commands */
#define FDC_CMD_SENSE_INT 0x08
#define FDC_CMD_CONFIGURE 0x13
#define FDC_CMD_SPECIFY 0x03
#define FDC_CMD_RECALIBRATE 0x07
#define FDC_CMD_READ 0x06
#define FDC_CMD_READ_TRACK 0x02
#define FDC_CMD_READ_ID 0x0A
#define FDC_CMD_DUMP_REG 0x0E
#define FDC_CMD_SEEK 0x0F
#define FDC_CMD_SENSE_INT_LEN 0x01
#define FDC_CMD_CONFIGURE_LEN 0x04
#define FDC_CMD_SPECIFY_LEN 0x03
#define FDC_CMD_RECALIBRATE_LEN 0x02
#define FDC_CMD_READ_LEN 0x09
#define FDC_CMD_READ_TRACK_LEN 0x09
#define FDC_CMD_READ_ID_LEN 0x02
#define FDC_CMD_DUMP_REG_LEN 0x01
#define FDC_CMD_SEEK_LEN 0x03
#define FDC_FIFO_THR 0x0C
#define FDC_FIFO_DIS 0x00
#define FDC_IMPLIED_SEEK 0x01
#define FDC_POLL_DIS 0x00
#define FDC_PRE_TRK 0x00
#define FDC_CONFIGURE FDC_FIFO_THR | (FDC_POLL_DIS<<4) | (FDC_FIFO_DIS<<5) | (FDC_IMPLIED_SEEK << 6)
#define FDC_MFM_MODE 0x01 /* MFM enable */
#define FDC_SKIP_MODE 0x00 /* skip enable */
#define FDC_TIME_OUT 100000 /* time out */
#define FDC_RW_RETRIES 3 /* read write retries */
#define FDC_CAL_RETRIES 3 /* calibration and seek retries */
/* Disk structure */
typedef struct {
unsigned int size; /* nr of sectors total */
unsigned int sect; /* sectors per track */
unsigned int head; /* nr of heads */
unsigned int track; /* nr of tracks */
unsigned int stretch; /* !=0 means double track steps */
unsigned char gap; /* gap1 size */
unsigned char rate; /* data rate. |= 0x40 for perpendicular */
unsigned char spec1; /* stepping rate, head unload time */
unsigned char fmt_gap;/* gap2 size */
unsigned char hlt; /* head load time */
unsigned char sect_code;/* Sector Size code */
const char * name; /* used only for predefined formats */
} FD_GEO_STRUCT;
/* supported Floppy types (currently only one) */
const static FD_GEO_STRUCT floppy_type[2] = {
{ 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,16,2,"H1440" }, /* 7 1.44MB 3.5" */
{ 0, 0,0, 0,0,0x00,0x00,0x00,0x00, 0,0,NULL }, /* end of table */
};
static FDC_COMMAND_STRUCT cmd; /* global command struct */
/* If the boot drive number is undefined, we assume it's drive 0 */
#ifndef CONFIG_SYS_FDC_DRIVE_NUMBER
#define CONFIG_SYS_FDC_DRIVE_NUMBER 0
#endif
/* Hardware access */
#ifndef CONFIG_SYS_ISA_IO_STRIDE
#define CONFIG_SYS_ISA_IO_STRIDE 1
#endif
#ifndef CONFIG_SYS_ISA_IO_OFFSET
#define CONFIG_SYS_ISA_IO_OFFSET 0
#endif
/* Supporting Functions */
/* reads a Register of the FDC */
unsigned char read_fdc_reg(unsigned int addr)
{
volatile unsigned char *val =
(volatile unsigned char *)(CONFIG_SYS_ISA_IO_BASE_ADDRESS +
(addr * CONFIG_SYS_ISA_IO_STRIDE) +
CONFIG_SYS_ISA_IO_OFFSET);
return val [0];
}
/* writes a Register of the FDC */
void write_fdc_reg(unsigned int addr, unsigned char val)
{
volatile unsigned char *tmp =
(volatile unsigned char *)(CONFIG_SYS_ISA_IO_BASE_ADDRESS +
(addr * CONFIG_SYS_ISA_IO_STRIDE) +
CONFIG_SYS_ISA_IO_OFFSET);
tmp[0]=val;
}
/* waits for an interrupt (polling) */
int wait_for_fdc_int(void)
{
unsigned long timeout;
timeout = FDC_TIME_OUT;
while((read_fdc_reg(FDC_SRA)&0x80)==0) {
timeout--;
udelay(10);
if(timeout==0) /* timeout occurred */
return false;
}
return true;
}
/* reads a byte from the FIFO of the FDC and checks direction and RQM bit
of the MSR. returns -1 if timeout, or byte if ok */
int read_fdc_byte(void)
{
unsigned long timeout;
timeout = FDC_TIME_OUT;
while((read_fdc_reg(FDC_MSR)&0xC0)!=0xC0) {
/* direction out and ready */
udelay(10);
timeout--;
if(timeout==0) /* timeout occurred */
return -1;
}
return read_fdc_reg(FDC_FIFO);
}
/* if the direction of the FIFO is wrong, this routine is used to
empty the FIFO. Should _not_ be used */
int fdc_need_more_output(void)
{
unsigned char c;
while((read_fdc_reg(FDC_MSR)&0xC0)==0xC0) {
c=(unsigned char)read_fdc_byte();
printf("Error: more output: %x\n",c);
}
return true;
}
/* writes a byte to the FIFO of the FDC and checks direction and RQM bit
of the MSR */
int write_fdc_byte(unsigned char val)
{
unsigned long timeout;
timeout = FDC_TIME_OUT;
while((read_fdc_reg(FDC_MSR)&0xC0)!=0x80) {
/* direction in and ready for byte */
timeout--;
udelay(10);
fdc_need_more_output();
if(timeout==0) /* timeout occurred */
return false;
}
write_fdc_reg(FDC_FIFO,val);
return true;
}
/* sets up all FDC commands and issues it to the FDC. If
the command causes direct results (no Execution Phase)
the result is be read as well. */
int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
{
int i;
unsigned long head,track,sect,timeout;
track = pCMD->blnr / (pFG->sect * pFG->head); /* track nr */
sect = pCMD->blnr % (pFG->sect * pFG->head); /* remaining blocks */
head = sect / pFG->sect; /* head nr */
sect = sect % pFG->sect; /* remaining blocks */
sect++; /* sectors are 1 based */
PRINTF("Cmd 0x%02x Track %ld, Head %ld, Sector %ld, Drive %d (blnr %ld)\n",
pCMD->cmd[0],track,head,sect,pCMD->drive,pCMD->blnr);
if(head|=0) { /* max heads = 2 */
pCMD->cmd[DRIVE]=pCMD->drive | 0x04; /* head 1 */
pCMD->cmd[HEAD]=(unsigned char) head; /* head register */
}
else {
pCMD->cmd[DRIVE]=pCMD->drive; /* head 0 */
pCMD->cmd[HEAD]=(unsigned char) head; /* head register */
}
pCMD->cmd[TRACK]=(unsigned char) track; /* track */
switch (pCMD->cmd[COMMAND]) {
case FDC_CMD_READ:
pCMD->cmd[SECTOR]=(unsigned char) sect; /* sector */
pCMD->cmd[SECTOR_SIZE]=pFG->sect_code; /* sector size code */
pCMD->cmd[LAST_TRACK]=pFG->sect; /* End of track */
pCMD->cmd[GAP]=pFG->gap; /* gap */
pCMD->cmd[DTL]=0xFF; /* DTL */
pCMD->cmdlen=FDC_CMD_READ_LEN;
pCMD->cmd[COMMAND]|=(FDC_MFM_MODE<<6); /* set MFM bit */
pCMD->cmd[COMMAND]|=(FDC_SKIP_MODE<<5); /* set Skip bit */
pCMD->resultlen=0; /* result only after execution */
break;
case FDC_CMD_SEEK:
pCMD->cmdlen=FDC_CMD_SEEK_LEN;
pCMD->resultlen=0; /* no result */
break;
case FDC_CMD_CONFIGURE:
pCMD->cmd[CONFIG0]=0;
pCMD->cmd[CONFIG1]=FDC_CONFIGURE; /* FIFO Threshold, Poll, Enable FIFO */
pCMD->cmd[CONFIG2]=FDC_PRE_TRK; /* Precompensation Track */
pCMD->cmdlen=FDC_CMD_CONFIGURE_LEN;
pCMD->resultlen=0; /* no result */
break;
case FDC_CMD_SPECIFY:
pCMD->cmd[SPEC_HUTSRT]=pFG->spec1;
pCMD->cmd[SPEC_HLT]=(pFG->hlt)<<1; /* head load time */
if(pCMD->dma==0)
pCMD->cmd[SPEC_HLT]|=0x1; /* no dma */
pCMD->cmdlen=FDC_CMD_SPECIFY_LEN;
pCMD->resultlen=0; /* no result */
break;
case FDC_CMD_DUMP_REG:
pCMD->cmdlen=FDC_CMD_DUMP_REG_LEN;
pCMD->resultlen=10; /* 10 byte result */
break;
case FDC_CMD_READ_ID:
pCMD->cmd[COMMAND]|=(FDC_MFM_MODE<<6); /* set MFM bit */
pCMD->cmdlen=FDC_CMD_READ_ID_LEN;
pCMD->resultlen=7; /* 7 byte result */
break;
case FDC_CMD_RECALIBRATE:
pCMD->cmd[DRIVE]&=0x03; /* don't set the head bit */
pCMD->cmdlen=FDC_CMD_RECALIBRATE_LEN;
pCMD->resultlen=0; /* no result */
break;
break;
case FDC_CMD_SENSE_INT:
pCMD->cmdlen=FDC_CMD_SENSE_INT_LEN;
pCMD->resultlen=2;
break;
}
for(i=0;i<pCMD->cmdlen;i++) {
/* PRINTF("write cmd%d = 0x%02X\n",i,pCMD->cmd[i]); */
if (write_fdc_byte(pCMD->cmd[i]) == false) {
PRINTF("Error: timeout while issue cmd%d\n",i);
return false;
}
}
timeout=FDC_TIME_OUT;
for(i=0;i<pCMD->resultlen;i++) {
while((read_fdc_reg(FDC_MSR)&0xC0)!=0xC0) {
timeout--;
if(timeout==0) {
PRINTF(" timeout while reading result%d MSR=0x%02X\n",i,read_fdc_reg(FDC_MSR));
return false;
}
}
pCMD->result[i]=(unsigned char)read_fdc_byte();
}
return true;
}
/* selects the drive assigned in the cmd structur and
switches on the Motor */
void select_fdc_drive(FDC_COMMAND_STRUCT *pCMD)
{
unsigned char val;
val=(1<<(4+pCMD->drive))|pCMD->drive|0xC; /* set reset, dma gate and motor bits */
if((read_fdc_reg(FDC_DOR)&val)!=val) {
write_fdc_reg(FDC_DOR,val);
for(val=0;val<255;val++)
udelay(500); /* wait some time to start motor */
}
}
/* switches off the Motor of the specified drive */
void stop_fdc_drive(FDC_COMMAND_STRUCT *pCMD)
{
unsigned char val;
val=(1<<(4+pCMD->drive))|pCMD->drive; /* sets motor bits */
write_fdc_reg(FDC_DOR,(read_fdc_reg(FDC_DOR)&~val));
}
/* issues a recalibrate command, waits for interrupt and
* issues a sense_interrupt */
int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
{
pCMD->cmd[COMMAND]=FDC_CMD_RECALIBRATE;
if (fdc_issue_cmd(pCMD, pFG) == false)
return false;
while (wait_for_fdc_int() != true);
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
return(fdc_issue_cmd(pCMD,pFG));
}
/* issues a recalibrate command, waits for interrupt and
* issues a sense_interrupt */
int fdc_seek(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG)
{
pCMD->cmd[COMMAND]=FDC_CMD_SEEK;
if (fdc_issue_cmd(pCMD, pFG) == false)
return false;
while (wait_for_fdc_int() != true);
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
return(fdc_issue_cmd(pCMD,pFG));
}
/* terminates current command, by not servicing the FIFO
* waits for interrupt and fills in the result bytes */
int fdc_terminate(FDC_COMMAND_STRUCT *pCMD)
{
int i;
for(i=0;i<100;i++)
udelay(500); /* wait 500usec for fifo overrun */
while((read_fdc_reg(FDC_SRA)&0x80)==0x00); /* wait as long as no int has occurred */
for(i=0;i<7;i++) {
pCMD->result[i]=(unsigned char)read_fdc_byte();
}
return true;
}
/* reads data from FDC, seek commands are issued automatic */
int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
{
/* first seek to start address */
unsigned long len,readblk,i,timeout,ii,offset;
unsigned char c,retriesrw,retriescal;
unsigned char *bufferw; /* working buffer */
int sect_size;
int flags;
flags=disable_interrupts(); /* switch off all Interrupts */
select_fdc_drive(pCMD); /* switch on drive */
sect_size=0x080<<pFG->sect_code;
retriesrw=0;
retriescal=0;
offset=0;
if (fdc_seek(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
return false;
}
if((pCMD->result[STATUS_0]&0x20)!=0x20) {
printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
return false;
}
/* now determine the next seek point */
/* lastblk=pCMD->blnr + blocks; */
/* readblk=(pFG->head*pFG->sect)-(pCMD->blnr%(pFG->head*pFG->sect)); */
readblk=pFG->sect-(pCMD->blnr%pFG->sect);
PRINTF("1st nr of block possible read %ld start %ld\n",readblk,pCMD->blnr);
if(readblk>blocks) /* is end within 1st track */
readblk=blocks; /* yes, correct it */
PRINTF("we read %ld blocks start %ld\n",readblk,pCMD->blnr);
bufferw = &buffer[0]; /* setup working buffer */
do {
retryrw:
len=sect_size * readblk;
pCMD->cmd[COMMAND]=FDC_CMD_READ;
if (fdc_issue_cmd(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
return false;
}
for (i=0;i<len;i++) {
timeout=FDC_TIME_OUT;
do {
c=read_fdc_reg(FDC_MSR);
if((c&0xC0)==0xC0) {
bufferw[i]=read_fdc_reg(FDC_FIFO);
break;
}
if((c&0xC0)==0x80) { /* output */
PRINTF("Transfer error transferred: at %ld, MSR=%02X\n",i,c);
if(i>6) {
for(ii=0;ii<7;ii++) {
pCMD->result[ii]=bufferw[(i-7+ii)];
} /* for */
}
if(retriesrw++>FDC_RW_RETRIES) {
if (retriescal++>FDC_CAL_RETRIES) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
return false;
}
else {
PRINTF(" trying to recalibrate Try %d\n",retriescal);
if (fdc_recalibrate(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
return false;
}
retriesrw=0;
goto retrycal;
} /* else >FDC_CAL_RETRIES */
}
else {
PRINTF("Read retry %d\n",retriesrw);
goto retryrw;
} /* else >FDC_RW_RETRIES */
}/* if output */
timeout--;
} while (true);
} /* for len */
/* the last sector of a track or all data has been read,
* we need to get the results */
fdc_terminate(pCMD);
offset+=(sect_size*readblk); /* set up buffer pointer */
bufferw = &buffer[offset];
pCMD->blnr+=readblk; /* update current block nr */
blocks-=readblk; /* update blocks */
if(blocks==0)
break; /* we are finish */
/* setup new read blocks */
/* readblk=pFG->head*pFG->sect; */
readblk=pFG->sect;
if(readblk>blocks)
readblk=blocks;
retrycal:
/* a seek is necessary */
if (fdc_seek(pCMD, pFG) == false) {
stop_fdc_drive(pCMD);
if (flags)
enable_interrupts();
return false;
}
if((pCMD->result[STATUS_0]&0x20)!=0x20) {
PRINTF("Seek error Status: %02X\n",pCMD->result[STATUS_0]);
stop_fdc_drive(pCMD);
return false;
}
} while (true); /* start over */
stop_fdc_drive(pCMD); /* switch off drive */
if (flags)
enable_interrupts();
return true;
}
/* Scan all drives and check if drive is present and disk is inserted */
int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
{
int i,drives,state;
/* OK procedure of data book is satisfied.
* trying to get some information over the drives */
state=0; /* no drives, no disks */
for(drives=0;drives<4;drives++) {
pCMD->drive=drives;
select_fdc_drive(pCMD);
pCMD->blnr=0; /* set to the 1st block */
if (fdc_recalibrate(pCMD, pFG) == false)
continue;
if((pCMD->result[STATUS_0]&0x10)==0x10)
continue;
/* ok drive connected check for disk */
state|=(1<<drives);
pCMD->blnr=pFG->size; /* set to the last block */
if (fdc_seek(pCMD, pFG) == false)
continue;
pCMD->blnr=0; /* set to the 1st block */
if (fdc_recalibrate(pCMD, pFG) == false)
continue;
pCMD->cmd[COMMAND]=FDC_CMD_READ_ID;
if (fdc_issue_cmd(pCMD, pFG) == false)
continue;
state|=(0x10<<drives);
}
stop_fdc_drive(pCMD);
for(i=0;i<4;i++) {
PRINTF("Floppy Drive %d %sconnected %sDisk inserted %s\n",i,
((state&(1<<i))==(1<<i)) ? "":"not ",
((state&(0x10<<i))==(0x10<<i)) ? "":"no ",
((state&(0x10<<i))==(0x10<<i)) ? pFG->name : "");
}
pCMD->flags=state;
return true;
}
/**************************************************************************
* int fdc_setup
* setup the fdc according the datasheet
* assuming in PS2 Mode
*/
int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
{
int i;
#ifdef CONFIG_SYS_FDC_HW_INIT
fdc_hw_init ();
#endif
/* first, we reset the FDC via the DOR */
write_fdc_reg(FDC_DOR,0x00);
for(i=0; i<255; i++) /* then we wait some time */
udelay(500);
/* then, we clear the reset in the DOR */
pCMD->drive=drive;
select_fdc_drive(pCMD);
/* initialize the CCR */
write_fdc_reg(FDC_CCR,pFG->rate);
/* then initialize the DSR */
write_fdc_reg(FDC_DSR,pFG->rate);
if (wait_for_fdc_int() == false) {
PRINTF("Time Out after writing CCR\n");
return false;
}
/* now issue sense Interrupt and status command
* assuming only one drive present (drive 0) */
pCMD->dma=0; /* we don't use any dma at all */
for(i=0;i<4;i++) {
/* issue sense interrupt for all 4 possible drives */
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
if (fdc_issue_cmd(pCMD, pFG) == false) {
PRINTF("Sense Interrupt for drive %d failed\n",i);
}
}
/* issue the configure command */
pCMD->drive=drive;
select_fdc_drive(pCMD);
pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
if (fdc_issue_cmd(pCMD, pFG) == false) {
PRINTF(" configure timeout\n");
stop_fdc_drive(pCMD);
return false;
}
/* issue specify command */
pCMD->cmd[COMMAND]=FDC_CMD_SPECIFY;
if (fdc_issue_cmd(pCMD, pFG) == false) {
PRINTF(" specify timeout\n");
stop_fdc_drive(pCMD);
return false;
}
/* then, we clear the reset in the DOR */
/* fdc_check_drive(pCMD,pFG); */
/* write_fdc_reg(FDC_DOR,0x04); */
return true;
}
/****************************************************************************
* main routine do_fdcboot
*/
int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
FDC_COMMAND_STRUCT *pCMD = &cmd;
unsigned long addr,imsize;
#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
image_header_t *hdr; /* used for fdc boot */
#endif
unsigned char boot_drive;
int i,nrofblk;
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
switch (argc) {
case 1:
addr = CONFIG_SYS_LOAD_ADDR;
boot_drive=CONFIG_SYS_FDC_DRIVE_NUMBER;
break;
case 2:
addr = simple_strtoul(argv[1], NULL, 16);
boot_drive=CONFIG_SYS_FDC_DRIVE_NUMBER;
break;
case 3:
addr = simple_strtoul(argv[1], NULL, 16);
boot_drive=simple_strtoul(argv[2], NULL, 10);
break;
default:
return CMD_RET_USAGE;
}
/* setup FDC and scan for drives */
if (fdc_setup(boot_drive, pCMD, pFG) == false) {
printf("\n** Error in setup FDC **\n");
return 1;
}
if (fdc_check_drive(pCMD, pFG) == false) {
printf("\n** Error in check_drives **\n");
return 1;
}
if((pCMD->flags&(1<<boot_drive))==0) {
/* drive not available */
printf("\n** Drive %d not availabe **\n",boot_drive);
return 1;
}
if((pCMD->flags&(0x10<<boot_drive))==0) {
/* no disk inserted */
printf("\n** No disk inserted in drive %d **\n",boot_drive);
return 1;
}
/* ok, we have a valid source */
pCMD->drive=boot_drive;
/* read first block */
pCMD->blnr=0;
if (fdc_read_data((unsigned char *)addr, 1, pCMD, pFG) == false) {
printf("\nRead error:");
for(i=0;i<7;i++)
printf("result%d: 0x%02X\n",i,pCMD->result[i]);
return 1;
}
switch (genimg_get_format ((void *)addr)) {
#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
image_print_contents (hdr);
imsize = image_get_image_size (hdr);
break;
#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *)addr;
puts ("Fit image detected...\n");
imsize = fit_get_size (fit_hdr);
break;
#endif
default:
puts ("** Unknown image type\n");
return 1;
}
nrofblk=imsize/512;
if((imsize%512)>0)
nrofblk++;
printf("Loading %ld Bytes (%d blocks) at 0x%08lx..\n",imsize,nrofblk,addr);
pCMD->blnr=0;
if (fdc_read_data((unsigned char *)addr, nrofblk, pCMD, pFG) == false) {
/* read image block */
printf("\nRead error:");
for(i=0;i<7;i++)
printf("result%d: 0x%02X\n",i,pCMD->result[i]);
return 1;
}
printf("OK %ld Bytes loaded.\n",imsize);
flush_cache (addr, imsize);
#if defined(CONFIG_FIT)
/* This cannot be done earlier, we need complete FIT image in RAM first */
if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
if (!fit_check_format (fit_hdr)) {
puts ("** Bad FIT image format\n");
return 1;
}
fit_print_contents (fit_hdr);
}
#endif
/* Loading ok, update default load address */
load_addr = addr;
return bootm_maybe_autostart(cmdtp, argv[0]);
}
U_BOOT_CMD(
fdcboot, 3, 1, do_fdcboot,
"boot from floppy device",
"loadAddr drive"
);

1
drivers/misc/Makefile
View file

@ -51,7 +51,6 @@ obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o

100
drivers/misc/ns87308.c
View file

@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*/
#include <config.h>
#include <ns87308.h>
void initialise_ns87308 (void)
{
#ifdef CONFIG_SYS_NS87308_PS2MOD
unsigned char data;
/*
* Switch floppy drive to PS/2 mode.
*/
read_pnp_config(SUPOERIO_CONF1, &data);
data &= 0xFB;
write_pnp_config(SUPOERIO_CONF1, data);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_KBC1)
PNP_SET_DEVICE_BASE(LDEV_KBC1, CONFIG_SYS_NS87308_KBC1_BASE);
write_pnp_config(LUN_CONFIG_REG, 0);
write_pnp_config(CBASE_HIGH, 0x00);
write_pnp_config(CBASE_LOW, 0x64);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_MOUSE)
PNP_ACTIVATE_DEVICE(LDEV_MOUSE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RTC_APC)
PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CONFIG_SYS_NS87308_RTC_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_FDC)
PNP_SET_DEVICE_BASE(LDEV_FDC, CONFIG_SYS_NS87308_FDC_BASE);
write_pnp_config(LUN_CONFIG_REG, 0x40);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RARP)
PNP_SET_DEVICE_BASE(LDEV_PARP, CONFIG_SYS_NS87308_LPT_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART1)
PNP_SET_DEVICE_BASE(LDEV_UART1, CONFIG_SYS_NS87308_UART1_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART2)
PNP_SET_DEVICE_BASE(LDEV_UART2, CONFIG_SYS_NS87308_UART2_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_GPIO)
PNP_SET_DEVICE_BASE(LDEV_GPIO, CONFIG_SYS_NS87308_GPIO_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_POWRMAN)
#ifndef CONFIG_SYS_NS87308_PWMAN_BASE
PNP_ACTIVATE_DEVICE(LDEV_POWRMAN);
#else
PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CONFIG_SYS_NS87308_PWMAN_BASE);
/*
* Enable all units
*/
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER1, 0x7d);
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER2, 0x87);
#ifdef CONFIG_SYS_NS87308_PMC1
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC1, CONFIG_SYS_NS87308_PMC1);
#endif
#ifdef CONFIG_SYS_NS87308_PMC2
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC2, CONFIG_SYS_NS87308_PMC2);
#endif
#ifdef CONFIG_SYS_NS87308_PMC3
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC3, CONFIG_SYS_NS87308_PMC3);
#endif
#endif
#endif
#ifdef CONFIG_SYS_NS87308_CS0_BASE
PNP_PGCS_CSLINE_BASE(0, CONFIG_SYS_NS87308_CS0_BASE);
PNP_PGCS_CSLINE_CONF(0, CONFIG_SYS_NS87308_CS0_CONF);
#endif
#ifdef CONFIG_SYS_NS87308_CS1_BASE
PNP_PGCS_CSLINE_BASE(1, CONFIG_SYS_NS87308_CS1_BASE);
PNP_PGCS_CSLINE_CONF(1, CONFIG_SYS_NS87308_CS1_CONF);
#endif
#ifdef CONFIG_SYS_NS87308_CS2_BASE
PNP_PGCS_CSLINE_BASE(2, CONFIG_SYS_NS87308_CS2_BASE);
PNP_PGCS_CSLINE_CONF(2, CONFIG_SYS_NS87308_CS2_CONF);
#endif
}

7
drivers/serial/serial_ns16550.c
View file

@ -5,14 +5,9 @@
*/
#include <common.h>
#include <linux/compiler.h>
#include <ns16550.h>
#ifdef CONFIG_NS87308
#include <ns87308.h>
#endif
#include <serial.h>
#include <linux/compiler.h>
#ifndef CONFIG_NS16550_MIN_FUNCTIONS

1
include/common.h
View file

@ -89,7 +89,6 @@ phys_size_t get_effective_memsize(void);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
void fdc_hw_init (void);
#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR

233
include/ns87308.h
View file

@ -1,233 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*/
#ifndef _NS87308_H_
#define _NS87308_H_
#include <asm/pci_io.h>
/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
void initialise_ns87308(void);
/*
* The following struct represents the GPIO registers on the NS87308/NS97307
*/
struct GPIO
{
unsigned char dta1; /* 0 data port 1 */
unsigned char dir1; /* 1 direction port 1 */
unsigned char out1; /* 2 output type port 1 */
unsigned char puc1; /* 3 pull-up control port 1 */
unsigned char dta2; /* 4 data port 2 */
unsigned char dir2; /* 5 direction port 2 */
unsigned char out2; /* 6 output type port 2 */
unsigned char puc2; /* 7 pull-up control port 2 */
};
/*
* The following represents the power management registers on the NS87308/NS97307
*/
#define PWM_FER1 0 /* 0 function enable reg. 1 */
#define PWM_FER2 1 /* 1 function enable reg. 2 */
#define PWM_PMC1 2 /* 2 power mgmt. control 1 */
#define PWM_PMC2 3 /* 3 power mgmt. control 2 */
#define PWM_PMC3 4 /* 4 power mgmt. control 3 */
#define PWM_WDTO 5 /* 5 watchdog time-out */
#define PWM_WDCF 6 /* 6 watchdog config. */
#define PWM_WDST 7 /* 7 watchdog status */
/*PNP config registers:
* these depend on the stated of BADDR1 and BADDR0 on startup
* so there's three versions here with the last two digits indicating
* for which configuration their valid
* the 1st of the two digits indicates the state of BADDR1
* the 2st of the two digits indicates the state of BADDR0
*/
#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
#if defined(CONFIG_SYS_NS87308_BADDR_0x)
#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
#elif defined(CONFIG_SYS_NS87308_BADDR_10)
#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
#elif defined(CONFIG_SYS_NS87308_BADDR_11)
#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
#endif
/* PnP register definitions */
#define SET_RD_DATA_PORT 0x00
#define SERIAL_ISOLATION 0x01
#define CONFIG_CONTROL 0x02
#define WAKE_CSN 0x03
#define RES_DATA 0x04
#define STATUS 0x05
#define SET_CSN 0x06
#define LOGICAL_DEVICE 0x07
/*vendor defined values */
#define SID_REG 0x20
#define SUPOERIO_CONF1 0x21
#define SUPOERIO_CONF2 0x22
#define PGCS_INDEX 0x23
#define PGCS_DATA 0x24
/* values above 30 are different for each logical device
but I can't be arsed to enter them all. the ones here
are pretty consistent between all logical devices
feel free to correct the situation if you want.. ;)
*/
#define ACTIVATE 0x30
#define ACTIVATE_OFF 0x00
#define ACTIVATE_ON 0x01
#define BASE_ADDR_HIGH 0x60
#define BASE_ADDR_LOW 0x61
#define LUN_CONFIG_REG 0xF0
#define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
#define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
#define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
#define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
/* the logical devices*/
#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
#define LDEV_KBC2 0x01
#define LDEV_MOUSE 0x01
#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
#define LDEV_FDC 0x03 /*floppy disk controller*/
#define LDEV_PARP 0x04 /*Parallel port*/
#define LDEV_UART2 0x05
#define LDEV_UART1 0x06
#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
#define LDEV_POWRMAN 0x08 /*Power Managment*/
#define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
#define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
#define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
#define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
#define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
#define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
#define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
#define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
#define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
#define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
/*some functions and macro's for doing configuration */
static inline void read_pnp_config(unsigned char index, unsigned char *data)
{
pci_writeb(index,IO_INDEX);
pci_readb(IO_DATA, *data);
}
static inline void write_pnp_config(unsigned char index, unsigned char data)
{
pci_writeb(index,IO_INDEX);
pci_writeb(data, IO_DATA);
}
static inline void pnp_set_device(unsigned char dev)
{
write_pnp_config(LOGICAL_DEVICE, dev);
}
static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
{
pci_writeb(index, CONFIG_SYS_ISA_IO + base);
eieio();
pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
}
/*void write_pnp_config(unsigned char index, unsigned char data);
void pnp_set_device(unsigned char dev);
*/
#define PNP_SET_DEVICE_BASE(dev,base) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
write_pnp_config(ACTIVATE, ACTIVATE_ON);
#define PNP_ACTIVATE_DEVICE(dev) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_ON);
#define PNP_DEACTIVATE_DEVICE(dev) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_OFF);
static inline void write_pgcs_config(unsigned char index, unsigned char data)
{
write_pnp_config(PGCS_INDEX, index);
write_pnp_config(PGCS_DATA, data);
}
/* these macrose configure the 3 CS lines
on the sandpoint board these controll NVRAM
CS0 is connected to NVRAMCS
CS1 is connected to NVRAMAS0
CS2 is connected to NVRAMAS1
*/
#define PGCS_CS_ASSERT_ON_WRITE 0x10
#define PGCS_CS_ASSERT_ON_READ 0x20
#define PNP_PGCS_CSLINE_BASE(cs, base) \
write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
#define PNP_PGCS_CSLINE_CONF(cs, conf) \
write_pgcs_config(((cs) << 2) + 2, (conf) );
/* The following sections are for 87308 extensions to the standard compoents it emulates */
/* extensions to 16550*/
#define MCR_MDSL_MSK 0xe0 /*mode select mask*/
#define MCR_MDSL_UART 0x00 /*uart, default*/
#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
#define MCR_MDSL_SIR 0x03 /*SIR*/
#define MCR_MDSL_CIR 0x06 /*Consumer IR*/
#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
#define FCR_TXFTH1 0x20 /* for interrupt trigger */
/*
* Default NS87308 configuration
*/
#ifndef CONFIG_SYS_NS87308_KBC1_BASE
#define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
#endif
#ifndef CONFIG_SYS_NS87308_RTC_BASE
#define CONFIG_SYS_NS87308_RTC_BASE 0x0070
#endif
#ifndef CONFIG_SYS_NS87308_FDC_BASE
#define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
#endif
#ifndef CONFIG_SYS_NS87308_LPT_BASE
#define CONFIG_SYS_NS87308_LPT_BASE 0x0278
#endif
#ifndef CONFIG_SYS_NS87308_UART1_BASE
#define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
#endif
#ifndef CONFIG_SYS_NS87308_UART2_BASE
#define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
#endif
#endif /*_NS87308_H_*/

34
scripts/config_whitelist.txt
View file

@ -1236,7 +1236,6 @@ CONFIG_NO_WAIT
CONFIG_NR_DRAM_POPULATED
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
CONFIG_NS87308
CONFIG_NUM_DSP_CPUS
CONFIG_NUM_PAMU
CONFIG_ODROID_REV_AIN
@ -2291,8 +2290,6 @@ CONFIG_SYS_FAST_CLK
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
CONFIG_SYS_FAULT_MII_ADDR
CONFIG_SYS_FCC_PSMR
CONFIG_SYS_FDC_DRIVE_NUMBER
CONFIG_SYS_FDC_HW_INIT
CONFIG_SYS_FDT_BASE
CONFIG_SYS_FDT_LOAD_ADDR
CONFIG_SYS_FDT_PAD
@ -2967,8 +2964,6 @@ CONFIG_SYS_IO_BASE
CONFIG_SYS_ISA_BASE
CONFIG_SYS_ISA_IO
CONFIG_SYS_ISA_IO_BASE_ADDRESS
CONFIG_SYS_ISA_IO_OFFSET
CONFIG_SYS_ISA_IO_STRIDE
CONFIG_SYS_ISA_MEM
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
@ -3328,35 +3323,6 @@ CONFIG_SYS_NS16550_MEM32
CONFIG_SYS_NS16550_PORT_MAPPED
CONFIG_SYS_NS16550_REG_SIZE
CONFIG_SYS_NS16550_SERIAL
CONFIG_SYS_NS87308_CS0_BASE
CONFIG_SYS_NS87308_CS0_CONF
CONFIG_SYS_NS87308_CS1_BASE
CONFIG_SYS_NS87308_CS1_CONF
CONFIG_SYS_NS87308_CS2_BASE
CONFIG_SYS_NS87308_CS2_CONF
CONFIG_SYS_NS87308_FDC
CONFIG_SYS_NS87308_FDC_BASE
CONFIG_SYS_NS87308_GPIO
CONFIG_SYS_NS87308_GPIO_BASE
CONFIG_SYS_NS87308_KBC1
CONFIG_SYS_NS87308_KBC1_BASE
CONFIG_SYS_NS87308_KBC2
CONFIG_SYS_NS87308_LPT_BASE
CONFIG_SYS_NS87308_MOUSE
CONFIG_SYS_NS87308_PARP
CONFIG_SYS_NS87308_PMC1
CONFIG_SYS_NS87308_PMC2
CONFIG_SYS_NS87308_PMC3
CONFIG_SYS_NS87308_POWRMAN
CONFIG_SYS_NS87308_PS2MOD
CONFIG_SYS_NS87308_PWMAN_BASE
CONFIG_SYS_NS87308_RARP
CONFIG_SYS_NS87308_RTC_APC
CONFIG_SYS_NS87308_RTC_BASE
CONFIG_SYS_NS87308_UART1
CONFIG_SYS_NS87308_UART1_BASE
CONFIG_SYS_NS87308_UART2
CONFIG_SYS_NS87308_UART2_BASE
CONFIG_SYS_NUM_ADDR_MAP
CONFIG_SYS_NUM_CPC
CONFIG_SYS_NUM_FM1_10GEC