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fpga: virtex2: cosmetic: Cleanup code style

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Address Checkpatch warnings in virtex2 code prior to making other
changes. No functional change intended.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Robert Hancock 2019-06-18 09:47:12 -06:00 • committed by Michal Simek
parent ac80ac09c8
commit fa57af0552
1 changed files with 136 additions and 134 deletions
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228
drivers/fpga/virtex2.c
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@ -19,16 +19,16 @@
#endif #endif
#ifdef FPGA_DEBUG #ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args) #define PRINTF(fmt, args...) printf(fmt, ##args)
#else #else
#define PRINTF(fmt,args...) #define PRINTF(fmt, args...)
#endif #endif
/* /*
* If the SelectMap interface can be overrun by the processor, define * If the SelectMap interface can be overrun by the processor, define
* CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
* file and add board-specific support for checking BUSY status. By default, * configuration file and add board-specific support for checking BUSY status.
* assume that the SelectMap interface cannot be overrun. * By default, assume that the SelectMap interface cannot be overrun.
*/ */
#ifndef CONFIG_SYS_FPGA_CHECK_BUSY #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_CHECK_BUSY #undef CONFIG_SYS_FPGA_CHECK_BUSY
@ -65,7 +65,7 @@
* an XC2V1000, if anyone can ever get ahold of one. * an XC2V1000, if anyone can ever get ahold of one.
*/ */
#ifndef CONFIG_SYS_FPGA_WAIT_INIT #ifndef CONFIG_SYS_FPGA_WAIT_INIT
#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */ #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
#endif #endif
/* /*
@ -74,14 +74,14 @@
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/ */
#ifndef CONFIG_SYS_FPGA_WAIT_BUSY #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/ #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
#endif #endif
/* Default timeout for waiting for FPGA to enter operational mode after /* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written. * configuration data has been written.
*/ */
#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
#endif #endif
static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
@ -97,18 +97,18 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
switch (desc->iface) { switch (desc->iface) {
case slave_serial: case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); PRINTF("%s: Launching Slave Serial Load\n", __func__);
ret_val = virtex2_ss_load(desc, buf, bsize); ret_val = virtex2_ss_load(desc, buf, bsize);
break; break;
case slave_selectmap: case slave_selectmap:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); PRINTF("%s: Launching Slave Parallel Load\n", __func__);
ret_val = virtex2_ssm_load(desc, buf, bsize); ret_val = virtex2_ssm_load(desc, buf, bsize);
break; break;
default: default:
printf ("%s: Unsupported interface type, %d\n", printf("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface); __func__, desc->iface);
} }
return ret_val; return ret_val;
} }
@ -119,18 +119,18 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) { switch (desc->iface) {
case slave_serial: case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); PRINTF("%s: Launching Slave Serial Dump\n", __func__);
ret_val = virtex2_ss_dump(desc, buf, bsize); ret_val = virtex2_ss_dump(desc, buf, bsize);
break; break;
case slave_parallel: case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
ret_val = virtex2_ssm_dump(desc, buf, bsize); ret_val = virtex2_ssm_dump(desc, buf, bsize);
break; break;
default: default:
printf ("%s: Unsupported interface type, %d\n", printf("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface); __func__, desc->iface);
} }
return ret_val; return ret_val;
} }
@ -159,26 +159,26 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
int ret_val = FPGA_FAIL; int ret_val = FPGA_FAIL;
xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
__FUNCTION__, __LINE__, fn); __func__, __LINE__, fn);
if (fn) { if (fn) {
size_t bytecount = 0; size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf; unsigned char *data = (unsigned char *)buf;
int cookie = desc->cookie; int cookie = desc->cookie;
unsigned long ts; unsigned long ts;
/* Gotta split this one up (so the stack won't blow??) */ /* Gotta split this one up (so the stack won't blow??) */
PRINTF ("%s:%d: Function Table:\n" PRINTF("%s:%d: Function Table:\n"
" base 0x%p\n" " base 0x%p\n"
" struct 0x%p\n" " struct 0x%p\n"
" pre 0x%p\n" " pre 0x%p\n"
" prog 0x%p\n" " prog 0x%p\n"
" init 0x%p\n" " init 0x%p\n"
" error 0x%p\n", " error 0x%p\n",
__FUNCTION__, __LINE__, __func__, __LINE__,
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err); &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
PRINTF (" clock 0x%p\n" PRINTF(" clock 0x%p\n"
" cs 0x%p\n" " cs 0x%p\n"
" write 0x%p\n" " write 0x%p\n"
" rdata 0x%p\n" " rdata 0x%p\n"
@ -190,104 +190,104 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
fn->busy, fn->abort, fn->post); fn->busy, fn->abort, fn->post);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Initializing FPGA Device %d...\n", cookie); printf("Initializing FPGA Device %d...\n", cookie);
#endif #endif
/* /*
* Run the pre configuration function if there is one. * Run the pre configuration function if there is one.
*/ */
if (*fn->pre) { if (*fn->pre)
(*fn->pre) (cookie); (*fn->pre)(cookie);
}
/* /*
* Assert the program line. The minimum pulse width for * Assert the program line. The minimum pulse width for
* Virtex II devices is 300 nS (Tprogram parameter in datasheet). * Virtex II devices is 300 nS (Tprogram parameter in
* There is no maximum value for the pulse width. Check to make * datasheet). There is no maximum value for the pulse width.
* sure that INIT_B goes low after assertion of PROG_B * Check to make sure that INIT_B goes low after assertion of
* PROG_B
*/ */
(*fn->pgm) (true, true, cookie); (*fn->pgm)(true, true, cookie);
udelay (10); udelay(10);
ts = get_timer (0); ts = get_timer(0);
do { do {
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
" to assert.\n", __FUNCTION__, __LINE__, __func__, __LINE__,
CONFIG_SYS_FPGA_WAIT_INIT); CONFIG_SYS_FPGA_WAIT_INIT);
(*fn->abort) (cookie); (*fn->abort)(cookie);
return FPGA_FAIL; return FPGA_FAIL;
} }
} while (!(*fn->init) (cookie)); } while (!(*fn->init)(cookie));
(*fn->pgm) (false, true, cookie); (*fn->pgm)(false, true, cookie);
CONFIG_FPGA_DELAY (); CONFIG_FPGA_DELAY();
(*fn->clk) (true, true, cookie); (*fn->clk)(true, true, cookie);
/* /*
* Start a timer and wait for INIT_B to go high * Start a timer and wait for INIT_B to go high
*/ */
ts = get_timer (0); ts = get_timer(0);
do { do {
CONFIG_FPGA_DELAY (); CONFIG_FPGA_DELAY();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
" to deassert.\n", __FUNCTION__, __LINE__, __func__, __LINE__,
CONFIG_SYS_FPGA_WAIT_INIT); CONFIG_SYS_FPGA_WAIT_INIT);
(*fn->abort) (cookie); (*fn->abort)(cookie);
return FPGA_FAIL; return FPGA_FAIL;
} }
} while ((*fn->init) (cookie) && (*fn->busy) (cookie)); } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
(*fn->wr) (true, true, cookie); (*fn->wr)(true, true, cookie);
(*fn->cs) (true, true, cookie); (*fn->cs)(true, true, cookie);
udelay (10000); mdelay(10);
/* /*
* Load the data byte by byte * Load the data byte by byte
*/ */
while (bytecount < bsize) { while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
if (ctrlc ()) { if (ctrlc()) {
(*fn->abort) (cookie); (*fn->abort)(cookie);
return FPGA_FAIL; return FPGA_FAIL;
} }
#endif #endif
if ((*fn->done) (cookie) == FPGA_SUCCESS) { if ((*fn->done)(cookie) == FPGA_SUCCESS) {
PRINTF ("%s:%d:done went active early, bytecount = %d\n", PRINTF("%s:%d:done went active early, bytecount = %d\n",
__FUNCTION__, __LINE__, bytecount); __func__, __LINE__, bytecount);
break; break;
} }
#ifdef CONFIG_SYS_FPGA_CHECK_ERROR #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
if ((*fn->init) (cookie)) { if ((*fn->init)(cookie)) {
printf ("\n%s:%d: ** Error: INIT asserted during" printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
" configuration\n", __FUNCTION__, __LINE__); __func__, __LINE__);
printf ("%d = buffer offset, %d = buffer size\n", printf("%d = buffer offset, %d = buffer size\n",
bytecount, bsize); bytecount, bsize);
(*fn->abort) (cookie); (*fn->abort)(cookie);
return FPGA_FAIL; return FPGA_FAIL;
} }
#endif #endif
(*fn->wdata) (data[bytecount++], true, cookie); (*fn->wdata)(data[bytecount++], true, cookie);
CONFIG_FPGA_DELAY (); CONFIG_FPGA_DELAY();
/* /*
* Cycle the clock pin * Cycle the clock pin
*/ */
(*fn->clk) (false, true, cookie); (*fn->clk)(false, true, cookie);
CONFIG_FPGA_DELAY (); CONFIG_FPGA_DELAY();
(*fn->clk) (true, true, cookie); (*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0); ts = get_timer(0);
while ((*fn->busy) (cookie)) { while ((*fn->busy)(cookie)) {
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
printf ("%s:%d: ** Timeout after %d ticks waiting for" printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
" BUSY to deassert\n", __func__, __LINE__,
__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY); CONFIG_SYS_FPGA_WAIT_BUSY);
(*fn->abort) (cookie); (*fn->abort)(cookie);
return FPGA_FAIL; return FPGA_FAIL;
} }
} }
@ -295,33 +295,35 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0) if (bytecount % (bsize / 40) == 0)
putc ('.'); putc('.');
#endif #endif
} }
/* /*
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals. * Finished writing the data; deassert FPGA CS_B and WRITE_B
* signals.
*/ */
CONFIG_FPGA_DELAY (); CONFIG_FPGA_DELAY();
(*fn->cs) (false, true, cookie); (*fn->cs)(false, true, cookie);
(*fn->wr) (false, true, cookie); (*fn->wr)(false, true, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); putc('\n');
#endif #endif
/* /*
* Check for successful configuration. FPGA INIT_B and DONE should * Check for successful configuration. FPGA INIT_B and DONE
* both be high upon successful configuration. * should both be high upon successful configuration.
*/ */
ts = get_timer (0); ts = get_timer(0);
ret_val = FPGA_SUCCESS; ret_val = FPGA_SUCCESS;
while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { while (((*fn->done)(cookie) == FPGA_FAIL) ||
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { (*fn->init)(cookie)) {
printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to" if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
"assert and INIT to deassert\n", printf("%s:%d: ** Timeout after %d ticks waiting for DONE toassert and INIT to deassert\n",
__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); __func__, __LINE__,
(*fn->abort) (cookie); CONFIG_SYS_FPGA_WAIT_CONFIG);
(*fn->abort)(cookie);
ret_val = FPGA_FAIL; ret_val = FPGA_FAIL;
break; break;
} }
@ -329,23 +331,23 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
if (ret_val == FPGA_SUCCESS) { if (ret_val == FPGA_SUCCESS) {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Initialization of FPGA device %d complete\n", cookie); printf("Initialization of FPGA device %d complete\n",
cookie);
#endif #endif
/* /*
* Run the post configuration function if there is one. * Run the post configuration function if there is one.
*/ */
if (*fn->post) { if (*fn->post)
(*fn->post) (cookie); (*fn->post)(cookie);
}
} else { } else {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("** Initialization of FPGA device %d FAILED\n", printf("** Initialization of FPGA device %d FAILED\n",
cookie); cookie);
#endif #endif
} }
} else { } else {
printf ("%s:%d: NULL Interface function table!\n", printf("%s:%d: NULL Interface function table!\n",
__FUNCTION__, __LINE__); __func__, __LINE__);
} }
return ret_val; return ret_val;
} }
@ -359,61 +361,61 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
if (fn) { if (fn) {
unsigned char *data = (unsigned char *) buf; unsigned char *data = (unsigned char *)buf;
size_t bytecount = 0; size_t bytecount = 0;
int cookie = desc->cookie; int cookie = desc->cookie;
printf ("Starting Dump of FPGA Device %d...\n", cookie); printf("Starting Dump of FPGA Device %d...\n", cookie);
(*fn->cs) (true, true, cookie); (*fn->cs)(true, true, cookie);
(*fn->clk) (true, true, cookie); (*fn->clk)(true, true, cookie);
while (bytecount < bsize) { while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
if (ctrlc ()) { if (ctrlc()) {
(*fn->abort) (cookie); (*fn->abort)(cookie);
return FPGA_FAIL; return FPGA_FAIL;
} }
#endif #endif
/* /*
* Cycle the clock and read the data * Cycle the clock and read the data
*/ */
(*fn->clk) (false, true, cookie); (*fn->clk)(false, true, cookie);
(*fn->clk) (true, true, cookie); (*fn->clk)(true, true, cookie);
(*fn->rdata) (&(data[bytecount++]), cookie); (*fn->rdata)(&data[bytecount++], cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0) if (bytecount % (bsize / 40) == 0)
putc ('.'); putc('.');
#endif #endif
} }
/* /*
* Deassert CS_B and cycle the clock to deselect the device. * Deassert CS_B and cycle the clock to deselect the device.
*/ */
(*fn->cs) (false, false, cookie); (*fn->cs)(false, false, cookie);
(*fn->clk) (false, true, cookie); (*fn->clk)(false, true, cookie);
(*fn->clk) (true, true, cookie); (*fn->clk)(true, true, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); putc('\n');
#endif #endif
puts ("Done.\n"); puts("Done.\n");
} else { } else {
printf ("%s:%d: NULL Interface function table!\n", printf("%s:%d: NULL Interface function table!\n",
__FUNCTION__, __LINE__); __func__, __LINE__);
} }
return ret_val; return ret_val;
} }
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{ {
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); printf("%s: Slave Serial Loading is unsupported\n", __func__);
return FPGA_FAIL; return FPGA_FAIL;
} }
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{ {
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); printf("%s: Slave Serial Dumping is unsupported\n", __func__);
return FPGA_FAIL; return FPGA_FAIL;
} }