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fpga: virtex2: cosmetic: Cleanup code style

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Address Checkpatch warnings in virtex2 code prior to making other
changes. No functional change intended.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Robert Hancock 2019-06-18 09:47:12 -06:00 • committed by Michal Simek
parent ac80ac09c8
commit fa57af0552
1 changed files with 136 additions and 134 deletions
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86
drivers/fpga/virtex2.c
View file

@ -26,9 +26,9 @@
/*
* If the SelectMap interface can be overrun by the processor, define
* CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
* file and add board-specific support for checking BUSY status. By default,
* assume that the SelectMap interface cannot be overrun.
* CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
* configuration file and add board-specific support for checking BUSY status.
* By default, assume that the SelectMap interface cannot be overrun.
*/
#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_CHECK_BUSY
@ -97,18 +97,18 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
PRINTF("%s: Launching Slave Serial Load\n", __func__);
ret_val = virtex2_ss_load(desc, buf, bsize);
break;
case slave_selectmap:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
PRINTF("%s: Launching Slave Parallel Load\n", __func__);
ret_val = virtex2_ssm_load(desc, buf, bsize);
break;
default:
printf("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
__func__, desc->iface);
}
return ret_val;
}
@ -119,18 +119,18 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
PRINTF("%s: Launching Slave Serial Dump\n", __func__);
ret_val = virtex2_ss_dump(desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
ret_val = virtex2_ssm_dump(desc, buf, bsize);
break;
default:
printf("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
__func__, desc->iface);
}
return ret_val;
}
@ -160,7 +160,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
__FUNCTION__, __LINE__, fn);
__func__, __LINE__, fn);
if (fn) {
size_t bytecount = 0;
@ -176,7 +176,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
" prog 0x%p\n"
" init 0x%p\n"
" error 0x%p\n",
__FUNCTION__, __LINE__,
__func__, __LINE__,
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
PRINTF(" clock 0x%p\n"
" cs 0x%p\n"
@ -195,23 +195,23 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
if (*fn->pre)
(*fn->pre)(cookie);
}
/*
* Assert the program line. The minimum pulse width for
* Virtex II devices is 300 nS (Tprogram parameter in datasheet).
* There is no maximum value for the pulse width. Check to make
* sure that INIT_B goes low after assertion of PROG_B
* Virtex II devices is 300 nS (Tprogram parameter in
* datasheet). There is no maximum value for the pulse width.
* Check to make sure that INIT_B goes low after assertion of
* PROG_B
*/
(*fn->pgm)(true, true, cookie);
udelay(10);
ts = get_timer(0);
do {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to assert.\n", __FUNCTION__, __LINE__,
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
__func__, __LINE__,
CONFIG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
@ -229,8 +229,8 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
do {
CONFIG_FPGA_DELAY();
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to deassert.\n", __FUNCTION__, __LINE__,
printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
__func__, __LINE__,
CONFIG_SYS_FPGA_WAIT_INIT);
(*fn->abort)(cookie);
return FPGA_FAIL;
@ -240,7 +240,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
(*fn->wr)(true, true, cookie);
(*fn->cs)(true, true, cookie);
udelay (10000);
mdelay(10);
/*
* Load the data byte by byte
@ -255,14 +255,14 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
if ((*fn->done)(cookie) == FPGA_SUCCESS) {
PRINTF("%s:%d:done went active early, bytecount = %d\n",
__FUNCTION__, __LINE__, bytecount);
__func__, __LINE__, bytecount);
break;
}
#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
if ((*fn->init)(cookie)) {
printf ("\n%s:%d: ** Error: INIT asserted during"
" configuration\n", __FUNCTION__, __LINE__);
printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
__func__, __LINE__);
printf("%d = buffer offset, %d = buffer size\n",
bytecount, bsize);
(*fn->abort)(cookie);
@ -284,9 +284,9 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
ts = get_timer(0);
while ((*fn->busy)(cookie)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
printf ("%s:%d: ** Timeout after %d ticks waiting for"
" BUSY to deassert\n",
__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
__func__, __LINE__,
CONFIG_SYS_FPGA_WAIT_BUSY);
(*fn->abort)(cookie);
return FPGA_FAIL;
}
@ -300,7 +300,8 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
}
/*
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
* Finished writing the data; deassert FPGA CS_B and WRITE_B
* signals.
*/
CONFIG_FPGA_DELAY();
(*fn->cs)(false, true, cookie);
@ -311,16 +312,17 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
#endif
/*
* Check for successful configuration. FPGA INIT_B and DONE should
* both be high upon successful configuration.
* Check for successful configuration. FPGA INIT_B and DONE
* should both be high upon successful configuration.
*/
ts = get_timer(0);
ret_val = FPGA_SUCCESS;
while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
while (((*fn->done)(cookie) == FPGA_FAIL) ||
(*fn->init)(cookie)) {
if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
"assert and INIT to deassert\n",
__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
printf("%s:%d: ** Timeout after %d ticks waiting for DONE toassert and INIT to deassert\n",
__func__, __LINE__,
CONFIG_SYS_FPGA_WAIT_CONFIG);
(*fn->abort)(cookie);
ret_val = FPGA_FAIL;
break;
@ -329,14 +331,14 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
if (ret_val == FPGA_SUCCESS) {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Initialization of FPGA device %d complete\n", cookie);
printf("Initialization of FPGA device %d complete\n",
cookie);
#endif
/*
* Run the post configuration function if there is one.
*/
if (*fn->post) {
if (*fn->post)
(*fn->post)(cookie);
}
} else {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf("** Initialization of FPGA device %d FAILED\n",
@ -345,7 +347,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
}
} else {
printf("%s:%d: NULL Interface function table!\n",
__FUNCTION__, __LINE__);
__func__, __LINE__);
}
return ret_val;
}
@ -380,7 +382,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
*/
(*fn->clk)(false, true, cookie);
(*fn->clk)(true, true, cookie);
(*fn->rdata) (&(data[bytecount++]), cookie);
(*fn->rdata)(&data[bytecount++], cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc('.');
@ -400,20 +402,20 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
puts("Done.\n");
} else {
printf("%s:%d: NULL Interface function table!\n",
__FUNCTION__, __LINE__);
__func__, __LINE__);
}
return ret_val;
}
static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
printf("%s: Slave Serial Loading is unsupported\n", __func__);
return FPGA_FAIL;
}
static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
printf("%s: Slave Serial Dumping is unsupported\n", __func__);
return FPGA_FAIL;
}