GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 14:41:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

mxs: Convert sys_proto.h prefixes to 'mxs'

Browse source 
The sys_proto.h functions (except the boot modes) are compatible with
i.MX233 and i.MX28 so we use 'mxs' prefix for its methods.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Otavio Salvador 2012-08-13 09:53:12 +00:00 • committed by Albert ARIBAUD
parent af963ba8f4
commit fa7a51cb82
11 changed files with 44 additions and 44 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
arch/arm/cpu/arm926ejs/mxs/mxs.c
View file

@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* 1 second delay should be plenty of time for block reset. */ /* 1 second delay should be plenty of time for block reset. */
#define RESET_MAX_TIMEOUT 1000000 #define RESET_MAX_TIMEOUT 1000000
#define MX28_BLOCK_SFTRST (1 << 31) #define MXS_BLOCK_SFTRST (1 << 31)
#define MX28_BLOCK_CLKGATE (1 << 30) #define MXS_BLOCK_CLKGATE (1 << 30)
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */ /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {} inline void lowlevel_init(void) {}
@ -81,7 +81,7 @@ void enable_caches(void)
#endif #endif
} }
int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout) int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
{ {
while (--timeout) { while (--timeout) {
if ((readl(&reg->reg) & mask) == mask) if ((readl(&reg->reg) & mask) == mask)
@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
return !timeout; return !timeout;
} }
int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout) int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
{ {
while (--timeout) { while (--timeout) {
if ((readl(&reg->reg) & mask) == 0) if ((readl(&reg->reg) & mask) == 0)
@ -103,34 +103,34 @@ int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
return !timeout; return !timeout;
} }
int mx28_reset_block(struct mxs_register_32 *reg) int mxs_reset_block(struct mxs_register_32 *reg)
{ {
/* Clear SFTRST */ /* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_clr); writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1; return 1;
/* Clear CLKGATE */ /* Clear CLKGATE */
writel(MX28_BLOCK_CLKGATE, &reg->reg_clr); writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
/* Set SFTRST */ /* Set SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_set); writel(MXS_BLOCK_SFTRST, &reg->reg_set);
/* Wait for CLKGATE being set */ /* Wait for CLKGATE being set */
if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1; return 1;
/* Clear SFTRST */ /* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_clr); writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
return 1; return 1;
/* Clear CLKGATE */ /* Clear CLKGATE */
writel(MX28_BLOCK_CLKGATE, &reg->reg_clr); writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
return 1; return 1;
return 0; return 0;
@ -229,7 +229,7 @@ int print_cpuinfo(void)
get_cpu_type(), get_cpu_type(),
get_cpu_rev(), get_cpu_rev(),
mxc_get_clock(MXC_ARM_CLK) / 1000000); mxc_get_clock(MXC_ARM_CLK) / 1000000);
printf("BOOT: %s\n", mx28_boot_modes[data->boot_mode_idx].mode); printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
return 0; return 0;
} }
#endif #endif
@ -299,7 +299,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
MXS_OCOTP_MAX_TIMEOUT)) { MXS_OCOTP_MAX_TIMEOUT)) {
printf("MXS FEC: Can't get MAC from OCOTP\n"); printf("MXS FEC: Can't get MAC from OCOTP\n");
return; return;

6
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View file

@ -82,9 +82,9 @@ uint8_t mxs_get_bootmode_index(void)
bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) { for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
masked = bootmode & mx28_boot_modes[i].boot_mask; masked = bootmode & mxs_boot_modes[i].boot_mask;
if (masked == mx28_boot_modes[i].boot_pads) if (masked == mxs_boot_modes[i].boot_pads)
break; break;
} }

2
arch/arm/cpu/arm926ejs/mxs/timer.c
View file

@ -66,7 +66,7 @@ int timer_init(void)
(struct mxs_timrot_regs *)MXS_TIMROT_BASE; (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
/* Reset Timers and Rotary Encoder module */ /* Reset Timers and Rotary Encoder module */
mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg); mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
/* Set fixed_count to 0 */ /* Set fixed_count to 0 */
writel(0, &timrot_regs->hw_timrot_fixed_count0); writel(0, &timrot_regs->hw_timrot_fixed_count0);

20
arch/arm/include/asm/arch-mxs/sys_proto.h
View file

@ -1,5 +1,5 @@
/* /*
* Freescale i.MX28 MX28 specific functions * Freescale i.MX233/i.MX28 specific functions
* *
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH * on behalf of DENX Software Engineering GmbH
@ -20,14 +20,14 @@
* *
*/ */
#ifndef __MX28_H__ #ifndef __SYS_PROTO_H__
#define __MX28_H__ #define __SYS_PROTO_H__
int mx28_reset_block(struct mxs_register_32 *reg); int mxs_reset_block(struct mxs_register_32 *reg);
int mx28_wait_mask_set(struct mxs_register_32 *reg, int mxs_wait_mask_set(struct mxs_register_32 *reg,
uint32_t mask, uint32_t mask,
int timeout); int timeout);
int mx28_wait_mask_clr(struct mxs_register_32 *reg, int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask, uint32_t mask,
int timeout); int timeout);
@ -39,13 +39,13 @@ void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size); const unsigned int iomux_size);
#endif #endif
struct mx28_pair { struct mxs_pair {
uint8_t boot_pads; uint8_t boot_pads;
uint8_t boot_mask; uint8_t boot_mask;
const char *mode; const char *mode;
}; };
static const struct mx28_pair mx28_boot_modes[] = { static const struct mxs_pair mxs_boot_modes[] = {
{ 0x00, 0x0f, "USB #0" }, { 0x00, 0x0f, "USB #0" },
{ 0x01, 0x1f, "I2C #0, master, 3V3" }, { 0x01, 0x1f, "I2C #0, master, 3V3" },
{ 0x11, 0x1f, "I2C #0, master, 1V8" }, { 0x11, 0x1f, "I2C #0, master, 1V8" },
@ -69,6 +69,6 @@ struct mxs_spl_data {
uint32_t mem_dram_size; uint32_t mem_dram_size;
}; };
int mx28_dram_init(void); int mxs_dram_init(void);
#endif /* __MX28_H__ */ #endif /* __SYS_PROTO_H__ */

2
board/bluegiga/apx4devkit/apx4devkit.c
View file

@ -130,7 +130,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
MXS_OCOTP_MAX_TIMEOUT)) { MXS_OCOTP_MAX_TIMEOUT)) {
printf("MXS: Can't get serial number from OCOTP\n"); printf("MXS: Can't get serial number from OCOTP\n");
return; return;

4
drivers/dma/apbh_dma.c
View file

@ -512,7 +512,7 @@ static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
if (ret) if (ret)
return ret; return ret;
if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg, if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
1 << chan, timeout)) { 1 << chan, timeout)) {
ret = -ETIMEDOUT; ret = -ETIMEDOUT;
mxs_dma_reset(chan); mxs_dma_reset(chan);
@ -557,7 +557,7 @@ void mxs_dma_init(void)
struct mxs_apbh_regs *apbh_regs = struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE; (struct mxs_apbh_regs *)MXS_APBH_BASE;
mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg); mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
#ifdef CONFIG_APBH_DMA_BURST8 #ifdef CONFIG_APBH_DMA_BURST8
writel(APBH_CTRL0_AHB_BURST8_EN, writel(APBH_CTRL0_AHB_BURST8_EN,

2
drivers/i2c/mxs_i2c.c
View file

@ -41,7 +41,7 @@ void mxs_i2c_reset(void)
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
int ret; int ret;
ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
if (ret) { if (ret) {
debug("MXS I2C: Block reset timeout\n"); debug("MXS I2C: Block reset timeout\n");
return; return;

2
drivers/mmc/mxsmmc.c
View file

@ -336,7 +336,7 @@ static int mxsmmc_init(struct mmc *mmc)
struct mxs_ssp_regs *ssp_regs = priv->regs; struct mxs_ssp_regs *ssp_regs = priv->regs;
/* Reset SSP */ /* Reset SSP */
mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
/* 8 bits word length in MMC mode */ /* 8 bits word length in MMC mode */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,

6
drivers/mtd/nand/mxs_nand.c
View file

@ -237,7 +237,7 @@ static int mxs_nand_wait_for_bch_complete(void)
int timeout = MXS_NAND_BCH_TIMEOUT; int timeout = MXS_NAND_BCH_TIMEOUT;
int ret; int ret;
ret = mx28_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
BCH_CTRL_COMPLETE_IRQ, timeout); BCH_CTRL_COMPLETE_IRQ, timeout);
writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
@ -972,7 +972,7 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
uint32_t tmp; uint32_t tmp;
/* Configure BCH and set NFC geometry */ /* Configure BCH and set NFC geometry */
mx28_reset_block(&bch_regs->hw_bch_ctrl_reg); mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
/* Configure layout 0 */ /* Configure layout 0 */
tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
@ -1080,7 +1080,7 @@ int mxs_nand_init(struct mxs_nand_info *info)
} }
/* Reset the GPMI block. */ /* Reset the GPMI block. */
mx28_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
/* /*
* Choose NAND mode, set IRQ polarity, disable write protection and * Choose NAND mode, set IRQ polarity, disable write protection and

4
drivers/rtc/mxsrtc.c
View file

@ -41,7 +41,7 @@ int mxs_rtc_set_time(uint32_t secs)
* is taken from the linux kernel driver for the STMP37xx RTC since * is taken from the linux kernel driver for the STMP37xx RTC since
* documentation doesn't mention it. * documentation doesn't mention it.
*/ */
ret = mx28_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg, ret = mxs_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
0x80 << RTC_STAT_STALE_REGS_OFFSET, MXS_RTC_MAX_TIMEOUT); 0x80 << RTC_STAT_STALE_REGS_OFFSET, MXS_RTC_MAX_TIMEOUT);
if (ret) if (ret)
@ -80,7 +80,7 @@ void rtc_reset(void)
mxs_rtc_set_time(0); mxs_rtc_set_time(0);
/* Reset the RTC block */ /* Reset the RTC block */
ret = mx28_reset_block(&rtc_regs->hw_rtc_ctrl_reg); ret = mxs_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
if (ret) if (ret)
printf("MXS RTC: Block reset timeout\n"); printf("MXS RTC: Block reset timeout\n");
} }

8
drivers/spi/mxs_spi.c
View file

@ -139,7 +139,7 @@ int spi_claim_bus(struct spi_slave *slave)
struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
uint32_t reg = 0; uint32_t reg = 0;
mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
@ -193,7 +193,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set); writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
if (mx28_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg, if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for start\n"); printf("MXS SPI: Timeout waiting for start\n");
return -ETIMEDOUT; return -ETIMEDOUT;
@ -205,7 +205,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set); writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
if (!write) { if (!write) {
if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_status_reg, if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) { SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for data\n"); printf("MXS SPI: Timeout waiting for data\n");
return -ETIMEDOUT; return -ETIMEDOUT;
@ -215,7 +215,7 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
data++; data++;
} }
if (mx28_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg, if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) { SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
printf("MXS SPI: Timeout waiting for finish\n"); printf("MXS SPI: Timeout waiting for finish\n");
return -ETIMEDOUT; return -ETIMEDOUT;