mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
This commit is contained in:
commit
fae56934a0
36 changed files with 2322 additions and 35 deletions
|
@ -36,11 +36,15 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static const struct gpio_bank gpio_bank_am33xx[4] = {
|
||||
static const struct gpio_bank gpio_bank_am33xx[] = {
|
||||
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
|
||||
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
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||||
{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
|
||||
{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
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#ifdef CONFIG_AM43XX
|
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{ (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
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#endif
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};
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|
||||
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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|
|
|
@ -94,6 +94,8 @@ void enable_basic_clocks(void)
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&cmper->gpio1clkctrl,
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&cmper->gpio2clkctrl,
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&cmper->gpio3clkctrl,
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&cmper->gpio4clkctrl,
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&cmper->gpio5clkctrl,
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&cmper->i2c1clkctrl,
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&cmper->emiffwclkctrl,
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&cmper->emifclkctrl,
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|
|
|
@ -211,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco)
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static u32 pll_sigma_delta_val(u32 clkout_dco)
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{
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u32 sig_val = 0;
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float frac_div;
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frac_div = (float) clkout_dco / 250;
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frac_div = frac_div + 0.90;
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sig_val = (int)frac_div;
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sig_val = (clkout_dco + 225) / 250;
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sig_val = sig_val << 24;
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return sig_val;
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|
|
|
@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = {
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.ddr = NULL
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};
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struct dplls omap4430_dplls_es20 = {
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.mpu = mpu_dpll_params_1200mhz,
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.core = core_dpll_params_es2_1600mhz_ddr200mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct dplls omap4430_dplls = {
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.mpu = mpu_dpll_params_1200mhz,
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.core = core_dpll_params_1600mhz,
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|
@ -413,6 +427,10 @@ void hw_data_init(void)
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break;
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case OMAP4430_ES2_0:
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*dplls_data = &omap4430_dplls_es20;
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*omap_vcores = &omap4430_volts;
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break;
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case OMAP4430_ES2_1:
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case OMAP4430_ES2_2:
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case OMAP4430_ES2_3:
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|
|
|
@ -432,7 +432,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
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.control_srcomp_code_latch = 0x4A002E84,
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.control_ddr_control_ext_0 = 0x4A002E88,
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.control_padconf_core_base = 0x4A003400,
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.control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24,
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.control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20,
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.control_port_emif1_sdram_config = 0x4AE0C110,
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.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
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.control_port_emif2_sdram_config = 0x4AE0C118,
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|
|
|
@ -171,7 +171,8 @@ struct cm_wkuppll {
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unsigned int resv11[1];
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unsigned int wkup_uart0ctrl; /* offset 0xB4 */
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unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
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unsigned int resv12[7];
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unsigned int wkup_adctscctrl; /* offset 0xBC */
|
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unsigned int resv12[6];
|
||||
unsigned int divm6dpllcore; /* offset 0xD8 */
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};
|
||||
|
||||
|
@ -221,7 +222,8 @@ struct cm_perpll {
|
|||
unsigned int tpccclkctrl; /* offset 0xBC */
|
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unsigned int dcan0clkctrl; /* offset 0xC0 */
|
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unsigned int dcan1clkctrl; /* offset 0xC4 */
|
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unsigned int resv6[2];
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unsigned int resv6;
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unsigned int epwmss1clkctrl; /* offset 0xCC */
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unsigned int emiffwclkctrl; /* offset 0xD0 */
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unsigned int epwmss0clkctrl; /* offset 0xD4 */
|
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unsigned int epwmss2clkctrl; /* offset 0xD8 */
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|
@ -351,7 +353,11 @@ struct cm_perpll {
|
|||
unsigned int gpio2clkctrl; /* offset 0x480 */
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unsigned int resv20;
|
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unsigned int gpio3clkctrl; /* offset 0x488 */
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unsigned int resv21[7];
|
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unsigned int resv41;
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unsigned int gpio4clkctrl; /* offset 0x490 */
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unsigned int resv42;
|
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unsigned int gpio5clkctrl; /* offset 0x498 */
|
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unsigned int resv21[3];
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|
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unsigned int i2c1clkctrl; /* offset 0x4A8 */
|
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unsigned int resv22;
|
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|
|
|
@ -58,6 +58,22 @@
|
|||
#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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||||
|
||||
/* Micron MT41K128M16JT-187E */
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#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
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#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
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#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
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#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
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#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
|
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#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
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#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
|
||||
#define MT41K128MJT187E_RATIO 0x40
|
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#define MT41K128MJT187E_INVERT_CLKOUT 0x1
|
||||
#define MT41K128MJT187E_RD_DQS 0x3B
|
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#define MT41K128MJT187E_WR_DQS 0x85
|
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#define MT41K128MJT187E_PHY_WR_DATA 0xC1
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#define MT41K128MJT187E_PHY_FIFO_WE 0x100
|
||||
#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
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|
||||
/* Micron MT41J64M16JT-125 */
|
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#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
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|
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|
|
|
@ -12,8 +12,8 @@
|
|||
#define AM33XX_GPIO1_BASE 0x4804C000
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#define AM33XX_GPIO2_BASE 0x481AC000
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#define AM33XX_GPIO3_BASE 0x481AE000
|
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|
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#define GPIO_22 22
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#define AM33XX_GPIO4_BASE 0x48320000
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#define AM33XX_GPIO5_BASE 0x48322000
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||||
|
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/* GPIO CTRL register */
|
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#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
|
||||
|
|
22
board/BuR/common/bur_common.h
Normal file
22
board/BuR/common/bur_common.h
Normal file
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* bur_comon.h
|
||||
*
|
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* common board information header for B&R boards
|
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*
|
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _BUR_COMMON_H_
|
||||
#define _BUR_COMMON_H_
|
||||
|
||||
void blink(u32 blinks, u32 intervall, u32 pin);
|
||||
void pmicsetup(u32 mpupll);
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
int board_eth_init(bd_t *bis);
|
||||
|
||||
#endif
|
216
board/BuR/common/common.c
Normal file
216
board/BuR/common/common.c
Normal file
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* common.c
|
||||
*
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* common board functions for B&R boards
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||||
*
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||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
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*
|
||||
*/
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|
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#include <common.h>
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#include <errno.h>
|
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#include <spl.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
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#include <asm/arch/omap.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
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#include <asm/io.h>
|
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#include <asm/gpio.h>
|
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#include <i2c.h>
|
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#include <miiphy.h>
|
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#include <cpsw.h>
|
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#include <power/tps65217.h>
|
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#include "bur_common.h"
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
/* --------------------------------------------------------------------------*/
|
||||
void blink(u32 blinks, u32 intervall, u32 pin)
|
||||
{
|
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gpio_direction_output(pin, 0);
|
||||
int val = 0;
|
||||
|
||||
do {
|
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val ^= 0x01;
|
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gpio_set_value(pin, val);
|
||||
mdelay(intervall);
|
||||
} while (blinks--);
|
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|
||||
gpio_set_value(pin, 0);
|
||||
}
|
||||
#ifdef CONFIG_SPL_BUILD
|
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void pmicsetup(u32 mpupll)
|
||||
{
|
||||
int mpu_vdd;
|
||||
int usb_cur_lim;
|
||||
|
||||
/* setup I2C */
|
||||
enable_i2c0_pin_mux();
|
||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
|
||||
|
||||
if (i2c_probe(TPS65217_CHIP_PM)) {
|
||||
puts("PMIC (0x24) not found! skip further initalization.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Get the frequency which is defined by device fuses */
|
||||
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
|
||||
printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
|
||||
|
||||
if (0 != mpupll) {
|
||||
dpll_mpu_opp100.m = MPUPLL_M_1000;
|
||||
printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
|
||||
} else {
|
||||
puts("ok.\n");
|
||||
}
|
||||
/*
|
||||
* Increase USB current limit to 1300mA or 1800mA and set
|
||||
* the MPU voltage controller as needed.
|
||||
*/
|
||||
if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
|
||||
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
|
||||
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
|
||||
} else {
|
||||
usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
|
||||
mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
|
||||
}
|
||||
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
|
||||
usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
|
||||
/* Set DCDC3 (CORE) voltage to 1.125V */
|
||||
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
|
||||
TPS65217_DCDC_VOLT_SEL_1125MV)) {
|
||||
puts("tps65217_voltage_update failure\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set CORE Frequencies to OPP100 */
|
||||
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
||||
|
||||
/* Set DCDC2 (MPU) voltage */
|
||||
if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
|
||||
puts("tps65217_voltage_update failure\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set LDO3 to 1.8V */
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS1,
|
||||
TPS65217_LDO_VOLTAGE_OUT_1_8,
|
||||
TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
/* Set LDO4 to 3.3V */
|
||||
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
|
||||
TPS65217_DEFLS2,
|
||||
TPS65217_LDO_VOLTAGE_OUT_3_3,
|
||||
TPS65217_LDO_MASK))
|
||||
puts("tps65217_reg_write failure\n");
|
||||
|
||||
/* Set MPU Frequency to what we detected now that voltages are set */
|
||||
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
enable_uart0_pin_mux();
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
return;
|
||||
}
|
||||
|
||||
/* describing port offsets of TI's CPSW block */
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_id = 0,
|
||||
},
|
||||
{
|
||||
.slave_reg_ofs = 0x308,
|
||||
.sliver_reg_ofs = 0xdc0,
|
||||
.phy_id = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
#endif /* CONFIG_DRIVER_TI_CPSW, ... */
|
||||
|
||||
#if defined(CONFIG_DRIVER_TI_CPSW)
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid0l);
|
||||
mac_hi = readl(&cdev->macid0h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
|
||||
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
|
||||
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
|
||||
if (!getenv("ethaddr")) {
|
||||
printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
|
||||
|
||||
if (is_valid_ether_addr(mac_addr)) {
|
||||
printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
|
||||
mac_addr[0], mac_addr[1], mac_addr[2],
|
||||
mac_addr[3], mac_addr[4], mac_addr[5]
|
||||
);
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||
}
|
||||
}
|
||||
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
|
||||
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0) {
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DRIVER_TI_CPSW, ... */
|
||||
return rv;
|
||||
}
|
||||
#endif /* CONFIG_DRIVER_TI_CPSW */
|
12
board/BuR/kwb/Makefile
Normal file
12
board/BuR/kwb/Makefile
Normal file
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Makefile
|
||||
#
|
||||
# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> -
|
||||
# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += mux.o
|
||||
obj-y += ../common/common.o
|
||||
obj-y += board.o
|
240
board/BuR/kwb/board.c
Normal file
240
board/BuR/kwb/board.c
Normal file
|
@ -0,0 +1,240 @@
|
|||
/*
|
||||
* board.c
|
||||
*
|
||||
* Board functions for B&R KWB Board
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
#include <power/tps65217.h>
|
||||
#include "../common/bur_common.h"
|
||||
|
||||
/* -------------------------------------------------------------------------*/
|
||||
/* -- defines for used GPIO Hardware -- */
|
||||
#define KEY (0+4)
|
||||
#define LCD_PWR (0+5)
|
||||
#define PUSH_KEY (0+31)
|
||||
#define USB2SD_NRST (32+29)
|
||||
#define USB2SD_PWR (96+13)
|
||||
/* -------------------------------------------------------------------------*/
|
||||
/* -- PSOC Resetcontroller Register defines -- */
|
||||
|
||||
/* I2C Address of controller */
|
||||
#define RSTCTRL_ADDR 0x75
|
||||
/* Register for CTRL-word */
|
||||
#define RSTCTRL_CTRLREG 0x01
|
||||
/* Register for giving some information to VxWorks OS */
|
||||
#define RSTCTRL_SCRATCHREG 0x04
|
||||
|
||||
/* -- defines for RSTCTRL_CTRLREG -- */
|
||||
#define RSTCTRL_FORCE_PWR_NEN 0x0404
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
/* TODO: check ram-timing ! */
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
|
||||
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
|
||||
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
|
||||
};
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
};
|
||||
static struct emif_regs ddr3_emif_reg_data = {
|
||||
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
|
||||
.zq_config = MT41K256M16HA125E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
static const struct ctrl_ioregs ddr3_ioregs = {
|
||||
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
void am33xx_spl_board_init(void)
|
||||
{
|
||||
unsigned int oldspeed;
|
||||
unsigned short buf;
|
||||
|
||||
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
|
||||
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
|
||||
/*
|
||||
* enable additional clocks of modules which are accessed later from
|
||||
* VxWorks OS
|
||||
*/
|
||||
u32 *const clk_domains[] = { 0 };
|
||||
|
||||
u32 *const clk_modules_kwbspecific[] = {
|
||||
&cmwkup->wkup_adctscctrl,
|
||||
&cmper->spi1clkctrl,
|
||||
&cmper->dcan0clkctrl,
|
||||
&cmper->dcan1clkctrl,
|
||||
&cmper->epwmss0clkctrl,
|
||||
&cmper->epwmss1clkctrl,
|
||||
&cmper->epwmss2clkctrl,
|
||||
0
|
||||
};
|
||||
do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
|
||||
|
||||
/* power-OFF LCD-Display */
|
||||
gpio_direction_output(LCD_PWR, 0);
|
||||
|
||||
/* setup I2C */
|
||||
enable_i2c0_pin_mux();
|
||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
|
||||
|
||||
/* power-ON 3V3 via Resetcontroller */
|
||||
oldspeed = i2c_get_bus_speed();
|
||||
if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
|
||||
buf = RSTCTRL_FORCE_PWR_NEN;
|
||||
i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
|
||||
(uint8_t *)&buf, sizeof(buf));
|
||||
i2c_set_bus_speed(oldspeed);
|
||||
} else {
|
||||
puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
|
||||
}
|
||||
|
||||
#if defined(CONFIG_AM335X_USB0)
|
||||
/* power on USB2SD Controller */
|
||||
gpio_direction_output(USB2SD_PWR, 1);
|
||||
mdelay(1);
|
||||
/* give a reset Pulse to USB2SD Controller */
|
||||
gpio_direction_output(USB2SD_NRST, 0);
|
||||
mdelay(1);
|
||||
gpio_set_value(USB2SD_NRST, 1);
|
||||
#endif
|
||||
pmicsetup(0);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
return &dpll_ddr3;
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
config_ddr(400, &ddr3_ioregs,
|
||||
&ddr3_data,
|
||||
&ddr3_cmd_ctrl_data,
|
||||
&ddr3_emif_reg_data, 0);
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
gpmc_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
const unsigned int ton = 250;
|
||||
const unsigned int toff = 1000;
|
||||
unsigned int cnt = 3;
|
||||
unsigned short buf = 0xAAAA;
|
||||
unsigned int oldspeed;
|
||||
|
||||
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
|
||||
TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
|
||||
|
||||
if (gpio_get_value(KEY)) {
|
||||
do {
|
||||
/* turn on light */
|
||||
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
|
||||
TPS65217_WLEDCTRL1, 0x09, 0xFF);
|
||||
mdelay(ton);
|
||||
/* turn off light */
|
||||
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
|
||||
TPS65217_WLEDCTRL1, 0x01, 0xFF);
|
||||
mdelay(toff);
|
||||
cnt--;
|
||||
if (!gpio_get_value(KEY) &&
|
||||
gpio_get_value(PUSH_KEY) && 1 == cnt) {
|
||||
puts("updating from USB ...\n");
|
||||
setenv("bootcmd", "run usbupdate");
|
||||
break;
|
||||
} else if (!gpio_get_value(KEY)) {
|
||||
break;
|
||||
}
|
||||
} while (cnt);
|
||||
}
|
||||
|
||||
switch (cnt) {
|
||||
case 0:
|
||||
puts("3 blinks ... entering BOOT mode.\n");
|
||||
buf = 0x0000;
|
||||
break;
|
||||
case 1:
|
||||
puts("2 blinks ... entering DIAGNOSE mode.\n");
|
||||
buf = 0x0F0F;
|
||||
break;
|
||||
case 2:
|
||||
puts("1 blinks ... entering SERVICE mode.\n");
|
||||
buf = 0xB4B4;
|
||||
break;
|
||||
case 3:
|
||||
puts("0 blinks ... entering RUN mode.\n");
|
||||
buf = 0x0404;
|
||||
break;
|
||||
}
|
||||
mdelay(ton);
|
||||
/* turn on light */
|
||||
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
|
||||
TPS65217_WLEDCTRL1, 0x09, 0xFF);
|
||||
/* write bootinfo into scratchregister of resetcontroller */
|
||||
oldspeed = i2c_get_bus_speed();
|
||||
if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) {
|
||||
i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
|
||||
(uint8_t *)&buf, sizeof(buf));
|
||||
i2c_set_bus_speed(oldspeed);
|
||||
} else {
|
||||
puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
|
||||
}
|
||||
/*
|
||||
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
|
||||
* expect that vectors are there, original u-boot moves them to _start
|
||||
*/
|
||||
__asm__("ldr r0,=0x20000");
|
||||
__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_BOARD_LATE_INIT */
|
195
board/BuR/kwb/mux.c
Normal file
195
board/BuR/kwb/mux.c
Normal file
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Pinmux Setting for B&R LEIT Board(s)
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
|
||||
static struct module_pin_mux usb0_pin_mux[] = {
|
||||
{OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
|
||||
/* USB0 DrvBus Receiver disable (from romcode 0x20) */
|
||||
{OFFSET(usb0_drvvbus), (MODE(0))},
|
||||
/* USB1 DrvBus as GPIO due to HW-Workaround */
|
||||
{OFFSET(usb1_drvvbus), (MODE(7))},
|
||||
{-1},
|
||||
};
|
||||
static struct module_pin_mux spi1_pin_mux[] = {
|
||||
/* SPI1_SCLK */
|
||||
{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
|
||||
/* SPI1_D0 */
|
||||
{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
|
||||
/* SPI1_D1 */
|
||||
{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
|
||||
/* SPI1_CS0 */
|
||||
{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux dcan0_pin_mux[] = {
|
||||
/* DCAN0 TX */
|
||||
{OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
|
||||
/* DCAN0 RX */
|
||||
{OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux dcan1_pin_mux[] = {
|
||||
/* DCAN1 TX */
|
||||
{OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
|
||||
/* DCAN1 RX */
|
||||
{OFFSET(uart1_txd), MODE(2) | RXACTIVE},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux gpios[] = {
|
||||
/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
|
||||
{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
|
||||
/* GPIO0_4 (SPI D1) - TA602 */
|
||||
{OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
|
||||
{OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
|
||||
/* GPIO0_7 (PWW0 OUT) - CAN TERM */
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
|
||||
{OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
|
||||
/* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
|
||||
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
|
||||
/* GPIO0_30 (GPMC_WAIT0) - TA601 */
|
||||
{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
|
||||
{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
|
||||
/* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
|
||||
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
|
||||
/* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO2_4 (GPMC_nWE) - TST_BAST */
|
||||
{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
|
||||
/* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
|
||||
{OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
|
||||
/* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
|
||||
{OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
/* UART0_CTS */
|
||||
{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* UART0_RXD */
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* UART0_TXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
/* I2C_DATA */
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
/* I2C_SCLK */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mii1_pin_mux[] = {
|
||||
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
|
||||
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
|
||||
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
|
||||
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
|
||||
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
|
||||
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mmc1_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
|
||||
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
|
||||
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
|
||||
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
|
||||
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
|
||||
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
|
||||
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux lcd_pin_mux[] = {
|
||||
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
|
||||
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
|
||||
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
|
||||
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
|
||||
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
|
||||
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
|
||||
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
|
||||
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
|
||||
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
|
||||
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
|
||||
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
|
||||
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
|
||||
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
|
||||
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
|
||||
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
|
||||
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
|
||||
|
||||
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
|
||||
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
|
||||
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
|
||||
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
|
||||
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
|
||||
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
|
||||
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
|
||||
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
|
||||
|
||||
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
|
||||
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
|
||||
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
|
||||
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(usb0_pin_mux);
|
||||
configure_module_pin_mux(spi1_pin_mux);
|
||||
configure_module_pin_mux(dcan0_pin_mux);
|
||||
configure_module_pin_mux(dcan1_pin_mux);
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
configure_module_pin_mux(lcd_pin_mux);
|
||||
configure_module_pin_mux(gpios);
|
||||
}
|
14
board/BuR/tseries/Makefile
Normal file
14
board/BuR/tseries/Makefile
Normal file
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Makefile
|
||||
#
|
||||
# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD),y)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
obj-y += ../common/common.o
|
||||
obj-y += board.o
|
147
board/BuR/tseries/board.c
Normal file
147
board/BuR/tseries/board.c
Normal file
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* board.c
|
||||
*
|
||||
* Board functions for B&R LEIT Board
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
#include <power/tps65217.h>
|
||||
#include "../common/bur_common.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* --------------------------------------------------------------------------*/
|
||||
/* -- defines for GPIO -- */
|
||||
#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
|
||||
#define REPSWITCH (0+20) /* GPIO0_20 */
|
||||
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
/* TODO: check ram-timing ! */
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
|
||||
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
|
||||
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd1csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
|
||||
.cmd2csratio = MT41K256M16HA125E_RATIO,
|
||||
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = {
|
||||
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
|
||||
.zq_config = MT41K256M16HA125E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
static const struct ctrl_ioregs ddr3_ioregs = {
|
||||
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
/*
|
||||
* called from spl_nand.c
|
||||
* return 0 for loading linux, return 1 for loading u-boot
|
||||
*/
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
if (0 == gpio_get_value(REPSWITCH)) {
|
||||
blink(5, 125, ETHLED_ORANGE);
|
||||
mdelay(1000);
|
||||
printf("SPL: entering u-boot instead kernel image.\n");
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SPL_OS_BOOT */
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
void am33xx_spl_board_init(void)
|
||||
{
|
||||
pmicsetup(1000);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
return &dpll_ddr3;
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
config_ddr(400, &ddr3_ioregs,
|
||||
&ddr3_data,
|
||||
&ddr3_cmd_ctrl_data,
|
||||
&ddr3_emif_reg_data, 0);
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
/* Basic board specific setup. Pinmux has been handled already. */
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
gpmc_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INIT
|
||||
int board_late_init(void)
|
||||
{
|
||||
gpio_direction_output(ETHLED_ORANGE, 0);
|
||||
|
||||
if (0 == gpio_get_value(REPSWITCH)) {
|
||||
printf("\n\n\n"
|
||||
"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
|
||||
"!!!!!!! recovery switch activated !!!!!!!\n"
|
||||
"!!!!!!! running usbupdate !!!!!!!\n"
|
||||
"!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
|
||||
setenv("bootcmd", "sleep 2; run netupdate;");
|
||||
}
|
||||
|
||||
printf("turning on display power+backlight ... ");
|
||||
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
|
||||
0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
|
||||
tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
|
||||
0x62, TPS65217_MASK_ALL_BITS); /* 100% */
|
||||
printf("ok.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_BOARD_LATE_INIT */
|
225
board/BuR/tseries/mux.c
Normal file
225
board/BuR/tseries/mux.c
Normal file
|
@ -0,0 +1,225 @@
|
|||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Pinmux Setting for B&R LEIT Board(s)
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
/* UART0_CTS */
|
||||
{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* UART0_RXD */
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* UART0_TXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
|
||||
{-1},
|
||||
};
|
||||
#ifdef CONFIG_MMC
|
||||
static struct module_pin_mux mmc1_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
|
||||
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
|
||||
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
|
||||
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
|
||||
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
|
||||
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
|
||||
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
/* I2C_DATA */
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
/* I2C_SCLK */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux spi0_pin_mux[] = {
|
||||
/* SPI0_SCLK */
|
||||
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
|
||||
/* SPI0_D0 */
|
||||
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
|
||||
/* SPI0_D1 */
|
||||
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
|
||||
/* SPI0_CS0 */
|
||||
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mii1_pin_mux[] = {
|
||||
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
|
||||
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
|
||||
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
|
||||
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
|
||||
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
|
||||
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux mii2_pin_mux[] = {
|
||||
{OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
|
||||
{OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
|
||||
{OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
|
||||
{OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
|
||||
{OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
|
||||
{OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
|
||||
{OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
|
||||
{OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
|
||||
{OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
|
||||
{OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
|
||||
{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
|
||||
{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
|
||||
{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
|
||||
/*
|
||||
* MII2_CRS is shared with
|
||||
* NAND_WAIT0
|
||||
*/
|
||||
{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
|
||||
{-1},
|
||||
};
|
||||
#ifdef CONFIG_NAND
|
||||
static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
static struct module_pin_mux gpIOs[] = {
|
||||
/* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
|
||||
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
|
||||
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
|
||||
/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
|
||||
{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
|
||||
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
|
||||
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
|
||||
{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
|
||||
{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
|
||||
{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
|
||||
{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO2_0 (GPMC_nCS3) - DCOK */
|
||||
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
|
||||
/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
|
||||
{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
|
||||
/*
|
||||
* GPIO0_7 (PWW0 OUT)
|
||||
* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
|
||||
*/
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
|
||||
/* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
|
||||
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO0_20 (DMA_INTR1) - REP-Switch */
|
||||
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
|
||||
/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
|
||||
{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
|
||||
/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
|
||||
{OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
|
||||
/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
|
||||
{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
|
||||
/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
|
||||
{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux lcd_pin_mux[] = {
|
||||
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
|
||||
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
|
||||
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
|
||||
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
|
||||
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
|
||||
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
|
||||
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
|
||||
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
|
||||
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
|
||||
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
|
||||
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
|
||||
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
|
||||
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
|
||||
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
|
||||
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
|
||||
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
|
||||
|
||||
{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
|
||||
{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
|
||||
{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
|
||||
{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
|
||||
{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
|
||||
{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
|
||||
{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
|
||||
{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
|
||||
|
||||
{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
|
||||
{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
|
||||
{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
|
||||
{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
|
||||
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mii2_pin_mux);
|
||||
#ifdef CONFIG_NAND
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#elif defined(CONFIG_MMC)
|
||||
configure_module_pin_mux(mmc1_pin_mux);
|
||||
#endif
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
configure_module_pin_mux(lcd_pin_mux);
|
||||
configure_module_pin_mux(gpIOs);
|
||||
}
|
|
@ -325,8 +325,6 @@ const omap3_sysinfo sysinfo = {
|
|||
MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
|
||||
/* SYS_nRESWARM */\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
|
||||
|
|
13
board/silica/pengwyn/Makefile
Normal file
13
board/silica/pengwyn/Makefile
Normal file
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# Makefile
|
||||
#
|
||||
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_NOR_BOOT),y)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
obj-y += board.o
|
207
board/silica/pengwyn/board.c
Normal file
207
board/silica/pengwyn/board.c
Normal file
|
@ -0,0 +1,207 @@
|
|||
/*
|
||||
* board.c
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
#include <phy.h>
|
||||
#include <cpsw.h>
|
||||
#include "board.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
|
||||
/* DDR3 RAM timings */
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41K128MJT187E_RD_DQS,
|
||||
.datawdsratio0 = MT41K128MJT187E_WR_DQS,
|
||||
.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41K128MJT187E_RATIO,
|
||||
.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
|
||||
.cmd1csratio = MT41K128MJT187E_RATIO,
|
||||
.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
|
||||
.cmd2csratio = MT41K128MJT187E_RATIO,
|
||||
.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = {
|
||||
.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
|
||||
.zq_config = MT41K128MJT187E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
|
||||
PHY_EN_DYN_PWRDN,
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ddr3_ioregs = {
|
||||
.cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
return serial_tstc() && serial_getc() == 'c';
|
||||
}
|
||||
#endif
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr_266 = {
|
||||
266, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_303 = {
|
||||
303, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_400 = {
|
||||
400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
void am33xx_spl_board_init(void)
|
||||
{
|
||||
/*
|
||||
* The pengwyn board uses the TPS650250 PMIC without I2C
|
||||
* interface and will output the following fixed voltages:
|
||||
* DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
|
||||
* VLDO1=1V8 (IO) VLDO2=1V8(IO)
|
||||
* Vcore=1V1 is fixed, generated by TPS62231
|
||||
*/
|
||||
|
||||
/* Get the frequency */
|
||||
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
|
||||
|
||||
/* Set CORE Frequencies to OPP100 */
|
||||
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
||||
|
||||
/* 720MHz cpu, this might change on newer board revisions */
|
||||
dpll_mpu_opp100.m = MPUPLL_M_720;
|
||||
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
/* future configs can return other clock settings */
|
||||
return &dpll_ddr_303;
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
enable_uart0_pin_mux();
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
config_ddr(303, &ddr3_ioregs, &ddr3_data,
|
||||
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
|
||||
}
|
||||
#endif /* if CONFIG_SPL_BUILD */
|
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
gpmc_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_id = 0,
|
||||
.phy_if = PHY_INTERFACE_MODE_MII,
|
||||
},
|
||||
{
|
||||
.slave_reg_ofs = 0x308,
|
||||
.sliver_reg_ofs = 0xdc0,
|
||||
.phy_id = 1,
|
||||
.phy_if = PHY_INTERFACE_MODE_MII,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
|
||||
printf("<ethaddr> not set. Reading from E-fuse\n");
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid0l);
|
||||
mac_hi = readl(&cdev->macid0h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
|
||||
if (is_valid_ether_addr(mac_addr))
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||
else
|
||||
return n;
|
||||
}
|
||||
|
||||
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
return n;
|
||||
}
|
||||
#endif /* if CONFIG_DRIVER_TI_CPSW */
|
15
board/silica/pengwyn/board.h
Normal file
15
board/silica/pengwyn/board.h
Normal file
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* board.h
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
|
||||
#endif
|
98
board/silica/pengwyn/mux.c
Normal file
98
board/silica/pengwyn/mux.c
Normal file
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include "board.h"
|
||||
|
||||
/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
|
||||
|
||||
/* I2C pins C16(scl)/C17(sda) */
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* MMC0 pins */
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* MII pins */
|
||||
static struct module_pin_mux mii1_pin_mux[] = {
|
||||
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
|
||||
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
|
||||
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
|
||||
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
|
||||
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
|
||||
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* NAND pins */
|
||||
static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux()
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
}
|
|
@ -346,14 +346,14 @@ static void enable_vtt_regulator(void)
|
|||
u32 temp;
|
||||
|
||||
/* enable module */
|
||||
writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
|
||||
writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
|
||||
|
||||
/* enable output for GPIO0_22 */
|
||||
writel(GPIO_SETDATAOUT(GPIO_22),
|
||||
AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
|
||||
temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
|
||||
temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
|
||||
writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
|
||||
/* enable output for GPIO5_7 */
|
||||
writel(GPIO_SETDATAOUT(7),
|
||||
AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
|
||||
temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
|
||||
temp = temp & ~(GPIO_OE_ENABLE(7));
|
||||
writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
|
|
|
@ -33,8 +33,8 @@ static struct module_pin_mux i2c0_pin_mux[] = {
|
|||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux gpio0_22_pin_mux[] = {
|
||||
{OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */
|
||||
static struct module_pin_mux gpio5_7_pin_mux[] = {
|
||||
{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
|
@ -49,7 +49,7 @@ void enable_board_pin_mux(void)
|
|||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
|
||||
if (board_is_gpevm())
|
||||
configure_module_pin_mux(gpio0_22_pin_mux);
|
||||
configure_module_pin_mux(gpio5_7_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
|
|
|
@ -256,6 +256,11 @@ Active arm armv7 am33xx phytec pcm051
|
|||
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
|
||||
Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
|
||||
Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
|
||||
Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
|
||||
Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
|
||||
Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
|
||||
Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
|
||||
Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
|
||||
Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
|
@ -31,6 +32,12 @@
|
|||
/* Always 128 KiB env size */
|
||||
#define CONFIG_ENV_SIZE (128 << 10)
|
||||
|
||||
/* Enhance our eMMC support / experience. */
|
||||
#define CONFIG_CMD_GPT
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
#define CONFIG_CMD_PART
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define NANDARGS \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
|
@ -64,6 +71,9 @@
|
|||
"bootfile=zImage\0" \
|
||||
"fdtfile=undefined\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"partitions=" \
|
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
|
@ -295,6 +305,9 @@
|
|||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
|
||||
/* disable host part of MUSB in SPL */
|
||||
#undef CONFIG_MUSB_HOST
|
||||
/* disable EFI partitions and partition UUID support */
|
||||
#undef CONFIG_PARTITION_UUIDS
|
||||
#undef CONFIG_EFI_PARTITION
|
||||
/*
|
||||
* Disable CPSW SPL support so we fit within the 101KiB limit.
|
||||
*/
|
||||
|
|
|
@ -84,6 +84,12 @@
|
|||
#define CONFIG_OMAP_USB_PHY
|
||||
#define CONFIG_AM437X_USB2PHY2_HOST
|
||||
|
||||
/* Enhance our eMMC support / experience. */
|
||||
#define CONFIG_CMD_GPT
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
#define CONFIG_CMD_PART
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x80200000\0" \
|
||||
|
@ -95,6 +101,9 @@
|
|||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"partitions=" \
|
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
|
|
197
include/configs/bur_am335x_common.h
Normal file
197
include/configs/bur_am335x_common.h
Normal file
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* bur_am335x_common.h
|
||||
*
|
||||
* common parts used by B&R AM335x based boards
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __BUR_AM335X_COMMON_H__
|
||||
#define __BUR_AM335X_COMMON_H__
|
||||
/* ------------------------------------------------------------------------- */
|
||||
#define CONFIG_AM33XX
|
||||
#define CONFIG_OMAP
|
||||
#define CONFIG_OMAP_COMMON
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
|
||||
|
||||
/* Timer information */
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
|
||||
|
||||
#define CONFIG_SPL_POWER_SUPPORT
|
||||
#define CONFIG_POWER_TPS65217
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
|
||||
|
||||
#include <asm/arch/omap.h>
|
||||
|
||||
/* NS16550 Configuration */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK 48000000
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Network defines */
|
||||
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_NET_RETRY_COUNT 4
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
|
||||
#define CONFIG_MII /* Required in net/eth.c */
|
||||
#define CONFIG_SPL_ETH_SUPPORT
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 1
|
||||
#define CONFIG_PHY_NATSEMI
|
||||
#define CONFIG_SPL_NET_SUPPORT
|
||||
#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
|
||||
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
|
||||
|
||||
/*
|
||||
* SPL related defines. The Public RAM memory map the ROM defines the
|
||||
* area between 0x402F0400 and 0x4030B800 as a download area and
|
||||
* 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
|
||||
* supports X-MODEM loading via UART, and we leverage this and then use
|
||||
* Y-MODEM to load u-boot.img, when booted over UART.
|
||||
*/
|
||||
#define CONFIG_SPL_TEXT_BASE 0x402F0400
|
||||
#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
|
||||
|
||||
/*
|
||||
* Since SPL did pll and ddr initialization for us,
|
||||
* we don't need to do it twice.
|
||||
*/
|
||||
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif /* !CONFIG_SPL_BUILD, ... */
|
||||
/*
|
||||
* Our DDR memory always starts at 0x80000000 and U-Boot shall have
|
||||
* relocated itself to higher in memory by the time this value is used.
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80000000
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* DDR information. We say (for simplicity) that we have 1 bank,
|
||||
* always, even when we have more. We always start at 0x80000000,
|
||||
* and we place the initial stack pointer in our SRAM.
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_OMAP24XX
|
||||
|
||||
/* GPIO */
|
||||
#define CONFIG_OMAP_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
/*
|
||||
* ----------------------------------------------------------------------------
|
||||
* The following are general good-enough settings for U-Boot. We set a
|
||||
* large malloc pool as we generally have a lot of DDR, and we opt for
|
||||
* function over binary size in the main portion of U-Boot as this is
|
||||
* generally easily constrained later if needed. We enable the config
|
||||
* options that give us information in the environment about what board
|
||||
* we are on so we do not need to rely on the command prompt. We set a
|
||||
* console baudrate of 115200 and use the default baud rate table.
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
|
||||
|
||||
/* As stated above, the following choices are optional. */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
/* We set the max number of command args high to avoid HUSH bugs. */
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 512
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/*
|
||||
* For commands to use, we take the default list and add a few other
|
||||
* useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
|
||||
* prior to this include, in order to skip a few commands. When we do
|
||||
* have flash, if we expect these commands they must be enabled in that
|
||||
* config. If desired, a specific list of desired commands can be used
|
||||
* instead.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
/* undefine commands, which we do not need */
|
||||
#undef CONFIG_CMD_EDITENV
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_ITEST
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_LOADB
|
||||
#undef CONFIG_CMD_NFS
|
||||
#undef CONFIG_CMD_SETGETDCR
|
||||
#undef CONFIG_CMD_XIMG
|
||||
#undef CONFIG_CMD_CRC32
|
||||
/* define command we need always */
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_SOURCE
|
||||
|
||||
/*
|
||||
* Our platforms make use of SPL to initalize the hardware (primarily
|
||||
* memory) enough for full U-Boot to be loaded. We also support Falcon
|
||||
* Mode so that the Linux kernel can be booted directly from SPL
|
||||
* instead, if desired. We make use of the general SPL framework found
|
||||
* under common/spl/. Given our generally common memory map, we set a
|
||||
* number of related defaults and sizes here.
|
||||
*/
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
/*
|
||||
* Place the image at the start of the ROM defined image space.
|
||||
* We limit our size to the ROM-defined downloaded image area, and use the
|
||||
* rest of the space for stack. We load U-Boot itself into memory at
|
||||
* 0x80800000 for legacy reasons (to not conflict with older SPLs). We
|
||||
* have our BSS be placed 1MiB after this, to allow for the default
|
||||
* Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
|
||||
* We have the SPL malloc pool at the end of the BSS area.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||
#undef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
|
||||
CONFIG_SPL_BSS_MAX_SIZE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
|
||||
/* General parts of the framework, required. */
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
|
||||
|
||||
#endif /* ! __BUR_AM335X_COMMON_H__ */
|
|
@ -45,13 +45,6 @@
|
|||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
/*
|
||||
* The early kernel mapping on ARM currently only maps from the base of DRAM
|
||||
* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
|
||||
* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
|
||||
* so that leaves DRAM base to DRAM base + 0x4000 available.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ 0x4000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
|
|
@ -34,8 +34,19 @@
|
|||
|
||||
#define CONFIG_SYS_OMAP_ABE_SYSCK
|
||||
|
||||
/* Define the default GPT table for eMMC */
|
||||
#define PARTS_DEFAULT \
|
||||
"uuid_disk=${uuid_gpt_disk};" \
|
||||
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
|
||||
|
||||
#include <configs/ti_omap5_common.h>
|
||||
|
||||
/* Enhance our eMMC support / experience. */
|
||||
#define CONFIG_CMD_GPT
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
#define CONFIG_CMD_PART
|
||||
|
||||
/* CPSW Ethernet */
|
||||
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
|
128
include/configs/kwb.h
Normal file
128
include/configs/kwb.h
Normal file
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* kwb.h
|
||||
*
|
||||
* specific parts for B&R KWB Motherboard
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_KWB_H__
|
||||
#define __CONFIG_KWB_H__
|
||||
|
||||
#include <configs/bur_am335x_common.h>
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#define CONFIG_POWER_TPS65217
|
||||
|
||||
#define CONFIG_MACH_TYPE 3589
|
||||
/* I2C IP block */
|
||||
#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000
|
||||
|
||||
/* GPIO */
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
|
||||
/* MMC/SD IP block */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_OMAP_HSMMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT
|
||||
/* RAW SD card / eMMC locations. */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
|
||||
#undef CONFIG_SPL_OS_BOOT
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
|
||||
|
||||
/* RAW SD card / eMMC */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
|
||||
|
||||
#endif /* CONFIG_SPL_OS_BOOT */
|
||||
|
||||
/* Always 128 KiB env size */
|
||||
#define CONFIG_ENV_SIZE (128 << 10)
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"autoload=0\0" \
|
||||
"loadaddr=0x80100000\0" \
|
||||
"bootfile=arimg\0" \
|
||||
"usbboot=echo Booting from USB-Stick ...; " \
|
||||
"usb start; " \
|
||||
"fatload usb 0 ${loadaddr} ${bootfile}; " \
|
||||
"usb stop; " \
|
||||
"go ${loadaddr};\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"setenv autoload 0; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} arimg; " \
|
||||
"go ${loadaddr}\0" \
|
||||
"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
|
||||
"usb start; " \
|
||||
"fatload usb 0 0x80000000 updateubootusb.img; " \
|
||||
"source;\0" \
|
||||
"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
|
||||
"setenv autoload 0; " \
|
||||
"dhcp;" \
|
||||
"tftp 0x80000000 updateUBOOT.img;" \
|
||||
"source;\0"
|
||||
#endif /* !CONFIG_SPL_BUILD*/
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"run usbupdate;"
|
||||
#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
|
||||
|
||||
/* undefine command which we not need here */
|
||||
#undef CONFIG_BOOTM_LINUX
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
#undef CONFIG_BOOTM_PLAN9
|
||||
#undef CONFIG_BOOTM_RTEMS
|
||||
#undef CONFIG_GZIP
|
||||
#undef CONFIG_ZLIB
|
||||
#undef CONFIG_CMD_CRC32
|
||||
|
||||
/* USB configuration */
|
||||
#define CONFIG_USB_MUSB_DSPS
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
#define CONFIG_MUSB_PIO_ONLY
|
||||
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
|
||||
/* attention! not only for gadget, enables also highspeed in hostmode */
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_MUSB_HOST
|
||||
#define CONFIG_AM335X_USB0
|
||||
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
|
||||
|
||||
#ifdef CONFIG_MUSB_HOST
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif /* CONFIG_MUSB_HOST */
|
||||
|
||||
#undef CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1
|
||||
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||
/*
|
||||
* Common filesystems support. When we have removable storage we
|
||||
* enabled a number of useful commands and support.
|
||||
*/
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_FAT_WRITE
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#endif /* CONFIG_MMC, ... */
|
||||
|
||||
#endif /* ! __CONFIG_TSERIES_H__ */
|
|
@ -98,6 +98,7 @@
|
|||
|
||||
/* EHCI */
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_OMAP3_GPIO_2
|
||||
#define CONFIG_OMAP3_GPIO_5
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_OMAP
|
||||
|
@ -263,10 +264,9 @@
|
|||
"${mtdparts} " \
|
||||
"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
|
||||
"omapdss.def_disp=lcd;" \
|
||||
"bootm 0x82000000 0x84000000\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"run nandboot"
|
||||
"bootm 0x82000000 0x84000000\0" \
|
||||
"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
|
||||
"then source 82000000;else run nandboot;fi\0"
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
@ -395,6 +395,7 @@
|
|||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
|
|
208
include/configs/pengwyn.h
Normal file
208
include/configs/pengwyn.h
Normal file
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* pengwyn.h
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*
|
||||
* based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PENGWYN_H
|
||||
#define __CONFIG_PENGWYN_H
|
||||
|
||||
#define CONFIG_NAND
|
||||
#define CONFIG_SERIAL1
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 24000000
|
||||
#define V_SCLK V_OSCK
|
||||
|
||||
/* set env size */
|
||||
#define CONFIG_ENV_SIZE 0x4000
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x80200000\0" \
|
||||
"fdtaddr=0x80F80000\0" \
|
||||
"bootpart=0:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"fdtfile=am335x-pengwyn.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"rootpath=/export/rootfs\0" \
|
||||
"nfsopts=nolock\0" \
|
||||
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
|
||||
"::off\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
||||
"ip=dhcp\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
||||
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"mmcloados=run mmcargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr};\0" \
|
||||
"mmcboot=mmc dev ${mmcdev}; " \
|
||||
"if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loadimage; then " \
|
||||
"run loadfdt;" \
|
||||
"run mmcloados;" \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"setenv autoload no; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} ${bootfile}; " \
|
||||
"tftp ${fdtaddr} ${fdtfile}; " \
|
||||
"run netargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
|
||||
"nandrootfstype=ubifs rootwait=1\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${fdtaddr} u-boot-spl-os; " \
|
||||
"nand read ${loadaddr} kernel; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"run mmcboot;" \
|
||||
"run nandboot;"
|
||||
|
||||
/* NS16550 Configuration: primary UART via FDTI */
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_POWER_SUPPORT
|
||||
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||
|
||||
/* General network SPL */
|
||||
#define CONFIG_SPL_NET_SUPPORT
|
||||
#define CONFIG_SPL_ENV_SUPPORT
|
||||
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
|
||||
|
||||
/* NAND support */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_OMAP_GPMC
|
||||
#define CONFIG_NAND_OMAP_ELM
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
26, 27, 28, 29, 30, 31, 32, 33, \
|
||||
34, 35, 36, 37, 38, 39, 40, 41, \
|
||||
42, 43, 44, 45, 46, 47, 48, 49, \
|
||||
50, 51, 52, 53, 54, 55, 56, 57, }
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
|
||||
#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
|
||||
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
|
||||
"128k(SPL.backup1)," \
|
||||
"128k(SPL.backup2)," \
|
||||
"128k(SPL.backup3),1792k(u-boot)," \
|
||||
"128k(u-boot-spl-os)," \
|
||||
"128k(u-boot-env),5m(kernel),-(rootfs)"
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||
|
||||
/*
|
||||
* USB configuration. We enable MUSB support, both for host and for
|
||||
* gadget. We set USB0 as peripheral and USB1 as host, based on the
|
||||
* board schematic and physical port wired to each. Then for host we
|
||||
* add mass storage support.
|
||||
*/
|
||||
#define CONFIG_USB_MUSB_DSPS
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
#define CONFIG_MUSB_GADGET
|
||||
#define CONFIG_MUSB_PIO_ONLY
|
||||
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
|
||||
#define CONFIG_USB_GADGET
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
||||
#define CONFIG_MUSB_HOST
|
||||
#define CONFIG_AM335X_USB0
|
||||
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
|
||||
#define CONFIG_AM335X_USB1
|
||||
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
||||
|
||||
#if defined(CONFIG_MUSB_HOST)
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
/* disable host part of MUSB in SPL */
|
||||
#undef CONFIG_MUSB_HOST
|
||||
/* Disable CPSW SPL support so we fit within the 101KiB limit. */
|
||||
#undef CONFIG_SPL_ETH_SUPPORT
|
||||
#endif
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 1
|
||||
#define CONFIG_PHY_RESET 1
|
||||
#define CONFIG_PHY_NATSEMI
|
||||
|
||||
/* CPSW support */
|
||||
#define CONFIG_SPL_ETH_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
|
||||
|
||||
#endif /* ! __CONFIG_PENGWYN_H */
|
|
@ -83,6 +83,13 @@
|
|||
#define CONFIG_OMAP_HSMMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* GPIO banks */
|
||||
#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
|
||||
#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
|
||||
#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
|
||||
#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
|
||||
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
#define __CONFIG_TI_AM335X_COMMON_H__
|
||||
|
||||
#define CONFIG_AM33XX
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
|
||||
|
|
|
@ -163,4 +163,10 @@
|
|||
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
|
||||
#undef CONFIG_SYS_I2C
|
||||
#undef CONFIG_SYS_I2C_OMAP24XX
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_TI_OMAP4_COMMON_H */
|
||||
|
|
265
include/configs/tseries.h
Normal file
265
include/configs/tseries.h
Normal file
|
@ -0,0 +1,265 @@
|
|||
/*
|
||||
* tseries.h
|
||||
*
|
||||
* specific parts for B&R T-Series Motherboard
|
||||
*
|
||||
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
|
||||
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_TSERIES_H__
|
||||
#define __CONFIG_TSERIES_H__
|
||||
|
||||
#include <configs/bur_am335x_common.h>
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#define CONFIG_POWER_TPS65217
|
||||
|
||||
/* Support both device trees and ATAGs. */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
/*#define CONFIG_MACH_TYPE 3589*/
|
||||
#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
|
||||
|
||||
/* MMC/SD IP block */
|
||||
#if defined(CONFIG_EMMC_BOOT)
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_OMAP_HSMMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT
|
||||
/* RAW SD card / eMMC locations. */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#endif /* CONFIG_EMMC_BOOT */
|
||||
|
||||
/*
|
||||
* When we have SPI or NAND flash we expect to be making use of mtdparts,
|
||||
* both for ease of use in U-Boot and for passing information on to
|
||||
* the Linux kernel.
|
||||
*/
|
||||
#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
|
||||
#define CONFIG_MTD_DEVICE /* Required for mtdparts */
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#endif /* CONFIG_SPI_BOOT, ... */
|
||||
|
||||
#undef CONFIG_SPL_OS_BOOT
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
|
||||
|
||||
/* RAW SD card / eMMC */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
|
||||
|
||||
/* NAND */
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_CMD_SPL_NAND_OFS 0x080000 /* end of u-boot */
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
|
||||
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
|
||||
#endif /* CONFIG_NAND */
|
||||
#endif /* CONFIG_SPL_OS_BOOT */
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_SPL_NAND_AM33XX_BCH /* OMAP4 and later ELM support */
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SPL_NAND_BASE
|
||||
#define CONFIG_SPL_NAND_DRIVERS
|
||||
#define CONFIG_SPL_NAND_ECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#endif /* CONFIG_NAND */
|
||||
|
||||
/* Always 128 KiB env size */
|
||||
#define CONFIG_ENV_SIZE (128 << 10)
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define NANDARGS \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \
|
||||
"nandrootfstype=ubifs rootwait=1\0" \
|
||||
"nandimgsize=0x500000\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} kernel ${nandimgsize}; " \
|
||||
"bootz ${loadaddr}\0"
|
||||
#else
|
||||
#define NANDARGS ""
|
||||
#endif /* CONFIG_NAND */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define MMCARGS \
|
||||
"silent=1\0"
|
||||
#else
|
||||
#define MMCARGS ""
|
||||
#endif /* CONFIG_MMC */
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"autoload=0\0" \
|
||||
"loadaddr=0x80200000\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"rootpath=/tftpboot/tseries/rootfs-small\0" \
|
||||
"nfsopts=nolock\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
||||
"ip=dhcp\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"setenv autoload no; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} ${bootfile}; " \
|
||||
"run netargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
|
||||
"usb start; " \
|
||||
"fatload usb 0 0x80000000 updateubootusb.img; " \
|
||||
"source;\0" \
|
||||
"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
|
||||
"setenv autoload 0; " \
|
||||
"dhcp;" \
|
||||
"tftp 0x80000000 updateUBOOT.img;" \
|
||||
"source;\0" \
|
||||
NANDARGS \
|
||||
MMCARGS
|
||||
#endif /* !CONFIG_SPL_BUILD*/
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"run mmcboot1;"
|
||||
#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
/*
|
||||
* GPMC block. We support 1 device and the physical address to
|
||||
* access CS0 at is 0x8000000.
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x8000000
|
||||
#define CONFIG_NAND_OMAP_GPMC
|
||||
#define CONFIG_CMD_NAND
|
||||
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
|
||||
#define CONFIG_NAND_OMAP_ELM
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
26, 27, 28, 29, 30, 31, 32, 33, \
|
||||
34, 35, 36, 37, 38, 39, 40, 41, \
|
||||
42, 43, 44, 45, 46, 47, 48, 49, \
|
||||
50, 51, 52, 53, 54, 55, 56, 57, }
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
|
||||
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
|
||||
"128k(SPL)," \
|
||||
"128k(SPL.backup1)," \
|
||||
"128k(SPL.backup2)," \
|
||||
"128k(SPL.backup3)," \
|
||||
"512k(u-boot)," \
|
||||
"128k(u-boot-spl-os)," \
|
||||
"128k(u-boot-env)," \
|
||||
"5m(kernel),"\
|
||||
"-(rootfs)"
|
||||
#endif /* CONFIG_NAND */
|
||||
|
||||
/* USB configuration */
|
||||
#define CONFIG_USB_MUSB_DSPS
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
#define CONFIG_MUSB_PIO_ONLY
|
||||
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
|
||||
/* attention! not only for gadget, enables also highspeed in hostmode */
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_MUSB_HOST
|
||||
#define CONFIG_AM335X_USB0
|
||||
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
|
||||
#define CONFIG_AM335X_USB1
|
||||
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
||||
|
||||
#ifdef CONFIG_MUSB_HOST
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif /* CONFIG_MUSB_HOST */
|
||||
|
||||
#if defined(CONFIG_SPI_BOOT)
|
||||
/* McSPI IP block */
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_OMAP3_SPI
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#undef CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
|
||||
#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
|
||||
|
||||
#elif defined(CONFIG_EMMC_BOOT)
|
||||
#undef CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1
|
||||
#define CONFIG_SYS_MMC_ENV_PART 2
|
||||
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||
|
||||
#elif defined(CONFIG_NAND)
|
||||
#undef CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET 0x120000 /* TODO: Adresse definieren */
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
#else
|
||||
#error "no storage for Environment defined!"
|
||||
#endif
|
||||
/*
|
||||
* Common filesystems support. When we have removable storage we
|
||||
* enabled a number of useful commands and support.
|
||||
*/
|
||||
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_FAT_WRITE
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#endif /* CONFIG_MMC, ... */
|
||||
|
||||
#endif /* ! __CONFIG_TSERIES_H__ */
|
Loading…
Add table
Reference in a new issue