mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
This commit is contained in:
Tom Rini
commit
fb651b10d4
30 changed files with 1154 additions and 227 deletions
|
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@ -83,6 +83,7 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_T4160) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
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COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
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@ -102,6 +103,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
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COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
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COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
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COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
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COBJS-$(CONFIG_PPC_T4160) += t4240_ids.o
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COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
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COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
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@ -137,6 +139,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
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COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
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COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
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COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
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COBJS-$(CONFIG_PPC_T4160) += t4240_serdes.o
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COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
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COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
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COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
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@ -637,6 +637,28 @@ skip_l2:
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}
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#endif
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#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
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ccsr_usb_phy_t *usb_phy =
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(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
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setbits_be32(&usb_phy->pllprg[1],
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CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
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CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
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CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
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CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
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setbits_be32(&usb_phy->port1.ctrl,
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CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
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setbits_be32(&usb_phy->port1.drvvbuscfg,
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CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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setbits_be32(&usb_phy->port1.pwrfltcfg,
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CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
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setbits_be32(&usb_phy->port2.ctrl,
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CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
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setbits_be32(&usb_phy->port2.drvvbuscfg,
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CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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setbits_be32(&usb_phy->port2.pwrfltcfg,
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CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
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#endif
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#ifdef CONFIG_FMAN_ENET
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fman_enet_init();
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#endif
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@ -142,7 +142,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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}
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
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out_be32(&ddr->debug[28], 0x00003000);
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out_be32(&ddr->debug[28], 0x30003000);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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@ -164,7 +164,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
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}
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cfg >>= sd_prctl_shift;
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printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
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printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
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if (!is_serdes_prtcl_valid(sd, cfg))
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printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
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@ -128,24 +128,32 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
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childoff = fdt_subnode_offset(blob, off, name);
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if (create) {
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char handle[64], *p;
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strncpy(handle, name, sizeof(handle));
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p = strchr(handle, '@');
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if (!strncmp(name, "fman", 4)) {
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*p = *(p + 1);
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p++;
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}
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*p = '\0';
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dev_off = fdt_path_offset(blob, handle);
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/* skip this node if alias is not found */
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if (dev_off == -FDT_ERR_BADPATH)
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return 0;
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if (dev_off < 0)
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return dev_off;
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if (childoff <= 0)
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childoff = fdt_add_subnode(blob, off, name);
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/* need to update the dev_off after adding a subnode */
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dev_off = fdt_path_offset(blob, handle);
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if (dev_off < 0)
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return dev_off;
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if (childoff > 0) {
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char handle[64], *p;
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strncpy(handle, name, sizeof(handle));
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p = strchr(handle, '@');
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if (!strncmp(name, "fman", 4)) {
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*p = *(p + 1);
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p++;
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}
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*p = '\0';
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dev_off = fdt_path_offset(blob, handle);
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if (dev_off < 0)
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return dev_off;
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dev_handle = fdt_get_phandle(blob, dev_off);
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if (dev_handle <= 0) {
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dev_handle = fdt_alloc_phandle(blob);
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@ -69,9 +69,9 @@ __secondary_start_page:
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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mfspr r3,977
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mfspr r3,SPRN_HDBCR1
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oris r3,r3,0x0100
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mtspr 977,r3
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mtspr SPRN_HDBCR1,r3
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
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@ -93,10 +93,10 @@ __secondary_start_page:
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1: /* Erratum says set bits 55:60 to 001001 */
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msync
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isync
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mfspr r3,976
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mfspr r3,SPRN_HDBCR0
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li r4,0x48
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rlwimi r3,r4,0,0x1f8
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mtspr 976,r3
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mtspr SPRN_HDBCR0,r3
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isync
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2:
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#endif
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@ -159,9 +159,9 @@ __secondary_start_page:
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* we cannot access it yet before setting up a new TLB
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*/
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mfspr r0,SPRN_PIR
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#if defined(CONFIG_E6500)
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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* PIR definition for E6500
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* PIR definition for Chassis 2
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* 0-17 Reserved (logic 0s)
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* 8-19 CHIP_ID, 2'b00 - SoC 1
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* all others - reserved
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@ -187,7 +187,7 @@ __secondary_start_page:
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slwi r8,r4,6 /* spin table is padded to 64 byte */
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add r10,r3,r8
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#ifdef CONFIG_E6500
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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mfspr r0,SPRN_PIR
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/*
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* core 0 thread 0: pir reset value 0x00, new pir 0
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@ -132,10 +132,15 @@ void get_sys_info (sys_info_t * sysInfo)
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sysInfo->freqProcessor[cpu] =
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freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
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}
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#ifdef CONFIG_PPC_B4860
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#define FM1_CLK_SEL 0xe0000000
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#define FM1_CLK_SHIFT 29
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#else
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#define PME_CLK_SEL 0xe0000000
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#define PME_CLK_SHIFT 29
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#define FM1_CLK_SEL 0x1c000000
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#define FM1_CLK_SHIFT 26
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#endif
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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#ifdef CONFIG_SYS_DPAA_PME
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@ -185,6 +190,9 @@ void get_sys_info (sys_info_t * sysInfo)
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case 4:
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sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
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break;
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case 5:
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sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
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break;
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case 6:
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sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
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break;
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@ -285,6 +293,10 @@ void get_sys_info (sys_info_t * sysInfo)
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_QBMAN
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sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
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#endif
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#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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#else /* CONFIG_FSL_CORENET */
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@ -116,10 +116,10 @@ _start_e500:
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/* Erratum says set bits 55:60 to 001001 */
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msync
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isync
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mfspr r3,976
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mfspr r3,SPRN_HDBCR0
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li r4,0x48
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rlwimi r3,r4,0,0x1f8
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mtspr 976,r3
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mtspr SPRN_HDBCR0,r3
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isync
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2:
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#endif
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@ -173,52 +173,6 @@ l2_disabled:
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mfspr r1,DBSR
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mtspr DBSR,r1 /* Clear all valid bits */
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/*
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* Enable L1 Caches early
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*
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*/
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#ifdef CONFIG_SYS_CACHE_STASHING
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/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
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li r2,(32 + 0)
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mtspr L1CSR2,r2
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#endif
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/* Enable/invalidate the I-Cache */
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lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
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ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
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mtspr SPRN_L1CSR1,r2
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1:
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mfspr r3,SPRN_L1CSR1
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and. r1,r3,r2
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bne 1b
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lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
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ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
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mtspr SPRN_L1CSR1,r3
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isync
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2:
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mfspr r3,SPRN_L1CSR1
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andi. r1,r3,L1CSR1_ICE@l
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beq 2b
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/* Enable/invalidate the D-Cache */
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lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
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ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
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mtspr SPRN_L1CSR0,r2
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1:
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mfspr r3,SPRN_L1CSR0
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and. r1,r3,r2
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bne 1b
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lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
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ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
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mtspr SPRN_L1CSR0,r3
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isync
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2:
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mfspr r3,SPRN_L1CSR0
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andi. r1,r3,L1CSR0_DCE@l
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beq 2b
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.macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
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lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
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@ -372,9 +326,9 @@ l2_disabled:
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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mfspr r3,977
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mfspr r3,SPRN_HDBCR1
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oris r3,r3,0x0100
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mtspr 977,r3
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mtspr SPRN_HDBCR1,r3
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#endif
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/* Enable Branch Prediction */
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@ -782,11 +736,57 @@ enable_l2_cluster_l2:
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bne 1b
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lis r4, L2CSR0_L2E@h
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sync
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stw r4, 0(r3) /* eanble L2 */
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stw r4, 0(r3) /* enable L2 */
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delete_ccsr_l2_tlb:
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delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
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#endif
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/*
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* Enable the L1. On e6500, this has to be done
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* after the L2 is up.
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*/
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#ifdef CONFIG_SYS_CACHE_STASHING
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/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
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li r2,(32 + 0)
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mtspr L1CSR2,r2
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#endif
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/* Enable/invalidate the I-Cache */
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lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
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ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
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mtspr SPRN_L1CSR1,r2
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1:
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mfspr r3,SPRN_L1CSR1
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and. r1,r3,r2
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bne 1b
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lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
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ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
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mtspr SPRN_L1CSR1,r3
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isync
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2:
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mfspr r3,SPRN_L1CSR1
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andi. r1,r3,L1CSR1_ICE@l
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beq 2b
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|
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/* Enable/invalidate the D-Cache */
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lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
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ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
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mtspr SPRN_L1CSR0,r2
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1:
|
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mfspr r3,SPRN_L1CSR0
|
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and. r1,r3,r2
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bne 1b
|
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|
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lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
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ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
|
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mtspr SPRN_L1CSR0,r3
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isync
|
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2:
|
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mfspr r3,SPRN_L1CSR0
|
||||
andi. r1,r3,L1CSR0_DCE@l
|
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beq 2b
|
||||
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
|
||||
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
|
||||
#define LAW_SIZE_1M 0x13
|
||||
|
|
|
|||
|
|
@ -31,7 +31,8 @@ struct serdes_config {
|
|||
u8 lanes[SRDS_MAX_LANES];
|
||||
};
|
||||
|
||||
static struct serdes_config serdes1_cfg_tbl[] = {
|
||||
#ifdef CONFIG_PPC_T4240
|
||||
static const struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
|
|
@ -66,7 +67,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
|
|||
NONE, NONE, QSGMII_FM1_A, NONE}},
|
||||
{}
|
||||
};
|
||||
static struct serdes_config serdes2_cfg_tbl[] = {
|
||||
static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
|
|
@ -150,7 +151,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
|
|||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
|
||||
{}
|
||||
};
|
||||
static struct serdes_config serdes3_cfg_tbl[] = {
|
||||
static const struct serdes_config serdes3_cfg_tbl[] = {
|
||||
/* SerDes 3 */
|
||||
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
|
||||
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
|
||||
|
|
@ -174,20 +175,151 @@ static struct serdes_config serdes3_cfg_tbl[] = {
|
|||
SRIO1, SRIO1, SRIO1, SRIO1}},
|
||||
{}
|
||||
};
|
||||
static struct serdes_config serdes4_cfg_tbl[] = {
|
||||
static const struct serdes_config serdes4_cfg_tbl[] = {
|
||||
/* SerDes 4 */
|
||||
{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
|
||||
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
|
||||
{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
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||||
{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
|
||||
{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
|
||||
{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
|
||||
{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
|
||||
{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
|
||||
{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
|
||||
{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
|
||||
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
|
||||
{}
|
||||
};
|
||||
static struct serdes_config *serdes_cfg_tbl[] = {
|
||||
#elif defined(CONFIG_PPC_T4160)
|
||||
static const struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
|
||||
XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
|
||||
{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
|
||||
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
|
||||
{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
|
||||
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
|
||||
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
|
||||
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
|
||||
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
|
||||
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
|
||||
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
|
||||
NONE, NONE, QSGMII_FM1_A, NONE} },
|
||||
{}
|
||||
};
|
||||
static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
NONE, NONE} },
|
||||
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
|
||||
NONE, QSGMII_FM1_A, NONE, NONE} },
|
||||
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
|
||||
NONE, QSGMII_FM1_A, NONE, NONE} },
|
||||
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
|
||||
NONE, QSGMII_FM1_A, NONE, NONE} },
|
||||
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
|
||||
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
|
||||
NONE, QSGMII_FM1_A, NONE, NONE} },
|
||||
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
|
||||
NONE, NONE, NONE, NONE} },
|
||||
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
NONE, NONE, NONE, NONE} },
|
||||
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
|
||||
NONE, NONE, NONE, NONE} },
|
||||
{56, {NONE, XFI_FM1_MAC10,
|
||||
XFI_FM2_MAC10, NONE,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
|
||||
{57, {NONE, XFI_FM1_MAC10,
|
||||
XFI_FM2_MAC10, NONE,
|
||||
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
|
||||
NONE, NONE} },
|
||||
{}
|
||||
};
|
||||
static const struct serdes_config serdes3_cfg_tbl[] = {
|
||||
/* SerDes 3 */
|
||||
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
|
||||
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
|
||||
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
|
||||
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
|
||||
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
|
||||
NONE, NONE, NONE, NONE} },
|
||||
{}
|
||||
};
|
||||
static const struct serdes_config serdes4_cfg_tbl[] = {
|
||||
/* SerDes 4 */
|
||||
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
|
||||
{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
|
||||
{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
|
||||
{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
|
||||
{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
|
||||
{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
|
||||
{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
|
||||
{}
|
||||
}
|
||||
;
|
||||
#else
|
||||
#error "Need to define SerDes protocol"
|
||||
#endif
|
||||
static const struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
serdes2_cfg_tbl,
|
||||
serdes3_cfg_tbl,
|
||||
|
|
@ -196,7 +328,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
|
|||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
struct serdes_config *ptr;
|
||||
const struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
|
@ -213,7 +345,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
|||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
struct serdes_config *ptr;
|
||||
const struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ static struct cpu_type cpu_type_list[] = {
|
|||
CPU_TYPE_ENTRY(P5040, P5040, 4),
|
||||
CPU_TYPE_ENTRY(T4240, T4240, 0),
|
||||
CPU_TYPE_ENTRY(T4120, T4120, 0),
|
||||
CPU_TYPE_ENTRY(T4160, T4160, 0),
|
||||
CPU_TYPE_ENTRY(B4860, B4860, 0),
|
||||
CPU_TYPE_ENTRY(G4860, G4860, 0),
|
||||
CPU_TYPE_ENTRY(G4060, G4060, 0),
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ const char * step_to_string(unsigned int step) {
|
|||
return step_string_tbl[s];
|
||||
}
|
||||
|
||||
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
|
||||
static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
|
||||
unsigned int dbw_cap_adj[])
|
||||
{
|
||||
int i, j;
|
||||
|
|
@ -354,6 +354,11 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
|
|||
return total_mem;
|
||||
}
|
||||
|
||||
/* Use weak function to allow board file to override the address assignment */
|
||||
__attribute__((weak, alias("__step_assign_addresses")))
|
||||
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
|
||||
unsigned int dbw_cap_adj[]);
|
||||
|
||||
unsigned long long
|
||||
fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
|
||||
unsigned int size_only)
|
||||
|
|
@ -541,14 +546,17 @@ phys_size_t fsl_ddr_sdram(void)
|
|||
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
|
||||
|
||||
/* setup 3-way interleaving before enabling DDRC */
|
||||
switch (info.memctl_opts[0].memctl_interleaving_mode) {
|
||||
case FSL_DDR_3WAY_1KB_INTERLEAVING:
|
||||
case FSL_DDR_3WAY_4KB_INTERLEAVING:
|
||||
case FSL_DDR_3WAY_8KB_INTERLEAVING:
|
||||
fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
if (info.memctl_opts[0].memctl_interleaving) {
|
||||
switch (info.memctl_opts[0].memctl_interleaving_mode) {
|
||||
case FSL_DDR_3WAY_1KB_INTERLEAVING:
|
||||
case FSL_DDR_3WAY_4KB_INTERLEAVING:
|
||||
case FSL_DDR_3WAY_8KB_INTERLEAVING:
|
||||
fsl_ddr_set_intl3r(
|
||||
info.memctl_opts[0].memctl_interleaving_mode);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Program configuration registers. */
|
||||
|
|
|
|||
|
|
@ -537,14 +537,46 @@
|
|||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
|
||||
#elif defined(CONFIG_PPC_T4160)
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
||||
#define CONFIG_MAX_CPUS 8
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SRDS_3
|
||||
#define CONFIG_SYS_FSL_SRDS_4
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_NUM_FMAN 2
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
||||
#define CONFIG_SYS_NUM_FM2_DTSEC 7
|
||||
#define CONFIG_SYS_NUM_FM2_10GEC 1
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
||||
#define CONFIG_SYS_FSL_ERRATUM_A005871
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
|
||||
#elif defined(CONFIG_PPC_B4420)
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
|
|
|
|||
|
|
@ -1676,18 +1676,17 @@ typedef struct cpc_corenet {
|
|||
/* Global Utilities Block */
|
||||
#ifdef CONFIG_FSL_CORENET
|
||||
typedef struct ccsr_gur {
|
||||
u32 porsr1; /* POR status */
|
||||
u8 res1[28];
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u8 res2[12];
|
||||
u32 gpiocr; /* GPIO control */
|
||||
u8 res3[12];
|
||||
u32 gpoutdr; /* General-purpose output data */
|
||||
u8 res4[12];
|
||||
u32 gpindr; /* General-purpose input data */
|
||||
u8 res5[12];
|
||||
u32 alt_pmuxcr; /* Alt function signal multiplex control */
|
||||
u8 res6[12];
|
||||
u32 gpporcr2; /* General-purpose POR configuration 2 */
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
|
||||
#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
|
||||
#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
|
||||
#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
|
|
@ -1831,7 +1830,7 @@ typedef struct ccsr_gur {
|
|||
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
#if defined(CONFIG_PPC_T4240)
|
||||
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
|
||||
|
|
@ -1899,7 +1898,7 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
|
||||
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T4240)
|
||||
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
|
||||
|
|
@ -2829,12 +2828,53 @@ typedef struct ccsr_pme {
|
|||
u8 res4[0x400];
|
||||
} ccsr_pme_t;
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
struct ccsr_usb_port_ctrl {
|
||||
u32 ctrl;
|
||||
u32 drvvbuscfg;
|
||||
u32 pwrfltcfg;
|
||||
u32 sts;
|
||||
u8 res_14[0xc];
|
||||
u32 bistcfg;
|
||||
u32 biststs;
|
||||
u32 abistcfg;
|
||||
u32 abiststs;
|
||||
u8 res_30[0x10];
|
||||
u32 xcvrprg;
|
||||
u32 anaprg;
|
||||
u32 anadrv;
|
||||
u32 anasts;
|
||||
};
|
||||
|
||||
typedef struct ccsr_usb_phy {
|
||||
u32 id;
|
||||
struct ccsr_usb_port_ctrl port1;
|
||||
u8 res_50[0xc];
|
||||
u32 tvr;
|
||||
u32 pllprg[4];
|
||||
u8 res_70[0x4];
|
||||
u32 anaccfg;
|
||||
u32 dbg;
|
||||
u8 res_7c[0x4];
|
||||
struct ccsr_usb_port_ctrl port2;
|
||||
u8 res_dc[0x334];
|
||||
} ccsr_usb_phy_t;
|
||||
|
||||
#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
|
||||
#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
|
||||
#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
|
||||
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
|
||||
#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
|
||||
#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
|
||||
#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
|
||||
#else
|
||||
typedef struct ccsr_usb_phy {
|
||||
u8 res0[0x18];
|
||||
u32 usb_enable_override;
|
||||
u8 res[0xe4];
|
||||
} ccsr_usb_phy_t;
|
||||
#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
|
||||
struct ccsr_raide {
|
||||
|
|
|
|||
|
|
@ -575,6 +575,16 @@
|
|||
#define SPRN_MSSSR0 0x3f7
|
||||
#endif
|
||||
|
||||
#define SPRN_HDBCR0 0x3d0
|
||||
#define SPRN_HDBCR1 0x3d1
|
||||
#define SPRN_HDBCR2 0x3d2
|
||||
#define SPRN_HDBCR3 0x3d3
|
||||
#define SPRN_HDBCR4 0x3d4
|
||||
#define SPRN_HDBCR5 0x3d5
|
||||
#define SPRN_HDBCR6 0x3d6
|
||||
#define SPRN_HDBCR7 0x277
|
||||
#define SPRN_HDBCR8 0x278
|
||||
|
||||
/* Short-hand versions for a number of the above SPRNs */
|
||||
|
||||
#define CTR SPRN_CTR /* Counter Register */
|
||||
|
|
@ -1099,6 +1109,7 @@
|
|||
#define SVR_P5040 0x820400
|
||||
#define SVR_T4240 0x824000
|
||||
#define SVR_T4120 0x824001
|
||||
#define SVR_T4160 0x824100
|
||||
#define SVR_B4860 0X868000
|
||||
#define SVR_G4860 0x868001
|
||||
#define SVR_G4060 0x868003
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/fsl_ddr_dimm_params.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -188,3 +189,74 @@ phys_size_t initdram(int board_type)
|
|||
puts(" DDR: ");
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
|
||||
unsigned int dbw_cap_adj[])
|
||||
{
|
||||
int i, j;
|
||||
unsigned long long total_mem, current_mem_base, total_ctlr_mem;
|
||||
unsigned long long rank_density, ctlr_density = 0;
|
||||
|
||||
current_mem_base = 0ull;
|
||||
total_mem = 0;
|
||||
/*
|
||||
* This board has soldered DDR chips. DDRC1 has two rank.
|
||||
* DDRC2 has only one rank.
|
||||
* Assigning DDRC2 to lower address and DDRC1 to higher address.
|
||||
*/
|
||||
if (pinfo->memctl_opts[0].memctl_interleaving) {
|
||||
rank_density = pinfo->dimm_params[0][0].rank_density >>
|
||||
dbw_cap_adj[0];
|
||||
ctlr_density = rank_density;
|
||||
|
||||
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
|
||||
rank_density, ctlr_density);
|
||||
for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
|
||||
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
|
||||
case FSL_DDR_CACHE_LINE_INTERLEAVING:
|
||||
case FSL_DDR_PAGE_INTERLEAVING:
|
||||
case FSL_DDR_BANK_INTERLEAVING:
|
||||
case FSL_DDR_SUPERBANK_INTERLEAVING:
|
||||
total_ctlr_mem = 2 * ctlr_density;
|
||||
break;
|
||||
default:
|
||||
panic("Unknown interleaving mode");
|
||||
}
|
||||
pinfo->common_timing_params[i].base_address =
|
||||
current_mem_base;
|
||||
pinfo->common_timing_params[i].total_mem =
|
||||
total_ctlr_mem;
|
||||
total_mem = current_mem_base + total_ctlr_mem;
|
||||
debug("ctrl %d base 0x%llx\n", i, current_mem_base);
|
||||
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Simple linear assignment if memory
|
||||
* controllers are not interleaved.
|
||||
*/
|
||||
for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
|
||||
total_ctlr_mem = 0;
|
||||
pinfo->common_timing_params[i].base_address =
|
||||
current_mem_base;
|
||||
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
|
||||
/* Compute DIMM base addresses. */
|
||||
unsigned long long cap =
|
||||
pinfo->dimm_params[i][j].capacity;
|
||||
pinfo->dimm_params[i][j].base_address =
|
||||
current_mem_base;
|
||||
debug("ctrl %d dimm %d base 0x%llx\n",
|
||||
i, j, current_mem_base);
|
||||
current_mem_base += cap;
|
||||
total_ctlr_mem += cap;
|
||||
}
|
||||
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
|
||||
pinfo->common_timing_params[i].total_mem =
|
||||
total_ctlr_mem;
|
||||
total_mem += total_ctlr_mem;
|
||||
}
|
||||
}
|
||||
debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
|
||||
|
||||
return total_mem;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
u32 rank_gb;
|
||||
u32 clk_adjust;
|
||||
u32 wrlvl_start;
|
||||
u32 wrlvl_ctl_2;
|
||||
|
|
@ -36,16 +37,19 @@ struct board_specific_parameters {
|
|||
static const struct board_specific_parameters udimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
|
||||
* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
|
||||
*/
|
||||
{2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
|
||||
{2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
|
||||
{1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
|
||||
{1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
|
||||
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
|
||||
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
|
||||
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
|
||||
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
|
||||
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
|
||||
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
|
||||
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
|
||||
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -61,19 +65,19 @@ static const struct board_specific_parameters *udimms[] = {
|
|||
static const struct board_specific_parameters rdimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
|
||||
* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
|
||||
*/
|
||||
{4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
|
||||
{4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
|
||||
{4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
|
||||
{2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
|
||||
{2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
|
||||
{1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
|
||||
{1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
|
||||
{4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
|
||||
{4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
|
||||
{2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
|
||||
{2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
|
||||
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
|
||||
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
|
||||
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -113,7 +117,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
|
|||
*/
|
||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
||||
while (pbsp->datarate_mhz_high) {
|
||||
if (pbsp->n_ranks == pdimm->n_ranks) {
|
||||
if (pbsp->n_ranks == pdimm->n_ranks &&
|
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
|
||||
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
||||
popts->cpo_override = pbsp->cpo;
|
||||
popts->write_data_delay =
|
||||
|
|
@ -146,6 +151,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
|
|||
panic("DIMM is not supported by this board");
|
||||
}
|
||||
found:
|
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
|
||||
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
|
||||
"wrlvl_ctrl_3 0x%x\n",
|
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
|
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
|
||||
pbsp->wrlvl_ctl_3);
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
#define EMI1_SLOT4 4
|
||||
#define EMI1_SLOT5 5
|
||||
#define EMI1_SLOT7 7
|
||||
#define EMI2 8 /* tmp, FIXME */
|
||||
#define EMI2 8
|
||||
/* Slot6 and Slot8 do not have EMI connections */
|
||||
|
||||
static int mdio_mux[NUM_FM_PORTS];
|
||||
|
|
@ -71,6 +71,14 @@ static const char *mdio_names[] = {
|
|||
|
||||
static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
|
||||
static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
|
||||
static u8 slot_qsgmii_phyaddr[5][4] = {
|
||||
{0, 0, 0, 0},/* not used, to make index match slot No. */
|
||||
{0, 1, 2, 3},
|
||||
{4, 5, 6, 7},
|
||||
{8, 9, 0xa, 0xb},
|
||||
{0xc, 0xd, 0xe, 0xf},
|
||||
};
|
||||
static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
|
||||
|
||||
static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
|
||||
{
|
||||
|
|
@ -180,21 +188,212 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
|
|||
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
|
||||
enum fm_port port, int offset)
|
||||
{
|
||||
if (mdio_mux[port] == EMI1_RGMII)
|
||||
fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
|
||||
|
||||
/* TODO: will do with dts */
|
||||
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
|
||||
switch (port) {
|
||||
case FM1_DTSEC1:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy21");
|
||||
break;
|
||||
case FM1_DTSEC2:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy22");
|
||||
break;
|
||||
case FM1_DTSEC3:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy23");
|
||||
break;
|
||||
case FM1_DTSEC4:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy24");
|
||||
break;
|
||||
case FM1_DTSEC6:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy12");
|
||||
break;
|
||||
case FM1_DTSEC9:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy14");
|
||||
else
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"phy_sgmii4");
|
||||
break;
|
||||
case FM1_DTSEC10:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy13");
|
||||
else
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"phy_sgmii3");
|
||||
break;
|
||||
case FM2_DTSEC1:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy41");
|
||||
break;
|
||||
case FM2_DTSEC2:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy42");
|
||||
break;
|
||||
case FM2_DTSEC3:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy43");
|
||||
break;
|
||||
case FM2_DTSEC4:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy44");
|
||||
break;
|
||||
case FM2_DTSEC6:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy32");
|
||||
break;
|
||||
case FM2_DTSEC9:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy34");
|
||||
else
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"phy_sgmii12");
|
||||
break;
|
||||
case FM2_DTSEC10:
|
||||
if (qsgmiiphy_fix[port])
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"sgmii_phy33");
|
||||
else
|
||||
fdt_set_phy_handle(blob, prop, pa,
|
||||
"phy_sgmii11");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fdt_fixup_board_enet(void *fdt)
|
||||
{
|
||||
/* TODO: will do with dts */
|
||||
int i;
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
|
||||
|
||||
prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
|
||||
for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
switch (mdio_mux[i]) {
|
||||
case EMI1_SLOT1:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot1");
|
||||
break;
|
||||
case EMI1_SLOT2:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot2");
|
||||
break;
|
||||
case EMI1_SLOT3:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot3");
|
||||
break;
|
||||
case EMI1_SLOT4:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot4");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
/* check if it's XFI interface for 10g */
|
||||
if ((prtcl2 == 56) || (prtcl2 == 57)) {
|
||||
fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
|
||||
break;
|
||||
}
|
||||
switch (i) {
|
||||
case FM1_10GEC1:
|
||||
fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
|
||||
break;
|
||||
case FM1_10GEC2:
|
||||
fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
|
||||
break;
|
||||
case FM2_10GEC1:
|
||||
fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
|
||||
break;
|
||||
case FM2_10GEC2:
|
||||
fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void initialize_qsgmiiphy_fix(void)
|
||||
{
|
||||
int i;
|
||||
unsigned short reg;
|
||||
|
||||
for (i = 1; i <= 4; i++) {
|
||||
/*
|
||||
* Try to read if a SGMII card is used, we do it slot by slot.
|
||||
* if a SGMII PHY address is valid on a slot, then we mark
|
||||
* all ports on the slot, then fix the PHY address for the
|
||||
* marked port when doing dtb fixup.
|
||||
*/
|
||||
if (miiphy_read(mdio_names[i],
|
||||
SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
|
||||
debug("Slot%d PHY ID register 2 read failed\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
|
||||
|
||||
if (reg == 0xFFFF) {
|
||||
/* No physical device present at this address */
|
||||
continue;
|
||||
}
|
||||
|
||||
switch (i) {
|
||||
case 1:
|
||||
qsgmiiphy_fix[FM1_DTSEC5] = 1;
|
||||
qsgmiiphy_fix[FM1_DTSEC6] = 1;
|
||||
qsgmiiphy_fix[FM1_DTSEC9] = 1;
|
||||
qsgmiiphy_fix[FM1_DTSEC10] = 1;
|
||||
break;
|
||||
case 2:
|
||||
qsgmiiphy_fix[FM1_DTSEC1] = 1;
|
||||
qsgmiiphy_fix[FM1_DTSEC2] = 1;
|
||||
qsgmiiphy_fix[FM1_DTSEC3] = 1;
|
||||
qsgmiiphy_fix[FM1_DTSEC4] = 1;
|
||||
break;
|
||||
case 3:
|
||||
qsgmiiphy_fix[FM2_DTSEC5] = 1;
|
||||
qsgmiiphy_fix[FM2_DTSEC6] = 1;
|
||||
qsgmiiphy_fix[FM2_DTSEC9] = 1;
|
||||
qsgmiiphy_fix[FM2_DTSEC10] = 1;
|
||||
break;
|
||||
case 4:
|
||||
qsgmiiphy_fix[FM2_DTSEC1] = 1;
|
||||
qsgmiiphy_fix[FM2_DTSEC2] = 1;
|
||||
qsgmiiphy_fix[FM2_DTSEC3] = 1;
|
||||
qsgmiiphy_fix[FM2_DTSEC4] = 1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FMAN_ENET)
|
||||
int i;
|
||||
int i, idx, lane, slot;
|
||||
struct memac_mdio_info dtsec_mdio_info;
|
||||
struct memac_mdio_info tgec_mdio_info;
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
|
@ -248,44 +447,48 @@ int board_eth_init(bd_t *bis)
|
|||
case 28:
|
||||
case 36:
|
||||
/* SGMII in Slot1 and Slot2 */
|
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
|
||||
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
|
||||
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
|
||||
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
|
||||
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
|
||||
fm_info_set_phy_address(FM1_DTSEC9,
|
||||
SGMII_CARD_PORT4_PHY_ADDR);
|
||||
slot_qsgmii_phyaddr[1][3]);
|
||||
fm_info_set_phy_address(FM1_DTSEC10,
|
||||
SGMII_CARD_PORT3_PHY_ADDR);
|
||||
slot_qsgmii_phyaddr[1][2]);
|
||||
}
|
||||
break;
|
||||
case 38:
|
||||
fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
|
||||
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
|
||||
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
|
||||
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
|
||||
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
|
||||
fm_info_set_phy_address(FM1_DTSEC9,
|
||||
QSGMII_CARD_PHY_ADDR);
|
||||
slot_qsgmii_phyaddr[1][3]);
|
||||
fm_info_set_phy_address(FM1_DTSEC10,
|
||||
QSGMII_CARD_PHY_ADDR);
|
||||
slot_qsgmii_phyaddr[1][2]);
|
||||
}
|
||||
break;
|
||||
case 40:
|
||||
case 46:
|
||||
case 48:
|
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
|
||||
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
|
||||
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
|
||||
fm_info_set_phy_address(FM1_DTSEC10,
|
||||
SGMII_CARD_PORT3_PHY_ADDR);
|
||||
slot_qsgmii_phyaddr[1][3]);
|
||||
fm_info_set_phy_address(FM1_DTSEC9,
|
||||
SGMII_CARD_PORT4_PHY_ADDR);
|
||||
slot_qsgmii_phyaddr[1][2]);
|
||||
}
|
||||
fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
|
||||
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
|
||||
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
|
||||
break;
|
||||
default:
|
||||
puts("Invalid SerDes1 protocol for T4240QDS\n");
|
||||
|
|
@ -293,7 +496,7 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
||||
int idx = i - FM1_DTSEC1, lane, slot;
|
||||
idx = i - FM1_DTSEC1;
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1,
|
||||
|
|
@ -334,8 +537,16 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
|
||||
idx = i - FM1_10GEC1;
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1,
|
||||
XAUI_FM1_MAC9 + idx);
|
||||
if (lane < 0)
|
||||
break;
|
||||
slot = lane_to_slot_fsm1[lane];
|
||||
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
||||
fm_disable_port(i);
|
||||
mdio_mux[i] = EMI2;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
|
|
@ -344,7 +555,6 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2)
|
||||
switch (srds_prtcl_s2) {
|
||||
case 1:
|
||||
|
|
@ -364,68 +574,64 @@ int board_eth_init(bd_t *bis)
|
|||
case 26:
|
||||
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
|
||||
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
||||
break;
|
||||
case 28:
|
||||
case 36:
|
||||
/* SGMII in Slot3 and Slot4 */
|
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
||||
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
|
||||
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
|
||||
break;
|
||||
case 38:
|
||||
/* QSGMII in Slot3 and Slot4 */
|
||||
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
||||
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
|
||||
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
|
||||
break;
|
||||
case 40:
|
||||
case 46:
|
||||
case 48:
|
||||
/* SGMII in Slot3 */
|
||||
fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
|
||||
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
|
||||
/* QSGMII in Slot4 */
|
||||
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
||||
break;
|
||||
case 50:
|
||||
case 52:
|
||||
case 54:
|
||||
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
||||
break;
|
||||
case 56:
|
||||
case 57:
|
||||
/* XFI in Slot3, SGMII in Slot4 */
|
||||
fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
|
||||
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
|
||||
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
|
||||
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
|
||||
break;
|
||||
default:
|
||||
puts("Invalid SerDes2 protocol for T4240QDS\n");
|
||||
|
|
@ -433,7 +639,7 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
|
||||
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
|
||||
int idx = i - FM2_DTSEC1, lane, slot;
|
||||
idx = i - FM2_DTSEC1;
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_2,
|
||||
|
|
@ -477,8 +683,16 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
|
||||
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
|
||||
idx = i - FM2_10GEC1;
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_2,
|
||||
XAUI_FM2_MAC9 + idx);
|
||||
if (lane < 0)
|
||||
break;
|
||||
slot = lane_to_slot_fsm2[lane];
|
||||
if (QIXIS_READ(present2) & (1 << (slot - 1)))
|
||||
fm_disable_port(i);
|
||||
mdio_mux[i] = EMI2;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
|
|
@ -488,6 +702,8 @@ int board_eth_init(bd_t *bis)
|
|||
}
|
||||
#endif /* CONFIG_SYS_NUM_FMAN */
|
||||
|
||||
initialize_qsgmiiphy_fix();
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FMAN_ENET */
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
#define QIXIS_DDRCLK_125 0x2
|
||||
#define QIXIS_DDRCLK_133 0x3
|
||||
|
||||
#define BRDCFG5_RESET 0x00
|
||||
#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
|
||||
|
||||
#define BRDCFG12_SD3EN_MASK 0x20
|
||||
#define BRDCFG12_SD3MX_MASK 0x08
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ int checkboard(void)
|
|||
for (i = 0; i < MAX_SERDES; i++) {
|
||||
static const char *freq[] = {
|
||||
"100", "125", "156.25", "161.1328125"};
|
||||
unsigned int clock = (sw >> (2 * i)) & 3;
|
||||
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
|
||||
|
||||
printf("SERDES%u=%sMHz ", i+1, freq[clock]);
|
||||
}
|
||||
|
|
@ -132,6 +132,228 @@ int select_i2c_ch_pca9547(u8 ch)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* read_voltage from sensor on I2C bus
|
||||
* We use average of 4 readings, waiting for 532us befor another reading
|
||||
*/
|
||||
#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
|
||||
#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
|
||||
|
||||
static inline int read_voltage(void)
|
||||
{
|
||||
int i, ret, voltage_read = 0;
|
||||
u16 vol_mon;
|
||||
|
||||
for (i = 0; i < NUM_READINGS; i++) {
|
||||
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
|
||||
I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
|
||||
if (ret) {
|
||||
printf("VID: failed to read core voltage\n");
|
||||
return ret;
|
||||
}
|
||||
if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
|
||||
printf("VID: Core voltage sensor error\n");
|
||||
return -1;
|
||||
}
|
||||
debug("VID: bus voltage reads 0x%04x\n", vol_mon);
|
||||
/* LSB = 4mv */
|
||||
voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
|
||||
udelay(WAIT_FOR_ADC);
|
||||
}
|
||||
/* calculate the average */
|
||||
voltage_read /= NUM_READINGS;
|
||||
|
||||
return voltage_read;
|
||||
}
|
||||
|
||||
/*
|
||||
* We need to calculate how long before the voltage starts to drop or increase
|
||||
* It returns with the loop count. Each loop takes several readings (532us)
|
||||
*/
|
||||
static inline int wait_for_voltage_change(int vdd_last)
|
||||
{
|
||||
int timeout, vdd_current;
|
||||
|
||||
vdd_current = read_voltage();
|
||||
/* wait until voltage starts to drop */
|
||||
for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
|
||||
timeout < 100; timeout++) {
|
||||
vdd_current = read_voltage();
|
||||
}
|
||||
if (timeout >= 100) {
|
||||
printf("VID: Voltage adjustment timeout\n");
|
||||
return -1;
|
||||
}
|
||||
return timeout;
|
||||
}
|
||||
|
||||
/*
|
||||
* argument 'wait' is the time we know the voltage difference can be measured
|
||||
* this function keeps reading the voltage until it is stable
|
||||
*/
|
||||
static inline int wait_for_voltage_stable(int wait)
|
||||
{
|
||||
int timeout, vdd_current, vdd_last;
|
||||
|
||||
vdd_last = read_voltage();
|
||||
udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
|
||||
/* wait until voltage is stable */
|
||||
vdd_current = read_voltage();
|
||||
for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
|
||||
timeout < 100; timeout++) {
|
||||
vdd_last = vdd_current;
|
||||
udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
|
||||
vdd_current = read_voltage();
|
||||
}
|
||||
if (timeout >= 100) {
|
||||
printf("VID: Voltage adjustment timeout\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return vdd_current;
|
||||
}
|
||||
|
||||
static inline int set_voltage(u8 vid)
|
||||
{
|
||||
int wait, vdd_last;
|
||||
|
||||
vdd_last = read_voltage();
|
||||
QIXIS_WRITE(brdcfg[6], vid);
|
||||
wait = wait_for_voltage_change(vdd_last);
|
||||
if (wait < 0)
|
||||
return -1;
|
||||
debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
|
||||
wait = wait ? wait : 1;
|
||||
|
||||
vdd_last = wait_for_voltage_stable(wait);
|
||||
if (vdd_last < 0)
|
||||
return -1;
|
||||
debug("VID: Current voltage is %d mV\n", vdd_last);
|
||||
|
||||
return vdd_last;
|
||||
}
|
||||
|
||||
|
||||
static int adjust_vdd(void)
|
||||
{
|
||||
int re_enable = disable_interrupts();
|
||||
ccsr_gur_t __iomem *gur =
|
||||
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 fusesr;
|
||||
u8 vid, vid_current;
|
||||
int vdd_target, vdd_current, vdd_last;
|
||||
int ret;
|
||||
static const uint16_t vdd[32] = {
|
||||
0, /* unused */
|
||||
9875, /* 0.9875V */
|
||||
9750,
|
||||
9625,
|
||||
9500,
|
||||
9375,
|
||||
9250,
|
||||
9125,
|
||||
9000,
|
||||
8875,
|
||||
8750,
|
||||
8625,
|
||||
8500,
|
||||
8375,
|
||||
8250,
|
||||
8125,
|
||||
10000, /* 1.0000V */
|
||||
10125,
|
||||
10250,
|
||||
10375,
|
||||
10500,
|
||||
10625,
|
||||
10750,
|
||||
10875,
|
||||
11000,
|
||||
0, /* reserved */
|
||||
};
|
||||
struct vdd_drive {
|
||||
u8 vid;
|
||||
unsigned voltage;
|
||||
};
|
||||
|
||||
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
|
||||
if (ret) {
|
||||
debug("VID: I2c failed to switch channel\n");
|
||||
ret = -1;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* get the voltage ID from fuse status register */
|
||||
fusesr = in_be32(&gur->dcfg_fusesr);
|
||||
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
|
||||
FSL_CORENET_DCFG_FUSESR_VID_MASK;
|
||||
if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
|
||||
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
|
||||
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
|
||||
}
|
||||
vdd_target = vdd[vid];
|
||||
if (vdd_target == 0) {
|
||||
debug("VID: VID not used\n");
|
||||
ret = 0;
|
||||
goto exit;
|
||||
} else {
|
||||
/* round up and divice by 10 to get a value in mV */
|
||||
vdd_target = DIV_ROUND_UP(vdd_target, 10);
|
||||
debug("VID: vid = %d mV\n", vdd_target);
|
||||
}
|
||||
|
||||
/*
|
||||
* Check current board VID setting
|
||||
* Voltage regulator support output to 6.250mv step
|
||||
* The highes voltage allowed for this board is (vid=0x40) 1.21250V
|
||||
* the lowest is (vid=0x7f) 0.81875V
|
||||
*/
|
||||
vid_current = QIXIS_READ(brdcfg[6]);
|
||||
vdd_current = 121250 - (vid_current - 0x40) * 625;
|
||||
debug("VID: Current vid setting is (0x%x) %d mV\n",
|
||||
vid_current, vdd_current/100);
|
||||
|
||||
/*
|
||||
* Read voltage monitor to check real voltage.
|
||||
* Voltage monitor LSB is 4mv.
|
||||
*/
|
||||
vdd_last = read_voltage();
|
||||
if (vdd_last < 0) {
|
||||
printf("VID: Could not read voltage sensor abort VID adjustment\n");
|
||||
ret = -1;
|
||||
goto exit;
|
||||
}
|
||||
debug("VID: Core voltage is at %d mV\n", vdd_last);
|
||||
/*
|
||||
* Adjust voltage to at or 8mV above target.
|
||||
* Each step of adjustment is 6.25mV.
|
||||
* Stepping down too fast may cause over current.
|
||||
*/
|
||||
while (vdd_last > 0 && vid_current < 0x80 &&
|
||||
vdd_last > (vdd_target + 8)) {
|
||||
vid_current++;
|
||||
vdd_last = set_voltage(vid_current);
|
||||
}
|
||||
/*
|
||||
* Check if we need to step up
|
||||
* This happens when board voltage switch was set too low
|
||||
*/
|
||||
while (vdd_last > 0 && vid_current >= 0x40 &&
|
||||
vdd_last < vdd_target + 2) {
|
||||
vid_current--;
|
||||
vdd_last = set_voltage(vid_current);
|
||||
}
|
||||
if (vdd_last > 0)
|
||||
printf("VID: Core voltage %d mV\n", vdd_last);
|
||||
else
|
||||
ret = -1;
|
||||
|
||||
exit:
|
||||
if (re_enable)
|
||||
enable_interrupts();
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure Crossbar switches for Front-Side SerDes Ports */
|
||||
int config_frontside_crossbar_vsc3316(void)
|
||||
{
|
||||
|
|
@ -282,8 +504,15 @@ int board_early_init_r(void)
|
|||
setup_portals();
|
||||
#endif
|
||||
|
||||
/* Disable remote I2C connectoin */
|
||||
QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
|
||||
/* Disable remote I2C connection to qixis fpga */
|
||||
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
|
||||
|
||||
/*
|
||||
* Adjust core voltage according to voltage ID
|
||||
* This function changes I2C mux to channel 2.
|
||||
*/
|
||||
if (adjust_vdd())
|
||||
printf("Warning: Adjusting core voltage failed.\n");
|
||||
|
||||
/* Configure board SERDES ports crossbar */
|
||||
config_frontside_crossbar_vsc3316();
|
||||
|
|
@ -357,7 +586,7 @@ int misc_init_r(void)
|
|||
|
||||
sw = QIXIS_READ(brdcfg[2]);
|
||||
for (i = 0; i < MAX_SERDES; i++) {
|
||||
unsigned int clock = (sw >> (2 * i)) & 3;
|
||||
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
|
||||
switch (clock) {
|
||||
case 0:
|
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
|
||||
|
|
|
|||
|
|
@ -890,9 +890,12 @@ BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freesca
|
|||
stxgp3 powerpc mpc85xx stxgp3 stx
|
||||
stxssa powerpc mpc85xx stxssa stx - stxssa
|
||||
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
|
||||
T4240QDS powerpc mpc85xx t4qds freescale
|
||||
T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
||||
T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
||||
T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240
|
||||
T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
||||
T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
||||
T4160QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160
|
||||
T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
||||
T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
||||
B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
|
||||
B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
|
||||
B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080.o
|
|||
COBJS-$(CONFIG_PPC_P5020) += p5020.o
|
||||
COBJS-$(CONFIG_PPC_P5040) += p5040.o
|
||||
COBJS-$(CONFIG_PPC_T4240) += t4240.o
|
||||
COBJS-$(CONFIG_PPC_T4160) += t4240.o
|
||||
COBJS-$(CONFIG_PPC_B4420) += b4860.o
|
||||
COBJS-$(CONFIG_PPC_B4860) += b4860.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -568,6 +568,8 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
|
|||
num = fm_eth->num;
|
||||
|
||||
#ifdef CONFIG_SYS_FMAN_V3
|
||||
if (fm_eth->type == FM_ETH_10G_E)
|
||||
num += 8;
|
||||
base = ®->memac[num].fm_memac;
|
||||
phyregs = ®->memac[num].fm_memac_mdio;
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -152,4 +152,6 @@ struct fm_eth {
|
|||
#define MAX_RXBUF_LOG2 11
|
||||
#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
|
||||
|
||||
#define PORT_IS_ENABLED(port) fm_info[fm_port_to_index(port)].enabled
|
||||
|
||||
#endif /* __FM_H__ */
|
||||
|
|
|
|||
|
|
@ -74,9 +74,15 @@ struct fm_eth_info fm_info[] = {
|
|||
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
|
||||
FM_TGEC_INFO_INITIALIZER(1, 1),
|
||||
#endif
|
||||
#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
|
||||
FM_TGEC_INFO_INITIALIZER(1, 2),
|
||||
#endif
|
||||
#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
|
||||
FM_TGEC_INFO_INITIALIZER(2, 1),
|
||||
#endif
|
||||
#if (CONFIG_SYS_NUM_FM2_10GEC >= 2)
|
||||
FM_TGEC_INFO_INITIALIZER(2, 2),
|
||||
#endif
|
||||
};
|
||||
|
||||
int fm_standard_init(bd_t *bis)
|
||||
|
|
@ -232,6 +238,26 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
|
|||
return ;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FMAN_V3
|
||||
/*
|
||||
* Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when
|
||||
* FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the
|
||||
* dual-role MAC is not disabled, ditto for other dual-role MACs.
|
||||
*/
|
||||
if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
|
||||
((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
|
||||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
|
||||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10)))
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2)
|
||||
||
|
||||
((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) ||
|
||||
((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) ||
|
||||
((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) ||
|
||||
((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
|
||||
#endif
|
||||
)
|
||||
return;
|
||||
#endif
|
||||
/* board code might have caused offset to change */
|
||||
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
|
||||
|
||||
|
|
@ -249,10 +275,15 @@ void fdt_fixup_fman_ethernet(void *blob)
|
|||
{
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_SYS_FMAN_V3
|
||||
for (i = 0; i < ARRAY_SIZE(fm_info); i++)
|
||||
ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
|
||||
#else
|
||||
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
|
||||
if (fm_info[i].type == FM_ETH_1G_E)
|
||||
ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac");
|
||||
else
|
||||
ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,12 +70,18 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
|
|||
if (is_device_disabled(port))
|
||||
return PHY_INTERFACE_MODE_NONE;
|
||||
|
||||
if ((port == FM1_10GEC1 || port == FM1_10GEC2)
|
||||
&& (is_serdes_configured(XAUI_FM1)))
|
||||
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
|
||||
((is_serdes_configured(XAUI_FM1_MAC9)) ||
|
||||
(is_serdes_configured(XAUI_FM1_MAC10)) ||
|
||||
(is_serdes_configured(XFI_FM1_MAC9)) ||
|
||||
(is_serdes_configured(XFI_FM1_MAC10))))
|
||||
return PHY_INTERFACE_MODE_XGMII;
|
||||
|
||||
if ((port == FM2_10GEC1 || port == FM2_10GEC2)
|
||||
&& (is_serdes_configured(XAUI_FM2)))
|
||||
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
|
||||
((is_serdes_configured(XAUI_FM2_MAC9)) ||
|
||||
(is_serdes_configured(XAUI_FM2_MAC10)) ||
|
||||
(is_serdes_configured(XFI_FM2_MAC9)) ||
|
||||
(is_serdes_configured(XFI_FM2_MAC10))))
|
||||
return PHY_INTERFACE_MODE_XGMII;
|
||||
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
|
|
|
|||
|
|
@ -48,6 +48,19 @@
|
|||
#define MIIM_VSC8601_SKEW_CTRL 0x1c
|
||||
|
||||
#define PHY_EXT_PAGE_ACCESS 0x1f
|
||||
#define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
|
||||
#define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3
|
||||
|
||||
/* Vitesse VSC8574 control register */
|
||||
#define MIIM_VSC8574_MAC_SERDES_CON 0x10
|
||||
#define MIIM_VSC8574_MAC_SERDES_ANEG 0x80
|
||||
#define MIIM_VSC8574_GENERAL18 0x12
|
||||
#define MIIM_VSC8574_GENERAL19 0x13
|
||||
|
||||
/* Vitesse VSC8574 gerenal purpose register 18 */
|
||||
#define MIIM_VSC8574_18G_SGMII 0x80f0
|
||||
#define MIIM_VSC8574_18G_QSGMII 0x80e0
|
||||
#define MIIM_VSC8574_18G_CMDSTAT 0x8000
|
||||
|
||||
/* CIS8201 */
|
||||
static int vitesse_config(struct phy_device *phydev)
|
||||
|
|
@ -145,6 +158,49 @@ static int vsc8601_config(struct phy_device *phydev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int vsc8574_config(struct phy_device *phydev)
|
||||
{
|
||||
u32 val;
|
||||
/* configure regiser 19G for MAC */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
|
||||
PHY_EXT_PAGE_ACCESS_GENERAL);
|
||||
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
|
||||
/* set bit 15:14 to '01' for QSGMII mode */
|
||||
val = (val & 0x3fff) | (1 << 14);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE,
|
||||
MIIM_VSC8574_GENERAL19, val);
|
||||
/* Enable 4 ports MAC QSGMII */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
|
||||
MIIM_VSC8574_18G_QSGMII);
|
||||
} else {
|
||||
/* set bit 15:14 to '00' for SGMII mode */
|
||||
val = val & 0x3fff;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
|
||||
/* Enable 4 ports MAC SGMII */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
|
||||
MIIM_VSC8574_18G_SGMII);
|
||||
}
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
|
||||
/* When bit 15 is cleared the command has completed */
|
||||
while (val & MIIM_VSC8574_18G_CMDSTAT)
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
|
||||
|
||||
/* Enable Serdes Auto-negotiation */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
|
||||
PHY_EXT_PAGE_ACCESS_EXTENDED3);
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
|
||||
val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
|
||||
|
||||
genphy_config_aneg(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy_driver VSC8211_driver = {
|
||||
.name = "Vitesse VSC8211",
|
||||
.uid = 0xfc4b0,
|
||||
|
|
@ -185,6 +241,16 @@ static struct phy_driver VSC8234_driver = {
|
|||
.shutdown = &genphy_shutdown,
|
||||
};
|
||||
|
||||
static struct phy_driver VSC8574_driver = {
|
||||
.name = "Vitesse VSC8574",
|
||||
.uid = 0x704a0,
|
||||
.mask = 0xffff0,
|
||||
.features = PHY_GBIT_FEATURES,
|
||||
.config = &vsc8574_config,
|
||||
.startup = &vitesse_startup,
|
||||
.shutdown = &genphy_shutdown,
|
||||
};
|
||||
|
||||
static struct phy_driver VSC8601_driver = {
|
||||
.name = "Vitesse VSC8601",
|
||||
.uid = 0x70420,
|
||||
|
|
@ -244,6 +310,7 @@ int phy_vitesse_init(void)
|
|||
phy_register(&VSC8244_driver);
|
||||
phy_register(&VSC8211_driver);
|
||||
phy_register(&VSC8221_driver);
|
||||
phy_register(&VSC8574_driver);
|
||||
phy_register(&VSC8662_driver);
|
||||
phy_register(&cis8201_driver);
|
||||
phy_register(&cis8204_driver);
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@
|
|||
*/
|
||||
#define CONFIG_T4240QDS
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_PPC_T4240
|
||||
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_PCIE4
|
||||
|
|
|
|||
|
|
@ -444,11 +444,19 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
|
||||
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
|
||||
|
||||
/* VSC Crossbar switches */
|
||||
#define CONFIG_VSC_CROSSBAR
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
#define I2C_MUX_CH_VOL_MONITOR 0xa
|
||||
#define I2C_MUX_CH_VSC3316_FS 0xc
|
||||
#define I2C_MUX_CH_VSC3316_BS 0xd
|
||||
|
||||
/* Voltage monitor on channel 2*/
|
||||
#define I2C_VOL_MONITOR_ADDR 0x40
|
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
||||
|
||||
/* VSC Crossbar switches */
|
||||
#define CONFIG_VSC_CROSSBAR
|
||||
#define VSC3316_FSM_TX_ADDR 0x70
|
||||
#define VSC3316_FSM_RX_ADDR 0x71
|
||||
|
||||
|
|
@ -504,7 +512,7 @@ unsigned long get_board_ddr_clk(void);
|
|||
*/
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_SPI_FLASH_SST
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE 0
|
||||
|
|
@ -641,15 +649,10 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||
#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */
|
||||
#define XFI_CARD_PORT2_PHY_ADDR 0x2
|
||||
#define XFI_CARD_PORT3_PHY_ADDR 0x3
|
||||
#define XFI_CARD_PORT4_PHY_ADDR 0x4
|
||||
#define QSGMII_CARD_PHY_ADDR 0x5
|
||||
#define FM1_10GEC1_PHY_ADDR 0x6
|
||||
#define FM1_10GEC2_PHY_ADDR 0x7
|
||||
#define FM2_10GEC1_PHY_ADDR 0x8
|
||||
#define FM2_10GEC2_PHY_ADDR 0x9
|
||||
#define FM1_10GEC1_PHY_ADDR 0x0
|
||||
#define FM1_10GEC2_PHY_ADDR 0x1
|
||||
#define FM2_10GEC1_PHY_ADDR 0x2
|
||||
#define FM2_10GEC2_PHY_ADDR 0x3
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
|
@ -783,8 +786,21 @@ unsigned long get_board_ddr_clk(void);
|
|||
|
||||
#define __USB_PHY_TYPE utmi
|
||||
|
||||
/*
|
||||
* T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
|
||||
* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
|
||||
* cacheline interleaving. It can be cacheline, page, bank, superbank.
|
||||
* See doc/README.fsl-ddr for details.
|
||||
*/
|
||||
#ifdef CONFIG_PPC_T4240
|
||||
#define CTRL_INTLV_PREFERED 3way_4KB
|
||||
#else
|
||||
#define CTRL_INTLV_PREFERED cacheline
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \
|
||||
"hwconfig=fsl_ddr:" \
|
||||
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
|
||||
"bank_intlv=auto;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ enum fm_eth_type {
|
|||
|
||||
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
|
||||
{ \
|
||||
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
|
||||
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
|
||||
.index = idx, \
|
||||
.num = n - 1, \
|
||||
.type = FM_ETH_10G_E, \
|
||||
|
|
@ -96,7 +96,7 @@ enum fm_eth_type {
|
|||
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
|
||||
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
|
||||
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
|
||||
offsetof(struct ccsr_fman, memac[n-1]),\
|
||||
offsetof(struct ccsr_fman, memac[n-1+8]),\
|
||||
}
|
||||
#else
|
||||
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ typedef enum {
|
|||
PHY_INTERFACE_MODE_MII,
|
||||
PHY_INTERFACE_MODE_GMII,
|
||||
PHY_INTERFACE_MODE_SGMII,
|
||||
PHY_INTERFACE_MODE_QSGMII,
|
||||
PHY_INTERFACE_MODE_TBI,
|
||||
PHY_INTERFACE_MODE_RMII,
|
||||
PHY_INTERFACE_MODE_RGMII,
|
||||
|
|
@ -67,6 +68,7 @@ static const char *phy_interface_strings[] = {
|
|||
[PHY_INTERFACE_MODE_MII] = "mii",
|
||||
[PHY_INTERFACE_MODE_GMII] = "gmii",
|
||||
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
|
||||
[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
|
||||
[PHY_INTERFACE_MODE_TBI] = "tbi",
|
||||
[PHY_INTERFACE_MODE_RMII] = "rmii",
|
||||
[PHY_INTERFACE_MODE_RGMII] = "rgmii",
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue