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cmd: fpga: Clean coding style

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No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Michal Simek 2013-04-26 13:10:07 +02:00
parent ee976c1b03
commit fc598412ce
1 changed files with 107 additions and 106 deletions
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61
common/cmd_fpga.c
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@ -66,8 +66,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
length = (*dataptr << 8) + *(dataptr + 1); length = (*dataptr << 8) + *(dataptr + 1);
dataptr += 2; dataptr += 2;
if (*dataptr++ != 0x61) { if (*dataptr++ != 0x61) {
debug("%s: Design name identifier not recognized " debug("%s: Design name id not recognized in bitstream\n",
"in bitstream\n",
__func__); __func__);
return FPGA_FAIL; return FPGA_FAIL;
} }
@ -81,8 +80,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
/* get part number (identifier, length, string) */ /* get part number (identifier, length, string) */
if (*dataptr++ != 0x62) { if (*dataptr++ != 0x62) {
printf("%s: Part number identifier not recognized " printf("%s: Part number id not recognized in bitstream\n",
"in bitstream\n",
__func__); __func__);
return FPGA_FAIL; return FPGA_FAIL;
} }
@ -121,7 +119,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
/* get fpga data length (identifier, length) */ /* get fpga data length (identifier, length) */
if (*dataptr++ != 0x65) { if (*dataptr++ != 0x65) {
printf("%s: Data length identifier not recognized in bitstream\n", printf("%s: Data length id not recognized in bitstream\n",
__func__); __func__);
return FPGA_FAIL; return FPGA_FAIL;
} }
@ -176,9 +174,9 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
if (fit_parse_subimage(argv[3], (ulong)fpga_data, if (fit_parse_subimage(argv[3], (ulong)fpga_data,
&fit_addr, &fit_uname)) { &fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr; fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image " debug("* fpga: subimage '%s' from FIT image ",
"at 0x%08lx\n", fit_uname);
fit_uname, fit_addr); debug("at 0x%08lx\n", fit_addr);
} else } else
#endif #endif
{ {
@ -192,7 +190,8 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
dev = (int)simple_strtoul(argv[2], NULL, 16); dev = (int)simple_strtoul(argv[2], NULL, 16);
debug("%s: device = %d\n", __func__, dev); debug("%s: device = %d\n", __func__, dev);
/* FIXME - this is a really weak test */ /* FIXME - this is a really weak test */
if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */ if ((argc == 3) && (dev > fpga_count())) {
/* must be buffer ptr */
debug("%s: Assuming buffer pointer in arg 3\n", debug("%s: Assuming buffer pointer in arg 3\n",
__func__); __func__);
@ -200,15 +199,15 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
if (fit_parse_subimage(argv[2], (ulong)fpga_data, if (fit_parse_subimage(argv[2], (ulong)fpga_data,
&fit_addr, &fit_uname)) { &fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr; fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image " debug("* fpga: subimage '%s' from FIT image ",
"at 0x%08lx\n", fit_uname);
fit_uname, fit_addr); debug("at 0x%08lx\n", fit_addr);
} else } else
#endif #endif
{ {
fpga_data = (void *)dev; fpga_data = (void *)dev;
debug("* fpga: cmdline image address = " debug("* fpga: cmdline image addr = 0x%08lx\n",
"0x%08lx\n", (ulong)fpga_data); (ulong)fpga_data);
} }
debug("%s: fpga_data = 0x%x\n", debug("%s: fpga_data = 0x%x\n",
@ -221,8 +220,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
break; break;
default: default:
debug("%s: Too many or too few args (%d)\n", debug("%s: Too many or too few args (%d)\n", __func__, argc);
__func__, argc);
op = FPGA_NONE; /* force usage display */ op = FPGA_NONE; /* force usage display */
break; break;
} }
@ -273,7 +271,8 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
switch (genimg_get_format(fpga_data)) { switch (genimg_get_format(fpga_data)) {
case IMAGE_FORMAT_LEGACY: case IMAGE_FORMAT_LEGACY:
{ {
image_header_t *hdr = (image_header_t *)fpga_data; image_header_t *hdr =
(image_header_t *)fpga_data;
ulong data; ulong data;
data = (ulong)image_get_data(hdr); data = (ulong)image_get_data(hdr);
@ -299,9 +298,11 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
} }
/* get fpga component image node offset */ /* get fpga component image node offset */
noffset = fit_image_get_node (fit_hdr, fit_uname); noffset = fit_image_get_node(fit_hdr,
fit_uname);
if (noffset < 0) { if (noffset < 0) {
printf ("Can't find '%s' FIT subimage\n", fit_uname); printf("Can't find '%s' FIT subimage\n",
fit_uname);
return 1; return 1;
} }
@ -312,8 +313,9 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
} }
/* get fpga subimage data address and length */ /* get fpga subimage data address and length */
if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) { if (fit_image_get_data(fit_hdr, noffset,
puts ("Could not find fpga subimage data\n"); &fit_data, &data_size)) {
puts("Fpga subimage data not found\n");
return 1; return 1;
} }
@ -336,7 +338,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
printf("Unknown operation\n"); printf("Unknown operation\n");
return CMD_RET_USAGE; return CMD_RET_USAGE;
} }
return (rc); return rc;
} }
/* /*
@ -347,21 +349,20 @@ static int fpga_get_op (char *opstr)
{ {
int op = FPGA_NONE; int op = FPGA_NONE;
if (!strcmp ("info", opstr)) { if (!strcmp("info", opstr))
op = FPGA_INFO; op = FPGA_INFO;
} else if (!strcmp ("loadb", opstr)) { else if (!strcmp("loadb", opstr))
op = FPGA_LOADB; op = FPGA_LOADB;
} else if (!strcmp ("load", opstr)) { else if (!strcmp("load", opstr))
op = FPGA_LOAD; op = FPGA_LOAD;
} else if (!strcmp ("loadmk", opstr)) { else if (!strcmp("loadmk", opstr))
op = FPGA_LOADMK; op = FPGA_LOADMK;
} else if (!strcmp ("dump", opstr)) { else if (!strcmp("dump", opstr))
op = FPGA_DUMP; op = FPGA_DUMP;
}
if (op == FPGA_NONE) { if (op == FPGA_NONE)
printf("Unknown fpga operation \"%s\"\n", opstr); printf("Unknown fpga operation \"%s\"\n", opstr);
}
return op; return op;
} }