From 555a6529532c0ac82d92f26d56e9becad72216db Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 15 Sep 2017 11:33:53 -0700 Subject: [PATCH 1/9] boston: Drop unused return value The boston lowlevel_init() function zeroes the return register v0, despite the function not being expected to return a value & that value never being used. Remove the redundant assignment to v0. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- board/imgtec/boston/lowlevel_init.S | 1 - 1 file changed, 1 deletion(-) diff --git a/board/imgtec/boston/lowlevel_init.S b/board/imgtec/boston/lowlevel_init.S index 0c01aa981d..46c9c1d269 100644 --- a/board/imgtec/boston/lowlevel_init.S +++ b/board/imgtec/boston/lowlevel_init.S @@ -34,7 +34,6 @@ LEAF(lowlevel_init) PTR_LA a0, msg_ddr_ok bal lowlevel_display - move v0, zero jr s0 END(lowlevel_init) From 64f733d3fab26d0444096cf8dd4f5fb2bb298c22 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 15 Sep 2017 11:34:31 -0700 Subject: [PATCH 2/9] boston: Remove unused label in lowlevel_display The lowlevel_display() function includes a "1:" label which is never used. Remove it. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- board/imgtec/boston/lowlevel_init.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/imgtec/boston/lowlevel_init.S b/board/imgtec/boston/lowlevel_init.S index 46c9c1d269..02a75a8ee7 100644 --- a/board/imgtec/boston/lowlevel_init.S +++ b/board/imgtec/boston/lowlevel_init.S @@ -51,5 +51,5 @@ LEAF(lowlevel_display) sw k1, 4(AT) #endif .set pop -1: jr ra + jr ra END(lowlevel_display) From 73780b012e2794246046a81ef7d2122454bf249f Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 15 Sep 2017 11:35:54 -0700 Subject: [PATCH 3/9] MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to 2 or 3 for 32 bit or 64 bit builds respectively. This macro is never actually used though, so remove the dead code. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- arch/mips/cpu/u-boot.lds | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index bd5536f013..fc943af923 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -5,12 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#if defined(CONFIG_64BIT) -#define PTR_COUNT_SHIFT 3 -#else -#define PTR_COUNT_SHIFT 2 -#endif - OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS From c5bf161facd5c10348c7e3963af6bd1cc9a79167 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 30 Oct 2017 16:58:21 -0700 Subject: [PATCH 4/9] Update Paul Burton's email address MIPS is no longer a part of Imagination Technologies, and as such my @imgtec.com email address will soon cease to function. This patch updates occurrances of it with my new @mips.com email address, and adds an entry in .mailmap such that git (& tools such as get_maintainer.pl when examining history) will use the new address. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- .mailmap | 1 + board/imgtec/boston/MAINTAINERS | 2 +- board/imgtec/malta/MAINTAINERS | 2 +- board/imgtec/malta/superio.c | 2 +- board/imgtec/malta/superio.h | 2 +- drivers/pci/pci_msc01.c | 2 +- include/msc01.h | 2 +- include/pci_msc01.h | 2 +- 8 files changed, 8 insertions(+), 7 deletions(-) diff --git a/.mailmap b/.mailmap index 14b5ad7e5c..bd7267241a 100644 --- a/.mailmap +++ b/.mailmap @@ -20,6 +20,7 @@ Jagan Teki Jagan Teki Jagan Teki Markus Klotzbuecher +Paul Burton Prabhakar Kushwaha Rajeshwari Shinde Ricardo Ribalda diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS index ec850d2f91..81f067d690 100644 --- a/board/imgtec/boston/MAINTAINERS +++ b/board/imgtec/boston/MAINTAINERS @@ -1,5 +1,5 @@ BOSTON BOARD -M: Paul Burton +M: Paul Burton S: Maintained F: board/imgtec/boston/ F: include/configs/boston.h diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS index 052ec67b14..b1cf297f4f 100644 --- a/board/imgtec/malta/MAINTAINERS +++ b/board/imgtec/malta/MAINTAINERS @@ -1,5 +1,5 @@ MALTA BOARD -M: Paul Burton +M: Paul Burton S: Maintained F: board/imgtec/malta/ F: include/configs/malta.h diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c index 7865ae2b70..d6ada4f87d 100644 --- a/board/imgtec/malta/superio.c +++ b/board/imgtec/malta/superio.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton + * Author: Paul Burton * * Setup code for the FDC37M817 super I/O controller * diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h index 271c462eac..f0ae1422b8 100644 --- a/board/imgtec/malta/superio.h +++ b/board/imgtec/malta/superio.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton + * Author: Paul Burton * * Setup code for the FDC37M817 super I/O controller * diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c index 284ffa09b6..a1b9116e4d 100644 --- a/drivers/pci/pci_msc01.c +++ b/drivers/pci/pci_msc01.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton + * Author: Paul Burton * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/msc01.h b/include/msc01.h index 37cf963f13..7ee243bec3 100644 --- a/include/msc01.h +++ b/include/msc01.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton + * Author: Paul Burton * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/include/pci_msc01.h b/include/pci_msc01.h index 54945a7a8f..066c6622da 100644 --- a/include/pci_msc01.h +++ b/include/pci_msc01.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2013 Imagination Technologies - * Author: Paul Burton + * Author: Paul Burton * * SPDX-License-Identifier: GPL-2.0+ */ From 219c2db384ffc4877c52bd58e7b55a62b663fed2 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 21 Nov 2017 11:18:37 -0800 Subject: [PATCH 5/9] MIPS: Ensure cache ops complete in cache maintenance functions A typical use of cache maintenance functions is to force writeback of data which a device is about to read using DMA - for example a descriptor or command structure. Such users of cache maintenance functions require that operations on the cache have completed before they proceed to instruct a device to read memory. This requires that we place a completion barrier (ie. sync instruction) between the cache ops and whatever write informs the device to perform DMA. Whilst strictly speaking this isn't all users of the cache maintenance functions & we could instead place the barriers in the drivers that require them, it would be much more invasive to do so than to just have the barrier be the default by placing it in the cache functions themselves. The cost is low enough that it shouldn't matter to us in any rare cases that we use the cache functions when not performing DMA. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- arch/mips/lib/cache.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 91b037f87d..eba7fff316 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -10,6 +10,7 @@ #ifdef CONFIG_MIPS_L2_CACHE #include #endif +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -116,7 +117,7 @@ void flush_cache(ulong start_addr, ulong size) /* flush I-cache & D-cache simultaneously */ cache_loop(start_addr, start_addr + size, ilsize, HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I); - return; + goto ops_done; } /* flush D-cache */ @@ -129,6 +130,10 @@ void flush_cache(ulong start_addr, ulong size) /* flush I-cache */ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); + +ops_done: + /* ensure cache ops complete before any further memory accesses */ + sync(); } void flush_dcache_range(ulong start_addr, ulong stop) @@ -145,6 +150,9 @@ void flush_dcache_range(ulong start_addr, ulong stop) /* flush L2 cache */ if (slsize) cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); + + /* ensure cache ops complete before any further memory accesses */ + sync(); } void invalidate_dcache_range(ulong start_addr, ulong stop) @@ -161,4 +169,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); + + /* ensure cache ops complete before any further memory accesses */ + sync(); } From d8b326976a44f185c52255458142086e0e8a7c34 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 21 Nov 2017 11:18:38 -0800 Subject: [PATCH 6/9] MIPS: Clear instruction hazards in flush_cache() When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to flush_cache(). This handles the bulk of the work to ensure the new instructions will execute as expected, however it does not ensure that the CPU pipeline doesn't already contain instructions taken from a stale view of the affected memory. This could theoretically be a problem for relocation, but in practice typically isn't because we sync caches for enough code after the entry point of the newly written code that by the time the CPU pipeline might possibly fetch any of it we'll have long ago written it back & invalidated any stale icache entries. This is however a problem for shorter regions of code. In preparation for later patches which write shorter segments of code, ensure any instruction hazards are cleared by flush_cache() by introducing & using a new instruction_hazard_barrier() function which makes use of the jr.hb instruction to clear the hazard. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- arch/mips/include/asm/system.h | 13 +++++++++++++ arch/mips/lib/cache.c | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index c9c5961462..eaf1b2290d 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -14,8 +14,10 @@ #ifndef _ASM_SYSTEM_H #define _ASM_SYSTEM_H +#include #include #include +#include #if 0 #include #endif @@ -270,4 +272,15 @@ static inline void execution_hazard_barrier(void) ".set reorder"); } +static inline void instruction_hazard_barrier(void) +{ + unsigned long tmp; + + asm volatile( + __stringify(PTR_LA) "\t%0, 1f\n" + " jr.hb %0\n" + "1: .insn" + : "=&r"(tmp)); +} + #endif /* _ASM_SYSTEM_H */ diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index eba7fff316..8e5b028c66 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -12,6 +12,7 @@ #endif #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -134,6 +135,9 @@ void flush_cache(ulong start_addr, ulong size) ops_done: /* ensure cache ops complete before any further memory accesses */ sync(); + + /* ensure the pipeline doesn't contain now-invalid instructions */ + instruction_hazard_barrier(); } void flush_dcache_range(ulong start_addr, ulong stop) From cc4f36435fb39c8c89aa6cfc9c0ffb680727352d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 21 Nov 2017 11:18:39 -0800 Subject: [PATCH 7/9] MIPS: Break out of cache loops for unimplemented caches If we run on a CPU which doesn't implement a particular cache then we would previously get stuck in an infinite loop, executing a cache op on the first "line" of the missing cache & then incrementing the address by 0. This was being avoided for the L2 caches, but not for the L1s. Fix this by generalising the check for a zero line size & avoiding the cache op loop when this is the case. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- arch/mips/lib/cache.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 8e5b028c66..e305f3207a 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -98,6 +98,9 @@ static inline unsigned long scache_line_size(void) const unsigned int cache_ops[] = { ops }; \ unsigned int i; \ \ + if (!lsize) \ + break; \ + \ for (; addr <= aend; addr += lsize) { \ for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \ mips_cache(cache_ops[i], addr); \ @@ -125,9 +128,7 @@ void flush_cache(ulong start_addr, ulong size) cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); /* flush L2 cache */ - if (slsize) - cache_loop(start_addr, start_addr + size, slsize, - HIT_WRITEBACK_INV_SD); + cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); /* flush I-cache */ cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); @@ -152,8 +153,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D); /* flush L2 cache */ - if (slsize) - cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); + cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); /* ensure cache ops complete before any further memory accesses */ sync(); @@ -169,8 +169,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop) return; /* invalidate L2 cache */ - if (slsize) - cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); + cache_loop(start_addr, stop, slsize, HIT_INVALIDATE_SD); cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D); From fabcffe9305842970c51661a3506fff818eefe8a Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 21 Nov 2017 12:35:31 -0800 Subject: [PATCH 8/9] boston: Set CONFIG_SYS_LOAD_ADDR to 0x88000000 Generally we load Linux kernels on Boston boards in the form of FIT images containing a compressed kernel binary. Linux is linked at 0x80100000 and so we need to decompress the kernel binary to that address, however this is our default load address which means that unless explicitly avoided we hit a decompression error as the uncompressed kernel binary overwrites its compressed version from the FIT image. Avoid this by adjusting CONFIG_SYS_LOAD_ADDR to 0x88000000 (or 0xffffffff88000000 for MIPS64 builds) which avoids the address overlap between compressed & uncompressed kernel binaries. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- include/configs/boston.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/boston.h b/include/configs/boston.h index ee4e4a37ea..fdd5ef5632 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -34,7 +34,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000) From caead80a66271d2de809acf410f8648c31ed5805 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 21 Nov 2017 14:31:07 -0800 Subject: [PATCH 9/9] boston: Add u-boot.mcs make target U-Boot is generally flashed to a MIPS Boston development board by means of a .mcs file which Xilinx Vivado software can write to the flash present on the board. As such we'd generally want to produce an mcs file when building U-Boot to target the Boston board. Introduce a make target for u-boot.mcs which generates it using the srec_cat tool available from the SRecord project, and build it by default when srec_cat is present. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de --- board/imgtec/boston/config.mk | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 board/imgtec/boston/config.mk diff --git a/board/imgtec/boston/config.mk b/board/imgtec/boston/config.mk new file mode 100644 index 0000000000..2775727744 --- /dev/null +++ b/board/imgtec/boston/config.mk @@ -0,0 +1,14 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -$2 $< -binary -offset $3 + +u-boot.mcs: u-boot.bin + $(call cmd,srec_cat,intel,0x7c00000) + +# if srec_cat is present build u-boot.mcs by default +has_srec_cat = $(call try-run,srec_cat -VERSion,y,n) +ALL-$(has_srec_cat) += u-boot.mcs +CLEAN_FILES += u-boot.mcs