Merge branch 'master' of git://git.denx.de/u-boot-socfpga

This commit is contained in:
Tom Rini 2018-10-31 17:15:55 -04:00
commit fdaccfeb5e
4 changed files with 16 additions and 3 deletions

View file

@ -807,7 +807,6 @@ config ARCH_SOCFPGA
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
select SYS_NS16550
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
imply CMD_DM
@ -817,6 +816,7 @@ config ARCH_SOCFPGA
imply DM_SPI_FLASH
imply FAT_WRITE
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"

View file

@ -453,7 +453,7 @@ int fpgamgr_program_finish(void)
*/
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
unsigned long status;
int status;
/* disable all signals from hps peripheral controller to fpga */
writel(0, &system_manager_base->fpgaintf_en_global);

View file

@ -204,7 +204,7 @@ static int fpgamgr_program_poll_usermode(void)
*/
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
unsigned long status;
int status;
if ((uint32_t)rbf_data & 0x3) {
puts("FPGA: Unaligned data, realign to 32bit boundary.\n");

View file

@ -31,8 +31,21 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
#endif
/*
* Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
* SRAM as bootcounter storage. Make sure to not put the stack directly
* at this address to not overwrite the bootcounter by checking, if the
* bootcounter address is located in the internal SRAM.
*/
#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
(CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)))
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1