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lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t type

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fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
This commit is contained in:
York Sun 2015-08-03 12:02:05 -07:00 • committed by Simon Glass
parent d1de41d7fa
commit fdb9f349be
3 changed files with 8 additions and 8 deletions
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10
drivers/pci/pci_tegra.c
View file

@ -445,11 +445,11 @@ static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
}
debug("PCI regions:\n");
debug(" I/O: %#x-%#x\n", pcie->io.start, pcie->io.end);
debug(" non-prefetchable memory: %#x-%#x\n", pcie->mem.start,
pcie->mem.end);
debug(" prefetchable memory: %#x-%#x\n", pcie->prefetch.start,
pcie->prefetch.end);
debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end);
debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start,
&pcie->mem.end);
debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start,
&pcie->prefetch.end);
return 0;
}

4
drivers/spi/fsl_dspi.c
View file

@ -664,8 +664,8 @@ static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
plat->speed_hz = fdtdec_get_int(blob,
node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
debug("DSPI: regs=0x%llx, max-frequency=%d, endianess=%s, num-cs=%d\n",
(u64)plat->regs_addr, plat->speed_hz,
debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
&plat->regs_addr, plat->speed_hz,
plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
plat->num_chipselect);

2
drivers/video/tegra.c
View file

@ -92,7 +92,7 @@ void lcd_ctrl_init(void *lcdbase)
/* Enable flushing after LCD writes if requested */
lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
debug("LCD frame buffer at %08X\n", disp_config->frame_buffer);
debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
}
ulong calc_fbsize(void)