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ddr cfg: DRAM_RESET needs 0x00020030
The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why. But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of DRAM_RESET. My thanks go to Liu Hui(Jason) for this information. Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
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DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
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DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
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