mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
commit
fe8b3212b7
140 changed files with 4246 additions and 1079 deletions
|
@ -15,7 +15,7 @@
|
|||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/apb_misc.h>
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||||
#include <asm/arch-tegra/board.h>
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||||
#include <asm/arch/spl.h>
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||||
#include <asm/spl.h>
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||||
#include "cpu.h"
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||||
|
||||
void spl_board_init(void)
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||||
|
|
|
@ -14,7 +14,7 @@
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|||
#include <asm/arch/hardware.h>
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#include <asm/arch/davinci_misc.h>
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#include <asm/arch/ddr2_defs.h>
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#include <asm/arch/emif_defs.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/arch/pll_defs.h>
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||||
void davinci_enable_uart0(void)
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|
|
|
@ -11,6 +11,7 @@
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|||
#include <nand.h>
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#include <ns16550.h>
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#include <post.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/arch/dm365_lowlevel.h>
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#include <asm/arch/hardware.h>
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|
|
|
@ -95,6 +95,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
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|||
&emif_reg[nr]->emif_rd_wr_exec_thresh);
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writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
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||||
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
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writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
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writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
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||||
|
||||
|
|
|
@ -61,6 +61,8 @@ int print_cpuinfo(void)
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|||
|
||||
void enable_caches(void)
|
||||
{
|
||||
icache_enable();
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||||
dcache_enable();
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||||
}
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||||
|
||||
unsigned int get_chip_id(void)
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||||
|
|
|
@ -162,7 +162,7 @@ void mem_ctrl_init(int reset)
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|||
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/* If there are any other memory variant, add their init call below */
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if (param->mem_type == DDR_MODE_DDR3) {
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ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
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ret = ddr3_mem_ctrl_init(mem, reset);
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if (ret) {
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/* will hang if failed to init memory control */
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while (1)
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|
|
|
@ -6,6 +6,7 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
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||||
*/
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|
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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|
@ -16,7 +17,11 @@
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|||
#include "exynos5_setup.h"
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#include "clock_init.h"
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#define TIMEOUT 10000
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#define TIMEOUT_US 10000
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#define NUM_BYTE_LANES 4
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#define DEFAULT_DQS 8
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#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
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|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
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#ifdef CONFIG_EXYNOS5250
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static void reset_phy_ctrl(void)
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|
@ -28,8 +33,7 @@ static void reset_phy_ctrl(void)
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writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
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}
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
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int reset)
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int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
|
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{
|
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unsigned int val;
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struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
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|
@ -177,7 +181,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
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|||
writel(val, &phy1_ctrl->phy_con1);
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writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
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i = TIMEOUT;
|
||||
i = TIMEOUT_US;
|
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while ((readl(&dmc->phystatus) &
|
||||
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
|
||||
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
|
||||
|
@ -221,8 +225,220 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_EXYNOS5420
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
||||
int reset)
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||||
/**
|
||||
* RAM address to use in the test.
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||||
*
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||||
* We'll use 4 words at this address and 4 at this address + 0x80 (Ares
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* interleaves channels every 128 bytes). This will allow us to evaluate all of
|
||||
* the chips in a 1 chip per channel (2GB) system and half the chips in a 2
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||||
* chip per channel (4GB) system. We can't test the 2nd chip since we need to
|
||||
* do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't
|
||||
* critical because the 1st and 2nd chip have very similar timings (they'd
|
||||
* better have similar timings, since there's only a single adjustment that is
|
||||
* shared by both chips).
|
||||
*/
|
||||
const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
|
||||
|
||||
/* Test pattern with which RAM will be tested */
|
||||
static const unsigned int test_pattern[] = {
|
||||
0x5a5a5a5a,
|
||||
0xa5a5a5a5,
|
||||
0xf0f0f0f0,
|
||||
0x0f0f0f0f,
|
||||
};
|
||||
|
||||
/**
|
||||
* This function is a test vector for sw read leveling,
|
||||
* it compares the read data with the written data.
|
||||
*
|
||||
* @param ch DMC channel number
|
||||
* @param byte_lane which DQS byte offset,
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* possible values are 0,1,2,3
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* @return TRUE if memory was good, FALSE if not.
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*/
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static bool dmc_valid_window_test_vector(int ch, int byte_lane)
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{
|
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unsigned int read_data;
|
||||
unsigned int mask;
|
||||
int i;
|
||||
|
||||
mask = 0xFF << (8 * byte_lane);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
|
||||
read_data = readl(test_addr + i * 4 + ch * 0x80);
|
||||
if ((read_data & mask) != (test_pattern[i] & mask))
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function returns current read offset value.
|
||||
*
|
||||
* @param phy_ctrl pointer to the current phy controller
|
||||
*/
|
||||
static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
|
||||
*phy_ctrl)
|
||||
{
|
||||
return readl(&phy_ctrl->phy_con4);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function performs resync, so that slave DLL is updated.
|
||||
*
|
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* @param phy_ctrl pointer to the current phy controller
|
||||
*/
|
||||
static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
|
||||
{
|
||||
setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
|
||||
clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sets read offset value register with 'offset'.
|
||||
*
|
||||
* ...we also call call ddr_phy_set_do_resync().
|
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*
|
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* @param phy_ctrl pointer to the current phy controller
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* @param offset offset to read DQS
|
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*/
|
||||
static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
|
||||
unsigned int offset)
|
||||
{
|
||||
writel(offset, &phy_ctrl->phy_con4);
|
||||
ddr_phy_set_do_resync(phy_ctrl);
|
||||
}
|
||||
|
||||
/**
|
||||
* Convert a 2s complement byte to a byte with a sign bit.
|
||||
*
|
||||
* NOTE: you shouldn't use normal math on the number returned by this function.
|
||||
* As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted
|
||||
* to do math and get the average of 10 and -10 (should be 0):
|
||||
* 0x8a + 0xa = 0x94 (-108)
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* 0x94 / 2 = 0xca (-54)
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* ...and 0xca = sign bit plus 0x4a, or -74
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||||
*
|
||||
* Also note that you lose the ability to represent -128 since there are two
|
||||
* representations of 0.
|
||||
*
|
||||
* @param b The byte to convert in two's complement.
|
||||
* @return The 7-bit value + sign bit.
|
||||
*/
|
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|
||||
unsigned char make_signed_byte(signed char b)
|
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{
|
||||
if (b < 0)
|
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return 0x80 | -b;
|
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else
|
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return b;
|
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}
|
||||
|
||||
/**
|
||||
* Test various shifts starting at 'start' and going to 'end'.
|
||||
*
|
||||
* For each byte lane, we'll walk through shift starting at 'start' and going
|
||||
* to 'end' (inclusive). When we are finally able to read the test pattern
|
||||
* we'll store the value in the results array.
|
||||
*
|
||||
* @param phy_ctrl pointer to the current phy controller
|
||||
* @param ch channel number
|
||||
* @param start the start shift. -127 to 127
|
||||
* @param end the end shift. -127 to 127
|
||||
* @param results we'll store results for each byte lane.
|
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*/
|
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|
||||
void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
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int start, int end, int results[NUM_BYTE_LANES])
|
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{
|
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int incr = (start < end) ? 1 : -1;
|
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int byte_lane;
|
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|
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for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
|
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int shift;
|
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|
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dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
|
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results[byte_lane] = DEFAULT_DQS;
|
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|
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for (shift = start; shift != (end + incr); shift += incr) {
|
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unsigned int byte_offsetr;
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unsigned int offsetr;
|
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|
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byte_offsetr = make_signed_byte(shift);
|
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|
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offsetr = dmc_get_read_offset_value(phy_ctrl);
|
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offsetr &= ~(0xFF << (8 * byte_lane));
|
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offsetr |= (byte_offsetr << (8 * byte_lane));
|
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dmc_set_read_offset_value(phy_ctrl, offsetr);
|
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|
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if (dmc_valid_window_test_vector(ch, byte_lane)) {
|
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results[byte_lane] = shift;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function performs SW read leveling to compensate DQ-DQS skew at
|
||||
* receiver it first finds the optimal read offset value on each DQS
|
||||
* then applies the value to PHY.
|
||||
*
|
||||
* Read offset value has its min margin and max margin. If read offset
|
||||
* value exceeds its min or max margin, read data will have corruption.
|
||||
* To avoid this we are doing sw read leveling.
|
||||
*
|
||||
* SW read leveling is:
|
||||
* 1> Finding offset value's left_limit and right_limit
|
||||
* 2> and calculate its center value
|
||||
* 3> finally programs that center value to PHY
|
||||
* 4> then PHY gets its optimal offset value.
|
||||
*
|
||||
* @param phy_ctrl pointer to the current phy controller
|
||||
* @param ch channel number
|
||||
* @param coarse_lock_val The coarse lock value read from PHY_CON13.
|
||||
* (0 - 0x7f)
|
||||
*/
|
||||
static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
|
||||
int ch, unsigned int coarse_lock_val)
|
||||
{
|
||||
unsigned int offsetr_cent;
|
||||
int byte_lane;
|
||||
int left_limit;
|
||||
int right_limit;
|
||||
int left[NUM_BYTE_LANES];
|
||||
int right[NUM_BYTE_LANES];
|
||||
int i;
|
||||
|
||||
/* Fill the memory with test patterns */
|
||||
for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
|
||||
writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
|
||||
|
||||
/* Figure out the limits we'll test with; keep -127 < limit < 127 */
|
||||
left_limit = DEFAULT_DQS - coarse_lock_val;
|
||||
right_limit = DEFAULT_DQS + coarse_lock_val;
|
||||
if (right_limit > 127)
|
||||
right_limit = 127;
|
||||
|
||||
/* Fill in the location where reads were OK from left and right */
|
||||
test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
|
||||
test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
|
||||
|
||||
/* Make a final value by taking the center between the left and right */
|
||||
offsetr_cent = 0;
|
||||
for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
|
||||
int temp_center;
|
||||
unsigned int vmwc;
|
||||
|
||||
temp_center = (left[byte_lane] + right[byte_lane]) / 2;
|
||||
vmwc = make_signed_byte(temp_center);
|
||||
offsetr_cent |= vmwc << (8 * byte_lane);
|
||||
}
|
||||
dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
|
||||
}
|
||||
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
|
||||
{
|
||||
struct exynos5420_clock *clk =
|
||||
(struct exynos5420_clock *)samsung_get_base_clock();
|
||||
|
@ -231,7 +447,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
|
||||
struct exynos5420_dmc *drex0, *drex1;
|
||||
struct exynos5420_tzasc *tzasc0, *tzasc1;
|
||||
struct exynos5_power *pmu;
|
||||
uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
|
||||
uint32_t lock0_info, lock1_info;
|
||||
int chip;
|
||||
int i;
|
||||
|
||||
|
@ -244,6 +462,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
|
||||
tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
|
||||
+ DMC_OFFSET);
|
||||
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
|
||||
|
||||
/* Enable PAUSE for DREX */
|
||||
setbits_le32(&clk->pause, ENABLE_BIT);
|
||||
|
@ -394,7 +613,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
*/
|
||||
dmc_config_mrs(mem, &drex0->directcmd);
|
||||
dmc_config_mrs(mem, &drex1->directcmd);
|
||||
} else {
|
||||
}
|
||||
|
||||
/*
|
||||
* Get PHY_CON13 from both phys. Gate CLKM around reading since
|
||||
* PHY_CON13 is glitchy when CLKM is running. We're paranoid and
|
||||
* wait until we get a "fine lock", though a coarse lock is probably
|
||||
* OK (we only use the coarse numbers below). We try to gate the
|
||||
* clock for as short a time as possible in case SDRAM is somehow
|
||||
* sensitive. sdelay(10) in the loop is arbitrary to make sure
|
||||
* there is some time for PHY_CON13 to get updated. In practice
|
||||
* no delay appears to be needed.
|
||||
*/
|
||||
val = readl(&clk->gate_bus_cdrex);
|
||||
while (true) {
|
||||
writel(val & ~0x1, &clk->gate_bus_cdrex);
|
||||
lock0_info = readl(&phy0_ctrl->phy_con13);
|
||||
writel(val, &clk->gate_bus_cdrex);
|
||||
|
||||
if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
|
||||
break;
|
||||
|
||||
sdelay(10);
|
||||
}
|
||||
while (true) {
|
||||
writel(val & ~0x2, &clk->gate_bus_cdrex);
|
||||
lock1_info = readl(&phy1_ctrl->phy_con13);
|
||||
writel(val, &clk->gate_bus_cdrex);
|
||||
|
||||
if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
|
||||
break;
|
||||
|
||||
sdelay(10);
|
||||
}
|
||||
|
||||
if (!reset) {
|
||||
/*
|
||||
* During Suspend-Resume & S/W-Reset, as soon as PMU releases
|
||||
* pad retention, CKE goes high. This causes memory contents
|
||||
|
@ -445,15 +698,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
|
||||
writel(val, &phy1_ctrl->phy_con1);
|
||||
|
||||
n_lock_r = readl(&phy0_ctrl->phy_con13);
|
||||
n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
|
||||
n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
|
||||
n_lock_r = readl(&phy0_ctrl->phy_con12);
|
||||
n_lock_r &= ~CTRL_DLL_ON;
|
||||
n_lock_r |= n_lock_w_phy0;
|
||||
writel(n_lock_r, &phy0_ctrl->phy_con12);
|
||||
|
||||
n_lock_r = readl(&phy1_ctrl->phy_con13);
|
||||
n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
|
||||
n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
|
||||
n_lock_r = readl(&phy1_ctrl->phy_con12);
|
||||
n_lock_r &= ~CTRL_DLL_ON;
|
||||
n_lock_r |= n_lock_w_phy1;
|
||||
|
@ -482,7 +733,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
writel(val, &phy1_ctrl->phy_con1);
|
||||
|
||||
writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
|
||||
i = TIMEOUT;
|
||||
i = TIMEOUT_US;
|
||||
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
|
||||
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
|
@ -497,7 +748,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
|
||||
|
||||
writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
|
||||
i = TIMEOUT;
|
||||
i = TIMEOUT_US;
|
||||
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
|
||||
RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
|
@ -522,77 +773,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
&drex1->directcmd);
|
||||
}
|
||||
|
||||
if (mem->read_leveling_enable) {
|
||||
/* Set Read DQ Calibration */
|
||||
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
|
||||
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
||||
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
||||
&drex0->directcmd);
|
||||
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
||||
&drex1->directcmd);
|
||||
}
|
||||
|
||||
val = readl(&phy0_ctrl->phy_con1);
|
||||
val |= READ_LEVELLING_DDR3;
|
||||
writel(val, &phy0_ctrl->phy_con1);
|
||||
val = readl(&phy1_ctrl->phy_con1);
|
||||
val |= READ_LEVELLING_DDR3;
|
||||
writel(val, &phy1_ctrl->phy_con1);
|
||||
|
||||
val = readl(&phy0_ctrl->phy_con2);
|
||||
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
|
||||
writel(val, &phy0_ctrl->phy_con2);
|
||||
val = readl(&phy1_ctrl->phy_con2);
|
||||
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
|
||||
writel(val, &phy1_ctrl->phy_con2);
|
||||
|
||||
setbits_le32(&drex0->rdlvl_config,
|
||||
CTRL_RDLVL_DATA_ENABLE);
|
||||
i = TIMEOUT;
|
||||
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
|
||||
!= RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
* TODO(waihong): Comment on how long this take
|
||||
* to timeout
|
||||
*/
|
||||
sdelay(100);
|
||||
i--;
|
||||
}
|
||||
if (!i)
|
||||
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
||||
|
||||
clrbits_le32(&drex0->rdlvl_config,
|
||||
CTRL_RDLVL_DATA_ENABLE);
|
||||
setbits_le32(&drex1->rdlvl_config,
|
||||
CTRL_RDLVL_DATA_ENABLE);
|
||||
i = TIMEOUT;
|
||||
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
|
||||
!= RDLVL_COMPLETE_CHO) && (i > 0)) {
|
||||
/*
|
||||
* TODO(waihong): Comment on how long this take
|
||||
* to timeout
|
||||
*/
|
||||
sdelay(100);
|
||||
i--;
|
||||
}
|
||||
if (!i)
|
||||
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
|
||||
|
||||
clrbits_le32(&drex1->rdlvl_config,
|
||||
CTRL_RDLVL_DATA_ENABLE);
|
||||
|
||||
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
|
||||
for (chip = 0; chip < mem->chips_to_configure; chip++) {
|
||||
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
||||
&drex0->directcmd);
|
||||
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
|
||||
&drex1->directcmd);
|
||||
}
|
||||
|
||||
update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
|
||||
update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
|
||||
}
|
||||
|
||||
/* Common Settings for Leveling */
|
||||
val = PHY_CON12_RESET_VAL;
|
||||
writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
|
||||
|
@ -602,6 +782,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Do software read leveling
|
||||
*
|
||||
* Do this before we turn on auto refresh since the auto refresh can
|
||||
* be in conflict with the resync operation that's part of setting
|
||||
* read leveling.
|
||||
*/
|
||||
if (!reset) {
|
||||
/* restore calibrated value after resume */
|
||||
dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
|
||||
dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
|
||||
} else {
|
||||
software_find_read_offset(phy0_ctrl, 0,
|
||||
CTRL_LOCK_COARSE(lock0_info));
|
||||
software_find_read_offset(phy1_ctrl, 1,
|
||||
CTRL_LOCK_COARSE(lock1_info));
|
||||
/* save calibrated value to restore after resume */
|
||||
writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
|
||||
writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
|
||||
}
|
||||
|
||||
/* Send PALL command */
|
||||
dmc_config_prech(mem, &drex0->directcmd);
|
||||
dmc_config_prech(mem, &drex1->directcmd);
|
||||
|
|
|
@ -282,8 +282,12 @@
|
|||
#define PHY_CON12_VAL 0x10107F50
|
||||
#define CTRL_START (1 << 6)
|
||||
#define CTRL_DLL_ON (1 << 5)
|
||||
#define CTRL_LOCK_COARSE_OFFSET 10
|
||||
#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET)
|
||||
#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \
|
||||
CTRL_LOCK_COARSE_OFFSET)
|
||||
#define CTRL_FORCE_MASK (0x7F << 8)
|
||||
#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
|
||||
#define CTRL_FINE_LOCKED 0x7
|
||||
|
||||
#define CTRL_OFFSETD_RESET_VAL 0x8
|
||||
#define CTRL_OFFSETD_VAL 0x7F
|
||||
|
@ -431,10 +435,10 @@
|
|||
|
||||
/*
|
||||
* Definitions that differ with SoC's.
|
||||
* Below is the part defining macros for smdk5250.
|
||||
* Else part introduces macros for smdk5420.
|
||||
* Below is the part defining macros for Exynos5250.
|
||||
* Else part introduces macros for Exynos5420.
|
||||
*/
|
||||
#ifndef CONFIG_SMDK5420
|
||||
#ifndef CONFIG_EXYNOS5420
|
||||
|
||||
/* APLL_CON1 */
|
||||
#define APLL_CON1_VAL (0x00203800)
|
||||
|
@ -890,16 +894,11 @@ enum {
|
|||
/*
|
||||
* Memory variant specific initialization code for DDR3
|
||||
*
|
||||
* @param mem Memory timings for this memory type.
|
||||
* @param mem_iv_size Memory interleaving size is a configurable parameter
|
||||
* which the DMC uses to decide how to split a memory
|
||||
* chunk into smaller chunks to support concurrent
|
||||
* accesses; may vary across boards.
|
||||
* @param mem Memory timings for this memory type.
|
||||
* @param reset Reset DDR PHY during initialization.
|
||||
* @return 0 if ok, SETUP_ERR_... if there is a problem
|
||||
*/
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
||||
int reset);
|
||||
int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
|
||||
|
||||
/* Memory variant specific initialization code for LPDDR3 */
|
||||
void lpddr3_mem_ctrl_init(void);
|
||||
|
|
|
@ -49,8 +49,6 @@ int do_lowlevel_init(void)
|
|||
|
||||
arch_cpu_init();
|
||||
|
||||
set_ps_hold_ctrl();
|
||||
|
||||
reset_status = get_reset_status();
|
||||
|
||||
switch (reset_status) {
|
||||
|
|
|
@ -5,7 +5,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += aemif.o
|
||||
obj-y += init.o
|
||||
obj-y += psc.o
|
||||
obj-y += clock.o
|
||||
|
|
|
@ -8,4 +8,5 @@
|
|||
#
|
||||
|
||||
obj-y := soc.o clock.o
|
||||
obj-$(CONFIG_SPL_BUILD) += ddr.o
|
||||
obj-$(CONFIG_SECURE_BOOT) += hab.o
|
||||
|
|
490
arch/arm/cpu/armv7/mx6/ddr.c
Normal file
490
arch/arm/cpu/armv7/mx6/ddr.c
Normal file
|
@ -0,0 +1,490 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation
|
||||
* Author: Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
|
||||
/* Configure MX6DQ mmdc iomux */
|
||||
void mx6dq_dram_iocfg(unsigned width,
|
||||
const struct mx6dq_iomux_ddr_regs *ddr,
|
||||
const struct mx6dq_iomux_grp_regs *grp)
|
||||
{
|
||||
volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
|
||||
volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
|
||||
|
||||
mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
|
||||
mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
|
||||
|
||||
/* DDR IO Type */
|
||||
mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
|
||||
mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
|
||||
|
||||
/* Clock */
|
||||
mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
|
||||
mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
|
||||
|
||||
/* Address */
|
||||
mx6_ddr_iomux->dram_cas = ddr->dram_cas;
|
||||
mx6_ddr_iomux->dram_ras = ddr->dram_ras;
|
||||
mx6_grp_iomux->grp_addds = grp->grp_addds;
|
||||
|
||||
/* Control */
|
||||
mx6_ddr_iomux->dram_reset = ddr->dram_reset;
|
||||
mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
|
||||
mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
|
||||
mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
|
||||
mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
|
||||
mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
|
||||
mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
|
||||
|
||||
/* Data Strobes */
|
||||
mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
|
||||
mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
|
||||
mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
|
||||
if (width >= 32) {
|
||||
mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
|
||||
mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
|
||||
}
|
||||
if (width >= 64) {
|
||||
mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
|
||||
mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
|
||||
mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
|
||||
mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
|
||||
}
|
||||
|
||||
/* Data */
|
||||
mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
|
||||
mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
|
||||
mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
|
||||
if (width >= 32) {
|
||||
mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
|
||||
mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
|
||||
}
|
||||
if (width >= 64) {
|
||||
mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
|
||||
mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
|
||||
mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
|
||||
mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
|
||||
}
|
||||
mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
|
||||
mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
|
||||
if (width >= 32) {
|
||||
mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
|
||||
mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
|
||||
}
|
||||
if (width >= 64) {
|
||||
mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
|
||||
mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
|
||||
mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
|
||||
mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
|
||||
/* Configure MX6SDL mmdc iomux */
|
||||
void mx6sdl_dram_iocfg(unsigned width,
|
||||
const struct mx6sdl_iomux_ddr_regs *ddr,
|
||||
const struct mx6sdl_iomux_grp_regs *grp)
|
||||
{
|
||||
volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
|
||||
volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
|
||||
|
||||
mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
|
||||
mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
|
||||
|
||||
/* DDR IO Type */
|
||||
mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
|
||||
mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
|
||||
|
||||
/* Clock */
|
||||
mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
|
||||
mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
|
||||
|
||||
/* Address */
|
||||
mx6_ddr_iomux->dram_cas = ddr->dram_cas;
|
||||
mx6_ddr_iomux->dram_ras = ddr->dram_ras;
|
||||
mx6_grp_iomux->grp_addds = grp->grp_addds;
|
||||
|
||||
/* Control */
|
||||
mx6_ddr_iomux->dram_reset = ddr->dram_reset;
|
||||
mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
|
||||
mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
|
||||
mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
|
||||
mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
|
||||
mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
|
||||
mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
|
||||
|
||||
/* Data Strobes */
|
||||
mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
|
||||
mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
|
||||
mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
|
||||
if (width >= 32) {
|
||||
mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
|
||||
mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
|
||||
}
|
||||
if (width >= 64) {
|
||||
mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
|
||||
mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
|
||||
mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
|
||||
mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
|
||||
}
|
||||
|
||||
/* Data */
|
||||
mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
|
||||
mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
|
||||
mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
|
||||
if (width >= 32) {
|
||||
mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
|
||||
mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
|
||||
}
|
||||
if (width >= 64) {
|
||||
mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
|
||||
mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
|
||||
mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
|
||||
mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
|
||||
}
|
||||
mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
|
||||
mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
|
||||
if (width >= 32) {
|
||||
mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
|
||||
mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
|
||||
}
|
||||
if (width >= 64) {
|
||||
mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
|
||||
mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
|
||||
mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
|
||||
mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Configure mx6 mmdc registers based on:
|
||||
* - board-specific memory configuration
|
||||
* - board-specific calibration data
|
||||
* - ddr3 chip details
|
||||
*
|
||||
* The various calculations here are derived from the Freescale
|
||||
* i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
|
||||
* configuration registers based on memory system and memory chip parameters.
|
||||
*
|
||||
* The defaults here are those which were specified in the spreadsheet.
|
||||
* For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
|
||||
* section titled MMDC initialization
|
||||
*/
|
||||
#define MR(val, ba, cmd, cs1) \
|
||||
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
|
||||
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
|
||||
const struct mx6_mmdc_calibration *c,
|
||||
const struct mx6_ddr3_cfg *m)
|
||||
{
|
||||
volatile struct mmdc_p_regs *mmdc0;
|
||||
volatile struct mmdc_p_regs *mmdc1;
|
||||
u32 reg;
|
||||
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
|
||||
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
|
||||
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
|
||||
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
|
||||
u16 CS0_END;
|
||||
u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
|
||||
int clkper; /* clock period in picoseconds */
|
||||
int clock; /* clock freq in mHz */
|
||||
int cs;
|
||||
|
||||
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
|
||||
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
|
||||
|
||||
/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
|
||||
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
|
||||
clock = 528;
|
||||
tcwl = 4;
|
||||
}
|
||||
/* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
|
||||
else {
|
||||
clock = 400;
|
||||
tcwl = 3;
|
||||
}
|
||||
clkper = (1000*1000)/clock; /* ps */
|
||||
todtlon = tcwl;
|
||||
taxpd = tcwl;
|
||||
tanpd = tcwl;
|
||||
tcwl = tcwl;
|
||||
|
||||
switch (m->density) {
|
||||
case 1: /* 1Gb per chip */
|
||||
trfc = DIV_ROUND_UP(110000, clkper) - 1;
|
||||
txs = DIV_ROUND_UP(120000, clkper) - 1;
|
||||
break;
|
||||
case 2: /* 2Gb per chip */
|
||||
trfc = DIV_ROUND_UP(160000, clkper) - 1;
|
||||
txs = DIV_ROUND_UP(170000, clkper) - 1;
|
||||
break;
|
||||
case 4: /* 4Gb per chip */
|
||||
trfc = DIV_ROUND_UP(260000, clkper) - 1;
|
||||
txs = DIV_ROUND_UP(270000, clkper) - 1;
|
||||
break;
|
||||
case 8: /* 8Gb per chip */
|
||||
trfc = DIV_ROUND_UP(350000, clkper) - 1;
|
||||
txs = DIV_ROUND_UP(360000, clkper) - 1;
|
||||
break;
|
||||
default:
|
||||
/* invalid density */
|
||||
printf("invalid chip density\n");
|
||||
hang();
|
||||
break;
|
||||
}
|
||||
txpr = txs;
|
||||
|
||||
switch (m->mem_speed) {
|
||||
case 800:
|
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
|
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
|
||||
if (m->pagesz == 1) {
|
||||
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
|
||||
} else {
|
||||
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
|
||||
}
|
||||
break;
|
||||
case 1066:
|
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
|
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
|
||||
if (m->pagesz == 1) {
|
||||
tfaw = DIV_ROUND_UP(37500, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
|
||||
} else {
|
||||
tfaw = DIV_ROUND_UP(50000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
|
||||
}
|
||||
break;
|
||||
case 1333:
|
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
|
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
|
||||
if (m->pagesz == 1) {
|
||||
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
|
||||
} else {
|
||||
tfaw = DIV_ROUND_UP(45000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
|
||||
}
|
||||
break;
|
||||
case 1600:
|
||||
txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
|
||||
tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
|
||||
if (m->pagesz == 1) {
|
||||
tfaw = DIV_ROUND_UP(30000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
|
||||
} else {
|
||||
tfaw = DIV_ROUND_UP(40000, clkper) - 1;
|
||||
trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("invalid memory speed\n");
|
||||
hang();
|
||||
break;
|
||||
}
|
||||
txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
|
||||
tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
|
||||
tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
|
||||
tcksrx = tcksre;
|
||||
taonpd = DIV_ROUND_UP(2000, clkper) - 1;
|
||||
taofpd = taonpd;
|
||||
trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
|
||||
trcd = trp;
|
||||
trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
|
||||
tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
|
||||
twr = DIV_ROUND_UP(15000, clkper) - 1;
|
||||
tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
|
||||
twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
|
||||
trtp = twtr;
|
||||
CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
|
||||
debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
|
||||
debug("clock: %dMHz (%d ps)\n", clock, clkper);
|
||||
debug("memspd:%d\n", m->mem_speed);
|
||||
debug("tcke=%d\n", tcke);
|
||||
debug("tcksrx=%d\n", tcksrx);
|
||||
debug("tcksre=%d\n", tcksre);
|
||||
debug("taofpd=%d\n", taofpd);
|
||||
debug("taonpd=%d\n", taonpd);
|
||||
debug("todtlon=%d\n", todtlon);
|
||||
debug("tanpd=%d\n", tanpd);
|
||||
debug("taxpd=%d\n", taxpd);
|
||||
debug("trfc=%d\n", trfc);
|
||||
debug("txs=%d\n", txs);
|
||||
debug("txp=%d\n", txp);
|
||||
debug("txpdll=%d\n", txpdll);
|
||||
debug("tfaw=%d\n", tfaw);
|
||||
debug("tcl=%d\n", tcl);
|
||||
debug("trcd=%d\n", trcd);
|
||||
debug("trp=%d\n", trp);
|
||||
debug("trc=%d\n", trc);
|
||||
debug("tras=%d\n", tras);
|
||||
debug("twr=%d\n", twr);
|
||||
debug("tmrd=%d\n", tmrd);
|
||||
debug("tcwl=%d\n", tcwl);
|
||||
debug("tdllk=%d\n", tdllk);
|
||||
debug("trtp=%d\n", trtp);
|
||||
debug("twtr=%d\n", twtr);
|
||||
debug("trrd=%d\n", trrd);
|
||||
debug("txpr=%d\n", txpr);
|
||||
debug("CS0_END=%d\n", CS0_END);
|
||||
debug("ncs=%d\n", i->ncs);
|
||||
debug("Rtt_wr=%d\n", i->rtt_wr);
|
||||
debug("Rtt_nom=%d\n", i->rtt_nom);
|
||||
debug("SRT=%d\n", m->SRT);
|
||||
debug("tcl=%d\n", tcl);
|
||||
debug("twr=%d\n", twr);
|
||||
|
||||
/*
|
||||
* board-specific configuration:
|
||||
* These values are determined empirically and vary per board layout
|
||||
* see:
|
||||
* appnote, ddr3 spreadsheet
|
||||
*/
|
||||
mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
|
||||
mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
|
||||
mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
|
||||
mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
|
||||
mmdc0->mprddlctl = c->p0_mprddlctl;
|
||||
mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
|
||||
if (i->dsize > 1) {
|
||||
mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
|
||||
mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
|
||||
mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
|
||||
mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
|
||||
mmdc1->mprddlctl = c->p1_mprddlctl;
|
||||
mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
|
||||
}
|
||||
|
||||
/* Read data DQ Byte0-3 delay */
|
||||
mmdc0->mprddqby0dl = (u32)0x33333333;
|
||||
mmdc0->mprddqby1dl = (u32)0x33333333;
|
||||
if (i->dsize > 0) {
|
||||
mmdc0->mprddqby2dl = (u32)0x33333333;
|
||||
mmdc0->mprddqby3dl = (u32)0x33333333;
|
||||
}
|
||||
if (i->dsize > 1) {
|
||||
mmdc1->mprddqby0dl = (u32)0x33333333;
|
||||
mmdc1->mprddqby1dl = (u32)0x33333333;
|
||||
mmdc1->mprddqby2dl = (u32)0x33333333;
|
||||
mmdc1->mprddqby3dl = (u32)0x33333333;
|
||||
}
|
||||
|
||||
/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
|
||||
reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
|
||||
mmdc0->mpodtctrl = reg;
|
||||
if (i->dsize > 1)
|
||||
mmdc1->mpodtctrl = reg;
|
||||
|
||||
/* complete calibration */
|
||||
reg = (1 << 11); /* Force measurement on delay-lines */
|
||||
mmdc0->mpmur0 = reg;
|
||||
if (i->dsize > 1)
|
||||
mmdc1->mpmur0 = reg;
|
||||
|
||||
/* Step 1: configuration request */
|
||||
mmdc0->mdscr = (u32)(1 << 15); /* config request */
|
||||
|
||||
/* Step 2: Timing configuration */
|
||||
reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
|
||||
(tfaw << 4) | tcl;
|
||||
mmdc0->mdcfg0 = reg;
|
||||
reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
|
||||
(1 << 15) | /* trpa */
|
||||
(twr << 9) | (tmrd << 5) | tcwl;
|
||||
mmdc0->mdcfg1 = reg;
|
||||
reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
|
||||
mmdc0->mdcfg2 = reg;
|
||||
reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
|
||||
(todtlon << 12) | (todt_idle_off << 4);
|
||||
mmdc0->mdotc = reg;
|
||||
mmdc0->mdasp = CS0_END; /* CS addressing */
|
||||
|
||||
/* Step 3: Configure DDR type */
|
||||
reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
|
||||
(i->mif3_mode << 9) | (i->ralat << 6);
|
||||
mmdc0->mdmisc = reg;
|
||||
|
||||
/* Step 4: Configure delay while leaving reset */
|
||||
reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
|
||||
mmdc0->mdor = reg;
|
||||
|
||||
/* Step 5: Configure DDR physical parameters (density and burst len) */
|
||||
reg = (m->rowaddr - 11) << 24 | /* ROW */
|
||||
(m->coladdr - 9) << 20 | /* COL */
|
||||
(1 << 19) | /* Burst Length = 8 for DDR3 */
|
||||
(i->dsize << 16); /* DDR data bus size */
|
||||
mmdc0->mdctl = reg;
|
||||
|
||||
/* Step 6: Perform ZQ calibration */
|
||||
reg = (u32)0xa1390001; /* one-time HW ZQ calib */
|
||||
mmdc0->mpzqhwctrl = reg;
|
||||
if (i->dsize > 1)
|
||||
mmdc1->mpzqhwctrl = reg;
|
||||
|
||||
/* Step 7: Enable MMDC with desired chip select */
|
||||
reg = mmdc0->mdctl |
|
||||
(1 << 31) | /* SDE_0 for CS0 */
|
||||
((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
|
||||
mmdc0->mdctl = reg;
|
||||
|
||||
/* Step 8: Write Mode Registers to Init DDR3 devices */
|
||||
for (cs = 0; cs < i->ncs; cs++) {
|
||||
/* MR2 */
|
||||
reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
|
||||
((tcwl - 3) & 3) << 3;
|
||||
mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
|
||||
/* MR3 */
|
||||
mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
|
||||
/* MR1 */
|
||||
reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
|
||||
((i->rtt_nom & 2) ? 1 : 0) << 6;
|
||||
mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
|
||||
reg = ((tcl - 1) << 4) | /* CAS */
|
||||
(1 << 8) | /* DLL Reset */
|
||||
((twr - 3) << 9); /* Write Recovery */
|
||||
/* MR0 */
|
||||
mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
|
||||
/* ZQ calibration */
|
||||
reg = (1 << 10);
|
||||
mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
|
||||
}
|
||||
|
||||
/* Step 10: Power down control and self-refresh */
|
||||
reg = (tcke & 0x7) << 16 |
|
||||
5 << 12 | /* PWDT_1: 256 cycles */
|
||||
5 << 8 | /* PWDT_0: 256 cycles */
|
||||
1 << 6 | /* BOTH_CS_PD */
|
||||
(tcksrx & 0x7) << 3 |
|
||||
(tcksre & 0x7);
|
||||
mmdc0->mdpdc = reg;
|
||||
mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
|
||||
|
||||
/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
|
||||
mmdc0->mpzqhwctrl = (u32)0xa1390003;
|
||||
if (i->dsize > 1)
|
||||
mmdc1->mpzqhwctrl = (u32)0xa1390003;
|
||||
|
||||
/* Step 12: Configure and activate periodic refresh */
|
||||
reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
|
||||
(7 << 11); /* REFR: Refresh Rate - 8 refreshes */
|
||||
mmdc0->mdref = reg;
|
||||
|
||||
/* Step 13: Deassert config request - init complete */
|
||||
mmdc0->mdscr = (u32)0x00000000;
|
||||
|
||||
/* wait for auto-ZQ calibration to complete */
|
||||
mdelay(1);
|
||||
}
|
|
@ -7,15 +7,69 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hab.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
/* -------- start of HAB API updates ------------*/
|
||||
#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
|
||||
#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
|
||||
#define hab_rvt_authenticate_image \
|
||||
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
|
||||
#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
|
||||
#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
|
||||
#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
|
||||
|
||||
#define hab_rvt_report_event_p \
|
||||
( \
|
||||
((is_cpu_type(MXC_CPU_MX6Q) || \
|
||||
is_cpu_type(MXC_CPU_MX6D)) && \
|
||||
(soc_rev() >= CHIP_REV_1_5)) ? \
|
||||
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
|
||||
(is_cpu_type(MXC_CPU_MX6DL) && \
|
||||
(soc_rev() >= CHIP_REV_1_2)) ? \
|
||||
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
|
||||
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
|
||||
)
|
||||
|
||||
#define hab_rvt_report_status_p \
|
||||
( \
|
||||
((is_cpu_type(MXC_CPU_MX6Q) || \
|
||||
is_cpu_type(MXC_CPU_MX6D)) && \
|
||||
(soc_rev() >= CHIP_REV_1_5)) ? \
|
||||
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
|
||||
(is_cpu_type(MXC_CPU_MX6DL) && \
|
||||
(soc_rev() >= CHIP_REV_1_2)) ? \
|
||||
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
|
||||
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
|
||||
)
|
||||
|
||||
#define hab_rvt_authenticate_image_p \
|
||||
( \
|
||||
((is_cpu_type(MXC_CPU_MX6Q) || \
|
||||
is_cpu_type(MXC_CPU_MX6D)) && \
|
||||
(soc_rev() >= CHIP_REV_1_5)) ? \
|
||||
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
|
||||
(is_cpu_type(MXC_CPU_MX6DL) && \
|
||||
(soc_rev() >= CHIP_REV_1_2)) ? \
|
||||
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
|
||||
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
|
||||
)
|
||||
|
||||
#define hab_rvt_entry_p \
|
||||
( \
|
||||
((is_cpu_type(MXC_CPU_MX6Q) || \
|
||||
is_cpu_type(MXC_CPU_MX6D)) && \
|
||||
(soc_rev() >= CHIP_REV_1_5)) ? \
|
||||
((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
|
||||
(is_cpu_type(MXC_CPU_MX6DL) && \
|
||||
(soc_rev() >= CHIP_REV_1_2)) ? \
|
||||
((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
|
||||
((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
|
||||
)
|
||||
|
||||
#define hab_rvt_exit_p \
|
||||
( \
|
||||
((is_cpu_type(MXC_CPU_MX6Q) || \
|
||||
is_cpu_type(MXC_CPU_MX6D)) && \
|
||||
(soc_rev() >= CHIP_REV_1_5)) ? \
|
||||
((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
|
||||
(is_cpu_type(MXC_CPU_MX6DL) && \
|
||||
(soc_rev() >= CHIP_REV_1_2)) ? \
|
||||
((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
|
||||
((hab_rvt_exit_t *)HAB_RVT_EXIT) \
|
||||
)
|
||||
|
||||
bool is_hab_enabled(void)
|
||||
{
|
||||
|
@ -52,6 +106,11 @@ int get_hab_status(void)
|
|||
size_t bytes = sizeof(event_data); /* Event size in bytes */
|
||||
enum hab_config config = 0;
|
||||
enum hab_state state = 0;
|
||||
hab_rvt_report_event_t *hab_rvt_report_event;
|
||||
hab_rvt_report_status_t *hab_rvt_report_status;
|
||||
|
||||
hab_rvt_report_event = hab_rvt_report_event_p;
|
||||
hab_rvt_report_status = hab_rvt_report_status_p;
|
||||
|
||||
if (is_hab_enabled())
|
||||
puts("\nSecure boot enabled\n");
|
||||
|
|
|
@ -121,7 +121,8 @@ void gpmc_init(void)
|
|||
writel(0x00000008, &gpmc_cfg->sysconfig);
|
||||
writel(0x00000000, &gpmc_cfg->irqstatus);
|
||||
writel(0x00000000, &gpmc_cfg->irqenable);
|
||||
writel(0x00000000, &gpmc_cfg->timeout_control);
|
||||
/* disable timeout, set a safe reset value */
|
||||
writel(0x00001ff0, &gpmc_cfg->timeout_control);
|
||||
#ifdef CONFIG_NOR
|
||||
writel(0x00000200, &gpmc_cfg->config);
|
||||
#else
|
||||
|
@ -133,5 +134,6 @@ void gpmc_init(void)
|
|||
writel(0, &gpmc_cfg->cs[0].config7);
|
||||
sdelay(1000);
|
||||
/* enable chip-select specific configurations */
|
||||
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
|
||||
if (base != 0)
|
||||
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
|
||||
}
|
||||
|
|
|
@ -147,7 +147,7 @@ void secure_unlock_mem(void)
|
|||
* configure secure registers and exit secure world
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void secureworld_exit()
|
||||
void secureworld_exit(void)
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
|
@ -178,7 +178,7 @@ void secureworld_exit()
|
|||
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void try_unlock_memory()
|
||||
void try_unlock_memory(void)
|
||||
{
|
||||
int mode;
|
||||
int in_sdram = is_running_in_sdram();
|
||||
|
|
|
@ -328,7 +328,7 @@ static int tegra_display_decode_config(const void *blob,
|
|||
rgb = fdt_subnode_offset(blob, node, "rgb");
|
||||
|
||||
config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
|
||||
if (!config->panel_node < 0) {
|
||||
if (config->panel_node < 0) {
|
||||
debug("%s: Cannot find panel information\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
|
|
@ -18,6 +18,7 @@ SECTIONS
|
|||
.text :
|
||||
{
|
||||
*(.__image_copy_start)
|
||||
*(.vectors)
|
||||
CPUDIR/start.o (.text*)
|
||||
*(.text*)
|
||||
}
|
||||
|
|
|
@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1)
|
|||
mrs x0, cnthctl_el2
|
||||
orr x0, x0, #0x3 /* Enable EL1 access to timers */
|
||||
msr cnthctl_el2, x0
|
||||
msr cntvoff_el2, x0
|
||||
msr cntvoff_el2, xzr
|
||||
mrs x0, cntkctl_el1
|
||||
orr x0, x0, #0x3 /* Enable EL0 access to timers */
|
||||
msr cntkctl_el1, x0
|
||||
|
|
|
@ -6,7 +6,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
|
|||
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
|
||||
exynos5250-snow.dtb \
|
||||
exynos5250-smdk5250.dtb \
|
||||
exynos5420-smdk5420.dtb
|
||||
exynos5420-smdk5420.dtb \
|
||||
exynos5420-peach-pit.dtb
|
||||
dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
|
||||
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
|
||||
tegra20-medcom-wide.dtb \
|
||||
|
|
127
arch/arm/dts/exynos5420-peach-pit.dts
Normal file
127
arch/arm/dts/exynos5420-peach-pit.dts
Normal file
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* SAMSUNG/GOOGLE Peach-Pit board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Samsung/Google Peach Pit board based on Exynos5420";
|
||||
|
||||
compatible = "google,pit-rev#", "google,pit",
|
||||
"google,peach", "samsung,exynos5420", "samsung,exynos5";
|
||||
|
||||
config {
|
||||
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
|
||||
hwid = "PIT TEST A-A 7848";
|
||||
lazy-init = <1>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = "/serial@12C30000";
|
||||
console = "/serial@12C30000";
|
||||
pmic = "/i2c@12ca0000";
|
||||
};
|
||||
|
||||
dmc {
|
||||
mem-manuf = "samsung";
|
||||
mem-type = "ddr3";
|
||||
clock-frequency = <800000000>;
|
||||
arm-frequency = <1700000000>;
|
||||
};
|
||||
|
||||
tmu@10060000 {
|
||||
samsung,min-temp = <25>;
|
||||
samsung,max-temp = <125>;
|
||||
samsung,start-warning = <95>;
|
||||
samsung,start-tripping = <105>;
|
||||
samsung,hw-tripping = <110>;
|
||||
samsung,efuse-min-value = <40>;
|
||||
samsung,efuse-value = <55>;
|
||||
samsung,efuse-max-value = <100>;
|
||||
samsung,slope = <274761730>;
|
||||
samsung,dc-value = <25>;
|
||||
};
|
||||
|
||||
/* MAX77802 is on i2c bus 4 */
|
||||
i2c@12ca0000 {
|
||||
clock-frequency = <400000>;
|
||||
power-regulator@9 {
|
||||
compatible = "maxim,max77802-pmic";
|
||||
reg = <0x9>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@12cd0000 { /* i2c7 */
|
||||
clock-frequency = <100000>;
|
||||
soundcodec@20 {
|
||||
reg = <0x20>;
|
||||
compatible = "maxim,max98090-codec";
|
||||
};
|
||||
};
|
||||
|
||||
sound@3830000 {
|
||||
samsung,codec-type = "max98090";
|
||||
};
|
||||
|
||||
i2c@12e10000 { /* i2c9 */
|
||||
clock-frequency = <400000>;
|
||||
tpm@20 {
|
||||
compatible = "infineon,slb9645-tpm";
|
||||
reg = <0x20>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@12d30000 { /* spi1 */
|
||||
spi-max-frequency = <50000000>;
|
||||
firmware_storage_spi: flash@0 {
|
||||
reg = <0>;
|
||||
|
||||
/*
|
||||
* A region for the kernel to store a panic event
|
||||
* which the firmware will add to the log.
|
||||
*/
|
||||
elog-panic-event-offset = <0x01e00000 0x100000>;
|
||||
|
||||
elog-shrink-size = <0x400>;
|
||||
elog-full-threshold = <0xc00>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@12d40000 { /* spi2 */
|
||||
spi-max-frequency = <4000000>;
|
||||
spi-deactivate-delay = <200>;
|
||||
cros-ec@0 {
|
||||
reg = <0>;
|
||||
compatible = "google,cros-ec";
|
||||
spi-half-duplex;
|
||||
spi-max-timeout-ms = <1100>;
|
||||
spi-frame-header = <0xec>;
|
||||
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
|
||||
|
||||
/*
|
||||
* This describes the flash memory within the EC. Note
|
||||
* that the STM32L flash erases to 0, not 0xff.
|
||||
*/
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
flash@8000000 {
|
||||
reg = <0x08000000 0x20000>;
|
||||
erase-value = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
xhci@12000000 {
|
||||
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
|
||||
};
|
||||
|
||||
xhci@12400000 {
|
||||
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
|
||||
};
|
||||
};
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "exynos5420.dtsi"
|
||||
/include/ "exynos54xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
|
||||
|
@ -19,27 +19,6 @@
|
|||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@12c60000";
|
||||
i2c1 = "/i2c@12c70000";
|
||||
i2c2 = "/i2c@12c80000";
|
||||
i2c3 = "/i2c@12c90000";
|
||||
i2c4 = "/i2c@12ca0000";
|
||||
i2c5 = "/i2c@12cb0000";
|
||||
i2c6 = "/i2c@12cc0000";
|
||||
i2c7 = "/i2c@12cd0000";
|
||||
i2c8 = "/i2c@12e00000";
|
||||
i2c9 = "/i2c@12e10000";
|
||||
i2c10 = "/i2c@12e20000";
|
||||
spi0 = "/spi@12d20000";
|
||||
spi1 = "/spi@12d30000";
|
||||
spi2 = "/spi@12d40000";
|
||||
spi3 = "/spi@131a0000";
|
||||
spi4 = "/spi@131b0000";
|
||||
mmc0 = "/mmc@12200000";
|
||||
mmc1 = "/mmc@12210000";
|
||||
mmc2 = "/mmc@12220000";
|
||||
xhci0 = "/xhci@12000000";
|
||||
xhci1 = "/xhci@12400000";
|
||||
serial0 = "/serial@12C30000";
|
||||
console = "/serial@12C30000";
|
||||
};
|
||||
|
|
|
@ -1,70 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2013 SAMSUNG Electronics
|
||||
* SAMSUNG EXYNOS5420 SoC device tree source
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/include/ "exynos5.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
machine-arch-id = <4151>;
|
||||
};
|
||||
|
||||
i2c@12ca0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CA0000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
};
|
||||
|
||||
i2c@12cb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CB0000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
};
|
||||
|
||||
i2c@12cc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CC0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
};
|
||||
|
||||
i2c@12cd0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CD0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
};
|
||||
|
||||
i2c@12e00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12E00000 0x100>;
|
||||
interrupts = <0 87 0>;
|
||||
};
|
||||
|
||||
i2c@12e10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12E10000 0x100>;
|
||||
interrupts = <0 88 0>;
|
||||
};
|
||||
|
||||
i2c@12e20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12E20000 0x100>;
|
||||
interrupts = <0 203 0>;
|
||||
};
|
||||
};
|
151
arch/arm/dts/exynos54xx.dtsi
Normal file
151
arch/arm/dts/exynos54xx.dtsi
Normal file
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* (C) Copyright 2013 SAMSUNG Electronics
|
||||
* SAMSUNG EXYNOS5420 SoC device tree source
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/include/ "exynos5.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
machine-arch-id = <4151>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = "/i2c@12c60000";
|
||||
i2c1 = "/i2c@12c70000";
|
||||
i2c2 = "/i2c@12c80000";
|
||||
i2c3 = "/i2c@12c90000";
|
||||
i2c4 = "/i2c@12ca0000";
|
||||
i2c5 = "/i2c@12cb0000";
|
||||
i2c6 = "/i2c@12cc0000";
|
||||
i2c7 = "/i2c@12cd0000";
|
||||
i2c8 = "/i2c@12e00000";
|
||||
i2c9 = "/i2c@12e10000";
|
||||
i2c10 = "/i2c@12e20000";
|
||||
spi0 = "/spi@12d20000";
|
||||
spi1 = "/spi@12d30000";
|
||||
spi2 = "/spi@12d40000";
|
||||
spi3 = "/spi@131a0000";
|
||||
spi4 = "/spi@131b0000";
|
||||
mmc0 = "/mmc@12200000";
|
||||
mmc1 = "/mmc@12210000";
|
||||
mmc2 = "/mmc@12220000";
|
||||
xhci0 = "/xhci@12000000";
|
||||
xhci1 = "/xhci@12400000";
|
||||
};
|
||||
|
||||
i2c@12ca0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CA0000 0x100>;
|
||||
interrupts = <0 60 0>;
|
||||
};
|
||||
|
||||
i2c@12cb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CB0000 0x100>;
|
||||
interrupts = <0 61 0>;
|
||||
};
|
||||
|
||||
i2c@12cc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CC0000 0x100>;
|
||||
interrupts = <0 62 0>;
|
||||
};
|
||||
|
||||
i2c@12cd0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12CD0000 0x100>;
|
||||
interrupts = <0 63 0>;
|
||||
};
|
||||
|
||||
i2c@12e00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12E00000 0x100>;
|
||||
interrupts = <0 87 0>;
|
||||
};
|
||||
|
||||
i2c@12e10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12E10000 0x100>;
|
||||
interrupts = <0 88 0>;
|
||||
};
|
||||
|
||||
i2c@12e20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
reg = <0x12E20000 0x100>;
|
||||
interrupts = <0 203 0>;
|
||||
};
|
||||
|
||||
mmc@12200000 {
|
||||
samsung,bus-width = <8>;
|
||||
samsung,timing = <1 3 3>;
|
||||
samsung,removable = <0>;
|
||||
samsung,pre-init;
|
||||
};
|
||||
|
||||
mmc@12210000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc@12220000 {
|
||||
samsung,bus-width = <4>;
|
||||
samsung,timing = <1 2 3>;
|
||||
samsung,removable = <1>;
|
||||
};
|
||||
|
||||
mmc@12230000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fimd@14400000 {
|
||||
/* sysmmu is not used in U-Boot */
|
||||
samsung,disable-sysmmu;
|
||||
};
|
||||
|
||||
dp@145b0000 {
|
||||
samsung,lt-status = <0>;
|
||||
|
||||
samsung,master-mode = <0>;
|
||||
samsung,bist-mode = <0>;
|
||||
samsung,bist-pattern = <0>;
|
||||
samsung,h-sync-polarity = <0>;
|
||||
samsung,v-sync-polarity = <0>;
|
||||
samsung,interlaced = <0>;
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
};
|
||||
|
||||
dmc {
|
||||
mem-type = "ddr3";
|
||||
};
|
||||
|
||||
xhci1: xhci@12400000 {
|
||||
compatible = "samsung,exynos5250-xhci";
|
||||
reg = <0x12400000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
phy {
|
||||
compatible = "samsung,exynos5250-usb3-phy";
|
||||
reg = <0x12500000 0x100>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
|
|||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
|
||||
obj-y += misc.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
endif
|
||||
ifeq ($(SOC),$(filter $(SOC),mx6))
|
||||
obj-$(CONFIG_CMD_SATA) += sata.o
|
||||
|
|
|
@ -58,6 +58,7 @@ char *get_reset_cause(void)
|
|||
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
|
||||
static const unsigned char bank_lookup[] = {3, 2};
|
||||
|
||||
/* these MMDC registers are common to the IMX53 and IMX6 */
|
||||
struct esd_mmdc_regs {
|
||||
uint32_t ctl;
|
||||
uint32_t pdc;
|
||||
|
@ -66,15 +67,6 @@ struct esd_mmdc_regs {
|
|||
uint32_t cfg1;
|
||||
uint32_t cfg2;
|
||||
uint32_t misc;
|
||||
uint32_t scr;
|
||||
uint32_t ref;
|
||||
uint32_t rsvd1;
|
||||
uint32_t rsvd2;
|
||||
uint32_t rwd;
|
||||
uint32_t or;
|
||||
uint32_t mrr;
|
||||
uint32_t cfg3lp;
|
||||
uint32_t mr4;
|
||||
};
|
||||
|
||||
#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
|
||||
|
@ -83,6 +75,12 @@ struct esd_mmdc_regs {
|
|||
#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
|
||||
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
|
||||
|
||||
/*
|
||||
* imx_ddr_size - return size in bytes of DRAM according MMDC config
|
||||
* The MMDC MDCTL register holds the number of bits for row, col, and data
|
||||
* width and the MMDC MDMISC register holds the number of banks. Combine
|
||||
* all these bits to determine the meme size the MMDC has been configured for
|
||||
*/
|
||||
unsigned imx_ddr_size(void)
|
||||
{
|
||||
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
|
||||
|
|
|
@ -11,6 +11,9 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#endif
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
||||
static void *base = (void *)IOMUXC_BASE_ADDR;
|
||||
|
@ -54,12 +57,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
|||
#endif
|
||||
}
|
||||
|
||||
/* configures a list of pads within declared with IOMUX_PADS macro */
|
||||
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
|
||||
unsigned count)
|
||||
{
|
||||
iomux_v3_cfg_t const *p = pad_list;
|
||||
int stride;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
imx_iomux_v3_setup_pad(*p++);
|
||||
#if defined(CONFIG_MX6QDL)
|
||||
stride = 2;
|
||||
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
|
||||
p += 1;
|
||||
#else
|
||||
stride = 1;
|
||||
#endif
|
||||
for (i = 0; i < count; i++) {
|
||||
imx_iomux_v3_setup_pad(*p);
|
||||
p += stride;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -8,13 +8,18 @@
|
|||
#include <asm/arch/iomux.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
int setup_sata(void)
|
||||
{
|
||||
struct iomuxc_base_regs *const iomuxc_regs
|
||||
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
int ret = enable_sata_clock();
|
||||
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
|
||||
return 1;
|
||||
|
||||
ret = enable_sata_clock();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
81
arch/arm/imx-common/spl.c
Normal file
81
arch/arm/imx-common/spl.c
Normal file
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation
|
||||
* Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/spl.h>
|
||||
#include <spl.h>
|
||||
|
||||
#if defined(CONFIG_MX6)
|
||||
/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
struct src *psrc = (struct src *)SRC_BASE_ADDR;
|
||||
unsigned reg = readl(&psrc->sbmr1);
|
||||
|
||||
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
|
||||
switch ((reg & 0x000000FF) >> 4) {
|
||||
/* EIM: See 8.5.1, Table 8-9 */
|
||||
case 0x0:
|
||||
/* BOOT_CFG1[3]: NOR/OneNAND Selection */
|
||||
if ((reg & 0x00000008) >> 3)
|
||||
return BOOT_DEVICE_ONENAND;
|
||||
else
|
||||
return BOOT_DEVICE_NOR;
|
||||
break;
|
||||
/* SATA: See 8.5.4, Table 8-20 */
|
||||
case 0x2:
|
||||
return BOOT_DEVICE_SATA;
|
||||
/* Serial ROM: See 8.5.5.1, Table 8-22 */
|
||||
case 0x3:
|
||||
/* BOOT_CFG4[2:0] */
|
||||
switch ((reg & 0x07000000) >> 24) {
|
||||
case 0x0 ... 0x4:
|
||||
return BOOT_DEVICE_SPI;
|
||||
case 0x5 ... 0x7:
|
||||
return BOOT_DEVICE_I2C;
|
||||
}
|
||||
break;
|
||||
/* SD/eSD: 8.5.3, Table 8-15 */
|
||||
case 0x4:
|
||||
case 0x5:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
/* MMC/eMMC: 8.5.3 */
|
||||
case 0x6:
|
||||
case 0x7:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
/* NAND Flash: 8.5.2 */
|
||||
case 0x8 ... 0xf:
|
||||
return BOOT_DEVICE_NAND;
|
||||
}
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPL_MMC_SUPPORT)
|
||||
/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
|
||||
u32 spl_boot_mode(void)
|
||||
{
|
||||
switch (spl_boot_device()) {
|
||||
/* for MMC return either RAW or FAT mode */
|
||||
case BOOT_DEVICE_MMC1:
|
||||
case BOOT_DEVICE_MMC2:
|
||||
#ifdef CONFIG_SPL_FAT_SUPPORT
|
||||
return MMCSD_MODE_FAT;
|
||||
#else
|
||||
return MMCSD_MODE_RAW;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
puts("spl: ERROR: unsupported device\n");
|
||||
hang();
|
||||
}
|
||||
}
|
||||
#endif
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
enum {
|
||||
BOOT_DEVICE_NONE,
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
BOOT_DEVICE_MMC1,
|
||||
BOOT_DEVICE_MMC2,
|
||||
BOOT_DEVICE_MMC2_2,
|
||||
#elif CONFIG_SYS_USE_NANDFLASH
|
||||
BOOT_DEVICE_NAND,
|
||||
#elif CONFIG_SYS_USE_SERIALFLASH
|
||||
BOOT_DEVICE_SPI,
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
|
@ -1,72 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _EMIF_DEFS_H_
|
||||
#define _EMIF_DEFS_H_
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
struct davinci_emif_regs {
|
||||
u_int32_t ercsr;
|
||||
u_int32_t awccr;
|
||||
u_int32_t sdbcr;
|
||||
u_int32_t sdrcr;
|
||||
u_int32_t ab1cr;
|
||||
u_int32_t ab2cr;
|
||||
u_int32_t ab3cr;
|
||||
u_int32_t ab4cr;
|
||||
u_int32_t sdtimr;
|
||||
u_int32_t ddrsr;
|
||||
u_int32_t ddrphycr;
|
||||
u_int32_t ddrphysr;
|
||||
u_int32_t totar;
|
||||
u_int32_t totactr;
|
||||
u_int32_t ddrphyid_rev;
|
||||
u_int32_t sdsretr;
|
||||
u_int32_t eirr;
|
||||
u_int32_t eimr;
|
||||
u_int32_t eimsr;
|
||||
u_int32_t eimcr;
|
||||
u_int32_t ioctrlr;
|
||||
u_int32_t iostatr;
|
||||
u_int8_t rsvd0[8];
|
||||
u_int32_t nandfcr;
|
||||
u_int32_t nandfsr;
|
||||
u_int8_t rsvd1[8];
|
||||
u_int32_t nandfecc[4];
|
||||
u_int8_t rsvd2[60];
|
||||
u_int32_t nand4biteccload;
|
||||
u_int32_t nand4bitecc[4];
|
||||
u_int32_t nanderradd1;
|
||||
u_int32_t nanderradd2;
|
||||
u_int32_t nanderrval1;
|
||||
u_int32_t nanderrval2;
|
||||
};
|
||||
|
||||
#define davinci_emif_regs \
|
||||
((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
|
||||
|
||||
#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
|
||||
#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
|
||||
#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
|
||||
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
|
||||
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
|
||||
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
|
||||
#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
|
||||
|
||||
/* Chip Select setup */
|
||||
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
|
||||
#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
|
||||
#define DAVINCI_ABCR_WSETUP(n) (n << 26)
|
||||
#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
|
||||
#define DAVINCI_ABCR_WHOLD(n) (n << 17)
|
||||
#define DAVINCI_ABCR_RSETUP(n) (n << 13)
|
||||
#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
|
||||
#define DAVINCI_ABCR_RHOLD(n) (n << 4)
|
||||
#define DAVINCI_ABCR_TA(n) (n << 2)
|
||||
#define DAVINCI_ABCR_ASIZE_16BIT 1
|
||||
#define DAVINCI_ABCR_ASIZE_8BIT 0
|
||||
|
||||
#endif
|
|
@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void)
|
|||
#if defined(CONFIG_SOC_DM365)
|
||||
#include <asm/arch/aintc_defs.h>
|
||||
#include <asm/arch/ddr2_defs.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pll_defs.h>
|
||||
#include <asm/arch/psc_defs.h>
|
||||
|
|
|
@ -1,38 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Parts shamelesly stolen from Linux Kernel source tree.
|
||||
*
|
||||
* ------------------------------------------------------------
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _NAND_DEFS_H_
|
||||
#define _NAND_DEFS_H_
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#ifdef CONFIG_SOC_DM646X
|
||||
#define MASK_CLE 0x80000
|
||||
#define MASK_ALE 0x40000
|
||||
#else
|
||||
#define MASK_CLE 0x10
|
||||
#define MASK_ALE 0x08
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_NAND_MASK_CLE
|
||||
#undef MASK_CLE
|
||||
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_MASK_ALE
|
||||
#undef MASK_ALE
|
||||
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
|
||||
#endif
|
||||
|
||||
#define NAND_READ_START 0x00
|
||||
#define NAND_READ_END 0x30
|
||||
#define NAND_STATUS 0x70
|
||||
|
||||
extern void davinci_nand_init(struct nand_chip *nand);
|
||||
|
||||
#endif
|
|
@ -1,16 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_NAND 1
|
||||
#define BOOT_DEVICE_SPI 2
|
||||
#define BOOT_DEVICE_MMC1 3
|
||||
#define BOOT_DEVICE_MMC2 4 /* dummy */
|
||||
#define BOOT_DEVICE_MMC2_2 5 /* dummy */
|
||||
|
||||
#endif
|
|
@ -467,6 +467,9 @@ enum mem_manuf {
|
|||
/* PHY_CON1 register fields */
|
||||
#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
|
||||
|
||||
/* PHY_CON4 rgister fields */
|
||||
#define PHY_CON10_CTRL_OFFSETR3 (1 << 24)
|
||||
|
||||
/* PHY_CON12 register fields */
|
||||
#define PHY_CON12_CTRL_START_POINT_SHIFT 24
|
||||
#define PHY_CON12_CTRL_INC_SHIFT 16
|
||||
|
|
|
@ -906,8 +906,8 @@ struct exynos5420_power {
|
|||
unsigned int sysip_dat3;
|
||||
unsigned char res11[0xe0];
|
||||
unsigned int pmu_spare0;
|
||||
unsigned int pmu_spare1;
|
||||
unsigned int pmu_spare2;
|
||||
unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */
|
||||
unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */
|
||||
unsigned int pmu_spare3;
|
||||
unsigned char res12[0x4];
|
||||
unsigned int cg_status0;
|
||||
|
|
|
@ -9,13 +9,6 @@
|
|||
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
|
||||
#define __ASM_ARCH_HARDWARE_K2HK_H
|
||||
|
||||
#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
|
||||
#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
|
||||
#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
|
||||
#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
|
||||
#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
|
||||
|
||||
#define K2HK_PLL_CNTRL_BASE 0x02310000
|
||||
#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
|
||||
#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
|
||||
|
|
|
@ -22,32 +22,6 @@
|
|||
typedef volatile unsigned int dv_reg;
|
||||
typedef volatile unsigned int *dv_reg_p;
|
||||
|
||||
#define ASYNC_EMIF_NUM_CS 4
|
||||
#define ASYNC_EMIF_MODE_NOR 0
|
||||
#define ASYNC_EMIF_MODE_NAND 1
|
||||
#define ASYNC_EMIF_MODE_ONENAND 2
|
||||
#define ASYNC_EMIF_PRESERVE -1
|
||||
|
||||
struct async_emif_config {
|
||||
unsigned mode;
|
||||
unsigned select_strobe;
|
||||
unsigned extend_wait;
|
||||
unsigned wr_setup;
|
||||
unsigned wr_strobe;
|
||||
unsigned wr_hold;
|
||||
unsigned rd_setup;
|
||||
unsigned rd_strobe;
|
||||
unsigned rd_hold;
|
||||
unsigned turn_around;
|
||||
enum {
|
||||
ASYNC_EMIF_8 = 0,
|
||||
ASYNC_EMIF_16 = 1,
|
||||
ASYNC_EMIF_32 = 2,
|
||||
} width;
|
||||
};
|
||||
|
||||
void init_async_emif(int num_cs, struct async_emif_config *config);
|
||||
|
||||
struct ddr3_phy_config {
|
||||
unsigned int pllcr;
|
||||
unsigned int pgcr1_mask;
|
||||
|
@ -145,6 +119,10 @@ struct ddr3_emif_config {
|
|||
#define KS2_UART0_BASE 0x02530c00
|
||||
#define KS2_UART1_BASE 0x02531000
|
||||
|
||||
/* AEMIF */
|
||||
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
|
||||
|
||||
#ifdef CONFIG_SOC_K2HK
|
||||
#include <asm/arch/hardware-k2hk.h>
|
||||
#endif
|
||||
|
|
|
@ -1,23 +0,0 @@
|
|||
/*
|
||||
* nand driver definitions to re-use davinci nand driver on Keystone2
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _NAND_DEFS_H_
|
||||
#define _NAND_DEFS_H_
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
#define MASK_CLE 0x4000
|
||||
#define MASK_ALE 0x2000
|
||||
|
||||
#define NAND_READ_START 0x00
|
||||
#define NAND_READ_END 0x30
|
||||
#define NAND_STATUS 0x70
|
||||
|
||||
#endif
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_NONE 0
|
||||
#define BOOT_DEVICE_XIP 1
|
||||
#define BOOT_DEVICE_XIPWAIT 2
|
||||
#define BOOT_DEVICE_NAND 3
|
||||
#define BOOT_DEVICE_ONENAND 4
|
||||
#define BOOT_DEVICE_MMC1 5
|
||||
#define BOOT_DEVICE_MMC2 6
|
||||
#define BOOT_DEVICE_MMC2_2 7
|
||||
#define BOOT_DEVICE_NOR 8
|
||||
#define BOOT_DEVICE_I2C 9
|
||||
#define BOOT_DEVICE_SPI 10
|
||||
|
||||
#endif
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SPL_H__
|
||||
#define __ASM_ARCH_SPL_H__
|
||||
|
||||
#define BOOT_DEVICE_NONE 0
|
||||
#define BOOT_DEVICE_NAND 1
|
||||
|
||||
#endif /* __ASM_ARCH_SPL_H__ */
|
|
@ -53,12 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
|
|||
void **, size_t *, hab_loader_callback_f_t);
|
||||
typedef void hapi_clock_init_t(void);
|
||||
|
||||
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
|
||||
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
|
||||
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
|
||||
#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
|
||||
#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
|
||||
#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
|
||||
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
|
||||
#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
|
||||
#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
|
||||
#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
|
||||
#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
|
||||
|
||||
#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
|
||||
#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
|
||||
#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
|
||||
#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
|
||||
#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
|
||||
|
||||
#define HAB_CID_ROM 0 /**< ROM Caller ID */
|
||||
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
|
||||
|
|
|
@ -217,6 +217,8 @@
|
|||
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_1_2 0x12
|
||||
#define CHIP_REV_1_5 0x15
|
||||
#define IRAM_SIZE 0x00040000
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
|
||||
#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
|
||||
#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
|
||||
#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12)
|
||||
#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
|
||||
#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
|
||||
|
||||
/*
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
#ifndef __ASM_ARCH_MX6_DDR_H__
|
||||
#define __ASM_ARCH_MX6_DDR_H__
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_MX6Q
|
||||
#include "mx6q-ddr.h"
|
||||
#else
|
||||
|
@ -15,6 +16,236 @@
|
|||
#error "Please select cpu"
|
||||
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
|
||||
#endif /* CONFIG_MX6Q */
|
||||
#else
|
||||
|
||||
/* MMDC P0/P1 Registers */
|
||||
struct mmdc_p_regs {
|
||||
u32 mdctl;
|
||||
u32 mdpdc;
|
||||
u32 mdotc;
|
||||
u32 mdcfg0;
|
||||
u32 mdcfg1;
|
||||
u32 mdcfg2;
|
||||
u32 mdmisc;
|
||||
u32 mdscr;
|
||||
u32 mdref;
|
||||
u32 res1[2];
|
||||
u32 mdrwd;
|
||||
u32 mdor;
|
||||
u32 res2[3];
|
||||
u32 mdasp;
|
||||
u32 res3[240];
|
||||
u32 mapsr;
|
||||
u32 res4[254];
|
||||
u32 mpzqhwctrl;
|
||||
u32 res5[2];
|
||||
u32 mpwldectrl0;
|
||||
u32 mpwldectrl1;
|
||||
u32 res6;
|
||||
u32 mpodtctrl;
|
||||
u32 mprddqby0dl;
|
||||
u32 mprddqby1dl;
|
||||
u32 mprddqby2dl;
|
||||
u32 mprddqby3dl;
|
||||
u32 res7[4];
|
||||
u32 mpdgctrl0;
|
||||
u32 mpdgctrl1;
|
||||
u32 res8;
|
||||
u32 mprddlctl;
|
||||
u32 res9;
|
||||
u32 mpwrdlctl;
|
||||
u32 res10[25];
|
||||
u32 mpmur0;
|
||||
};
|
||||
|
||||
/*
|
||||
* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
|
||||
*/
|
||||
#define MX6DQ_IOM_DDR_BASE 0x020e0500
|
||||
struct mx6dq_iomux_ddr_regs {
|
||||
u32 res1[3];
|
||||
u32 dram_sdqs5;
|
||||
u32 dram_dqm5;
|
||||
u32 dram_dqm4;
|
||||
u32 dram_sdqs4;
|
||||
u32 dram_sdqs3;
|
||||
u32 dram_dqm3;
|
||||
u32 dram_sdqs2;
|
||||
u32 dram_dqm2;
|
||||
u32 res2[16];
|
||||
u32 dram_cas;
|
||||
u32 res3[2];
|
||||
u32 dram_ras;
|
||||
u32 dram_reset;
|
||||
u32 res4[2];
|
||||
u32 dram_sdclk_0;
|
||||
u32 dram_sdba2;
|
||||
u32 dram_sdcke0;
|
||||
u32 dram_sdclk_1;
|
||||
u32 dram_sdcke1;
|
||||
u32 dram_sdodt0;
|
||||
u32 dram_sdodt1;
|
||||
u32 res5;
|
||||
u32 dram_sdqs0;
|
||||
u32 dram_dqm0;
|
||||
u32 dram_sdqs1;
|
||||
u32 dram_dqm1;
|
||||
u32 dram_sdqs6;
|
||||
u32 dram_dqm6;
|
||||
u32 dram_sdqs7;
|
||||
u32 dram_dqm7;
|
||||
};
|
||||
|
||||
#define MX6DQ_IOM_GRP_BASE 0x020e0700
|
||||
struct mx6dq_iomux_grp_regs {
|
||||
u32 res1[18];
|
||||
u32 grp_b7ds;
|
||||
u32 grp_addds;
|
||||
u32 grp_ddrmode_ctl;
|
||||
u32 res2;
|
||||
u32 grp_ddrpke;
|
||||
u32 res3[6];
|
||||
u32 grp_ddrmode;
|
||||
u32 res4[3];
|
||||
u32 grp_b0ds;
|
||||
u32 grp_b1ds;
|
||||
u32 grp_ctlds;
|
||||
u32 res5;
|
||||
u32 grp_b2ds;
|
||||
u32 grp_ddr_type;
|
||||
u32 grp_b3ds;
|
||||
u32 grp_b4ds;
|
||||
u32 grp_b5ds;
|
||||
u32 grp_b6ds;
|
||||
};
|
||||
|
||||
#define MX6SDL_IOM_DDR_BASE 0x020e0400
|
||||
struct mx6sdl_iomux_ddr_regs {
|
||||
u32 res1[25];
|
||||
u32 dram_cas;
|
||||
u32 res2[2];
|
||||
u32 dram_dqm0;
|
||||
u32 dram_dqm1;
|
||||
u32 dram_dqm2;
|
||||
u32 dram_dqm3;
|
||||
u32 dram_dqm4;
|
||||
u32 dram_dqm5;
|
||||
u32 dram_dqm6;
|
||||
u32 dram_dqm7;
|
||||
u32 dram_ras;
|
||||
u32 dram_reset;
|
||||
u32 res3[2];
|
||||
u32 dram_sdba2;
|
||||
u32 dram_sdcke0;
|
||||
u32 dram_sdcke1;
|
||||
u32 dram_sdclk_0;
|
||||
u32 dram_sdclk_1;
|
||||
u32 dram_sdodt0;
|
||||
u32 dram_sdodt1;
|
||||
u32 dram_sdqs0;
|
||||
u32 dram_sdqs1;
|
||||
u32 dram_sdqs2;
|
||||
u32 dram_sdqs3;
|
||||
u32 dram_sdqs4;
|
||||
u32 dram_sdqs5;
|
||||
u32 dram_sdqs6;
|
||||
u32 dram_sdqs7;
|
||||
};
|
||||
|
||||
#define MX6SDL_IOM_GRP_BASE 0x020e0700
|
||||
struct mx6sdl_iomux_grp_regs {
|
||||
u32 res1[18];
|
||||
u32 grp_b7ds;
|
||||
u32 grp_addds;
|
||||
u32 grp_ddrmode_ctl;
|
||||
u32 grp_ddrpke;
|
||||
u32 res2[2];
|
||||
u32 grp_ddrmode;
|
||||
u32 grp_b0ds;
|
||||
u32 res3;
|
||||
u32 grp_ctlds;
|
||||
u32 grp_b1ds;
|
||||
u32 grp_ddr_type;
|
||||
u32 grp_b2ds;
|
||||
u32 grp_b3ds;
|
||||
u32 grp_b4ds;
|
||||
u32 grp_b5ds;
|
||||
u32 res4;
|
||||
u32 grp_b6ds;
|
||||
};
|
||||
|
||||
/* Device Information: Varies per DDR3 part number and speed grade */
|
||||
struct mx6_ddr3_cfg {
|
||||
u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
|
||||
u8 density; /* chip density (Gb) (1,2,4,8) */
|
||||
u8 width; /* bus width (bits) (4,8,16) */
|
||||
u8 banks; /* number of banks */
|
||||
u8 rowaddr; /* row address bits (11-16)*/
|
||||
u8 coladdr; /* col address bits (9-12) */
|
||||
u8 pagesz; /* page size (K) (1-2) */
|
||||
u16 trcd; /* tRCD=tRP=CL (ns*100) */
|
||||
u16 trcmin; /* tRC min (ns*100) */
|
||||
u16 trasmin; /* tRAS min (ns*100) */
|
||||
u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
|
||||
};
|
||||
|
||||
/* System Information: Varies per board design, layout, and term choices */
|
||||
struct mx6_ddr_sysinfo {
|
||||
u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
|
||||
u8 cs_density; /* density per chip select (Gb) */
|
||||
u8 ncs; /* number chip selects used (1|2) */
|
||||
char cs1_mirror;/* enable address mirror (0|1) */
|
||||
char bi_on; /* Bank interleaving enable */
|
||||
u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
|
||||
u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
|
||||
u8 ralat; /* Read Additional Latency (0-7) */
|
||||
u8 walat; /* Write Additional Latency (0-3) */
|
||||
u8 mif3_mode; /* Command prediction working mode */
|
||||
u8 rst_to_cke; /* Time from SDE enable to CKE rise */
|
||||
u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
|
||||
};
|
||||
|
||||
/*
|
||||
* Board specific calibration:
|
||||
* This includes write leveling calibration values as well as DQS gating
|
||||
* and read/write delays. These values are board/layout/device specific.
|
||||
* Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
|
||||
* (DOC-96412) to determine these values over a range of boards and
|
||||
* temperatures.
|
||||
*/
|
||||
struct mx6_mmdc_calibration {
|
||||
/* write leveling calibration */
|
||||
u32 p0_mpwldectrl0;
|
||||
u32 p0_mpwldectrl1;
|
||||
u32 p1_mpwldectrl0;
|
||||
u32 p1_mpwldectrl1;
|
||||
/* read DQS gating */
|
||||
u32 p0_mpdgctrl0;
|
||||
u32 p0_mpdgctrl1;
|
||||
u32 p1_mpdgctrl0;
|
||||
u32 p1_mpdgctrl1;
|
||||
/* read delay */
|
||||
u32 p0_mprddlctl;
|
||||
u32 p1_mprddlctl;
|
||||
/* write delay */
|
||||
u32 p0_mpwrdlctl;
|
||||
u32 p1_mpwrdlctl;
|
||||
};
|
||||
|
||||
/* configure iomux (pinctl/padctl) */
|
||||
void mx6dq_dram_iocfg(unsigned width,
|
||||
const struct mx6dq_iomux_ddr_regs *,
|
||||
const struct mx6dq_iomux_grp_regs *);
|
||||
void mx6sdl_dram_iocfg(unsigned width,
|
||||
const struct mx6sdl_iomux_ddr_regs *,
|
||||
const struct mx6sdl_iomux_grp_regs *);
|
||||
|
||||
/* configure mx6 mmdc registers */
|
||||
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
|
||||
const struct mx6_mmdc_calibration *,
|
||||
const struct mx6_ddr3_cfg *);
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
#define MX6_MMDC_P0_MDCTL 0x021b0000
|
||||
#define MX6_MMDC_P0_MDPDC 0x021b0004
|
||||
|
|
|
@ -11,7 +11,9 @@
|
|||
#include <asm/imx-common/regs-common.h>
|
||||
#include "../arch-imx/cpu.h"
|
||||
|
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
|
||||
#define soc_rev() (get_cpu_rev() & 0xFF)
|
||||
#define is_soc_rev(rev) (soc_rev() - rev)
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
|
||||
/* returns MXC_CPU_ value */
|
||||
|
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif
|
|
@ -1,13 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2010-2013
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif /* _ASM_ARCH_SPL_H_ */
|
|
@ -1,12 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif
|
|
@ -1,12 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif
|
|
@ -1 +0,0 @@
|
|||
#include <asm/arch-davinci/emif_defs.h>
|
|
@ -155,4 +155,6 @@ int wdt_kick(void);
|
|||
#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
|
||||
#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
|
||||
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
||||
|
|
|
@ -1,23 +0,0 @@
|
|||
/*
|
||||
* TNETV107X: NAND definitions
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _NAND_DEFS_H_
|
||||
#define _NAND_DEFS_H_
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
|
||||
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
|
||||
|
||||
#define MASK_CLE 0x4000
|
||||
#define MASK_ALE 0x2000
|
||||
|
||||
#define NAND_READ_START 0x00
|
||||
#define NAND_READ_END 0x30
|
||||
#define NAND_STATUS 0x70
|
||||
|
||||
extern void davinci_nand_init(struct nand_chip *nand);
|
||||
|
||||
#endif
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -150,6 +150,9 @@ struct anadig_reg {
|
|||
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
|
||||
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
|
||||
|
||||
#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
|
||||
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
|
||||
#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
|
||||
#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
|
||||
#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
|
||||
#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
|
||||
|
@ -161,6 +164,11 @@ struct anadig_reg {
|
|||
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
|
||||
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
|
||||
|
||||
#define CCM_CSCDR3_QSPI0_EN (1 << 4)
|
||||
#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
|
||||
#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
|
||||
#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
|
||||
|
||||
#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
|
||||
#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
|
||||
#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
|
||||
|
@ -170,6 +178,7 @@ struct anadig_reg {
|
|||
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
|
||||
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
|
||||
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
|
||||
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
|
||||
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
|
||||
#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
|
||||
#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -87,6 +87,8 @@
|
|||
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
|
||||
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
|
||||
|
||||
#define QSPI0_AMBA_BASE 0x20000000
|
||||
|
||||
/* MUX mode and PAD ctrl are in one register */
|
||||
#define CONFIG_IOMUX_SHARE_CONF_REG
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright 2013-2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
@ -20,6 +20,9 @@
|
|||
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
|
||||
PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
|
||||
|
||||
#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
|
||||
|
||||
enum {
|
||||
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
|
||||
VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
|
||||
|
@ -53,6 +56,18 @@ enum {
|
|||
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
|
||||
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
|
||||
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
|
||||
VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
|
||||
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
|
||||
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
|
||||
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
|
||||
|
|
|
@ -123,12 +123,14 @@ typedef u64 iomux_v3_cfg_t;
|
|||
#define PAD_CTL_SPEED_MED (1 << 12)
|
||||
#define PAD_CTL_SPEED_HIGH (3 << 12)
|
||||
|
||||
#define PAD_CTL_DSE_150ohm (1 << 6)
|
||||
#define PAD_CTL_DSE_50ohm (3 << 6)
|
||||
#define PAD_CTL_DSE_25ohm (6 << 6)
|
||||
#define PAD_CTL_DSE_20ohm (7 << 6)
|
||||
|
||||
#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
|
||||
#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
|
||||
#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
|
||||
#define PAD_CTL_PKE (1 << 3)
|
||||
#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
|
||||
|
||||
|
@ -175,4 +177,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
|||
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
|
||||
unsigned count);
|
||||
|
||||
/* macros for declaring and using pinmux array */
|
||||
#if defined(CONFIG_MX6QDL)
|
||||
#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
|
||||
#define SETUP_IOMUX_PAD(def) \
|
||||
if (is_cpu_type(MXC_CPU_MX6Q)) { \
|
||||
imx_iomux_v3_setup_pad(MX6Q_##def); \
|
||||
} else { \
|
||||
imx_iomux_v3_setup_pad(MX6DL_##def); \
|
||||
}
|
||||
#define SETUP_IOMUX_PADS(x) \
|
||||
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
|
||||
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
|
||||
#define IOMUX_PADS(x) MX6Q_##x
|
||||
#define SETUP_IOMUX_PAD(def) \
|
||||
imx_iomux_v3_setup_pad(MX6Q_##def);
|
||||
#define SETUP_IOMUX_PADS(x) \
|
||||
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
|
||||
#else
|
||||
#define IOMUX_PADS(x) MX6DL_##x
|
||||
#define SETUP_IOMUX_PAD(def) \
|
||||
imx_iomux_v3_setup_pad(MX6DL_##def);
|
||||
#define SETUP_IOMUX_PADS(x) \
|
||||
imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_IOMUX_V3_H__*/
|
||||
|
|
|
@ -7,9 +7,29 @@
|
|||
#ifndef _ASM_SPL_H_
|
||||
#define _ASM_SPL_H_
|
||||
|
||||
#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \
|
||||
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|
||||
|| defined(CONFIG_EXYNOS4210)
|
||||
/* Platform-specific defines */
|
||||
#include <asm/arch/spl.h>
|
||||
|
||||
#else
|
||||
enum {
|
||||
BOOT_DEVICE_RAM,
|
||||
BOOT_DEVICE_MMC1,
|
||||
BOOT_DEVICE_MMC2,
|
||||
BOOT_DEVICE_MMC2_2,
|
||||
BOOT_DEVICE_NAND,
|
||||
BOOT_DEVICE_ONENAND,
|
||||
BOOT_DEVICE_NOR,
|
||||
BOOT_DEVICE_UART,
|
||||
BOOT_DEVICE_SPI,
|
||||
BOOT_DEVICE_SATA,
|
||||
BOOT_DEVICE_I2C,
|
||||
BOOT_DEVICE_NONE
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Linker symbols. */
|
||||
extern char __bss_start[], __bss_end[];
|
||||
|
||||
|
|
|
@ -1,23 +1,45 @@
|
|||
/*
|
||||
* emif definitions to re-use davinci emif driver on Keystone2
|
||||
* NAND Flash Driver
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
* Copyright (C) 2006-2014 Texas Instruments.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
* Based on Linux DaVinci NAND driver by TI.
|
||||
*/
|
||||
#ifndef _EMIF_DEFS_H_
|
||||
#define _EMIF_DEFS_H_
|
||||
|
||||
#ifndef _DAVINCI_NAND_H_
|
||||
#define _DAVINCI_NAND_H_
|
||||
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define NAND_READ_START 0x00
|
||||
#define NAND_READ_END 0x30
|
||||
#define NAND_STATUS 0x70
|
||||
|
||||
#define MASK_CLE 0x10
|
||||
#define MASK_ALE 0x08
|
||||
|
||||
#ifdef CONFIG_SYS_NAND_MASK_CLE
|
||||
#undef MASK_CLE
|
||||
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_MASK_ALE
|
||||
#undef MASK_ALE
|
||||
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
|
||||
#endif
|
||||
|
||||
struct davinci_emif_regs {
|
||||
uint32_t ercsr;
|
||||
uint32_t awccr;
|
||||
uint32_t sdbcr;
|
||||
uint32_t sdrcr;
|
||||
uint32_t abncr[4];
|
||||
union {
|
||||
uint32_t abncr[4];
|
||||
uint32_t ab1cr;
|
||||
uint32_t ab2cr;
|
||||
uint32_t ab3cr;
|
||||
uint32_t ab4cr;
|
||||
};
|
||||
uint32_t sdtimr;
|
||||
uint32_t ddrsr;
|
||||
uint32_t ddrphycr;
|
||||
|
@ -56,18 +78,21 @@ struct davinci_emif_regs {
|
|||
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
|
||||
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
|
||||
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
|
||||
#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
|
||||
|
||||
/* Chip Select setup */
|
||||
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
|
||||
#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
|
||||
#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
|
||||
#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
|
||||
#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
|
||||
#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
|
||||
#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
|
||||
#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
|
||||
#define DAVINCI_ABCR_TA(n) ((n) << 2)
|
||||
#define DAVINCI_ABCR_WSETUP(n) (n << 26)
|
||||
#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
|
||||
#define DAVINCI_ABCR_WHOLD(n) (n << 17)
|
||||
#define DAVINCI_ABCR_RSETUP(n) (n << 13)
|
||||
#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
|
||||
#define DAVINCI_ABCR_RHOLD(n) (n << 4)
|
||||
#define DAVINCI_ABCR_TA(n) (n << 2)
|
||||
#define DAVINCI_ABCR_ASIZE_16BIT 1
|
||||
#define DAVINCI_ABCR_ASIZE_8BIT 0
|
||||
|
||||
void davinci_nand_init(struct nand_chip *nand);
|
||||
|
||||
#endif
|
39
arch/arm/include/asm/ti-common/ti-aemif.h
Normal file
39
arch/arm/include/asm/ti-common/ti-aemif.h
Normal file
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* AEMIF definitions
|
||||
*
|
||||
* (C) Copyright 2012-2014
|
||||
* Texas Instruments Incorporated, <www.ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _AEMIF_H_
|
||||
#define _AEMIF_H_
|
||||
|
||||
#define AEMIF_NUM_CS 4
|
||||
#define AEMIF_MODE_NOR 0
|
||||
#define AEMIF_MODE_NAND 1
|
||||
#define AEMIF_MODE_ONENAND 2
|
||||
#define AEMIF_PRESERVE -1
|
||||
|
||||
struct aemif_config {
|
||||
unsigned mode;
|
||||
unsigned select_strobe;
|
||||
unsigned extend_wait;
|
||||
unsigned wr_setup;
|
||||
unsigned wr_strobe;
|
||||
unsigned wr_hold;
|
||||
unsigned rd_setup;
|
||||
unsigned rd_strobe;
|
||||
unsigned rd_hold;
|
||||
unsigned turn_around;
|
||||
enum {
|
||||
AEMIF_WIDTH_8 = 0,
|
||||
AEMIF_WIDTH_16 = 1,
|
||||
AEMIF_WIDTH_32 = 2,
|
||||
} width;
|
||||
};
|
||||
|
||||
void aemif_init(int num_cs, struct aemif_config *config);
|
||||
|
||||
#endif
|
|
@ -43,8 +43,6 @@
|
|||
*************************************************************************
|
||||
*/
|
||||
|
||||
_start:
|
||||
|
||||
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
|
||||
.word CONFIG_SYS_DV_NOR_BOOT_CFG
|
||||
#endif
|
||||
|
|
|
@ -24,31 +24,31 @@ void dcache_clean_range(volatile void *start, size_t size)
|
|||
sync_write_buffer();
|
||||
}
|
||||
|
||||
void dcache_invalidate_range(volatile void *start, size_t size)
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
unsigned long v, begin, end, linesz;
|
||||
unsigned long v, linesz;
|
||||
|
||||
linesz = CONFIG_SYS_DCACHE_LINESZ;
|
||||
|
||||
/* You asked for it, you got it */
|
||||
begin = (unsigned long)start & ~(linesz - 1);
|
||||
end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
|
||||
start = start & ~(linesz - 1);
|
||||
stop = (stop + linesz - 1) & ~(linesz - 1);
|
||||
|
||||
for (v = begin; v < end; v += linesz)
|
||||
for (v = start; v < stop; v += linesz)
|
||||
dcache_invalidate_line((void *)v);
|
||||
}
|
||||
|
||||
void dcache_flush_range(volatile void *start, size_t size)
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
unsigned long v, begin, end, linesz;
|
||||
unsigned long v, linesz;
|
||||
|
||||
linesz = CONFIG_SYS_DCACHE_LINESZ;
|
||||
|
||||
/* You asked for it, you got it */
|
||||
begin = (unsigned long)start & ~(linesz - 1);
|
||||
end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
|
||||
start = start & ~(linesz - 1);
|
||||
stop = (stop + linesz - 1) & ~(linesz - 1);
|
||||
|
||||
for (v = begin; v < end; v += linesz)
|
||||
for (v = start; v < stop; v += linesz)
|
||||
dcache_flush_line((void *)v);
|
||||
|
||||
sync_write_buffer();
|
||||
|
|
|
@ -49,9 +49,7 @@ static inline void icache_invalidate_line(volatile void *vaddr)
|
|||
* Applies the above functions on all lines that are touched by the
|
||||
* specified virtual address range.
|
||||
*/
|
||||
void dcache_invalidate_range(volatile void *start, size_t len);
|
||||
void dcache_clean_range(volatile void *start, size_t len);
|
||||
void dcache_flush_range(volatile void *start, size_t len);
|
||||
void icache_invalidate_range(volatile void *start, size_t len);
|
||||
|
||||
static inline void dcache_flush_unlocked(void)
|
||||
|
|
|
@ -23,13 +23,15 @@ static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
|
|||
|
||||
switch (dir) {
|
||||
case DMA_BIDIRECTIONAL:
|
||||
dcache_flush_range(vaddr, len);
|
||||
flush_dcache_range((unsigned long)vaddr,
|
||||
(unsigned long)vaddr + len);
|
||||
break;
|
||||
case DMA_TO_DEVICE:
|
||||
dcache_clean_range(vaddr, len);
|
||||
break;
|
||||
case DMA_FROM_DEVICE:
|
||||
dcache_invalidate_range(vaddr, len);
|
||||
invalidate_dcache_range((unsigned long)vaddr,
|
||||
(unsigned long)vaddr + len);
|
||||
break;
|
||||
default:
|
||||
/* This will cause a linker error */
|
||||
|
|
|
@ -65,8 +65,8 @@ static void dma_alloc_init(void)
|
|||
printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
|
||||
dma_alloc_start, dma_alloc_end);
|
||||
|
||||
dcache_invalidate_range(cached(dma_alloc_start),
|
||||
dma_alloc_end - dma_alloc_start);
|
||||
invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
|
||||
dma_alloc_end);
|
||||
}
|
||||
|
||||
void *dma_alloc_coherent(size_t len, unsigned long *handle)
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
#include <spi.h>
|
||||
#include <spi_flash.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/arch/pinmux_defs.h>
|
||||
#include <asm/io.h>
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
#ifdef CONFIG_DAVINCI_MMC
|
||||
#include <mmc.h>
|
||||
|
|
|
@ -25,12 +25,11 @@
|
|||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/arch/pinmux_defs.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
|
||||
#ifdef CONFIG_DAVINCI_MMC
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
#include <spi.h>
|
||||
#include <spi_flash.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/arch/pinmux_defs.h>
|
||||
#include <asm/io.h>
|
||||
|
|
|
@ -8,8 +8,7 @@
|
|||
#include <nand.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
|
|
|
@ -8,8 +8,7 @@
|
|||
#include <nand.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
|
|
|
@ -8,7 +8,8 @@
|
|||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <nand.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
|
||||
|
|
|
@ -14,7 +14,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/iomux-mx53.h>
|
||||
#include <asm/imx-common/mx5_video.h>
|
||||
#include <asm/arch/spl.h>
|
||||
#include <asm/spl.h>
|
||||
#include <asm/errno.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
|
|
|
@ -29,7 +29,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/da850_lowlevel.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux_defs.h>
|
||||
|
|
|
@ -23,11 +23,19 @@ To boot MX28EVK from an SD card, set the boot mode DIP switches as:
|
|||
* VDD 5V: To the left (off)
|
||||
* Hold Button: Down (off)
|
||||
|
||||
To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
|
||||
|
||||
* Boot Mode Select: 0 0 1 0 (Boot from SSP2)
|
||||
* JTAG PSWITCH RESET: To the right (reset disabled)
|
||||
* Battery Source: Down
|
||||
* Wall 5V: Up
|
||||
* VDD 5V: To the left (off)
|
||||
* Hold Button: Down (off)
|
||||
|
||||
Environment Storage
|
||||
-------------------
|
||||
|
||||
There are two targets for mx28evk:
|
||||
There are three targets for mx28evk:
|
||||
|
||||
"make mx28evk_config" - store environment variables into MMC
|
||||
|
||||
|
@ -35,12 +43,20 @@ or
|
|||
|
||||
"make mx28evk_nand_config" - store environment variables into NAND flash
|
||||
|
||||
or
|
||||
|
||||
"make mx28evk_spi_config" - store enviroment variables into SPI NOR flash
|
||||
|
||||
Choose the target accordingly.
|
||||
|
||||
Note: The mx28evk board does not come with a NAND flash populated from the
|
||||
factory. It comes with an empty slot (U23), which allows the insertion of a
|
||||
48-pin TSOP flash device.
|
||||
|
||||
Follow the instructions from doc/README.mxs to generate a bootable SD card.
|
||||
mx28evk does not come with SPI NOR flash populated from the factory either.
|
||||
It is possible to solder a SOIC memory on U49 or use a DIP8 on J89.
|
||||
To get SPI communication to work R320, R321,R322 and C178 need to be populated.
|
||||
Look in the schematics for the proper component values.
|
||||
|
||||
Insert the SD card in slot 0, power up the board and U-boot will boot.
|
||||
Follow the instructions from doc/README.mxs to generate a bootable SD card or
|
||||
to generate a binary to be flashed into SPI NOR.
|
||||
|
|
130
board/freescale/mx6qsabreauto/mx6dl.cfg
Normal file
130
board/freescale/mx6qsabreauto/mx6dl.cfg
Normal file
|
@ -0,0 +1,130 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
||||
* Jason Liu <r64343@freescale.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
DATA 4 0x020e0774 0x000C0000
|
||||
DATA 4 0x020e0754 0x00000000
|
||||
DATA 4 0x020e04ac 0x00000030
|
||||
DATA 4 0x020e04b0 0x00000030
|
||||
DATA 4 0x020e0464 0x00000030
|
||||
DATA 4 0x020e0490 0x00000030
|
||||
DATA 4 0x020e074c 0x00000030
|
||||
DATA 4 0x020e0494 0x00000030
|
||||
DATA 4 0x020e04a0 0x00000000
|
||||
DATA 4 0x020e04b4 0x00000030
|
||||
DATA 4 0x020e04b8 0x00000030
|
||||
DATA 4 0x020e076c 0x00000030
|
||||
DATA 4 0x020e0750 0x00020000
|
||||
DATA 4 0x020e04bc 0x00000028
|
||||
DATA 4 0x020e04c0 0x00000028
|
||||
DATA 4 0x020e04c4 0x00000028
|
||||
DATA 4 0x020e04c8 0x00000028
|
||||
DATA 4 0x020e04cc 0x00000028
|
||||
DATA 4 0x020e04d0 0x00000028
|
||||
DATA 4 0x020e04d4 0x00000028
|
||||
DATA 4 0x020e04d8 0x00000028
|
||||
DATA 4 0x020e0760 0x00020000
|
||||
DATA 4 0x020e0764 0x00000028
|
||||
DATA 4 0x020e0770 0x00000028
|
||||
DATA 4 0x020e0778 0x00000028
|
||||
DATA 4 0x020e077c 0x00000028
|
||||
DATA 4 0x020e0780 0x00000028
|
||||
DATA 4 0x020e0784 0x00000028
|
||||
DATA 4 0x020e078c 0x00000028
|
||||
DATA 4 0x020e0748 0x00000028
|
||||
DATA 4 0x020e0470 0x00000028
|
||||
DATA 4 0x020e0474 0x00000028
|
||||
DATA 4 0x020e0478 0x00000028
|
||||
DATA 4 0x020e047c 0x00000028
|
||||
DATA 4 0x020e0480 0x00000028
|
||||
DATA 4 0x020e0484 0x00000028
|
||||
DATA 4 0x020e0488 0x00000028
|
||||
DATA 4 0x020e048c 0x00000028
|
||||
DATA 4 0x021b0800 0xa1390003
|
||||
DATA 4 0x021b080c 0x001F001F
|
||||
DATA 4 0x021b0810 0x001F001F
|
||||
DATA 4 0x021b480c 0x001F001F
|
||||
DATA 4 0x021b4810 0x001F001F
|
||||
DATA 4 0x021b083c 0x42190217
|
||||
DATA 4 0x021b0840 0x017B017B
|
||||
DATA 4 0x021b483c 0x4176017B
|
||||
DATA 4 0x021b4840 0x015F016C
|
||||
DATA 4 0x021b0848 0x4C4C4D4C
|
||||
DATA 4 0x021b4848 0x4A4D4C48
|
||||
DATA 4 0x021b0850 0x3F3F3F40
|
||||
DATA 4 0x021b4850 0x3538382E
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
DATA 4 0x021b481c 0x33333333
|
||||
DATA 4 0x021b4820 0x33333333
|
||||
DATA 4 0x021b4824 0x33333333
|
||||
DATA 4 0x021b4828 0x33333333
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
DATA 4 0x021b48b8 0x00000800
|
||||
DATA 4 0x021b0004 0x00020025
|
||||
DATA 4 0x021b0008 0x00333030
|
||||
DATA 4 0x021b000c 0x676B5313
|
||||
DATA 4 0x021b0010 0xB66E8B63
|
||||
DATA 4 0x021b0014 0x01FF00DB
|
||||
DATA 4 0x021b0018 0x00001740
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b002c 0x000026d2
|
||||
DATA 4 0x021b0030 0x006B1023
|
||||
DATA 4 0x021b0040 0x00000047
|
||||
DATA 4 0x021b0000 0x841A0000
|
||||
DATA 4 0x021b001c 0x04008032
|
||||
DATA 4 0x021b001c 0x00008033
|
||||
DATA 4 0x021b001c 0x00048031
|
||||
DATA 4 0x021b001c 0x05208030
|
||||
DATA 4 0x021b001c 0x04008040
|
||||
DATA 4 0x021b0020 0x00005800
|
||||
DATA 4 0x021b0818 0x00011117
|
||||
DATA 4 0x021b4818 0x00011117
|
||||
DATA 4 0x021b0004 0x00025565
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
|
||||
/* set the default clock gate to save power */
|
||||
DATA 4 0x020c4068 0x00C03F3F
|
||||
DATA 4 0x020c406c 0x0030FC03
|
||||
DATA 4 0x020c4070 0x0FFFC000
|
||||
DATA 4 0x020c4074 0x3FF00000
|
||||
DATA 4 0x020c4078 0xFFFFF300
|
||||
DATA 4 0x020c407c 0x0F0000C3
|
||||
DATA 4 0x020c4080 0x00000FFF
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4 0x020e0010 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4 0x020e0018 0x007F007F
|
||||
DATA 4 0x020e001c 0x007F007F
|
|
@ -12,6 +12,7 @@
|
|||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/imx-common/video.h>
|
||||
|
@ -23,6 +24,9 @@
|
|||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze100_pmic.h>
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
|
@ -39,6 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PMIC 1
|
||||
|
||||
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
@ -129,6 +141,19 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
|
|||
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(4, 12)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(4, 13)
|
||||
}
|
||||
};
|
||||
|
||||
static void setup_spi(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
|
||||
|
@ -426,6 +451,64 @@ int board_init(void)
|
|||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spi();
|
||||
#endif
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pfuze_init(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
unsigned int reg;
|
||||
|
||||
ret = power_pfuze100_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
p = pmic_get("PFUZE100_PMIC");
|
||||
ret = pmic_probe(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
|
||||
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
|
||||
|
||||
/* Increase VGEN3 from 2.5 to 2.8V */
|
||||
pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
|
||||
reg &= ~0xf;
|
||||
reg |= 0xa;
|
||||
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
|
||||
|
||||
/* Increase VGEN5 from 2.8 to 3V */
|
||||
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
|
||||
reg &= ~0xf;
|
||||
reg |= 0xc;
|
||||
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
|
||||
|
||||
/* Set SW1AB stanby volage to 0.975V */
|
||||
pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
|
||||
reg &= ~0x3f;
|
||||
reg |= 0x1b;
|
||||
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
|
||||
|
||||
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
|
||||
|
||||
/* Set SW1C standby voltage to 0.975V */
|
||||
pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
|
||||
reg &= ~0x3f;
|
||||
reg |= 0x1b;
|
||||
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
|
||||
|
||||
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
|
||||
pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
|
||||
reg &= ~0xc0;
|
||||
reg |= 0x40;
|
||||
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -446,6 +529,7 @@ int board_late_init(void)
|
|||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
pfuze_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -278,6 +278,26 @@ static void setup_iomux_i2c(void)
|
|||
imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_qspi(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t qspi0_pads[] = {
|
||||
VF610_PAD_PTD0__QSPI0_A_QSCK,
|
||||
VF610_PAD_PTD1__QSPI0_A_CS0,
|
||||
VF610_PAD_PTD2__QSPI0_A_DATA3,
|
||||
VF610_PAD_PTD3__QSPI0_A_DATA2,
|
||||
VF610_PAD_PTD4__QSPI0_A_DATA1,
|
||||
VF610_PAD_PTD5__QSPI0_A_DATA0,
|
||||
VF610_PAD_PTD7__QSPI0_B_QSCK,
|
||||
VF610_PAD_PTD8__QSPI0_B_CS0,
|
||||
VF610_PAD_PTD9__QSPI0_B_DATA3,
|
||||
VF610_PAD_PTD10__QSPI0_B_DATA2,
|
||||
VF610_PAD_PTD11__QSPI0_B_DATA1,
|
||||
VF610_PAD_PTD12__QSPI0_B_DATA0,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg esdhc_cfg[1] = {
|
||||
{ESDHC1_BASE_ADDR},
|
||||
|
@ -321,7 +341,8 @@ static void clock_init(void)
|
|||
clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
|
||||
CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
|
||||
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
|
||||
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
|
||||
CCM_CCGR2_QSPI0_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR3_ANADIG_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
|
||||
|
@ -352,11 +373,14 @@ static void clock_init(void)
|
|||
CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
|
||||
CCM_CACRR_ARM_CLK_DIV(0));
|
||||
clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCMR1_ESDHC1_CLK_SEL(3));
|
||||
CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
|
||||
clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR1_RMII_CLK_EN);
|
||||
clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
|
||||
clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
|
||||
CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
|
||||
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCMR2_RMII_CLK_SEL(0));
|
||||
}
|
||||
|
@ -386,6 +410,7 @@ int board_early_init_f(void)
|
|||
setup_iomux_uart();
|
||||
setup_iomux_enet();
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_qspi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -6,5 +6,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := gw_ventana.o gsc.o
|
||||
obj-y := gw_ventana.o gsc.o eeprom.o
|
||||
obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
|
||||
|
||||
|
|
|
@ -3,53 +3,81 @@ U-Boot for the Gateworks Ventana Product Family boards
|
|||
This file contains information for the port of U-Boot to the Gateworks
|
||||
Ventana Product family boards.
|
||||
|
||||
1. Boot source, boot from NAND
|
||||
1. Secondary Program Loader (SPL)
|
||||
---------------------------------
|
||||
|
||||
The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
|
||||
an executable image from various boot devices.
|
||||
|
||||
The Gateworks Ventana board config uses an SPL build configuration. This
|
||||
will build the following artifacts from u-boot source:
|
||||
- SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
|
||||
Loader) boots. This detects CPU/DRAM configuration, configures
|
||||
The DRAM controller, loads u-boot.img from the detected boot device,
|
||||
and jumps to it. As this is booted from the PPL, it has an IVT/DCD
|
||||
table.
|
||||
- u-boot.img - The main u-boot core which is u-boot.bin with a image header.
|
||||
|
||||
|
||||
2. Build
|
||||
--------
|
||||
|
||||
To build U-Boot for the Gateworks Ventana product family:
|
||||
|
||||
make gwventana_config
|
||||
make
|
||||
|
||||
|
||||
3. Boot source, boot from NAND
|
||||
------------------------------
|
||||
|
||||
The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
|
||||
and bad block information (referred to as 'bootstreams') which are replicated
|
||||
multiple times in NAND. The number of replications is configurable through
|
||||
board strapping options and eFUSE settings. The Freescale 'kobs-ng'
|
||||
application from the Freescale LTIB BSP, which runs under Linux, must be used
|
||||
to program the bootstream in order to setup the replicated headers correctly.
|
||||
multiple times in NAND. The number of replications and their spacing (referred
|
||||
to as search stride) is configurable through board strapping options and/or
|
||||
eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In
|
||||
addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
|
||||
copies of a bootloader in flash in the case that a bad block has corrupted one.
|
||||
The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs
|
||||
under Linux and operates on an MTD partition, must be used to program the
|
||||
bootstream in order to setup this flash structure correctly.
|
||||
|
||||
The Gateworks Ventana boards with NAND flash have been factory programmed
|
||||
such that their eFUSE settings expect 2 copies of the boostream (this is
|
||||
specified by providing kobs-ng with the --search_exponent=1 argument). Once in
|
||||
Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream
|
||||
Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL
|
||||
with:
|
||||
|
||||
kobs-ng init -v -x --search_exponent=1 u-boot.imx
|
||||
kobs-ng init -v -x --search_exponent=1 SPL
|
||||
|
||||
The kobs-ng application uses an imximage (u-boot.imx) which contains the
|
||||
Image Vector Table (IVT) and Device Configuration Data (DCD) structures that
|
||||
the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware
|
||||
Configuration Block (FCB) and Discovered Bad Block Table (DBBT).
|
||||
The kobs-ng application uses an imximage which contains the Image Vector Table
|
||||
(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
|
||||
requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and
|
||||
Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is
|
||||
an imximage.
|
||||
|
||||
The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image
|
||||
header must be programmed in the NAND flash boot device at an offset hard
|
||||
coded in the SPL. For the Ventana boards, this has been chosen to be 14MB.
|
||||
The image can be programmed from either u-boot or Linux:
|
||||
|
||||
u-boot:
|
||||
Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)
|
||||
Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \
|
||||
nand write ${loadaddr} uboot ${filesize}
|
||||
|
||||
Linux:
|
||||
nandwrite /dev/mtd1 u-boot.img
|
||||
|
||||
The above assumes the default Ventana partitioning scheme which is configured
|
||||
via the mtdparts env var:
|
||||
- spl: 14MB
|
||||
- uboot: 2M
|
||||
- env: 1M
|
||||
- rootfs: the rest
|
||||
|
||||
This information is taken from:
|
||||
http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
|
||||
|
||||
More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
|
||||
|
||||
2. Build
|
||||
--------
|
||||
|
||||
There are several Gateworks Ventana boards that share a simliar design but
|
||||
vary based on CPU, Memory configuration, and subloaded devices. Although
|
||||
the subloaded devices are handled dynamically in the bootloader using
|
||||
factory configured EEPROM data to modify the device-tree, the CPU choice
|
||||
(IMX6Q vs IMX6DL) and memory configurations are currently compile-time
|
||||
options.
|
||||
|
||||
The following Gateworks Ventana configurations exist:
|
||||
gwventanaq1gspi: MX6Q,1GB,SPI FLASH
|
||||
gwventanaq : MX6Q,512MB,NAND FLASH
|
||||
gwventanaq1g : MX6Q,1GB,NAND FLASH
|
||||
gwventanadl : MX6DL,512MB,NAND FLASH
|
||||
gwventanadl1g : MX6DL,1GB,NAND FLASH
|
||||
|
||||
To build U-Boot for the MX6Q,1GB,NAND FLASH for example:
|
||||
|
||||
make gwventanaq1g_config
|
||||
make
|
||||
|
||||
|
|
89
board/gateworks/gw_ventana/eeprom.c
Normal file
89
board/gateworks/gw_ventana/eeprom.c
Normal file
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation
|
||||
* Author: Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#include "gsc.h"
|
||||
#include "ventana_eeprom.h"
|
||||
|
||||
/* read ventana EEPROM, check for validity, and return baseboard type */
|
||||
int
|
||||
read_eeprom(int bus, struct ventana_board_info *info)
|
||||
{
|
||||
int i;
|
||||
int chksum;
|
||||
char baseboard;
|
||||
int type;
|
||||
unsigned char *buf = (unsigned char *)info;
|
||||
|
||||
memset(info, 0, sizeof(*info));
|
||||
|
||||
/*
|
||||
* On a board with a missing/depleted backup battery for GSC, the
|
||||
* board may be ready to probe the GSC before its firmware is
|
||||
* running. We will wait here indefinately for the GSC/EEPROM.
|
||||
*/
|
||||
while (1) {
|
||||
if (0 == i2c_set_bus_num(bus) &&
|
||||
0 == i2c_probe(GSC_EEPROM_ADDR))
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
/* read eeprom config section */
|
||||
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
|
||||
puts("EEPROM: Failed to read EEPROM\n");
|
||||
info->model[0] = 0;
|
||||
return GW_UNKNOWN;
|
||||
}
|
||||
|
||||
/* sanity checks */
|
||||
if (info->model[0] != 'G' || info->model[1] != 'W') {
|
||||
puts("EEPROM: Invalid Model in EEPROM\n");
|
||||
info->model[0] = 0;
|
||||
return GW_UNKNOWN;
|
||||
}
|
||||
|
||||
/* validate checksum */
|
||||
for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
|
||||
chksum += buf[i];
|
||||
if ((info->chksum[0] != chksum>>8) ||
|
||||
(info->chksum[1] != (chksum&0xff))) {
|
||||
puts("EEPROM: Failed EEPROM checksum\n");
|
||||
info->model[0] = 0;
|
||||
return GW_UNKNOWN;
|
||||
}
|
||||
|
||||
/* original GW5400-A prototype */
|
||||
baseboard = info->model[3];
|
||||
if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
|
||||
baseboard = '0';
|
||||
|
||||
switch (baseboard) {
|
||||
case '0': /* original GW5400-A prototype */
|
||||
type = GW54proto;
|
||||
break;
|
||||
case '1':
|
||||
type = GW51xx;
|
||||
break;
|
||||
case '2':
|
||||
type = GW52xx;
|
||||
break;
|
||||
case '3':
|
||||
type = GW53xx;
|
||||
break;
|
||||
case '4':
|
||||
type = GW54xx;
|
||||
break;
|
||||
default:
|
||||
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
|
||||
type = GW_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
return type;
|
||||
}
|
|
@ -84,122 +84,153 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
*/
|
||||
static struct ventana_board_info ventana_info;
|
||||
|
||||
enum {
|
||||
GW54proto, /* original GW5400-A prototype */
|
||||
GW51xx,
|
||||
GW52xx,
|
||||
GW53xx,
|
||||
GW54xx,
|
||||
GW_UNKNOWN,
|
||||
};
|
||||
|
||||
int board_type;
|
||||
|
||||
/* UART1: Function varies per baseboard */
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||
};
|
||||
|
||||
/* UART2: Serial Console */
|
||||
iomux_v3_cfg_t const uart2_pads[] = {
|
||||
MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
||||
};
|
||||
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
|
||||
/* I2C1: GSC */
|
||||
struct i2c_pads_info i2c_pad_info0 = {
|
||||
struct i2c_pads_info mx6q_i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
|
||||
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 21)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
|
||||
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 28)
|
||||
}
|
||||
};
|
||||
struct i2c_pads_info mx6dl_i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 21)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 28)
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
struct i2c_pads_info mx6q_i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
|
||||
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 12)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
|
||||
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 13)
|
||||
}
|
||||
};
|
||||
struct i2c_pads_info mx6dl_i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 12)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 13)
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C3: Misc/Expansion */
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
struct i2c_pads_info mx6q_i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
|
||||
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
|
||||
.i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 6)
|
||||
}
|
||||
};
|
||||
struct i2c_pads_info mx6dl_i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 6)
|
||||
}
|
||||
};
|
||||
|
||||
/* MMC */
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
||||
/* CD */
|
||||
IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
/* ENET */
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
|
||||
MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
|
||||
MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
|
||||
MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
||||
/* PHY nRST */
|
||||
MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
/* NAND */
|
||||
iomux_v3_cfg_t const nfc_pads[] = {
|
||||
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
|
@ -208,7 +239,7 @@ static void setup_gpmi_nand(void)
|
|||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
|
||||
SETUP_IOMUX_PADS(nfc_pads);
|
||||
|
||||
/* config gpmi and bch clock to 100 MHz */
|
||||
clrsetbits_le32(&mxc_ccm->cs2cdr,
|
||||
|
@ -234,7 +265,7 @@ static void setup_gpmi_nand(void)
|
|||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
|
||||
SETUP_IOMUX_PADS(enet_pads);
|
||||
|
||||
/* toggle PHY_RST# */
|
||||
gpio_direction_output(GP_PHY_RST, 0);
|
||||
|
@ -244,35 +275,36 @@ static void setup_iomux_enet(void)
|
|||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||
SETUP_IOMUX_PADS(uart1_pads);
|
||||
SETUP_IOMUX_PADS(uart2_pads);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
iomux_v3_cfg_t const usb_pads[] = {
|
||||
MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
|
||||
MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
|
||||
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
|
||||
/* OTG PWR */
|
||||
IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
struct ventana_board_info *info = &ventana_info;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
|
||||
SETUP_IOMUX_PADS(usb_pads);
|
||||
|
||||
/* Reset USB HUB (present on GW54xx/GW53xx) */
|
||||
switch (info->model[3]) {
|
||||
case '3': /* GW53xx */
|
||||
imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
|
||||
MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
|
||||
MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
|
||||
mdelay(2);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 9), 1);
|
||||
break;
|
||||
case '4': /* GW54xx */
|
||||
imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
|
||||
MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
|
||||
MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
|
||||
mdelay(2);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 16), 1);
|
||||
|
@ -304,7 +336,7 @@ int board_mmc_getcd(struct mmc *mmc)
|
|||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
/* Only one USDHC controller on Ventana */
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
SETUP_IOMUX_PADS(usdhc3_pads);
|
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
usdhc_cfg.max_bus_width = 4;
|
||||
|
||||
|
@ -315,17 +347,16 @@ int board_mmc_init(bd_t *bis)
|
|||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
/* SS1 */
|
||||
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||
IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static void setup_spi(void)
|
||||
{
|
||||
gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
|
||||
ARRAY_SIZE(ecspi1_pads));
|
||||
SETUP_IOMUX_PADS(ecspi1_pads);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -395,8 +426,7 @@ static void enable_lvds(struct display_info_t const *dev)
|
|||
writel(reg, &iomux->gpr[2]);
|
||||
|
||||
/* Enable Backlight */
|
||||
imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
|
||||
MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
|
||||
}
|
||||
|
||||
|
@ -493,90 +523,11 @@ static void setup_display(void)
|
|||
writel(reg, &iomux->gpr[3]);
|
||||
|
||||
/* Backlight CABEN on LVDS connector */
|
||||
imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
|
||||
MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
|
||||
}
|
||||
#endif /* CONFIG_VIDEO_IPUV3 */
|
||||
|
||||
/* read ventana EEPROM, check for validity, and return baseboard type */
|
||||
static int
|
||||
read_eeprom(void)
|
||||
{
|
||||
int i;
|
||||
int chksum;
|
||||
char baseboard;
|
||||
int type;
|
||||
struct ventana_board_info *info = &ventana_info;
|
||||
unsigned char *buf = (unsigned char *)&ventana_info;
|
||||
|
||||
memset(info, 0, sizeof(ventana_info));
|
||||
|
||||
/*
|
||||
* On a board with a missing/depleted backup battery for GSC, the
|
||||
* board may be ready to probe the GSC before its firmware is
|
||||
* running. We will wait here indefinately for the GSC/EEPROM.
|
||||
*/
|
||||
while (1) {
|
||||
if (0 == i2c_set_bus_num(I2C_GSC) &&
|
||||
0 == i2c_probe(GSC_EEPROM_ADDR))
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
/* read eeprom config section */
|
||||
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
|
||||
puts("EEPROM: Failed to read EEPROM\n");
|
||||
info->model[0] = 0;
|
||||
return GW_UNKNOWN;
|
||||
}
|
||||
|
||||
/* sanity checks */
|
||||
if (info->model[0] != 'G' || info->model[1] != 'W') {
|
||||
puts("EEPROM: Invalid Model in EEPROM\n");
|
||||
info->model[0] = 0;
|
||||
return GW_UNKNOWN;
|
||||
}
|
||||
|
||||
/* validate checksum */
|
||||
for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
|
||||
chksum += buf[i];
|
||||
if ((info->chksum[0] != chksum>>8) ||
|
||||
(info->chksum[1] != (chksum&0xff))) {
|
||||
puts("EEPROM: Failed EEPROM checksum\n");
|
||||
info->model[0] = 0;
|
||||
return GW_UNKNOWN;
|
||||
}
|
||||
|
||||
/* original GW5400-A prototype */
|
||||
baseboard = info->model[3];
|
||||
if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
|
||||
baseboard = '0';
|
||||
|
||||
switch (baseboard) {
|
||||
case '0': /* original GW5400-A prototype */
|
||||
type = GW54proto;
|
||||
break;
|
||||
case '1':
|
||||
type = GW51xx;
|
||||
break;
|
||||
case '2':
|
||||
type = GW52xx;
|
||||
break;
|
||||
case '3':
|
||||
type = GW53xx;
|
||||
break;
|
||||
case '4':
|
||||
type = GW54xx;
|
||||
break;
|
||||
default:
|
||||
printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
|
||||
type = GW_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
return type;
|
||||
}
|
||||
|
||||
/*
|
||||
* Baseboard specific GPIO
|
||||
*/
|
||||
|
@ -584,118 +535,118 @@ read_eeprom(void)
|
|||
/* common to add baseboards */
|
||||
static iomux_v3_cfg_t const gw_gpio_pads[] = {
|
||||
/* MSATA_EN */
|
||||
MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* RS232_EN# */
|
||||
MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
/* prototype */
|
||||
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
|
||||
/* PANLEDG# */
|
||||
MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PANLEDR# */
|
||||
MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* LOCLED# */
|
||||
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* RS485_EN */
|
||||
MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_PWREN# */
|
||||
MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_IRQ# */
|
||||
MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* VID_EN */
|
||||
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* DIOI2C_DIS# */
|
||||
MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCICK_SSON */
|
||||
MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCI_RST# */
|
||||
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
|
||||
/* PANLEDG# */
|
||||
MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PANLEDR# */
|
||||
MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_PWREN# */
|
||||
MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_IRQ# */
|
||||
MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
|
||||
/* GPS_SHDN */
|
||||
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* VID_PWR */
|
||||
MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCI_RST# */
|
||||
MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
|
||||
/* PANLEDG# */
|
||||
MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PANLEDR# */
|
||||
MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_PWREN# */
|
||||
MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_IRQ# */
|
||||
MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
|
||||
/* MX6_LOCLED# */
|
||||
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* GPS_SHDN */
|
||||
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* USBOTG_SEL */
|
||||
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* VID_PWR */
|
||||
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCI_RST# */
|
||||
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
|
||||
/* PANLEDG# */
|
||||
MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PANLEDR# */
|
||||
MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_PWREN# */
|
||||
MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_IRQ# */
|
||||
MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
|
||||
/* MX6_LOCLED# */
|
||||
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* GPS_SHDN */
|
||||
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* VID_EN */
|
||||
MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCI_RST# */
|
||||
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
|
||||
/* PANLEDG# */
|
||||
MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PANLEDR# */
|
||||
MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* MX6_LOCLED# */
|
||||
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* MIPI_DIO */
|
||||
MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* RS485_EN */
|
||||
MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_PWREN# */
|
||||
MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* IOEXP_IRQ# */
|
||||
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* DIOI2C_DIS# */
|
||||
MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* DIOI2C_DIS# */
|
||||
MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCICK_SSON */
|
||||
MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
/* PCI_RST# */
|
||||
MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -703,9 +654,9 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
|
|||
* be pinmuxed as a GPIO or in some cases a PWM
|
||||
*/
|
||||
struct dio_cfg {
|
||||
iomux_v3_cfg_t gpio_padmux;
|
||||
iomux_v3_cfg_t gpio_padmux[2];
|
||||
unsigned gpio_param;
|
||||
iomux_v3_cfg_t pwm_padmux;
|
||||
iomux_v3_cfg_t pwm_padmux[2];
|
||||
unsigned pwm_param;
|
||||
};
|
||||
|
||||
|
@ -732,16 +683,32 @@ struct ventana gpio_cfg[] = {
|
|||
/* GW5400proto */
|
||||
{
|
||||
.gpio_pads = gw54xx_gpio_pads,
|
||||
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
|
||||
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
|
||||
.dio_cfg = {
|
||||
{ MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
|
||||
MX6_PAD_GPIO_9__PWM1_OUT, 1 },
|
||||
{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
|
||||
MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
|
||||
{ MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
|
||||
MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
|
||||
{ MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
|
||||
MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
|
||||
{
|
||||
{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
|
||||
IMX_GPIO_NR(1, 9),
|
||||
{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
|
||||
1
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
||||
IMX_GPIO_NR(1, 19),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
||||
2
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
|
||||
IMX_GPIO_NR(2, 9),
|
||||
{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
|
||||
3
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
|
||||
IMX_GPIO_NR(2, 10),
|
||||
{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
|
||||
4
|
||||
},
|
||||
},
|
||||
.leds = {
|
||||
IMX_GPIO_NR(4, 6),
|
||||
|
@ -759,16 +726,32 @@ struct ventana gpio_cfg[] = {
|
|||
/* GW51xx */
|
||||
{
|
||||
.gpio_pads = gw51xx_gpio_pads,
|
||||
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
|
||||
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
|
||||
.dio_cfg = {
|
||||
{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
|
||||
0, 0 },
|
||||
{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
|
||||
MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
|
||||
{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
|
||||
MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
|
||||
{ MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
|
||||
MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
||||
IMX_GPIO_NR(1, 16),
|
||||
{ 0, 0 },
|
||||
0
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
||||
IMX_GPIO_NR(1, 19),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
||||
2
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
||||
IMX_GPIO_NR(1, 17),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
||||
3
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
|
||||
IMX_GPIO_NR(1, 18),
|
||||
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
|
||||
4
|
||||
},
|
||||
},
|
||||
.leds = {
|
||||
IMX_GPIO_NR(4, 6),
|
||||
|
@ -784,16 +767,32 @@ struct ventana gpio_cfg[] = {
|
|||
/* GW52xx */
|
||||
{
|
||||
.gpio_pads = gw52xx_gpio_pads,
|
||||
.num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
|
||||
.num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
|
||||
.dio_cfg = {
|
||||
{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
|
||||
0, 0 },
|
||||
{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
|
||||
MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
|
||||
{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
|
||||
MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
|
||||
{ MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
|
||||
0, 0 },
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
||||
IMX_GPIO_NR(1, 16),
|
||||
{ 0, 0 },
|
||||
0
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
||||
IMX_GPIO_NR(1, 19),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
||||
2
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
||||
IMX_GPIO_NR(1, 17),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
||||
3
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
||||
IMX_GPIO_NR(1, 20),
|
||||
{ 0, 0 },
|
||||
0
|
||||
},
|
||||
},
|
||||
.leds = {
|
||||
IMX_GPIO_NR(4, 6),
|
||||
|
@ -811,16 +810,32 @@ struct ventana gpio_cfg[] = {
|
|||
/* GW53xx */
|
||||
{
|
||||
.gpio_pads = gw53xx_gpio_pads,
|
||||
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
|
||||
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
|
||||
.dio_cfg = {
|
||||
{ MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
|
||||
0, 0 },
|
||||
{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
|
||||
MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
|
||||
{ MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
|
||||
MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
|
||||
{ MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
|
||||
0, 0 },
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
|
||||
IMX_GPIO_NR(1, 16),
|
||||
{ 0, 0 },
|
||||
0
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
||||
IMX_GPIO_NR(1, 19),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
||||
2
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
|
||||
IMX_GPIO_NR(1, 17),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
|
||||
3
|
||||
},
|
||||
{
|
||||
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
|
||||
IMX_GPIO_NR(1, 20),
|
||||
{ 0, 0 },
|
||||
0
|
||||
},
|
||||
},
|
||||
.leds = {
|
||||
IMX_GPIO_NR(4, 6),
|
||||
|
@ -837,16 +852,32 @@ struct ventana gpio_cfg[] = {
|
|||
/* GW54xx */
|
||||
{
|
||||
.gpio_pads = gw54xx_gpio_pads,
|
||||
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
|
||||
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
|
||||
.dio_cfg = {
|
||||
{ MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
|
||||
MX6_PAD_GPIO_9__PWM1_OUT, 1 },
|
||||
{ MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
|
||||
MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
|
||||
{ MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
|
||||
MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
|
||||
{ MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
|
||||
MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
|
||||
{
|
||||
{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
|
||||
IMX_GPIO_NR(1, 9),
|
||||
{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
|
||||
1
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
|
||||
IMX_GPIO_NR(1, 19),
|
||||
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
|
||||
2
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
|
||||
IMX_GPIO_NR(2, 9),
|
||||
{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
|
||||
3
|
||||
},
|
||||
{
|
||||
{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
|
||||
IMX_GPIO_NR(2, 10),
|
||||
{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
|
||||
4
|
||||
},
|
||||
},
|
||||
.leds = {
|
||||
IMX_GPIO_NR(4, 6),
|
||||
|
@ -992,6 +1023,7 @@ static void setup_board_gpio(int board)
|
|||
for (i = 0; i < 4; i++) {
|
||||
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
|
||||
unsigned ctrl = DIO_PAD_CTRL;
|
||||
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
|
||||
|
||||
sprintf(arg, "dio%d", i);
|
||||
if (!hwconfig(arg))
|
||||
|
@ -1006,14 +1038,14 @@ static void setup_board_gpio(int board)
|
|||
cfg->gpio_param%32,
|
||||
cfg->gpio_param);
|
||||
}
|
||||
imx_iomux_v3_setup_pad(cfg->gpio_padmux |
|
||||
imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
|
||||
MUX_PAD_CTRL(ctrl));
|
||||
gpio_direction_input(cfg->gpio_param);
|
||||
} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
|
||||
cfg->pwm_padmux) {
|
||||
if (!quiet)
|
||||
printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
|
||||
imx_iomux_v3_setup_pad(cfg->pwm_padmux |
|
||||
imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
|
||||
MUX_PAD_CTRL(ctrl));
|
||||
}
|
||||
}
|
||||
|
@ -1033,9 +1065,10 @@ static void setup_board_gpio(int board)
|
|||
int imx6_pcie_toggle_reset(void)
|
||||
{
|
||||
if (board_type < GW_UNKNOWN) {
|
||||
gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
|
||||
uint pin = gpio_cfg[board_type].pcie_rst;
|
||||
gpio_direction_output(pin, 0);
|
||||
mdelay(50);
|
||||
gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
|
||||
gpio_direction_output(pin, 1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
@ -1069,6 +1102,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
|
|||
* Board Support
|
||||
*/
|
||||
|
||||
/* called from SPL board_init_f() */
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
@ -1082,9 +1116,7 @@ int board_early_init_f(void)
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
|
||||
CONFIG_DDR_MB*1024*1024);
|
||||
|
||||
gd->ram_size = imx_ddr_size();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -1106,22 +1138,29 @@ int board_init(void)
|
|||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spi();
|
||||
#endif
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
if (is_cpu_type(MXC_CPU_MX6Q)) {
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
|
||||
} else {
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
setup_sata();
|
||||
#endif
|
||||
/* read Gateworks EEPROM into global struct (used later) */
|
||||
board_type = read_eeprom();
|
||||
board_type = read_eeprom(I2C_GSC, &ventana_info);
|
||||
|
||||
/* board-specifc GPIO iomux */
|
||||
SETUP_IOMUX_PADS(gw_gpio_pads);
|
||||
if (board_type < GW_UNKNOWN) {
|
||||
imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
|
||||
ARRAY_SIZE(gw_gpio_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
|
||||
gpio_cfg[board_type].num_pads);
|
||||
iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
|
||||
int count = gpio_cfg[board_type].num_pads;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(p, count);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -1219,9 +1258,11 @@ int misc_init_r(void)
|
|||
* env scripts will try loading each from most specific to
|
||||
* least.
|
||||
*/
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
if (is_cpu_type(MXC_CPU_MX6Q) ||
|
||||
is_cpu_type(MXC_CPU_MX6D))
|
||||
cputype = "imx6q";
|
||||
else if (is_cpu_type(MXC_CPU_MX6DL))
|
||||
else if (is_cpu_type(MXC_CPU_MX6DL) ||
|
||||
is_cpu_type(MXC_CPU_MX6SOLO))
|
||||
cputype = "imx6dl";
|
||||
memset(str, 0, sizeof(str));
|
||||
for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
|
||||
|
|
|
@ -24,21 +24,6 @@ BOOT_FROM nand
|
|||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
/* Memory configuration (size is overridden via eeprom config) */
|
||||
#include "../../boundary/nitrogen6x/ddr-setup.cfg"
|
||||
#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024
|
||||
#include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"
|
||||
#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024
|
||||
#include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"
|
||||
#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512
|
||||
#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
|
||||
#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512
|
||||
#include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
|
||||
#else
|
||||
#error "Unsupported CPU/Memory configuration"
|
||||
#endif
|
||||
#include "clocks.cfg"
|
||||
|
|
419
board/gateworks/gw_ventana/gw_ventana_spl.c
Normal file
419
board/gateworks/gw_ventana/gw_ventana_spl.c
Normal file
|
@ -0,0 +1,419 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Gateworks Corporation
|
||||
* Author: Tim Harvey <tharvey@gateworks.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <spl.h>
|
||||
|
||||
#include "ventana_eeprom.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
|
||||
#define I2C_GSC 0
|
||||
#define GSC_EEPROM_ADDR 0x51
|
||||
#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
|
||||
#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* I2C1: GSC */
|
||||
static struct i2c_pads_info mx6q_i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 21)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 28)
|
||||
}
|
||||
};
|
||||
static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 21)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 28)
|
||||
}
|
||||
};
|
||||
|
||||
static void i2c_setup_iomux(void)
|
||||
{
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
|
||||
else
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
|
||||
}
|
||||
|
||||
/* configure MX6Q/DUAL mmdc DDR io registers */
|
||||
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
|
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
|
||||
.dram_sdclk_0 = 0x00020030,
|
||||
.dram_sdclk_1 = 0x00020030,
|
||||
.dram_cas = 0x00020030,
|
||||
.dram_ras = 0x00020030,
|
||||
.dram_reset = 0x00020030,
|
||||
/* SDCKE[0:1]: 100k pull-up */
|
||||
.dram_sdcke0 = 0x00003000,
|
||||
.dram_sdcke1 = 0x00003000,
|
||||
/* SDBA2: pull-up disabled */
|
||||
.dram_sdba2 = 0x00000000,
|
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */
|
||||
.dram_sdodt0 = 0x00003030,
|
||||
.dram_sdodt1 = 0x00003030,
|
||||
/* SDQS[0:7]: Differential input, 40 ohm */
|
||||
.dram_sdqs0 = 0x00000030,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_sdqs2 = 0x00000030,
|
||||
.dram_sdqs3 = 0x00000030,
|
||||
.dram_sdqs4 = 0x00000030,
|
||||
.dram_sdqs5 = 0x00000030,
|
||||
.dram_sdqs6 = 0x00000030,
|
||||
.dram_sdqs7 = 0x00000030,
|
||||
|
||||
/* DQM[0:7]: Differential input, 40 ohm */
|
||||
.dram_dqm0 = 0x00020030,
|
||||
.dram_dqm1 = 0x00020030,
|
||||
.dram_dqm2 = 0x00020030,
|
||||
.dram_dqm3 = 0x00020030,
|
||||
.dram_dqm4 = 0x00020030,
|
||||
.dram_dqm5 = 0x00020030,
|
||||
.dram_dqm6 = 0x00020030,
|
||||
.dram_dqm7 = 0x00020030,
|
||||
};
|
||||
|
||||
/* configure MX6Q/DUAL mmdc GRP io registers */
|
||||
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
|
||||
/* DDR3 */
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
/* disable DDR pullups */
|
||||
.grp_ddrpke = 0x00000000,
|
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
|
||||
.grp_addds = 0x00000030,
|
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
|
||||
.grp_ctlds = 0x00000030,
|
||||
/* DATA[00:63]: Differential input, 40 ohm */
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_b2ds = 0x00000030,
|
||||
.grp_b3ds = 0x00000030,
|
||||
.grp_b4ds = 0x00000030,
|
||||
.grp_b5ds = 0x00000030,
|
||||
.grp_b6ds = 0x00000030,
|
||||
.grp_b7ds = 0x00000030,
|
||||
};
|
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
|
||||
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
|
||||
/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
|
||||
.dram_sdclk_0 = 0x00020030,
|
||||
.dram_sdclk_1 = 0x00020030,
|
||||
.dram_cas = 0x00020030,
|
||||
.dram_ras = 0x00020030,
|
||||
.dram_reset = 0x00020030,
|
||||
/* SDCKE[0:1]: 100k pull-up */
|
||||
.dram_sdcke0 = 0x00003000,
|
||||
.dram_sdcke1 = 0x00003000,
|
||||
/* SDBA2: pull-up disabled */
|
||||
.dram_sdba2 = 0x00000000,
|
||||
/* SDODT[0:1]: 100k pull-up, 40 ohm */
|
||||
.dram_sdodt0 = 0x00003030,
|
||||
.dram_sdodt1 = 0x00003030,
|
||||
/* SDQS[0:7]: Differential input, 40 ohm */
|
||||
.dram_sdqs0 = 0x00000030,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_sdqs2 = 0x00000030,
|
||||
.dram_sdqs3 = 0x00000030,
|
||||
.dram_sdqs4 = 0x00000030,
|
||||
.dram_sdqs5 = 0x00000030,
|
||||
.dram_sdqs6 = 0x00000030,
|
||||
.dram_sdqs7 = 0x00000030,
|
||||
|
||||
/* DQM[0:7]: Differential input, 40 ohm */
|
||||
.dram_dqm0 = 0x00020030,
|
||||
.dram_dqm1 = 0x00020030,
|
||||
.dram_dqm2 = 0x00020030,
|
||||
.dram_dqm3 = 0x00020030,
|
||||
.dram_dqm4 = 0x00020030,
|
||||
.dram_dqm5 = 0x00020030,
|
||||
.dram_dqm6 = 0x00020030,
|
||||
.dram_dqm7 = 0x00020030,
|
||||
};
|
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
|
||||
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
|
||||
/* DDR3 */
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
/* SDQS[0:7]: Differential input, 40 ohm */
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
/* disable DDR pullups */
|
||||
.grp_ddrpke = 0x00000000,
|
||||
/* ADDR[00:16], SDBA[0:1]: 40 ohm */
|
||||
.grp_addds = 0x00000030,
|
||||
/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
|
||||
.grp_ctlds = 0x00000030,
|
||||
/* DATA[00:63]: Differential input, 40 ohm */
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_b2ds = 0x00000030,
|
||||
.grp_b3ds = 0x00000030,
|
||||
.grp_b4ds = 0x00000030,
|
||||
.grp_b5ds = 0x00000030,
|
||||
.grp_b6ds = 0x00000030,
|
||||
.grp_b7ds = 0x00000030,
|
||||
};
|
||||
|
||||
/* MT41K128M16JT-125 */
|
||||
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
|
||||
.mem_speed = 1600,
|
||||
.density = 2,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
.rowaddr = 14,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1375,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
/* GW54xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x00190018,
|
||||
.p0_mpwldectrl1 = 0x0021001D,
|
||||
.p1_mpwldectrl0 = 0x00160027,
|
||||
.p1_mpwldectrl1 = 0x0012001E,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x43370346,
|
||||
.p0_mpdgctrl1 = 0x032A0321,
|
||||
.p1_mpdgctrl0 = 0x433A034D,
|
||||
.p1_mpdgctrl1 = 0x032F0235,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x3C313539,
|
||||
.p1_mprddlctl = 0x37333140,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x37393C38,
|
||||
.p1_mpwrdlctl = 0x42334538,
|
||||
};
|
||||
|
||||
/* GW53xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x00160013,
|
||||
.p0_mpwldectrl1 = 0x00090024,
|
||||
.p1_mpwldectrl0 = 0x001F0018,
|
||||
.p1_mpwldectrl1 = 0x000C001C,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x433A034C,
|
||||
.p0_mpdgctrl1 = 0x0336032F,
|
||||
.p1_mpdgctrl0 = 0x4343034A,
|
||||
.p1_mpdgctrl1 = 0x03370222,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x3F343638,
|
||||
.p1_mprddlctl = 0x38373442,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x343A3E39,
|
||||
.p1_mpwrdlctl = 0x44344239,
|
||||
};
|
||||
static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x003C003C,
|
||||
.p0_mpwldectrl1 = 0x00330038,
|
||||
.p1_mpwldectrl0 = 0x001F002A,
|
||||
.p1_mpwldectrl1 = 0x0022003F,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x42410244,
|
||||
.p0_mpdgctrl1 = 0x022D022D,
|
||||
.p1_mpdgctrl0 = 0x4234023A,
|
||||
.p1_mpdgctrl1 = 0x021C0228,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x484A4C4B,
|
||||
.p1_mprddlctl = 0x4B4D4E4B,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x33342B32,
|
||||
.p1_mpwrdlctl = 0x3933332B,
|
||||
};
|
||||
|
||||
/* GW52xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x0040003F,
|
||||
.p0_mpwldectrl1 = 0x00370037,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x42420244,
|
||||
.p0_mpdgctrl1 = 0x022F022F,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x49464B4A,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x32362C32,
|
||||
};
|
||||
|
||||
/* GW51xx specific calibration */
|
||||
static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x00150016,
|
||||
.p0_mpwldectrl1 = 0x001F0017,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x433D034D,
|
||||
.p0_mpdgctrl1 = 0x033D032F,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x3F313639,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x33393F36,
|
||||
};
|
||||
|
||||
static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
|
||||
/* write leveling calibration determine */
|
||||
.p0_mpwldectrl0 = 0x003D003F,
|
||||
.p0_mpwldectrl1 = 0x002F0038,
|
||||
/* Read DQS Gating calibration */
|
||||
.p0_mpdgctrl0 = 0x423A023A,
|
||||
.p0_mpdgctrl1 = 0x022A0228,
|
||||
/* Read Calibration: DQS delay relative to DQ read access */
|
||||
.p0_mprddlctl = 0x48494C4C,
|
||||
/* Write Calibration: DQ/DM delay relative to DQS write access */
|
||||
.p0_mpwrdlctl = 0x34352D31,
|
||||
};
|
||||
|
||||
static void spl_dram_init(int width, int size, int board_model)
|
||||
{
|
||||
struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
|
||||
struct mx6_mmdc_calibration *calib;
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
/* width of data bus:0=16,1=32,2=64 */
|
||||
.dsize = width/32,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32, /* 32Gb per CS */
|
||||
/* single chip select */
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|
||||
#ifdef RTT_NOM_120OHM
|
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
|
||||
#else
|
||||
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
|
||||
#endif
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
};
|
||||
|
||||
/*
|
||||
* MMDC Calibration requires the following data:
|
||||
* mx6_mmdc_calibration - board-specific calibration (routing delays)
|
||||
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
|
||||
* mx6_ddr_cfg - chip specific timing/layout details
|
||||
*/
|
||||
switch (board_model) {
|
||||
default:
|
||||
case GW51xx:
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
calib = &gw51xxq_mmdc_calib;
|
||||
else
|
||||
calib = &gw51xxdl_mmdc_calib;
|
||||
break;
|
||||
case GW52xx:
|
||||
calib = &gw52xxdl_mmdc_calib;
|
||||
break;
|
||||
case GW53xx:
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
calib = &gw53xxq_mmdc_calib;
|
||||
else
|
||||
calib = &gw53xxdl_mmdc_calib;
|
||||
break;
|
||||
case GW54xx:
|
||||
calib = &gw54xxq_mmdc_calib;
|
||||
break;
|
||||
}
|
||||
|
||||
if (is_cpu_type(MXC_CPU_MX6Q))
|
||||
mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
|
||||
&mx6dq_grp_ioregs);
|
||||
else
|
||||
mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
|
||||
&mx6sdl_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, calib, mem);
|
||||
}
|
||||
|
||||
/*
|
||||
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
|
||||
* - we have a stack and a place to store GD, both in SRAM
|
||||
* - no variable global data is available
|
||||
*/
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct ventana_board_info ventana_info;
|
||||
int board_model;
|
||||
|
||||
/*
|
||||
* Zero out global data:
|
||||
* - this shoudl be done by crt0.S
|
||||
* - failure to zero it will cause i2c_setup to fail
|
||||
*/
|
||||
memset((void *)gd, 0, sizeof(struct global_data));
|
||||
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
/* iomux and setup of i2c */
|
||||
board_early_init_f();
|
||||
i2c_setup_iomux();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* read/validate EEPROM info to determine board model and SDRAM cfg */
|
||||
board_model = read_eeprom(I2C_GSC, &ventana_info);
|
||||
|
||||
/* provide some some default: 32bit 128MB */
|
||||
if (GW_UNKNOWN == board_model) {
|
||||
ventana_info.sdram_width = 2;
|
||||
ventana_info.sdram_size = 3;
|
||||
}
|
||||
|
||||
/* configure MMDC for SDRAM width/size and per-model calibration */
|
||||
spl_dram_init(8 << ventana_info.sdram_width,
|
||||
16 << ventana_info.sdram_size,
|
||||
board_model);
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
|
@ -103,4 +103,15 @@ enum {
|
|||
EECONFIG_RES15,
|
||||
};
|
||||
|
||||
enum {
|
||||
GW54proto, /* original GW5400-A prototype */
|
||||
GW51xx,
|
||||
GW52xx,
|
||||
GW53xx,
|
||||
GW54xx,
|
||||
GW_UNKNOWN,
|
||||
};
|
||||
|
||||
int read_eeprom(int bus, struct ventana_board_info *);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/emif_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/arch/pinmux_defs.h>
|
||||
#include <asm/arch/davinci_misc.h>
|
||||
|
|
|
@ -267,12 +267,14 @@ int misc_init_r(void)
|
|||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "dvi");
|
||||
setenv("expansionname", "summit");
|
||||
break;
|
||||
case GUMSTIX_TOBI:
|
||||
printf("Recognized Tobi expansion board (rev %d %s)\n",
|
||||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "dvi");
|
||||
setenv("expansionname", "tobi");
|
||||
break;
|
||||
case GUMSTIX_TOBI_DUO:
|
||||
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
|
||||
|
@ -293,12 +295,14 @@ int misc_init_r(void)
|
|||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd43");
|
||||
setenv("expansionname", "palo43");
|
||||
break;
|
||||
case GUMSTIX_CHESTNUT43:
|
||||
printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
|
||||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd43");
|
||||
setenv("expansionname", "chestnut43");
|
||||
break;
|
||||
case GUMSTIX_PINTO:
|
||||
printf("Recognized Pinto expansion board (rev %d %s)\n",
|
||||
|
@ -310,6 +314,7 @@ int misc_init_r(void)
|
|||
expansion_config.revision,
|
||||
expansion_config.fab_revision);
|
||||
setenv("defaultdisplay", "lcd43");
|
||||
setenv("expansionname", "gallop43");
|
||||
break;
|
||||
case GUMSTIX_ALTO35:
|
||||
printf("Recognized Alto35 expansion board (rev %d %s)\n",
|
||||
|
@ -317,6 +322,7 @@ int misc_init_r(void)
|
|||
expansion_config.fab_revision);
|
||||
MUX_ALTO35();
|
||||
setenv("defaultdisplay", "lcd35");
|
||||
setenv("expansionname", "alto35");
|
||||
break;
|
||||
case GUMSTIX_STAGECOACH:
|
||||
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
|
||||
|
@ -349,8 +355,11 @@ int misc_init_r(void)
|
|||
break;
|
||||
case GUMSTIX_NO_EEPROM:
|
||||
puts("No EEPROM on expansion board\n");
|
||||
setenv("expansionname", "tobi");
|
||||
break;
|
||||
default:
|
||||
if (expansion_id == 0x0)
|
||||
setenv("expansionname", "tobi");
|
||||
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
|
||||
break;
|
||||
}
|
||||
|
@ -360,6 +369,11 @@ int misc_init_r(void)
|
|||
|
||||
dieid_num_r();
|
||||
|
||||
if (get_cpu_family() == CPU_OMAP34XX)
|
||||
setenv("boardname", "overo");
|
||||
else
|
||||
setenv("boardname", "overo-storm");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -332,7 +332,7 @@ int exynos_power_init(void)
|
|||
|
||||
if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
|
||||
puts("No battery detected\n");
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
p_fg->fg->fg_battery_check(p_fg, p_bat);
|
||||
|
|
|
@ -214,7 +214,7 @@ int exynos_power_init(void)
|
|||
|
||||
if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
|
||||
puts("No battery detected\n");
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
p_fg->fg->fg_battery_check(p_fg, p_bat);
|
||||
|
|
|
@ -217,6 +217,28 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
|
|||
.emif_rd_wr_exec_thresh = 0x00000405
|
||||
};
|
||||
|
||||
static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
|
||||
.sdram_config = 0x638413b2,
|
||||
.sdram_config2 = 0x00000000,
|
||||
.ref_ctrl = 0x00000c30,
|
||||
.sdram_tim1 = 0xeaaad4db,
|
||||
.sdram_tim2 = 0x266b7fda,
|
||||
.sdram_tim3 = 0x107f8678,
|
||||
.read_idle_ctrl = 0x00050000,
|
||||
.zq_config = 0x50074be4,
|
||||
.temp_alert_config = 0x0,
|
||||
.emif_ddr_phy_ctlr_1 = 0x0e084008,
|
||||
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
|
||||
.emif_ddr_ext_phy_ctrl_2 = 0x89,
|
||||
.emif_ddr_ext_phy_ctrl_3 = 0x90,
|
||||
.emif_ddr_ext_phy_ctrl_4 = 0x8e,
|
||||
.emif_ddr_ext_phy_ctrl_5 = 0x8d,
|
||||
.emif_rd_wr_lvl_rmp_win = 0x0,
|
||||
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
|
||||
.emif_rd_wr_lvl_ctl = 0x00000000,
|
||||
.emif_rd_wr_exec_thresh = 0x00000000,
|
||||
};
|
||||
|
||||
const u32 ext_phy_ctrl_const_base_ddr3[] = {
|
||||
0x00400040,
|
||||
0x00350035,
|
||||
|
@ -240,6 +262,48 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = {
|
|||
0x08102040
|
||||
};
|
||||
|
||||
static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
|
||||
/* first 5 are taken care by emif_regs */
|
||||
0x00700070,
|
||||
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
0x00350035,
|
||||
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
0x00150015,
|
||||
|
||||
0x00800080,
|
||||
0x00800080,
|
||||
|
||||
0x40000000,
|
||||
|
||||
0x08102040,
|
||||
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
|
||||
{
|
||||
if (board_is_eposevm()) {
|
||||
|
@ -248,6 +312,9 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
|
|||
} else if (board_is_gpevm()) {
|
||||
*regs = ext_phy_ctrl_const_base_ddr3;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
|
||||
} else if (board_is_sk()) {
|
||||
*regs = ext_phy_ctrl_const_base_ddr3_sk;
|
||||
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
|
||||
}
|
||||
|
||||
return;
|
||||
|
@ -257,10 +324,10 @@ const struct dpll_params *get_dpll_ddr_params(void)
|
|||
{
|
||||
if (board_is_eposevm())
|
||||
return &epos_evm_dpll_ddr;
|
||||
else if (board_is_gpevm())
|
||||
else if (board_is_gpevm() || board_is_sk())
|
||||
return &gp_evm_dpll_ddr;
|
||||
|
||||
puts(" Board not supported\n");
|
||||
printf(" Board '%s' not supported\n", am43xx_board_name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
@ -410,6 +477,9 @@ void sdram_init(void)
|
|||
enable_vtt_regulator();
|
||||
config_ddr(0, &ioregs_ddr3, NULL, NULL,
|
||||
&ddr3_emif_regs_400Mhz, 0);
|
||||
} else if (board_is_sk()) {
|
||||
config_ddr(400, &ioregs_ddr3, NULL, NULL,
|
||||
&ddr3_sk_emif_regs_400Mhz, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
@ -524,6 +594,11 @@ int board_eth_init(bd_t *bis)
|
|||
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
|
||||
cpsw_slaves[0].phy_addr = 16;
|
||||
} else if (board_is_sk()) {
|
||||
writel(RGMII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
|
||||
cpsw_slaves[0].phy_addr = 4;
|
||||
cpsw_slaves[1].phy_addr = 5;
|
||||
} else {
|
||||
writel(RGMII_MODE_ENABLE, &cdev->miisel);
|
||||
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
|
||||
|
|
|
@ -47,6 +47,11 @@ static inline int board_is_gpevm(void)
|
|||
return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
static inline int board_is_sk(void)
|
||||
{
|
||||
return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
|
||||
}
|
||||
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
void enable_i2c0_pin_mux(void);
|
||||
|
|
|
@ -97,6 +97,9 @@ void enable_board_pin_mux(void)
|
|||
if (board_is_gpevm()) {
|
||||
configure_module_pin_mux(gpio5_7_pin_mux);
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
} else if (board_is_sk()) {
|
||||
configure_module_pin_mux(rgmii1_pin_mux);
|
||||
configure_module_pin_mux(qspi_pin_mux);
|
||||
} else if (board_is_eposevm()) {
|
||||
configure_module_pin_mux(rmii1_pin_mux);
|
||||
configure_module_pin_mux(qspi_pin_mux);
|
||||
|
|
|
@ -16,9 +16,9 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
#include <asm/arch/psc_defs.h>
|
||||
#include <asm/ti-common/ti-aemif.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -40,9 +40,9 @@ unsigned int external_clk[ext_clk_count] = {
|
|||
what is that */
|
||||
};
|
||||
|
||||
static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
|
||||
static struct aemif_config aemif_configs[] = {
|
||||
{ /* CS0 */
|
||||
.mode = ASYNC_EMIF_MODE_NAND,
|
||||
.mode = AEMIF_MODE_NAND,
|
||||
.wr_setup = 0xf,
|
||||
.wr_strobe = 0x3f,
|
||||
.wr_hold = 7,
|
||||
|
@ -50,7 +50,7 @@ static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
|
|||
.rd_strobe = 0x3f,
|
||||
.rd_hold = 7,
|
||||
.turn_around = 3,
|
||||
.width = ASYNC_EMIF_8,
|
||||
.width = AEMIF_WIDTH_8,
|
||||
},
|
||||
|
||||
};
|
||||
|
@ -67,7 +67,7 @@ int dram_init(void)
|
|||
|
||||
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_MAX_RAM_BANK_SIZE);
|
||||
init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
|
||||
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/arch/nand_defs.h>
|
||||
#include <asm/ti-common/davinci_nand.h>
|
||||
#include <asm/arch/mux.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
13
boards.cfg
13
boards.cfg
|
@ -209,6 +209,7 @@ Active arm arm926ejs mxs freescale mx23evk
|
|||
Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm arm926ejs mxs freescale mx28evk mx28evk_spi mx28evk:ENV_IS_IN_SPI_FLASH Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
|
||||
Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
|
||||
Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
|
||||
|
@ -288,6 +289,7 @@ Active arm armv7 exynos samsung origen
|
|||
Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
|
||||
Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
|
||||
Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
|
||||
Active arm armv7 exynos samsung smdk5420 peach-pit - Akshay Saraswat <akshay.s@samsung.com>
|
||||
Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
|
||||
Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
|
||||
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
|
||||
|
@ -320,14 +322,11 @@ Active arm armv7 mx6 embest mx6boards
|
|||
Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com>
|
||||
Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6qsabreauto mx6dlsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey <tharvey@gateworks.com>
|
||||
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
|
||||
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
|
||||
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
|
||||
|
@ -369,10 +368,8 @@ Active arm armv7 omap5 ti omap5_uevm
|
|||
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
|
||||
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
|
||||
Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga <r.baldyga@samsung.com>
|
||||
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
|
||||
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
|
||||
Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII -
|
||||
|
|
|
@ -23,6 +23,7 @@ Contents
|
|||
2) Compiling U-Boot for a MXS based board
|
||||
3) Installation of U-Boot for a MXS based board to SD card
|
||||
4) Installation of U-Boot into NAND flash on a MX28 based board
|
||||
5) Installation of U-boot into SPI NOR flash on a MX28 based board
|
||||
|
||||
1) Prerequisites
|
||||
----------------
|
||||
|
@ -262,3 +263,28 @@ There are two possibilities when preparing an image writable to NAND flash.
|
|||
In case the user needs to boot a firmware image bigger than 1Mb, the
|
||||
user has to adjust the "update_nand_firmware_maxsz" variable for the
|
||||
update scripts to work properly.
|
||||
|
||||
5) Installation of U-Boot into SPI NOR flash on a MX28 based board
|
||||
------------------------------------------------------------------
|
||||
|
||||
The u-boot.sb file can be directly written to SPI NOR from U-boot prompt.
|
||||
|
||||
Load u-boot.sb into RAM, this can be done in several ways and one way is to use
|
||||
tftp:
|
||||
=> tftp u-boot.sb 0x42000000
|
||||
|
||||
Probe the SPI NOR flash:
|
||||
=> sf probe
|
||||
|
||||
(SPI NOR should be succesfully detected in this step)
|
||||
|
||||
Erase the blocks where U-boot binary will be written to:
|
||||
=> sf erase 0x0 0x80000
|
||||
|
||||
Write u-boot.sb to SPI NOR:
|
||||
=> sf write 0x42000000 0 0x80000
|
||||
|
||||
Power off the board and set the boot mode DIP switches to boot from the SPI NOR
|
||||
according to MX28 manual section 12.2.1 (Table 12-2)
|
||||
|
||||
Last step is to power up the board and U-boot should start from SPI NOR.
|
||||
|
|
|
@ -14,3 +14,4 @@ obj-y += twserial/
|
|||
obj-y += video/
|
||||
obj-y += watchdog/
|
||||
obj-$(CONFIG_QE) += qe/
|
||||
obj-y += memory/
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include "dwc_ahsata.h"
|
||||
|
||||
struct sata_port_regs {
|
||||
|
@ -558,6 +559,10 @@ int init_sata(int dev)
|
|||
u32 linkmap;
|
||||
struct ahci_probe_ent *probe_ent = NULL;
|
||||
|
||||
#if defined(CONFIG_MX6)
|
||||
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
|
||||
return 1;
|
||||
#endif
|
||||
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
|
||||
printf("The sata index %d is out of ranges\n\r", dev);
|
||||
return -1;
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue