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Merge branch 'master' of git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini 2016-12-12 07:18:53 -05:00
commit fe9822556e
21 changed files with 2919 additions and 2079 deletions
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1
arch/arm/Kconfig
View file

@ -829,7 +829,6 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs" bool "Socionext UniPhier SoCs"
select BLK
select CLK_UNIPHIER select CLK_UNIPHIER
select DM select DM
select DM_GPIO select DM_GPIO

177
arch/arm/dts/uniphier-common32.dtsi
View file

@ -1,177 +0,0 @@
/*
* Device Tree Source commonly used by UniPhier ARM SoCs
*
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/include/ "skeleton.dtsi"
/ {
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks {
refclk: ref {
#clock-cells = <0>;
compatible = "fixed-clock";
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
};
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
mio_clk: clock {
#clock-cells = <1>;
};
mio_rst: reset {
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
#clock-cells = <1>;
};
peri_rst: reset {
#reset-cells = <1>;
};
};
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
/* specify compatible in each SoC DTSI */
u-boot,dm-pre-reloc;
};
};
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
sys_clk: clock {
#clock-cells = <1>;
};
sys_rst: reset {
#reset-cells = <1>;
};
};
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"

111
arch/arm/dts/uniphier-ld11.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ /memreserve/ 0x80000000 0x00080000;
/ { / {
compatible = "socionext,uniphier-ld11"; compatible = "socionext,uniphier-ld11";
@ -34,31 +34,66 @@
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>; reg = <0 0x000>;
enable-method = "spin-table"; clocks = <&sys_clk 33>;
cpu-release-addr = <0 0x80000000>; enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>; reg = <0 0x001>;
enable-method = "spin-table"; clocks = <&sys_clk 33>;
cpu-release-addr = <0 0x80000000>; enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
}; };
}; };
cluster0_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp@245000000 {
opp-hz = /bits/ 64 <245000000>;
clock-latency-ns = <300>;
};
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@490000000 {
opp-hz = /bits/ 64 <490000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@653334000 {
opp-hz = /bits/ 64 <653334000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@980000000 {
opp-hz = /bits/ 64 <980000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks { clocks {
refclk: ref { refclk: ref {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <25000000>; clock-frequency = <25000000>;
}; };
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
}; };
timer { timer {
@ -129,7 +164,7 @@
interrupts = <0 41 4>; interrupts = <0 41 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>; clocks = <&peri_clk 4>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -142,7 +177,7 @@
interrupts = <0 42 4>; interrupts = <0 42 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>; clocks = <&peri_clk 5>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -152,7 +187,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 43 4>; interrupts = <0 43 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 6>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -165,7 +200,7 @@
interrupts = <0 44 4>; interrupts = <0 44 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>; clocks = <&peri_clk 7>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -178,7 +213,7 @@
interrupts = <0 45 4>; interrupts = <0 45 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>; pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 8>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -188,7 +223,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 25 4>; interrupts = <0 25 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 9>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -207,8 +242,19 @@
reg = <0x59801000 0x400>; reg = <0x59801000 0x400>;
}; };
sdctrl@59810000 {
compatible = "socionext,uniphier-ld11-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
sd_rst: reset {
compatible = "socionext,uniphier-ld11-sd-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 { perictrl@59820000 {
compatible = "socionext,uniphier-perictrl", compatible = "socionext,uniphier-ld11-perictrl",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x59820000 0x200>; reg = <0x59820000 0x200>;
@ -223,6 +269,19 @@
}; };
}; };
emmc: sdhc@5a000000 {
compatible = "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
/* mmc-hs400-1_8v; support depends on board design */
};
usb0: usb@5a800100 { usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci"; compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled"; status = "disabled";
@ -277,7 +336,7 @@
}; };
soc-glue@5f800000 { soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue", compatible = "socionext,uniphier-ld11-soc-glue",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>; reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
@ -305,7 +364,7 @@
sysctrl@61840000 { sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl", compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x61840000 0x4000>; reg = <0x61840000 0x10000>;
sys_clk: clock { sys_clk: clock {
compatible = "socionext,uniphier-ld11-clock"; compatible = "socionext,uniphier-ld11-clock";
@ -317,6 +376,18 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
}; };
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
}; };
}; };

188
arch/arm/dts/uniphier-ld20.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ /memreserve/ 0x80000000 0x00080000;
/ { / {
compatible = "socionext,uniphier-ld20"; compatible = "socionext,uniphier-ld20";
@ -43,47 +43,126 @@
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8"; compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>; reg = <0 0x000>;
enable-method = "spin-table"; clocks = <&sys_clk 32>;
cpu-release-addr = <0 0x80000000>; enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8"; compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>; reg = <0 0x001>;
enable-method = "spin-table"; clocks = <&sys_clk 32>;
cpu-release-addr = <0 0x80000000>; enable-method = "psci";
operating-points-v2 = <&cluster0_opp>;
}; };
cpu2: cpu@100 { cpu2: cpu@100 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>; reg = <0 0x100>;
enable-method = "spin-table"; clocks = <&sys_clk 33>;
cpu-release-addr = <0 0x80000000>; enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
}; };
cpu3: cpu@101 { cpu3: cpu@101 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>; reg = <0 0x101>;
enable-method = "spin-table"; clocks = <&sys_clk 33>;
cpu-release-addr = <0 0x80000000>; enable-method = "psci";
operating-points-v2 = <&cluster1_opp>;
}; };
}; };
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@250000000 {
opp-hz = /bits/ 64 <250000000>;
clock-latency-ns = <300>;
};
opp@275000000 {
opp-hz = /bits/ 64 <275000000>;
clock-latency-ns = <300>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <300>;
};
opp@550000000 {
opp-hz = /bits/ 64 <550000000>;
clock-latency-ns = <300>;
};
opp@666667000 {
opp-hz = /bits/ 64 <666667000>;
clock-latency-ns = <300>;
};
opp@733334000 {
opp-hz = /bits/ 64 <733334000>;
clock-latency-ns = <300>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <300>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks { clocks {
refclk: ref { refclk: ref {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <25000000>; clock-frequency = <25000000>;
}; };
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
}; };
timer { timer {
@ -154,7 +233,7 @@
interrupts = <0 41 4>; interrupts = <0 41 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>; clocks = <&peri_clk 4>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -167,7 +246,7 @@
interrupts = <0 42 4>; interrupts = <0 42 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>; clocks = <&peri_clk 5>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -177,7 +256,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 43 4>; interrupts = <0 43 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 6>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -190,7 +269,7 @@
interrupts = <0 44 4>; interrupts = <0 44 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>; clocks = <&peri_clk 7>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -203,7 +282,7 @@
interrupts = <0 45 4>; interrupts = <0 45 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>; pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 8>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -213,7 +292,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 25 4>; interrupts = <0 25 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 9>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -232,24 +311,24 @@
reg = <0x59801000 0x400>; reg = <0x59801000 0x400>;
}; };
mioctrl@59810000 { sdctrl@59810000 {
compatible = "socionext,uniphier-mioctrl", compatible = "socionext,uniphier-ld20-sdctrl",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x59810000 0x800>; reg = <0x59810000 0x800>;
mio_clk: clock { sd_clk: clock {
compatible = "socionext,uniphier-ld20-mio-clock"; compatible = "socionext,uniphier-ld20-sd-clock";
#clock-cells = <1>; #clock-cells = <1>;
}; };
mio_rst: reset { sd_rst: reset {
compatible = "socionext,uniphier-ld20-mio-reset"; compatible = "socionext,uniphier-ld20-sd-reset";
#reset-cells = <1>; #reset-cells = <1>;
}; };
}; };
perictrl@59820000 { perictrl@59820000 {
compatible = "socionext,uniphier-perictrl", compatible = "socionext,uniphier-ld20-perictrl",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x59820000 0x200>; reg = <0x59820000 0x200>;
@ -264,6 +343,19 @@
}; };
}; };
emmc: sdhc@5a000000 {
compatible = "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_1v8>;
clocks = <&sys_clk 4>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
/* mmc-hs400-1_8v; support depends on board design */
};
sd: sdhc@5a400000 { sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
@ -271,14 +363,15 @@
interrupts = <0 76 4>; interrupts = <0 76 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>; pinctrl-0 = <&pinctrl_sd>;
clocks = <&mio_clk 0>; clocks = <&sd_clk 0>;
reset-names = "host"; reset-names = "host";
resets = <&mio_rst 0>; resets = <&sd_rst 0>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
}; };
soc-glue@5f800000 { soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue", compatible = "socionext,uniphier-ld20-soc-glue",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>; reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
@ -304,9 +397,9 @@
}; };
sysctrl@61840000 { sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl", compatible = "socionext,uniphier-ld20-sysctrl",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0x61840000 0x4000>; reg = <0x61840000 0x10000>;
sys_clk: clock { sys_clk: clock {
compatible = "socionext,uniphier-ld20-clock"; compatible = "socionext,uniphier-ld20-clock";
@ -318,6 +411,35 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
}; };
usb: usb@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3";
reg = <0x65b00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
<&pinctrl_usb2>, <&pinctrl_usb3>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
tx-fifo-resize;
};
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
}; };
}; };

243
arch/arm/dts/uniphier-ld4.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/include/ "uniphier-common32.dtsi" /include/ "skeleton.dtsi"
/ { / {
compatible = "socionext,uniphier-ld4"; compatible = "socionext,uniphier-ld4";
@ -25,25 +25,37 @@
}; };
}; };
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks { clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
arm_timer_clk: arm_timer_clk { arm_timer_clk: arm_timer_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
}; };
&soc { soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache"; compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>; interrupts = <0 174 4>, <0 175 4>;
cache-unified; cache-unified;
cache-size = <(512 * 1024)>; cache-size = <(512 * 1024)>;
@ -52,6 +64,50 @@
cache-level = <2>; cache-level = <2>;
}; };
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <36864000>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <36864000>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <36864000>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 29 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <36864000>;
};
port0x: gpio@55000008 { port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio"; compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>; reg = <0x55000008 0x8>;
@ -173,7 +229,7 @@
interrupts = <0 41 1>; interrupts = <0 41 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>; clocks = <&peri_clk 4>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -186,7 +242,7 @@
interrupts = <0 42 1>; interrupts = <0 42 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&iobus_clk>; clocks = <&peri_clk 5>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -199,7 +255,7 @@
interrupts = <0 43 1>; interrupts = <0 43 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&iobus_clk>; clocks = <&peri_clk 6>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -212,10 +268,57 @@
interrupts = <0 44 1>; interrupts = <0 44 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&iobus_clk>; clocks = <&peri_clk 7>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-ld4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-ld4-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld4-mio-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-ld4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-ld4-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-ld4-peri-reset";
#reset-cells = <1>;
};
};
sd: sdhc@5a400000 { sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
@ -228,6 +331,10 @@
reset-names = "host", "bridge"; reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>; resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
}; };
emmc: sdhc@5a500000 { emmc: sdhc@5a500000 {
@ -239,10 +346,12 @@
pinctrl-0 = <&pinctrl_emmc>; pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>; pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>; clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw-reset"; reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
}; };
usb0: usb@5a800100 { usb0: usb@5a800100 {
@ -281,57 +390,73 @@
<&mio_rst 14>; <&mio_rst 14>;
}; };
soc-glue@5f800000 {
compatible = "socionext,uniphier-ld4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
u-boot,dm-pre-reloc;
};
};
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
aidet@61830000 { aidet@61830000 {
compatible = "simple-mfd", "syscon"; compatible = "simple-mfd", "syscon";
reg = <0x61830000 0x200>; reg = <0x61830000 0x200>;
}; };
};
&refclk { sysctrl@61840000 {
clock-frequency = <24576000>; compatible = "socionext,uniphier-ld4-sysctrl",
}; "simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
&serial0 { sys_clk: clock {
clock-frequency = <36864000>;
};
&serial1 {
clock-frequency = <36864000>;
};
&serial2 {
clock-frequency = <36864000>;
};
&serial3 {
interrupts = <0 29 4>;
clock-frequency = <36864000>;
};
&mio_clk {
compatible = "socionext,uniphier-ld4-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-ld4-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-ld4-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-ld4-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-ld4-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-ld4-clock"; compatible = "socionext,uniphier-ld4-clock";
#clock-cells = <1>;
}; };
&sys_rst { sys_rst: reset {
compatible = "socionext,uniphier-ld4-reset"; compatible = "socionext,uniphier-ld4-reset";
#reset-cells = <1>;
}; };
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"

12
arch/arm/dts/uniphier-pro4-ref.dts
View file

@ -68,10 +68,6 @@
status = "okay"; status = "okay";
}; };
&usb0 {
status = "okay";
};
&usb2 { &usb2 {
status = "okay"; status = "okay";
}; };
@ -80,6 +76,14 @@
status = "okay"; status = "okay";
}; };
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* for U-Boot only */ /* for U-Boot only */
&serial0 { &serial0 {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;

293
arch/arm/dts/uniphier-pro4.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/include/ "uniphier-common32.dtsi" /include/ "skeleton.dtsi"
/ { / {
compatible = "socionext,uniphier-pro4"; compatible = "socionext,uniphier-pro4";
@ -33,31 +33,37 @@
}; };
}; };
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks { clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
arm_timer_clk: arm_timer_clk { arm_timer_clk: arm_timer_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <73728000>;
}; };
i2c_clk: i2c_clk { soc {
#clock-cells = <0>; compatible = "simple-bus";
compatible = "fixed-clock"; #address-cells = <1>;
clock-frequency = <50000000>; #size-cells = <1>;
}; ranges;
}; interrupt-parent = <&intc>;
}; u-boot,dm-pre-reloc;
&soc {
l2: l2-cache@500c0000 { l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache"; compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>; interrupts = <0 174 4>, <0 175 4>;
cache-unified; cache-unified;
cache-size = <(768 * 1024)>; cache-size = <(768 * 1024)>;
@ -66,6 +72,50 @@
cache-level = <2>; cache-level = <2>;
}; };
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <73728000>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <73728000>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <73728000>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <73728000>;
};
port0x: gpio@55000008 { port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio"; compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>; reg = <0x55000008 0x8>;
@ -278,7 +328,7 @@
interrupts = <0 41 4>; interrupts = <0 41 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>; clocks = <&peri_clk 4>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -291,7 +341,7 @@
interrupts = <0 42 4>; interrupts = <0 42 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>; clocks = <&peri_clk 5>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -304,7 +354,7 @@
interrupts = <0 43 4>; interrupts = <0 43 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&i2c_clk>; clocks = <&peri_clk 6>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -317,7 +367,7 @@
interrupts = <0 44 4>; interrupts = <0 44 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>; clocks = <&peri_clk 7>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -330,7 +380,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 25 4>; interrupts = <0 25 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 9>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -341,10 +391,58 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 26 4>; interrupts = <0 26 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 10>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-pro4-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
mio_clk: clock {
compatible = "socionext,uniphier-pro4-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-pro4-mio-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-pro4-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-pro4-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-pro4-peri-reset";
#reset-cells = <1>;
};
};
sd: sdhc@5a400000 { sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
@ -357,6 +455,10 @@
reset-names = "host", "bridge"; reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>; resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
}; };
emmc: sdhc@5a500000 { emmc: sdhc@5a500000 {
@ -368,10 +470,12 @@
pinctrl-0 = <&pinctrl_emmc>; pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>; pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>; clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw-reset"; reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
}; };
sd1: sdhc@5a600000 { sd1: sdhc@5a600000 {
@ -385,6 +489,10 @@
clocks = <&mio_clk 2>; clocks = <&mio_clk 2>;
resets = <&mio_rst 2>, <&mio_rst 5>; resets = <&mio_rst 2>, <&mio_rst 5>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
}; };
usb2: usb@5a800100 { usb2: usb@5a800100 {
@ -411,74 +519,107 @@
<&mio_rst 13>; <&mio_rst 13>;
}; };
soc-glue@5f800000 {
compatible = "socionext,uniphier-pro4-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
u-boot,dm-pre-reloc;
};
};
aidet@5fc20000 { aidet@5fc20000 {
compatible = "simple-mfd", "syscon"; compatible = "simple-mfd", "syscon";
reg = <0x5fc20000 0x200>; reg = <0x5fc20000 0x200>;
}; };
usb0: usb@65a00000 { timer@60000200 {
compatible = "socionext,uniphier-xhci", "generic-xhci"; compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x304>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x304>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-pro4-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-pro4-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-pro4-reset";
#reset-cells = <1>;
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3";
status = "disabled"; status = "disabled";
reg = <0x65a00000 0x100>; reg = <0x65b00000 0x1000>;
interrupts = <0 134 4>; #address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>; pinctrl-0 = <&pinctrl_usb0>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
tx-fifo-resize;
};
}; };
usb1: usb@65c00000 { usb1: usb@65d00000 {
compatible = "socionext,uniphier-xhci", "generic-xhci"; compatible = "socionext,uniphier-pro4-dwc3";
status = "disabled"; status = "disabled";
reg = <0x65c00000 0x100>; reg = <0x65d00000 0x1000>;
interrupts = <0 137 4>; #address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>; pinctrl-0 = <&pinctrl_usb1>;
dwc3@65c00000 {
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
tx-fifo-resize;
}; };
}; };
&refclk { nand: nand@68000000 {
clock-frequency = <25000000>; compatible = "socionext,denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
}; };
&serial0 { /include/ "uniphier-pinctrl.dtsi"
clock-frequency = <73728000>;
};
&serial1 {
clock-frequency = <73728000>;
};
&serial2 {
clock-frequency = <73728000>;
};
&serial3 {
clock-frequency = <73728000>;
};
&mio_clk {
compatible = "socionext,uniphier-pro4-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pro4-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-pro4-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-pro4-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-pro4-clock";
};
&sys_rst {
compatible = "socionext,uniphier-pro4-reset";
};

391
arch/arm/dts/uniphier-pro5.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/include/ "uniphier-common32.dtsi" /include/ "skeleton.dtsi"
/ { / {
compatible = "socionext,uniphier-pro5"; compatible = "socionext,uniphier-pro5";
@ -20,38 +20,124 @@
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0>; reg = <0>;
clocks = <&sys_clk 32>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&l2>; next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <1>; reg = <1>;
clocks = <&sys_clk 32>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&l2>; next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
}; };
}; };
cpu_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
clock-latency-ns = <300>;
};
opp@116667000 {
opp-hz = /bits/ 64 <116667000>;
clock-latency-ns = <300>;
};
opp@150000000 {
opp-hz = /bits/ 64 <150000000>;
clock-latency-ns = <300>;
};
opp@175000000 {
opp-hz = /bits/ 64 <175000000>;
clock-latency-ns = <300>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <300>;
};
opp@233334000 {
opp-hz = /bits/ 64 <233334000>;
clock-latency-ns = <300>;
};
opp@300000000 {
opp-hz = /bits/ 64 <300000000>;
clock-latency-ns = <300>;
};
opp@350000000 {
opp-hz = /bits/ 64 <350000000>;
clock-latency-ns = <300>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
clock-latency-ns = <300>;
};
opp@466667000 {
opp-hz = /bits/ 64 <466667000>;
clock-latency-ns = <300>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
clock-latency-ns = <300>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
clock-latency-ns = <300>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <300>;
};
opp@933334000 {
opp-hz = /bits/ 64 <933334000>;
clock-latency-ns = <300>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
clock-latency-ns = <300>;
};
opp@1400000000 {
opp-hz = /bits/ 64 <1400000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks { clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
arm_timer_clk: arm_timer_clk { arm_timer_clk: arm_timer_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
}; };
&soc { soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache"; compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
interrupts = <0 190 4>, <0 191 4>; interrupts = <0 190 4>, <0 191 4>;
cache-unified; cache-unified;
cache-size = <(2 * 1024 * 1024)>; cache-size = <(2 * 1024 * 1024)>;
@ -63,7 +149,8 @@
l3: l3-cache@500c8000 { l3: l3-cache@500c8000 {
compatible = "socionext,uniphier-system-cache"; compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
interrupts = <0 174 4>, <0 175 4>; interrupts = <0 174 4>, <0 175 4>;
cache-unified; cache-unified;
cache-size = <(2 * 1024 * 1024)>; cache-size = <(2 * 1024 * 1024)>;
@ -72,6 +159,50 @@
cache-level = <3>; cache-level = <3>;
}; };
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <73728000>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <73728000>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <73728000>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <73728000>;
};
port0x: gpio@55000008 { port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio"; compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>; reg = <0x55000008 0x8>;
@ -284,7 +415,7 @@
interrupts = <0 41 4>; interrupts = <0 41 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>; clocks = <&peri_clk 4>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -297,7 +428,7 @@
interrupts = <0 42 4>; interrupts = <0 42 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>; clocks = <&peri_clk 5>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -310,7 +441,7 @@
interrupts = <0 43 4>; interrupts = <0 43 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&i2c_clk>; clocks = <&peri_clk 6>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -323,7 +454,7 @@
interrupts = <0 44 4>; interrupts = <0 44 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>; clocks = <&peri_clk 7>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -336,7 +467,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 25 4>; interrupts = <0 25 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 9>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -347,15 +478,159 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 26 4>; interrupts = <0 26 4>;
clocks = <&i2c_clk>; clocks = <&peri_clk 10>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
sdctrl@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
sd_clk: clock {
compatible = "socionext,uniphier-pro5-sd-clock";
#clock-cells = <1>;
};
sd_rst: reset {
compatible = "socionext,uniphier-pro5-sd-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-pro5-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-pro5-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-pro5-peri-reset";
#reset-cells = <1>;
};
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-pro5-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pro5-pinctrl";
u-boot,dm-pre-reloc;
};
};
aidet@5fc20000 { aidet@5fc20000 {
compatible = "simple-mfd", "syscon"; compatible = "simple-mfd", "syscon";
reg = <0x5fc20000 0x200>; reg = <0x5fc20000 0x200>;
}; };
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x304>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x304>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-pro5-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
sys_clk: clock {
compatible = "socionext,uniphier-pro5-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-pro5-reset";
#reset-cells = <1>;
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3";
status = "disabled";
reg = <0x65b00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
tx-fifo-resize;
};
};
usb1: usb@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3";
status = "disabled";
reg = <0x65d00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
dwc3@65c00000 {
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
tx-fifo-resize;
};
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
emmc: sdhc@68400000 { emmc: sdhc@68400000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
@ -363,11 +638,14 @@
interrupts = <0 78 4>; interrupts = <0 78 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>; pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>; clocks = <&sd_clk 1>;
reset-names = "host", "hw-reset"; reset-names = "host";
resets = <&mio_rst 1>, <&mio_rst 6>; resets = <&sd_rst 1>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
no-3-3-v;
}; };
sd: sdhc@68800000 { sd: sdhc@68800000 {
@ -378,75 +656,16 @@
pinctrl-names = "default", "1.8v"; pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>; pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>; pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>; clocks = <&sd_clk 0>;
reset-names = "host"; reset-names = "host";
resets = <&mio_rst 0>; resets = <&sd_rst 0>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
}; };
usb0: usb@65a00000 {
compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65a00000 0x100>;
interrupts = <0 134 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
};
usb1: usb@65c00000 {
compatible = "socionext,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65c00000 0x100>;
interrupts = <0 137 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
}; };
}; };
&refclk { /include/ "uniphier-pinctrl.dtsi"
clock-frequency = <20000000>;
};
&serial0 {
clock-frequency = <73728000>;
};
&serial1 {
clock-frequency = <73728000>;
};
&serial2 {
clock-frequency = <73728000>;
};
&serial3 {
clock-frequency = <73728000>;
};
&mio_clk {
compatible = "socionext,uniphier-pro5-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pro5-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-pro5-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-pro5-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-pro5-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-pro5-clock";
};
&sys_rst {
compatible = "socionext,uniphier-pro5-reset";
};

2
arch/arm/dts/uniphier-pxs2-gentil.dts
View file

@ -71,7 +71,7 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&mio_clk { &sd_clk {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };

2
arch/arm/dts/uniphier-pxs2-vodka.dts
View file

@ -55,7 +55,7 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
&mio_clk { &sd_clk {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };

322
arch/arm/dts/uniphier-pxs2.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/include/ "uniphier-common32.dtsi" /include/ "skeleton.dtsi"
/ { / {
compatible = "socionext,uniphier-pxs2"; compatible = "socionext,uniphier-pxs2";
@ -20,36 +20,93 @@
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0>; reg = <0>;
clocks = <&sys_clk 32>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&l2>; next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <1>; reg = <1>;
clocks = <&sys_clk 32>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&l2>; next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
}; };
cpu@2 { cpu@2 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <2>; reg = <2>;
clocks = <&sys_clk 32>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&l2>; next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
}; };
cpu@3 { cpu@3 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <3>; reg = <3>;
clocks = <&sys_clk 32>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&l2>; next-level-cache = <&l2>;
operating-points-v2 = <&cpu_opp>;
}; };
}; };
cpu_opp: opp_table {
compatible = "operating-points-v2";
opp-shared;
opp@100000000 {
opp-hz = /bits/ 64 <100000000>;
clock-latency-ns = <300>;
};
opp@150000000 {
opp-hz = /bits/ 64 <150000000>;
clock-latency-ns = <300>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <300>;
};
opp@300000000 {
opp-hz = /bits/ 64 <300000000>;
clock-latency-ns = <300>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
clock-latency-ns = <300>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
clock-latency-ns = <300>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <300>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
clock-latency-ns = <300>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks { clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
arm_timer_clk: arm_timer_clk { arm_timer_clk: arm_timer_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -62,12 +119,19 @@
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
}; };
};
&soc { soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache"; compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
cache-unified; cache-unified;
cache-size = <(1280 * 1024)>; cache-size = <(1280 * 1024)>;
@ -76,6 +140,50 @@
cache-level = <2>; cache-level = <2>;
}; };
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <88900000>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <88900000>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <88900000>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <88900000>;
};
port0x: gpio@55000008 { port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio"; compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>; reg = <0x55000008 0x8>;
@ -304,9 +412,9 @@
reg = <0x58782000 0x80>; reg = <0x58782000 0x80>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 43 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
interrupts = <0 43 4>;
clocks = <&i2c_clk>; clocks = <&i2c_clk>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -357,6 +465,54 @@
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
sdctrl@59810000 {
compatible = "socionext,uniphier-pxs2-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
u-boot,dm-pre-reloc;
sd_clk: clock {
compatible = "socionext,uniphier-pxs2-sd-clock";
#clock-cells = <1>;
};
sd_rst: reset {
compatible = "socionext,uniphier-pxs2-sd-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-pxs2-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-pxs2-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-pxs2-peri-reset";
#reset-cells = <1>;
};
};
emmc: sdhc@5a000000 { emmc: sdhc@5a000000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
@ -364,11 +520,14 @@
interrupts = <0 78 4>; interrupts = <0 78 4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>; pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>; clocks = <&sd_clk 1>;
reset-names = "host", "hw-reset"; reset-names = "host";
resets = <&mio_rst 1>, <&mio_rst 6>; resets = <&sd_rst 1>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
no-3-3-v;
}; };
sd: sdhc@5a400000 { sd: sdhc@5a400000 {
@ -379,10 +538,26 @@
pinctrl-names = "default", "1.8v"; pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>; pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>; pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>; clocks = <&sd_clk 0>;
reset-names = "host"; reset-names = "host";
resets = <&mio_rst 0>; resets = <&sd_rst 0>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-pxs2-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-pxs2-pinctrl";
u-boot,dm-pre-reloc;
};
}; };
aidet@5fc20000 { aidet@5fc20000 {
@ -390,69 +565,90 @@
reg = <0x5fc20000 0x200>; reg = <0x5fc20000 0x200>;
}; };
usb0: usb@65a00000 { timer@60000200 {
compatible = "socionext,uniphier-xhci", "generic-xhci"; compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0xf04>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0xf04>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-pxs2-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
sys_clk: clock {
compatible = "socionext,uniphier-pxs2-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-pxs2-reset";
#reset-cells = <1>;
};
};
usb0: usb@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3";
status = "disabled"; status = "disabled";
reg = <0x65a00000 0x100>; reg = <0x65b00000 0x1000>;
interrupts = <0 134 4>; #address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
dwc3@65a00000 {
compatible = "snps,dwc3";
reg = <0x65a00000 0x10000>;
interrupts = <0 134 4>;
tx-fifo-resize;
};
}; };
usb1: usb@65c00000 { usb1: usb@65d00000 {
compatible = "socionext,uniphier-xhci", "generic-xhci"; compatible = "socionext,uniphier-pxs2-dwc3";
status = "disabled"; status = "disabled";
reg = <0x65c00000 0x100>; reg = <0x65d00000 0x1000>;
interrupts = <0 137 4>; #address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
dwc3@65c00000 {
compatible = "snps,dwc3";
reg = <0x65c00000 0x10000>;
interrupts = <0 137 4>;
tx-fifo-resize;
}; };
}; };
&refclk { nand: nand@68000000 {
clock-frequency = <25000000>; compatible = "socionext,denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
}; };
&serial0 { /include/ "uniphier-pinctrl.dtsi"
clock-frequency = <88900000>;
};
&serial1 {
clock-frequency = <88900000>;
};
&serial2 {
clock-frequency = <88900000>;
};
&serial3 {
clock-frequency = <88900000>;
};
&mio_clk {
compatible = "socionext,uniphier-pxs2-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-pxs2-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-pxs2-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-pxs2-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-pxs2-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-pxs2-clock";
};
&sys_rst {
compatible = "socionext,uniphier-pxs2-reset";
};

37
arch/arm/dts/uniphier-sld3.dtsi
View file

@ -50,12 +50,6 @@
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
}; };
soc { soc {
@ -251,7 +245,7 @@
interrupts = <0 41 1>; interrupts = <0 41 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>; clocks = <&sys_clk 1>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -262,7 +256,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 42 1>; interrupts = <0 42 1>;
clocks = <&iobus_clk>; clocks = <&sys_clk 1>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -273,7 +267,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 43 1>; interrupts = <0 43 1>;
clocks = <&iobus_clk>; clocks = <&sys_clk 1>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -284,7 +278,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 44 1>; interrupts = <0 44 1>;
clocks = <&iobus_clk>; clocks = <&sys_clk 1>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -295,7 +289,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <0 45 1>; interrupts = <0 45 1>;
clocks = <&iobus_clk>; clocks = <&sys_clk 1>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -339,9 +333,12 @@
pinctrl-0 = <&pinctrl_emmc>; pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>; pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>; clocks = <&mio_clk 1>;
reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>; resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
}; };
sd: sdhc@5a500000 { sd: sdhc@5a500000 {
@ -353,8 +350,13 @@
pinctrl-0 = <&pinctrl_sd>; pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>; pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio_clk 0>; clocks = <&mio_clk 0>;
reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>; resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
}; };
usb0: usb@5a800100 { usb0: usb@5a800100 {
@ -406,7 +408,8 @@
}; };
soc-glue@5f800000 { soc-glue@5f800000 {
compatible = "simple-mfd", "syscon"; compatible = "socionext,uniphier-sld3-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>; reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
@ -422,7 +425,7 @@
}; };
sysctrl@f1840000 { sysctrl@f1840000 {
compatible = "socionext,uniphier-sysctrl", compatible = "socionext,uniphier-sld3-sysctrl",
"simple-mfd", "syscon"; "simple-mfd", "syscon";
reg = <0xf1840000 0x4000>; reg = <0xf1840000 0x4000>;
@ -438,9 +441,13 @@
}; };
nand: nand@f8000000 { nand: nand@f8000000 {
compatible = "denali,denali-nand-dt"; compatible = "socionext,denali-nand-v5a";
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; status = "disabled";
reg-names = "nand_data", "denali_reg"; reg-names = "nand_data", "denali_reg";
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
interrupts = <0 65 4>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
}; };
}; };
}; };

245
arch/arm/dts/uniphier-sld8.dtsi
View file

@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+ X11 * SPDX-License-Identifier: GPL-2.0+ X11
*/ */
/include/ "uniphier-common32.dtsi" /include/ "skeleton.dtsi"
/ { / {
compatible = "socionext,uniphier-sld8"; compatible = "socionext,uniphier-sld8";
@ -25,25 +25,37 @@
}; };
}; };
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
clocks { clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
arm_timer_clk: arm_timer_clk { arm_timer_clk: arm_timer_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
iobus_clk: iobus_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
}; };
&soc { soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
l2: l2-cache@500c0000 { l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache"; compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>; interrupts = <0 174 4>, <0 175 4>;
cache-unified; cache-unified;
cache-size = <(256 * 1024)>; cache-size = <(256 * 1024)>;
@ -52,6 +64,50 @@
cache-level = <2>; cache-level = <2>;
}; };
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
clock-frequency = <80000000>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
clock-frequency = <80000000>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
clock-frequency = <80000000>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 29 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
clock-frequency = <80000000>;
};
port0x: gpio@55000008 { port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio"; compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>; reg = <0x55000008 0x8>;
@ -173,7 +229,7 @@
interrupts = <0 41 1>; interrupts = <0 41 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&iobus_clk>; clocks = <&peri_clk 4>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -186,7 +242,7 @@
interrupts = <0 42 1>; interrupts = <0 42 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&iobus_clk>; clocks = <&peri_clk 5>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
@ -199,7 +255,7 @@
interrupts = <0 43 1>; interrupts = <0 43 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&iobus_clk>; clocks = <&peri_clk 6>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
@ -212,10 +268,57 @@
interrupts = <0 44 1>; interrupts = <0 44 1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&iobus_clk>; clocks = <&peri_clk 7>;
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-sld8-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-sld8-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-sld8-mio-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-sld8-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-sld8-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-sld8-peri-reset";
#reset-cells = <1>;
};
};
sd: sdhc@5a400000 { sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
@ -228,21 +331,27 @@
reset-names = "host", "bridge"; reset-names = "host", "bridge";
resets = <&mio_rst 0>, <&mio_rst 3>; resets = <&mio_rst 0>, <&mio_rst 3>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
}; };
emmc: sdhc@5a500000 { emmc: sdhc@5a500000 {
compatible = "socionext,uniphier-sdhc"; compatible = "socionext,uniphier-sdhc";
status = "disabled"; status = "disabled";
interrupts = <0 78 4>;
reg = <0x5a500000 0x200>; reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v"; pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>; pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>; pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio_clk 1>; clocks = <&mio_clk 1>;
reset-names = "host", "bridge", "hw-reset"; reset-names = "host", "bridge";
resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; resets = <&mio_rst 1>, <&mio_rst 4>;
bus-width = <8>; bus-width = <8>;
non-removable; non-removable;
cap-mmc-highspeed;
cap-mmc-hw-reset;
}; };
usb0: usb@5a800100 { usb0: usb@5a800100 {
@ -281,57 +390,73 @@
<&mio_rst 14>; <&mio_rst 14>;
}; };
soc-glue@5f800000 {
compatible = "socionext,uniphier-sld8-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-sld8-pinctrl";
u-boot,dm-pre-reloc;
};
};
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
clocks = <&arm_timer_clk>;
};
intc: interrupt-controller@60001000 {
compatible = "arm,cortex-a9-gic";
reg = <0x60001000 0x1000>,
<0x60000100 0x100>;
#interrupt-cells = <3>;
interrupt-controller;
};
aidet@61830000 { aidet@61830000 {
compatible = "simple-mfd", "syscon"; compatible = "simple-mfd", "syscon";
reg = <0x61830000 0x200>; reg = <0x61830000 0x200>;
}; };
};
&refclk { sysctrl@61840000 {
clock-frequency = <25000000>; compatible = "socionext,uniphier-sld8-sysctrl",
}; "simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
&serial0 { sys_clk: clock {
clock-frequency = <80000000>;
};
&serial1 {
clock-frequency = <80000000>;
};
&serial2 {
clock-frequency = <80000000>;
};
&serial3 {
interrupts = <0 29 4>;
clock-frequency = <80000000>;
};
&mio_clk {
compatible = "socionext,uniphier-sld8-mio-clock";
};
&mio_rst {
compatible = "socionext,uniphier-sld8-mio-reset";
};
&peri_clk {
compatible = "socionext,uniphier-sld8-peri-clock";
};
&peri_rst {
compatible = "socionext,uniphier-sld8-peri-reset";
};
&pinctrl {
compatible = "socionext,uniphier-sld8-pinctrl";
};
&sys_clk {
compatible = "socionext,uniphier-sld8-clock"; compatible = "socionext,uniphier-sld8-clock";
#clock-cells = <1>;
}; };
&sys_rst { sys_rst: reset {
compatible = "socionext,uniphier-sld8-reset"; compatible = "socionext,uniphier-sld8-reset";
#reset-cells = <1>;
}; };
};
nand: nand@68000000 {
compatible = "socionext,denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clocks = <&sys_clk 2>;
nand-ecc-strength = <8>;
};
};
};
/include/ "uniphier-pinctrl.dtsi"

6
arch/arm/mach-uniphier/dram/umc-ld20.c
View file

@ -1,7 +1,7 @@
/* /*
* Copyright (C) 2016 Socionext Inc. * Copyright (C) 2016 Socionext Inc.
* *
* based on commit a7a36122aa072fe1bb06e02b73b3634b7a6c555a of Diag * based on commit 5e1cb0f1caeabc6c99469dd997cb6b4f46834443 of Diag
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -264,8 +264,8 @@ static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = {
static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane, static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
unsigned int bit) unsigned int bit)
{ {
WARN_ON(lane >= (1 << PHY_LANE_SEL_LANE_WIDTH)); WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
WARN_ON(bit >= (1 << PHY_LANE_SEL_BIT_WIDTH)); WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
writel((bit << PHY_LANE_SEL_BIT_SHIFT) | writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
(lane << PHY_LANE_SEL_LANE_SHIFT), (lane << PHY_LANE_SEL_LANE_SHIFT),

6
arch/arm/mach-uniphier/memconf/memconf.c
View file

@ -1,5 +1,7 @@
/* /*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> * Copyright (C) 2011-2015 Panasonic Corporation
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -14,7 +16,7 @@
int memconf_init(const struct uniphier_board_data *bd) int memconf_init(const struct uniphier_board_data *bd)
{ {
u32 tmp = 0; u32 tmp;
unsigned long size_per_word; unsigned long size_per_word;
tmp = readl(SG_MEMCONF); tmp = readl(SG_MEMCONF);

1
configs/uniphier_ld11_defconfig
View file

@ -6,6 +6,7 @@ CONFIG_ARCH_UNIPHIER_LD11=y
CONFIG_MICRO_SUPPORT_CARD=y CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref" CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set # CONFIG_CMD_XIMG is not set

1
configs/uniphier_ld20_defconfig
View file

@ -6,6 +6,7 @@ CONFIG_ARCH_UNIPHIER_LD20=y
CONFIG_MICRO_SUPPORT_CARD=y CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
# CONFIG_CMD_XIMG is not set # CONFIG_CMD_XIMG is not set

1
configs/uniphier_ld4_sld8_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
CONFIG_MICRO_SUPPORT_CARD=y CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref" CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTZ=y

1
configs/uniphier_pro4_defconfig
View file

@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MICRO_SUPPORT_CARD=y CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref" CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTZ=y

1
configs/uniphier_pxs2_ld6b_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
CONFIG_MICRO_SUPPORT_CARD=y CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka" CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTZ=y

1
configs/uniphier_sld3_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_ARCH_UNIPHIER_SLD3=y
CONFIG_MICRO_SUPPORT_CARD=y CONFIG_MICRO_SUPPORT_CARD=y
CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_SYS_TEXT_BASE=0x84000000
CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref" CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTZ=y