mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 05:31:32 +00:00
- Remove unused bcm2835 watchdog driver (still non-DM) - Cosmetic fixup of mtk_wdt.c
This commit is contained in:
commit
fef408679b
5 changed files with 16 additions and 57 deletions
|
@ -23,11 +23,7 @@
|
||||||
/* max ticks timeout */
|
/* max ticks timeout */
|
||||||
#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
|
#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
|
||||||
|
|
||||||
#ifdef CONFIG_BCM2835_WDT
|
|
||||||
extern void hw_watchdog_disable(void);
|
|
||||||
#else
|
|
||||||
void hw_watchdog_disable(void) {}
|
void hw_watchdog_disable(void) {}
|
||||||
#endif
|
|
||||||
|
|
||||||
__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
|
__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
|
||||||
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
|
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
|
||||||
|
|
|
@ -17,15 +17,6 @@ config WATCHDOG_RESET_DISABLE
|
||||||
Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
|
Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
|
||||||
that the watchdog will not be fed in u-boot.
|
that the watchdog will not be fed in u-boot.
|
||||||
|
|
||||||
config BCM2835_WDT
|
|
||||||
bool "Enable BCM2835/2836 watchdog driver"
|
|
||||||
select HW_WATCHDOG
|
|
||||||
help
|
|
||||||
Say Y here to enable the BCM2835/2836 watchdog
|
|
||||||
|
|
||||||
This provides basic infrastructure to support BCM2835/2836 watchdog
|
|
||||||
hardware, with a max timeout of ~15secs.
|
|
||||||
|
|
||||||
config IMX_WATCHDOG
|
config IMX_WATCHDOG
|
||||||
bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
|
bool "Enable Watchdog Timer support for IMX and LSCH2 of NXP"
|
||||||
select HW_WATCHDOG if !WDT
|
select HW_WATCHDOG if !WDT
|
||||||
|
|
|
@ -20,7 +20,6 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
|
||||||
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
|
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
|
||||||
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
|
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
|
||||||
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
|
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
|
||||||
obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
|
|
||||||
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
|
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
|
||||||
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
|
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
|
||||||
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
|
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
|
||||||
|
|
|
@ -1,34 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Watchdog driver for Broadcom BCM2835
|
|
||||||
*
|
|
||||||
* Copyright (C) 2017 Paolo Pisati <p.pisati@gmail.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <efi_loader.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/arch/wdog.h>
|
|
||||||
|
|
||||||
#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
|
|
||||||
#define MAX_TIMEOUT 0xf /* ~15s */
|
|
||||||
|
|
||||||
static __efi_runtime_data bool enabled = true;
|
|
||||||
|
|
||||||
extern void reset_cpu(ulong ticks);
|
|
||||||
|
|
||||||
void hw_watchdog_reset(void)
|
|
||||||
{
|
|
||||||
if (enabled)
|
|
||||||
reset_cpu(SECS_TO_WDOG_TICKS(MAX_TIMEOUT));
|
|
||||||
}
|
|
||||||
|
|
||||||
void hw_watchdog_init(void)
|
|
||||||
{
|
|
||||||
hw_watchdog_reset();
|
|
||||||
}
|
|
||||||
|
|
||||||
void __efi_runtime hw_watchdog_disable(void)
|
|
||||||
{
|
|
||||||
enabled = false;
|
|
||||||
}
|
|
|
@ -70,9 +70,12 @@ static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
|
static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
|
||||||
{
|
{
|
||||||
struct mtk_wdt_priv *priv = dev_get_priv(dev);
|
struct mtk_wdt_priv *priv = dev_get_priv(dev);
|
||||||
|
u64 timeout_us;
|
||||||
|
u32 timeout_cc;
|
||||||
|
u32 length;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* One WDT_LENGTH count is 512 ticks of the wdt clock
|
* One WDT_LENGTH count is 512 ticks of the wdt clock
|
||||||
|
@ -88,21 +91,25 @@ static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms)
|
||||||
* The MediaTek docs lack details to know if this is the case here.
|
* The MediaTek docs lack details to know if this is the case here.
|
||||||
* So we enforce a minimum of 1 to guarantee operation.
|
* So we enforce a minimum of 1 to guarantee operation.
|
||||||
*/
|
*/
|
||||||
if(timeout_ms > 15984) timeout_ms = 15984;
|
if (timeout_ms > 15984)
|
||||||
u64 timeout_us = timeout_ms * 1000;
|
timeout_ms = 15984;
|
||||||
u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 );
|
|
||||||
if(timeout_cc == 0) timeout_cc = 1;
|
timeout_us = timeout_ms * 1000;
|
||||||
u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
|
timeout_cc = (15624 + timeout_us) / 15625;
|
||||||
|
if (timeout_cc == 0)
|
||||||
|
timeout_cc = 1;
|
||||||
|
|
||||||
|
length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
|
||||||
writel(length, priv->base + MTK_WDT_LENGTH);
|
writel(length, priv->base + MTK_WDT_LENGTH);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
|
static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
|
||||||
{
|
{
|
||||||
struct mtk_wdt_priv *priv = dev_get_priv(dev);
|
struct mtk_wdt_priv *priv = dev_get_priv(dev);
|
||||||
|
|
||||||
mtk_wdt_set_timeout(dev, timeout);
|
mtk_wdt_set_timeout(dev, timeout_ms);
|
||||||
|
|
||||||
mtk_wdt_reset(dev);
|
mtk_wdt_reset(dev);
|
||||||
|
|
||||||
/* Enable watchdog reset signal */
|
/* Enable watchdog reset signal */
|
||||||
setbits_le32(priv->base + MTK_WDT_MODE,
|
setbits_le32(priv->base + MTK_WDT_MODE,
|
||||||
|
|
Loading…
Add table
Reference in a new issue