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rockchip: clk: rk3399: allow requests for HDMI clocks

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This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF,
which are clock gates in the HDMI output path for the RK3399.

As these are enabled by default (i.e. after reset), we don't implement
any logic to actively open/close these clock gates and simply assume
that their reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Philipp Tomsich 2017-04-28 18:33:57 +02:00 • committed by Simon Glass
parent e92e580350
commit ffc1fac549
1 changed files with 7 additions and 0 deletions
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7
drivers/clk/rockchip/clk_rk3399.c
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@ -882,6 +882,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_UART0:
case SCLK_UART2:
return 24000000;
break;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
case DCLK_VOP1:
break;
@ -922,6 +925,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SPI0...SCLK_SPI5:
ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
break;
case PCLK_HDMI_CTRL:
case PCLK_VIO_GRF:
/* the PCLK gates for video are enabled by default */
break;
case DCLK_VOP0:
case DCLK_VOP1:
ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);