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powerpc/mpc8548cds: Code cleanup and refactoring
- Rework tlb and law tables. - PCI2 is not available on MPC8548CDS, so remove it. - Move the memory map to the board config file. - Rewrite the board info according to the manual. - Remove unnecessary macros and redefine some macros to align with other boards. - Fix some typos. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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34fdbdf8d9
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4 changed files with 83 additions and 105 deletions
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@ -27,36 +27,9 @@
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe10f_ffff PCI1 IO 1M
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* 0xe280_0000 0xe20f_ffff PCI2 IO 1M
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* 0xe300_0000 0xe30f_ffff PCIe IO 1M
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* 0xf000_0000 0xf3ff_ffff SDRAM 64M
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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* LAW 0 is reserved for boot mapping
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*/
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struct law_entry law_table[] = {
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#ifdef CONFIG_SYS_PCI2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
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#endif
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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/* LBC window - maps 256M */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -50,10 +50,10 @@ int checkboard (void)
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uint cpu_board_rev = get_cpu_board_revision ();
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printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
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get_board_version (), pci_slot);
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printf ("CPU Board Revision %d.%d (0x%04x)\n",
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puts("Board: MPC8548CDS");
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printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
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get_board_version(), pci_slot);
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printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
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/*
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@ -41,63 +41,63 @@ struct fsl_e_tlb_entry tlb_table[] = {
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/*
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* TLB 0: 16M Non-cacheable, guarded
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* 0xff000000 16M FLASH
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* Out of reset this entry is only 4K.
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* Entry 0:
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* FLASH(cover boot page) 16M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_16M, 1),
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/*
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* TLB 1: 1G Non-cacheable, guarded
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* 0x80000000 1G PCI1/PCIE 8,9,a,b
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1G, 1),
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/*
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* TLB 2: 256M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 3: 256M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 5: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 1M PCI1 IO
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* 0xe210_0000 1M PCI2 IO
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* 0xe300_0000 1M PCIe IO
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* Entry 1:
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* CCSRBAR 1M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_64M, 1),
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0, 1, BOOKE_PAGESZ_1M, 1),
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/*
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* TLB 6: 64M Cacheable, non-guarded
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* 0xf000_0000 64M LBC SDRAM
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* Entry 2:
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* LBC SDRAM 64M Cacheable, non-guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
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CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 6, BOOKE_PAGESZ_64M, 1),
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0, 2, BOOKE_PAGESZ_64M, 1),
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/*
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* TLB 7: 64M Non-cacheable, guarded
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* 0xf8000000 64M CADMUS registers, relocated L2SRAM
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* Entry 3:
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* CADMUS registers 1M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
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SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_64M, 1),
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0, 3, BOOKE_PAGESZ_1M, 1),
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/*
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* Entry 4:
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* PCI and PCIe MEM 1G Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1G, 1),
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/*
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* Entry 5:
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* PCI1 IO 1M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_1M, 1),
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/*
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* Entry 6:
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* PCIe IO 1M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_1M, 1),
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -106,6 +106,24 @@ extern unsigned long get_clock_freq(void);
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Physical Address Map
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*
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* 32bit:
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* 0x0000_0000 0x7fff_ffff DDR 2G cacheable
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
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* 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
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* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
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* 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
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* 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
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* 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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*/
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/*
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* Local Bus Definitions
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@ -141,16 +159,20 @@ extern unsigned long get_clock_freq(void);
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* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
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*/
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#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BR0_PRELIM 0xff801001
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#define CONFIG_SYS_BR1_PRELIM 0xff001001
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#define CONFIG_SYS_BR0_PRELIM \
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(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
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| BR_PS_16 | BR_V)
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#define CONFIG_SYS_BR1_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR0_PRELIM 0xff806e65
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#define CONFIG_SYS_OR1_PRELIM 0xff806e65
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#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
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#define CONFIG_SYS_FLASH_BANKS_LIST \
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{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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/*
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* SDRAM on the Local Bus
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*/
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#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
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#define CONFIG_SYS_LBC_CACHE_SIZE 64
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#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
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#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
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#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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/*
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* FIXME: the top 17 bits of BR2.
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*/
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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#define CONFIG_SYS_BR2_PRELIM \
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(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
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| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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#define CONFIG_FSL_CADMUS
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#define CADMUS_BASE_ADDR 0xf8000000
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#define CONFIG_SYS_BR3_PRELIM 0xf8000801
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#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
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#define CONFIG_SYS_BR3_PRELIM \
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(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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@ -326,9 +346,6 @@ extern unsigned long get_clock_freq(void);
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
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#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
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#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#ifdef CONFIG_PCI2
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#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
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#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
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#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
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#endif
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#ifdef CONFIG_PCIE1
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#define CONFIG_SYS_PCIE1_NAME "Slot"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
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/*
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* RapidIO MMU
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
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#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
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#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
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#ifdef CONFIG_LEGACY
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