6 commits

Author	SHA1	Message	Date
York Sun	ef87cab664	driver/ddr/fsl: Add support of overriding chip select write leveling ... JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>	2014-09-08 10:30:34 -07:00
York Sun	353527d527	driver/ddr/fsl: Fix printing unspecified module info for DDR4 ... The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun <yorksun@freescale.com>	2014-06-05 13:45:07 -07:00
Simon Glass	e1bf824dfd	Add cli_ prefix to readline functions ... This makes it clear where the code resides. Signed-off-by: Simon Glass <sjg@chromium.org>	2014-05-29 17:45:31 -04:00
Simon Glass	18d66533ac	move CLI prototypes to cli.h and add comments ... Move the CLI prototypes from common.h to cli.h as part of an effort to reduce the size of common.h. Signed-off-by: Simon Glass <sjg@chromium.org>	2014-05-29 17:45:31 -04:00
York Sun	34e026f9b1	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver ... Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>	2014-04-22 17:58:48 -07:00
York Sun	5614e71b49	Driver/DDR: Moving Freescale DDR driver to a common driver ... Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>	2013-11-25 11:43:43 -08:00

Renamed from arch/powerpc/cpu/mpc8xxx/ddr/interactive.c (Browse further)