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During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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.. | ||
arm_ddr_gen3.c | ||
ctrl_regs.c | ||
ddr1_dimm_params.c | ||
ddr2_dimm_params.c | ||
ddr3_dimm_params.c | ||
ddr4_dimm_params.c | ||
fsl_ddr_gen4.c | ||
interactive.c | ||
lc_common_dimm_params.c | ||
main.c | ||
Makefile | ||
mpc85xx_ddr_gen1.c | ||
mpc85xx_ddr_gen2.c | ||
mpc85xx_ddr_gen3.c | ||
mpc86xx_ddr.c | ||
options.c | ||
util.c |