Lukas Auer 1446b26f76 riscv: save hart ID in register tp instead of s0 ... The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>		2019-04-08 09:44:26 +08:00
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cpu	riscv: save hart ID in register tp instead of s0	2019-04-08 09:44:26 +08:00
dts	riscv: Remove ae350.dts	2018-12-18 09:56:27 +08:00
include/asm	riscv: import the supervisor binary interface header file	2019-04-08 09:44:25 +08:00
lib	riscv: implement IPI platform functions using SBI	2019-04-08 09:44:26 +08:00
config.mk	riscv: qemu: define standalone load address	2019-01-15 09:36:31 +08:00
Kconfig	riscv: implement IPI platform functions using SBI	2019-04-08 09:44:26 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00