Siva Durga Prasad Paladugu 5473f245d0 arm64: zynqmp: Fix logic in CG/EG/EV detection ... The VCU disable bit(8) in IP disable register of efuse is valid only if PL powered up and hence PL powerup status has to be considered while determining the CG part also. This patch considers the PL powerup status and ignores the VCU disable bit if PL not powered up. This fixes the issue of "unknown" id for CG parts if PL not powered up and VCU bit(8) is not set. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2018-11-26 10:50:54 +01:00
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microblaze-generic	microblaze: Add missing quotes around XILINX_MICROBLAZE0_HW_VER	2018-08-06 08:44:35 +02:00
versal	arm64: versal: Add support for new Xilinx Versal ACAPs	2018-10-16 16:53:21 +02:00
zynq	arm: zynq: Add support for DLC20 board	2018-10-16 14:58:45 +02:00
zynqmp	arm64: zynqmp: Fix logic in CG/EG/EV detection	2018-11-26 10:50:54 +01:00
zynqmp_r5	lib: fdtdec: Rename routine fdtdec_setup_memory_size()	2018-07-19 10:49:56 +02:00
Kconfig	arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig variable	2018-07-19 10:49:53 +02:00