mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-04-26 00:01:30 +00:00
This commit adds support for 96Boards Dragonboard820C. The board is based on APQ8086 Qualcomm Soc, complying with the 96Boards specification. Features - 4x Kyro CPU (64 bit) up to 2.15GHz - USB2.0 - USB3.0 - ISP - Qualcomm Hexagon DSP - SD 3.0 (UHS-I) - UFS 2.0 - Qualcomm Adreno 530 GPU - GPS - BT 4.2 - Wi-Fi 2.4GHz, 5GHz (802.11ac) - PCIe 2.0 - MIPI-CSI, MIPI-DSI - I2S U-Boot boots chained from LK (LK implements the fastboot protocol) in 64-bit mode. For detailed build instructions see readme.txt in the board directory. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
29 lines
749 B
C
29 lines
749 B
C
/*
|
|
* Qualcomm APQ8096 sysmap
|
|
*
|
|
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
#ifndef _MACH_SYSMAP_APQ8096_H
|
|
#define _MACH_SYSMAP_APQ8096_H
|
|
|
|
#define TLMM_BASE_ADDR (0x1010000)
|
|
|
|
/* Strength (sdc1) */
|
|
#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
|
|
|
|
/* Clocks: (from CLK_CTL_BASE) */
|
|
#define GPLL0_STATUS (0x0000)
|
|
#define APCS_GPLL_ENA_VOTE (0x52000)
|
|
|
|
#define SDCC2_BCR (0x14000) /* block reset */
|
|
#define SDCC2_APPS_CBCR (0x14004) /* branch control */
|
|
#define SDCC2_AHB_CBCR (0x14008)
|
|
#define SDCC2_CMD_RCGR (0x14010)
|
|
#define SDCC2_CFG_RCGR (0x14014)
|
|
#define SDCC2_M (0x14018)
|
|
#define SDCC2_N (0x1401C)
|
|
#define SDCC2_D (0x14020)
|
|
|
|
#endif
|