Marek Vasut 9da1d8f5b4 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 ... The read_group and write_group params have the same value for all (one) invocations of this function, just merge them into a single param. Signed-off-by: Marek Vasut <marex@denx.de>		2015-08-08 14:14:18 +02:00
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altera	ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2	2015-08-08 14:14:18 +02:00
fsl	drivers/ddr/fsl: Adjust bstopre value	2015-08-03 12:06:38 -07:00
marvell	arm: mvebu: a38x: Use correct PEX register access macros	2015-07-23 10:39:25 +02:00