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Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
18 lines
503 B
C
18 lines
503 B
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SOCFPGA_BASE_ADDRS_H_
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#define _SOCFPGA_BASE_ADDRS_H_
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#define SOCFPGA_L3REGS_ADDRESS 0xff800000
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#define SOCFPGA_UART0_ADDRESS 0xffc02000
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#define SOCFPGA_UART1_ADDRESS 0xffc03000
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#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
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#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
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#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
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#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
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#endif /* _SOCFPGA_BASE_ADDRS_H_ */
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