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soc: sifive: ccache: Add StarFive JH71x0 support
This adds support for the StarFive JH7100 and JH7110 SoCs which also feature this SiFive cache controller. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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parent
978c0ca11f
commit
0e409232a9
4 changed files with 15 additions and 3 deletions
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@ -25,6 +25,8 @@ config SOC_STARFIVE
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bool "StarFive SoCs"
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select PINCTRL
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select RESET_CONTROLLER
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select SIFIVE_CCACHE
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select SIFIVE_PLIC
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help
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This enables support for StarFive SoC platform hardware.
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@ -27,7 +27,7 @@ obj-y += qcom/
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obj-y += renesas/
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obj-y += rockchip/
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obj-$(CONFIG_SOC_SAMSUNG) += samsung/
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obj-$(CONFIG_SOC_SIFIVE) += sifive/
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obj-y += sifive/
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obj-y += sunxi/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-y += ti/
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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if SOC_SIFIVE
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if SOC_SIFIVE || SOC_STARFIVE
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config SIFIVE_CCACHE
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bool "Sifive Composable Cache controller"
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@ -106,6 +106,8 @@ static void ccache_config_read(void)
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static const struct of_device_id sifive_ccache_ids[] = {
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{ .compatible = "sifive,fu540-c000-ccache" },
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{ .compatible = "sifive,fu740-c000-ccache" },
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{ .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
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{ .compatible = "starfive,jh7110-ccache" },
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{ .compatible = "sifive,ccache0" },
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{ /* end of table */ }
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};
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@ -210,11 +212,15 @@ static int __init sifive_ccache_init(void)
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struct device_node *np;
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struct resource res;
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int i, rc, intr_num;
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const struct of_device_id *match;
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unsigned long broken_irqs;
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np = of_find_matching_node(NULL, sifive_ccache_ids);
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np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
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if (!np)
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return -ENODEV;
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broken_irqs = (uintptr_t)match->data;
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if (of_address_to_resource(np, 0, &res)) {
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rc = -ENODEV;
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goto err_node_put;
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@ -240,6 +246,10 @@ static int __init sifive_ccache_init(void)
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for (i = 0; i < intr_num; i++) {
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g_irq[i] = irq_of_parse_and_map(np, i);
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if (broken_irqs & BIT(i))
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continue;
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rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
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NULL);
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if (rc) {
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