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soc: sifive: ccache: Add StarFive JH71x0 support

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This adds support for the StarFive JH7100 and JH7110 SoCs which also
feature this SiFive cache controller.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
This commit is contained in:
Emil Renner Berthing 2022-04-06 00:38:05 +02:00 • committed by Emil Renner Berthing
parent 978c0ca11f
commit 0e409232a9
4 changed files with 15 additions and 3 deletions
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2
arch/riscv/Kconfig.socs
View file

@ -25,6 +25,8 @@ config SOC_STARFIVE
bool "StarFive SoCs"
select PINCTRL
select RESET_CONTROLLER
select SIFIVE_CCACHE
select SIFIVE_PLIC
help
This enables support for StarFive SoC platform hardware.

2
drivers/soc/Makefile
View file

@ -27,7 +27,7 @@ obj-y += qcom/
obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-$(CONFIG_SOC_SIFIVE) += sifive/
obj-y += sifive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/

2
drivers/soc/sifive/Kconfig
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
if SOC_SIFIVE
if SOC_SIFIVE || SOC_STARFIVE
config SIFIVE_CCACHE
bool "Sifive Composable Cache controller"

12
drivers/soc/sifive/sifive_ccache.c
View file

@ -106,6 +106,8 @@ static void ccache_config_read(void)
static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
{ .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
{ .compatible = "starfive,jh7110-ccache" },
{ .compatible = "sifive,ccache0" },
{ /* end of table */ }
};
@ -210,11 +212,15 @@ static int __init sifive_ccache_init(void)
struct device_node *np;
struct resource res;
int i, rc, intr_num;
const struct of_device_id *match;
unsigned long broken_irqs;
np = of_find_matching_node(NULL, sifive_ccache_ids);
np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
if (!np)
return -ENODEV;
broken_irqs = (uintptr_t)match->data;
if (of_address_to_resource(np, 0, &res)) {
rc = -ENODEV;
goto err_node_put;
@ -240,6 +246,10 @@ static int __init sifive_ccache_init(void)
for (i = 0; i < intr_num; i++) {
g_irq[i] = irq_of_parse_and_map(np, i);
if (broken_irqs & BIT(i))
continue;
rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
NULL);
if (rc) {