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dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property

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Add the 'uncached-offset' property to be used for specifying the
uncached memory offset required for handling non-coherent DMA
transactions.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230211031821.976408-3-cristian.ciocaltea@collabora.com
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Cristian Ciocaltea 2023-02-11 05:18:11 +02:00 • committed by Emil Renner Berthing
parent 0e409232a9
commit 944a2191d3
1 changed files with 5 additions and 0 deletions
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Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
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@ -74,6 +74,11 @@ properties:
next-level-cache: true
uncached-offset:
$ref: /schemas/types.yaml#/definitions/uint64
description: |
Uncached memory offset for handling non-coherent DMA transactions.
memory-region:
maxItems: 1
description: |