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dt-bindings: pinctrl: Add bindings for StarFive JH7110 pinctrl
Add bindings for StarFive JH7110 pinctrl Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Pin Controller Device Tree Bindings
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description: |
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Bindings for the JH7110 RISC-V SoC from StarFive Ltd.
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maintainers:
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- Jianlong Huang <jianlong.huang@starfivetech.com>
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properties:
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compatible:
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enum:
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- starfive,jh7110-sys-pinctrl
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- starfive,jh7110-aon-pinctrl
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reg:
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minItems: 2
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maxItems: 2
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reg-names:
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items:
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- const: control
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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"#gpio-cells":
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const: 2
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interrupts:
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maxItems: 1
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description: The GPIO parent interrupt.
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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ngpios:
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enum:
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- 64
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- 4
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- "#gpio-cells"
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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examples:
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- |
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gpio: gpio@13040000 {
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compatible = "starfive,jh7110-sys-pinctrl";
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reg = <0x0 0x13040000 0x0 0x10000>;
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reg-names = "control";
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clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
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resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
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interrupts = <86>;
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interrupt-controller;
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#gpio-cells = <2>;
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ngpios = <64>;
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status = "okay";
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};
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...
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@ -20847,3 +20847,8 @@ M: Jianlong Huang <jianlong.huang@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/riscv/starfive-jh7110.yaml
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STARFIVE JH7110 PINCTRL
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M: Jianlong Huang <jianlong.huang@starfivetech.com>
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S: Maintained
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F: Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml
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