dt-bindings: pinctrl: Add bindings for StarFive JH7110 pinctrl

Add bindings for StarFive JH7110 pinctrl

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
This commit is contained in:
Jianlong Huang 2022-08-25 16:30:11 +08:00
parent 86a842cd55
commit e47b60eae9
2 changed files with 82 additions and 0 deletions

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 Pin Controller Device Tree Bindings
description: |
Bindings for the JH7110 RISC-V SoC from StarFive Ltd.
maintainers:
- Jianlong Huang <jianlong.huang@starfivetech.com>
properties:
compatible:
enum:
- starfive,jh7110-sys-pinctrl
- starfive,jh7110-aon-pinctrl
reg:
minItems: 2
maxItems: 2
reg-names:
items:
- const: control
clocks:
maxItems: 1
resets:
maxItems: 1
"#gpio-cells":
const: 2
interrupts:
maxItems: 1
description: The GPIO parent interrupt.
interrupt-controller: true
"#interrupt-cells":
const: 2
ngpios:
enum:
- 64
- 4
required:
- compatible
- reg
- reg-names
- clocks
- "#gpio-cells"
- interrupts
- interrupt-controller
- "#interrupt-cells"
examples:
- |
gpio: gpio@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
reg-names = "control";
clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
interrupts = <86>;
interrupt-controller;
#gpio-cells = <2>;
ngpios = <64>;
status = "okay";
};
...

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@ -20847,3 +20847,8 @@ M: Jianlong Huang <jianlong.huang@starfivetech.com>
S: Maintained
F: Documentation/devicetree/bindings/riscv/starfive-jh7110.yaml
STARFIVE JH7110 PINCTRL
M: Jianlong Huang <jianlong.huang@starfivetech.com>
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml