Commit graph

1199858 commits

Author SHA1 Message Date
Hal Feng
67e8df01b8 [NOT-FOR-UPSTREAM] Add readme 2023-08-15 15:40:50 +08:00
Hal Feng
5db37e0445 [NOT-FOR-UPSTREAM] Add starfive_visionfive2_defconfig for test
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-08-15 15:16:25 +08:00
Hal Feng
7629caabd7 MAINTAINERS: Update all StarFive entries
Merge all StarFive maintainers changes together.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-08-15 14:53:11 +08:00
Hal Feng
659c33e796 riscv: dts: starfive: Add full support for JH7110 and VisionFive 2 board
Merge all StarFive dts patches together.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-08-15 14:53:11 +08:00
Keith Zhao
12ff0d9ae3 drm/vs: Add hdmi
add hdmi driver as encoder and connect

Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-08-15 14:53:11 +08:00
Keith Zhao
22dcdb8337 drm/vs: Add KMS crtc&plane
add 2 crtcs and 8 planes in vs-drm

Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-08-15 14:53:11 +08:00
Keith Zhao
b1a534b903 drm/vs: Register DRM device
Implement drm device registration interface

Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-08-15 14:53:10 +08:00
Keith Zhao
0595505eb7 drm/fourcc: Add drm/vs tiled modifiers
These are mainly used internally in vs-drm,
I'm not sure if the new modifiers can be used with the existing ones.
If there is a problem, I will improve it further.

Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-08-15 14:53:10 +08:00
Keith Zhao
ca62b1dec0 dt-bindings: display: Add yamls for JH7110 display system
StarFive SoCs JH7110 display system:
lcd-controller bases verisilicon dc8200 IP,
and hdmi bases Innosilicon IP.
Add bindings for them.

Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
ee830e175b media: starfive: camss: Add VIN driver
Add Video In Controller driver for StarFive Camera Subsystem.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
6895697d6d media: starfive: camss: Add ISP driver
Add ISP driver for StarFive Camera Subsystem.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
769f44952e media: starfive: camss: Add video driver
Add video driver for StarFive Camera Subsystem.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
082c341ba0 media: starfive: camss: Add basic driver
Add basic platform driver for StarFive Camera Subsystem.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
3e59c19f82 media: admin-guide: Add starfive_camss.rst for Starfive Camera Subsystem
Add starfive_camss.rst file that documents the Starfive Camera
Subsystem driver which is used for handing image sensor data.

Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
b58c7477ae media: dt-bindings: Add JH7110 Camera Subsystem
Add the bindings documentation for Starfive JH7110 Camera Subsystem
which is used for handing image sensor data.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
2023-08-15 14:53:10 +08:00
Jack Zhu
a719fdcb69 media: cadence: Add support for JH7110 SoC
Add support for Starfive JH7110 SoC which has the cadence csi2 receiver.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2023-08-15 14:53:10 +08:00
Jack Zhu
ac200a088c media: cadence: Add support for external dphy
Add support for external MIPI D-PHY.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2023-08-15 14:53:10 +08:00
Jack Zhu
3eca1c84b3 media: cadence: Add operation on reset
Add operation on reset for Cadence MIPI-CSI2 RX Controller.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2023-08-15 14:53:10 +08:00
Jack Zhu
43acdcf5b9 media: dt-bindings: cadence-csi2rx: Add resets property
Add resets property for Cadence MIPI-CSI2 RX controller

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2023-08-15 14:53:09 +08:00
Jack Zhu
00aff4ee54 media: dt-bindings: cadence-csi2rx: Convert to DT schema
Convert DT bindings document for Cadence MIPI-CSI2 RX controller to
DT schema format.

For compatible, new compatibles should not be messed with conversion,
but the original binding did not specify any SoC-specific compatible
string, so add the StarFive compatible string.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2023-08-15 14:53:09 +08:00
Geert Uytterhoeven
8d889b365c phy: starfive: StarFive PHYs should depend on ARCH_STARFIVE
The various StarFive PHYs are only present on StarFive SoCs.  Hence add
a dependency on ARCH_STARFIVE, to prevent asking the user about these
drivers when configuring a kernel without StarFive SoC support.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://lore.kernel.org/r/12097f6107a18e2f7cfb80f47ac7b27808e062c4.1690300076.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-15 14:53:09 +08:00
Vinod Koul
7323800556 phy: starfive: make phys depend on HAS_IOMEM
the startfive phy drivers use devm_platform_ioremap_resource() which on
some archs (s390) is not present. So make the drivers depend on HAS_IOMEM

Fixes: f8aa660841 ("phy: starfive: Add mipi dphy rx support")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202307250509.oeudxG28-lkp@intel.com/
Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20230725063856.482696-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-15 14:53:09 +08:00
Changhuang Liang
17eedd103e phy: starfive: Add mipi dphy rx support
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
transfer CSI camera data.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Minda Chen <minda.chen@starfivetech.com>
Link: https://lore.kernel.org/r/20230718070803.16660-3-changhuang.liang@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-15 14:53:09 +08:00
Changhuang Liang
05ad2cfcb0 dt-bindings: phy: Add starfive,jh7110-dphy-rx
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718070803.16660-2-changhuang.liang@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-15 14:53:09 +08:00
Changhuang Liang
7559d06257 soc: starfive: Add JH7110 AON PMU support
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
dphy rx/tx power switch.

Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:09 +08:00
Changhuang Liang
8110a6a510 soc: starfive: Extract JH7110 pmu private operations
Move JH7110 private operation into private data of compatible. Convenient
to add AON PMU which would not have interrupts property.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:09 +08:00
Changhuang Liang
d5cd8b4fa2 soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE
Using ARCH_FOO symbol is preferred than SOC_FOO.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:09 +08:00
Changhuang Liang
916794cb93 dt-bindings: power: Add power-domain header for JH7110
Add power-domain header for JH7110 SoC, it can use to operate dphy
power.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:09 +08:00
Xingyu Wu
877f6906ca riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1
These pins are actually I2STX1 clock input, not I2STX0,
so their names should be changed.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-08-15 14:53:09 +08:00
Xingyu Wu
9fd4ed8ced ASoC: dwc: i2s: Add StarFive JH7110 SoC support
Add StarFive JH7110(TX0/TX1/RX channels) SoC support in the
designware I2S driver and a flag to check if it is on the JH7110 SoC.

These channels need to enable clocks, resets and syscon register on the
JH7110 SoC. So add init ops in platform data for the JH7110 SoC to do this.
Their resets should be deassert before changing the parent of clocks so
these are done in the init ops of platform data. The I2S controllers use
DMA controller by platform data on the JH7110 and these settings about
snd_dmaengine_dai_dma_data() should be added in the
dw_configure_dai_by_pd(). And use dmaengine PCM registration if these
do not have IRQ on the JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-08-15 14:53:09 +08:00
Xingyu Wu
ed0677fcce ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
of Designware I2S controller. The I2S controller needs two reset items
to work properly on the JH7110 SoC. And TX0 channel as master mode needs
5 clock items and TX1/RX channels as slave mode need 9 clock items on
the JH7110 SoC. The RX channel needs System Register Controller property
to enable it and other platforms do not need it.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-08-15 14:53:08 +08:00
Xingyu Wu
e3c3001b66 ASoC: dwc: Use ops to get platform data
Use of_device_get_match_data() to get platform data.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
2023-08-15 14:53:08 +08:00
Hal Feng
1cf055937a ASoC: starfive: Add JH7110 PWM-DAC driver
Add PWM-DAC driver support for the StarFive JH7110 SoC.

Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-08-15 14:53:08 +08:00
Hal Feng
a7106268b4 ASoC: dt-bindings: Add StarFive JH7110 PWM-DAC controller
Add bindings for the PWM-DAC controller on the JH7110
RISC-V SoC by StarFive Ltd.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-08-15 14:53:08 +08:00
Uwe Kleine-König
0a3752e0df ASoC: starfive: jh7110_tdm: Convert to platform remove callback returning void
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new() which already returns void. Eventually after all drivers
are converted, .remove_new() is renamed to .remove().

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230707072830.3395789-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
2023-08-15 14:53:08 +08:00
Minda Chen
8b02ee43b9 PCI: starfive: Add JH7110 PCIe controller
Add StarFive JH7110 SoC PCIe controller platform
driver codes, and add host init/deinit to pcie-plda-host.c

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Co-developed-by: Kevin Xie <kevin.xie@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
2023-08-15 14:53:08 +08:00
Minda Chen
6876665317 dt-bindings: PCI: Add StarFive JH7110 PCIe controller
Add StarFive JH7110 SoC PCIe controller dt-bindings.
JH7110 using PLDA XpressRICH PCIe host controller IP.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:08 +08:00
Minda Chen
e88f7346fd PCI: microchip: Move IRQ init functions to pcie-plda-host.c
Move IRQ init functions to pcie-plda-host.c. mc_handle_event
merge to plda_handle_event, Add get_events functions,
PolarFire PCIe uses get_events function pointer to get
their events num.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-15 14:53:08 +08:00
Minda Chen
a309a06d07 PCI: microchip: Rename IRQ init function
Rename IRQ init function and prepare for re-use
IRQ init function.

rename list:
mc_init_interrupts -> plda_init_interrupts
mc_pcie_init_irq_domain-> plda_pcie_init_irq_domains

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-15 14:53:08 +08:00
Minda Chen
0e66b56b1f PCI: plda: Add event interrupt codes and IRQ domain ops
For PolarFire implements non-PLDA local interrupt events, most of
event interrupt process codes can not be re-used. PLDA implements
new codes and IRQ domain ops like PolarFire.

plda_handle_event adds a new IRQ num to event num mapping codes for
PLDA local event except DMA engine interrupt events. The DMA engine
interrupt events are implemented by vendors.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-15 14:53:08 +08:00
Minda Chen
439334b869 PCI: plda: Move the common functions to pcie-plda-host.c
Move MSI IRQ, INTx IRQ and setup functions to common
pcie-plda-host.c.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:08 +08:00
Minda Chen
2221063ca3 PCI: microchip: Rename data structure and functions
Rename mc_* to plda_* for common data structures,
setup and IRQ functions.

The modification includes:
- Add related data structures of PCIe host instance.
  mc_pcie --> plda_pcie_rp (Get most of data members)
  mc_msi  --> plda_msi
- function rename list:
  mc_pcie_setup_window     --> plda_pcie_setup_window
  mc_pcie_setup_windows    --> plda_pcie_setup_iomems
  mc_allocate_msi_domains  --> plda_allocate_msi_domains
  MSI interrupts related functions and IRQ domain
  (primary function is mc_handle_msi):
  mc_handle_msi            --> plda_handle_msi
  INTx interrupts related functions and IRQ domain
  (primary function is mc_handle_intx):
  mc_handle_intx           --> plda_handle_intx

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:08 +08:00
Minda Chen
a2ae0382aa PCI: microchip: Move PLDA IP register macros to pcie-plda.h
Move PLDA PCIe host controller IP registers macros to
pcie-plda.h, Including bridge and configuration space
registers.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Minda Chen
c2917fdfdc PCI: microchip: Move pcie-microchip-host.c to plda directory
For Microchip Polarfire PCIe host is PLDA XpressRich IP,
move to plda directory. Prepare for refactor the codes.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Minda Chen
f7af66821f dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties
Add PLDA XpressRICH PCIe host common properties dt-binding doc.
Microchip PolarFire PCIe host using PLDA IP.
Move common properties from Microchip PolarFire PCIe host
to PLDA files.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Daire McNamara
92ed02d039 PCI: microchip: Re-partition code between probe() and init()
Continuing to use pci_host_common_probe() for the PCIe Root Complex on
PolarFire SoC is leading to an extremely large _init() function and some
unnatural code flow. Re-partition the code so that some tasks are done
in a _probe() routine, which calls pci_host_common_probe() and then use
a much smaller _init() function, mainly to enable interrupts after
address translation tables are set up.

Link: https://lore.kernel.org/r/20230728131401.1615724-8-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Daire McNamara
59a637c6c4 PCI: microchip: Gather MSI information from hardware config registers
The PCIe Root Complex on PolarFire SoC is configured at bitstream creation
time using Libero. Key MSI-related parameters include the number of
MSIs (1/2/4/8/16/32) and the MSI address. In the device driver, extract
this information from hardware registers at init time, and use it to configure
MSI system, including configuring MSI capability structure correctly in
configuration space.

Link: https://lore.kernel.org/r/20230728131401.1615724-7-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Daire McNamara
b80db06212 PCI: microchip: Clean up initialisation of interrupts
Refactor interrupt handling in _init() function into
disable_interrupts(), init_interrupts(), clear_sec_errors() and clear
ded_errors() because current code is unwieldy and prone to bugs.

Disable interrupts as soon as possible and only enable interrupts after
address translation is setup to prevent spurious axi2pcie and pcie2axi
translation errors being reported.

Link: https://lore.kernel.org/r/20230728131401.1615724-6-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Daire McNamara
c34d65b884 PCI: microchip: Enable event handlers to access bridge and control pointers
Minor re-organisation so that event handlers can access both a pointer
to the bridge area of the PCIe Root Port and the control area of the PCIe
Root Port.

Link: https://lore.kernel.org/r/20230728131401.1615724-5-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00
Daire McNamara
4118b54037 PCI: microchip: Align register, offset, and mask names with HW docs
Minor code re-organisation so that macros representing registers ascend in
numerical order and use the same names as their hardware documentation.
Removed registers not used by the driver.

Link: https://lore.kernel.org/r/20230728131401.1615724-4-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15 14:53:07 +08:00