These are mainly used internally in vs-drm,
I'm not sure if the new modifiers can be used with the existing ones.
If there is a problem, I will improve it further.
Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
Add starfive_camss.rst file that documents the Starfive Camera
Subsystem driver which is used for handing image sensor data.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add the bindings documentation for Starfive JH7110 Camera Subsystem
which is used for handing image sensor data.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add support for Starfive JH7110 SoC which has the cadence csi2 receiver.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Convert DT bindings document for Cadence MIPI-CSI2 RX controller to
DT schema format.
For compatible, new compatibles should not be messed with conversion,
but the original binding did not specify any SoC-specific compatible
string, so add the StarFive compatible string.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
The various StarFive PHYs are only present on StarFive SoCs. Hence add
a dependency on ARCH_STARFIVE, to prevent asking the user about these
drivers when configuring a kernel without StarFive SoC support.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://lore.kernel.org/r/12097f6107a18e2f7cfb80f47ac7b27808e062c4.1690300076.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
transfer CSI camera data.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Minda Chen <minda.chen@starfivetech.com>
Link: https://lore.kernel.org/r/20230718070803.16660-3-changhuang.liang@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718070803.16660-2-changhuang.liang@starfivetech.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the
dphy rx/tx power switch.
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Move JH7110 private operation into private data of compatible. Convenient
to add AON PMU which would not have interrupts property.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add power-domain header for JH7110 SoC, it can use to operate dphy
power.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add StarFive JH7110(TX0/TX1/RX channels) SoC support in the
designware I2S driver and a flag to check if it is on the JH7110 SoC.
These channels need to enable clocks, resets and syscon register on the
JH7110 SoC. So add init ops in platform data for the JH7110 SoC to do this.
Their resets should be deassert before changing the parent of clocks so
these are done in the init ops of platform data. The I2S controllers use
DMA controller by platform data on the JH7110 and these settings about
snd_dmaengine_dai_dma_data() should be added in the
dw_configure_dai_by_pd(). And use dmaengine PCM registration if these
do not have IRQ on the JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
of Designware I2S controller. The I2S controller needs two reset items
to work properly on the JH7110 SoC. And TX0 channel as master mode needs
5 clock items and TX1/RX channels as slave mode need 9 clock items on
the JH7110 SoC. The RX channel needs System Register Controller property
to enable it and other platforms do not need it.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Add PWM-DAC driver support for the StarFive JH7110 SoC.
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Add bindings for the PWM-DAC controller on the JH7110
RISC-V SoC by StarFive Ltd.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve here there is a quest to make the remove callback return
void. In the first step of this quest all drivers are converted to
.remove_new() which already returns void. Eventually after all drivers
are converted, .remove_new() is renamed to .remove().
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230707072830.3395789-3-u.kleine-koenig@pengutronix.de
Signed-off-by: Mark Brown <broonie@kernel.org>
Move IRQ init functions to pcie-plda-host.c. mc_handle_event
merge to plda_handle_event, Add get_events functions,
PolarFire PCIe uses get_events function pointer to get
their events num.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
For PolarFire implements non-PLDA local interrupt events, most of
event interrupt process codes can not be re-used. PLDA implements
new codes and IRQ domain ops like PolarFire.
plda_handle_event adds a new IRQ num to event num mapping codes for
PLDA local event except DMA engine interrupt events. The DMA engine
interrupt events are implemented by vendors.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Rename mc_* to plda_* for common data structures,
setup and IRQ functions.
The modification includes:
- Add related data structures of PCIe host instance.
mc_pcie --> plda_pcie_rp (Get most of data members)
mc_msi --> plda_msi
- function rename list:
mc_pcie_setup_window --> plda_pcie_setup_window
mc_pcie_setup_windows --> plda_pcie_setup_iomems
mc_allocate_msi_domains --> plda_allocate_msi_domains
MSI interrupts related functions and IRQ domain
(primary function is mc_handle_msi):
mc_handle_msi --> plda_handle_msi
INTx interrupts related functions and IRQ domain
(primary function is mc_handle_intx):
mc_handle_intx --> plda_handle_intx
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Move PLDA PCIe host controller IP registers macros to
pcie-plda.h, Including bridge and configuration space
registers.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Continuing to use pci_host_common_probe() for the PCIe Root Complex on
PolarFire SoC is leading to an extremely large _init() function and some
unnatural code flow. Re-partition the code so that some tasks are done
in a _probe() routine, which calls pci_host_common_probe() and then use
a much smaller _init() function, mainly to enable interrupts after
address translation tables are set up.
Link: https://lore.kernel.org/r/20230728131401.1615724-8-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
The PCIe Root Complex on PolarFire SoC is configured at bitstream creation
time using Libero. Key MSI-related parameters include the number of
MSIs (1/2/4/8/16/32) and the MSI address. In the device driver, extract
this information from hardware registers at init time, and use it to configure
MSI system, including configuring MSI capability structure correctly in
configuration space.
Link: https://lore.kernel.org/r/20230728131401.1615724-7-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Refactor interrupt handling in _init() function into
disable_interrupts(), init_interrupts(), clear_sec_errors() and clear
ded_errors() because current code is unwieldy and prone to bugs.
Disable interrupts as soon as possible and only enable interrupts after
address translation is setup to prevent spurious axi2pcie and pcie2axi
translation errors being reported.
Link: https://lore.kernel.org/r/20230728131401.1615724-6-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Minor re-organisation so that event handlers can access both a pointer
to the bridge area of the PCIe Root Port and the control area of the PCIe
Root Port.
Link: https://lore.kernel.org/r/20230728131401.1615724-5-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Minor code re-organisation so that macros representing registers ascend in
numerical order and use the same names as their hardware documentation.
Removed registers not used by the driver.
Link: https://lore.kernel.org/r/20230728131401.1615724-4-daire.mcnamara@microchip.com
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
