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[feat] add bl602 driver and board

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jzlv 2021-06-04 17:53:16 +08:00
parent 8db230f7c4
commit bc120c8861
123 changed files with 94252 additions and 0 deletions
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30
bsp/board/bl602_iot/bl602_config.h Normal file
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/**
* @file bl602_config.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __BL702_CONFIG_H__
#define __BL702_CONFIG_H__
#include "peripheral_config.h"
#include "clock_config.h"
#endif

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bsp/board/bl602_iot/board.c Normal file
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/**
* @file board.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_gpio.h"
#include "hal_clock.h"
#include "bl602_glb.h"
#include "pinmux_config.h"
struct pin_mux_cfg
{
uint8_t pin;
uint16_t func;
};
static const struct pin_mux_cfg af_pin_table[] =
{
{
.pin = GPIO_PIN_0,
.func = CONFIG_GPIO0_FUNC
},
{
.pin = GPIO_PIN_1,
.func = CONFIG_GPIO1_FUNC
},
{
.pin = GPIO_PIN_2,
.func = CONFIG_GPIO2_FUNC
},
{
.pin = GPIO_PIN_3,
.func = CONFIG_GPIO3_FUNC
},
{
.pin = GPIO_PIN_4,
.func = CONFIG_GPIO4_FUNC
},
{
.pin = GPIO_PIN_5,
.func = CONFIG_GPIO5_FUNC
},
{
.pin = GPIO_PIN_6,
.func = CONFIG_GPIO6_FUNC
},
{
.pin = GPIO_PIN_7,
.func = CONFIG_GPIO7_FUNC
},
{
.pin = GPIO_PIN_8,
.func = CONFIG_GPIO8_FUNC
},
{
.pin = GPIO_PIN_9,
.func = CONFIG_GPIO9_FUNC
},
{
.pin = GPIO_PIN_10,
.func = CONFIG_GPIO10_FUNC
},
{
.pin = GPIO_PIN_11,
.func = CONFIG_GPIO11_FUNC
},
{
.pin = GPIO_PIN_12,
.func = CONFIG_GPIO12_FUNC
},
{
.pin = GPIO_PIN_13,
.func = CONFIG_GPIO13_FUNC
},
{
.pin = GPIO_PIN_14,
.func = CONFIG_GPIO14_FUNC
},
{
.pin = GPIO_PIN_15,
.func = CONFIG_GPIO15_FUNC
},
{
.pin = GPIO_PIN_16,
.func = CONFIG_GPIO16_FUNC
},
{
.pin = GPIO_PIN_17,
.func = CONFIG_GPIO17_FUNC
},
{
.pin = GPIO_PIN_18,
.func = CONFIG_GPIO18_FUNC
},
{
.pin = GPIO_PIN_19,
.func = CONFIG_GPIO19_FUNC
},
{
.pin = GPIO_PIN_20,
.func = CONFIG_GPIO20_FUNC
},
{
.pin = GPIO_PIN_21,
.func = CONFIG_GPIO21_FUNC
},
{
.pin = GPIO_PIN_22,
.func = CONFIG_GPIO22_FUNC
},
{
.pin = GPIO_PIN_23,
.func = CONFIG_GPIO23_FUNC
},
{
.pin = GPIO_PIN_24,
.func = CONFIG_GPIO24_FUNC
},
{
.pin = GPIO_PIN_25,
.func = CONFIG_GPIO25_FUNC
},
{
.pin = GPIO_PIN_26,
.func = CONFIG_GPIO26_FUNC
},
{
.pin = GPIO_PIN_27,
.func = CONFIG_GPIO27_FUNC
},
{
.pin = GPIO_PIN_28,
.func = CONFIG_GPIO28_FUNC
},
};
static void board_pin_mux_init(void)
{
GLB_GPIO_Cfg_Type gpio_cfg;
gpio_cfg.drive = 0;
gpio_cfg.smtCtrl = 1;
for (int i = 0; i < sizeof(af_pin_table)/sizeof(af_pin_table[0]); i++)
{
gpio_cfg.gpioMode = GPIO_MODE_AF;
gpio_cfg.pullType = GPIO_PULL_UP;
gpio_cfg.gpioPin = af_pin_table[i].pin;
gpio_cfg.gpioFun = af_pin_table[i].func;
if(af_pin_table[i].func == GPIO_FUN_UNUSED)
{
continue;
}
else if(af_pin_table[i].func == GPIO_FUN_PWM)
{
gpio_cfg.pullType = GPIO_PULL_DOWN;
}
// else if((af_pin_table[i].func == GPIO_FUN_DAC)|| (af_pin_table[i].func == GPIO_FUN_DAC))
// {
// gpio_cfg.gpioFun = GPIO_FUN_ANALOG;
// gpio_cfg.gpioMode = GPIO_MODE_ANALOG;
// }
else if((af_pin_table[i].func & 0x70) == 0x70)
{
gpio_cfg.gpioFun = GPIO_FUN_UART;
uint8_t sig = af_pin_table[i].func & 0x07;
GLB_UART_Fun_Sel((gpio_cfg.gpioPin % 8), sig);
}
GLB_GPIO_Init(&gpio_cfg);
}
}
static void board_clock_init(void)
{
system_clock_init();
peripheral_clock_init();
}
void bl_show_info(void)
{
MSG(" ____ __ __ _ _ _ \r\n");
MSG(" | _ \\ / _|/ _| | | | | | | \r\n");
MSG(" | |_) | ___ _ _| |_| |_ __ _| | ___ | | __ _| |__ \r\n");
MSG(" | _ < / _ \\| | | | _| _/ _` | |/ _ \\| |/ _` | '_ \\ \r\n");
MSG(" | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |\r\n");
MSG(" |____/ \\___/ \\__,_|_| |_| \\__,_|_|\\___/|_|\\__,_|_.__/ \r\n");
MSG("\r\n");
MSG("Build:%s,%s\r\n",__TIME__,__DATE__);
MSG("Copyright (c) 2021 Bouffalolab team\r\n");
#if 0
MSG("root clock:%dM\r\n",system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK)/1000000);
MSG("fclk clock:%dM\r\n",system_clock_get(SYSTEM_CLOCK_FCLK)/1000000);
MSG("bclk clock:%dM\r\n",system_clock_get(SYSTEM_CLOCK_BCLK)/1000000);
MSG("uart clock:%dM\r\n",peripheral_clock_get(PERIPHERAL_CLOCK_UART)/1000000);
MSG("spi clock:%dM\r\n",peripheral_clock_get(PERIPHERAL_CLOCK_SPI)/1000000);
MSG("i2c clock:%dM\r\n",peripheral_clock_get(PERIPHERAL_CLOCK_I2C)/1000000);
#endif
}
void board_init(void)
{
board_clock_init();
board_pin_mux_init();
}

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bsp/board/bl602_iot/clock_config.h Normal file
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/**
* @file clock_config.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _CLOCK_CONFIG_H
#define _CLOCK_CONFIG_H
#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M
#if defined(BSP_ROOT_CLOCK_SOURCE)
#define BSP_HCLK_DIV 0
#define BSP_BCLK_DIV 1
#endif
#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1)
#define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M
#define BSP_UART_CLOCK_DIV 0
#endif
#if defined(BSP_USING_I2C0)
#define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
#define BSP_I2C_CLOCK_DIV 0
#endif
#if defined(BSP_USING_SPI0)
#define BSP_SPI_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK
#define BSP_SPI_CLOCK_DIV 0
#endif
#if defined(BSP_USING_ADC0)
#define BSP_ADC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK
#define BSP_ADC_CLOCK_DIV 0
#endif
#if defined(BSP_USING_DAC0)
#define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL
#define BSP_DAC_CLOCK_DIV 1
#endif
#endif

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bsp/board/bl602_iot/peripheral_config.h Normal file
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/**
* @file peripheral_config.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _PERIPHERAL_CONFIG_H_
#define _PERIPHERAL_CONFIG_H_
/* PERIPHERAL USING LIST */
#define BSP_USING_UART0
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
#define BSP_USING_DMA0_CH3
#define BSP_USING_DMA0_CH4
#define BSP_USING_DMA0_CH2
#define BSP_USING_DMA0_CH6
/* PERIPHERAL CONFIG */
#if defined(BSP_USING_ADC0)
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
{ \
.clk_div = ADC_CLOCK_DIV_32,\
.vref = ADC_VREF_3P2V,\
.continuous_conv_mode = DISABLE,\
.differential_mode = DISABLE,\
.data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE,\
.fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE,\
.gain = ADC_GAIN_1\
}
#endif
#endif
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ,\
.pin.dac0 = GLB_GPIO_PIN_11,\
.pin.pin_num = 1,\
}
#endif
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.id = 0, \
.baudrate = 2000000,\
.databits = UART_DATA_LEN_8, \
.stopbits = UART_STOP_ONE, \
.parity = UART_PAR_NONE, \
.fifo_threshold = 1, \
}
#endif
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.id = 1, \
.baudrate = 2000000,\
.databits = UART_DATA_LEN_8, \
.stopbits = UART_STOP_ONE, \
.parity = UART_PAR_NONE, \
.fifo_threshold = 64, \
}
#endif
#endif
#if defined(BSP_USING_SPI0)
#ifndef SPI0_CONFIG
#define SPI0_CONFIG \
{ \
.id = 0, \
.clk = 18000000,\
.mode = SPI_MASTER_MODE, \
.direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \
.clk_polaraity = SPI_POLARITY_LOW, \
.clk_phase = SPI_PHASE_1EDGE, \
.datasize = SPI_DATASIZE_8BIT, \
.fifo_threshold = 1, \
}
#endif
#endif
#if defined(BSP_USING_PWM_CH2)
#ifndef PWM_CH2_CONFIG
#define PWM_CH2_CONFIG \
{ \
.ch = 2, \
.frequency = 1000000, \
.dutycycle = 0, \
.it_pulse_count = 0,\
}
#endif
#endif
#if defined(BSP_USING_I2S0)
#ifndef I2S0_CONFIG
#define I2S0_CONFIG \
{ \
.id = 0, \
.iis_mode = I2S_MODE_MASTER,\
.interface_mode = I2S_MODE_LEFT, \
.sampl_freq_hz = 16*1000, \
.channel_num = I2S_FS_CHANNELS_NUM_MONO, \
.frame_size = I2S_FRAME_LEN_16, \
.data_size = I2S_DATA_LEN_16, \
.fifo_threshold = 8, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0,\
.direction = DMA_MEMORY_TO_MEMORY,\
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT , \
.dst_width = DMA_TRANSFER_WIDTH_32BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1,\
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT , \
.dst_width = DMA_TRANSFER_WIDTH_16BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2,\
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT , \
.dst_width = DMA_TRANSFER_WIDTH_8BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3,\
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT , \
.dst_width = DMA_TRANSFER_WIDTH_8BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4,\
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT , \
.dst_width = DMA_TRANSFER_WIDTH_8BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5,\
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT , \
.dst_width = DMA_TRANSFER_WIDTH_16BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6,\
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT , \
.dst_width = DMA_TRANSFER_WIDTH_16BIT , \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 0,\
.direction = DMA_MEMORY_TO_MEMORY,\
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT , \
.dst_width = DMA_TRANSFER_WIDTH_32BIT , \
}
#endif
#endif
#if defined(BSP_USING_I2C0)
#ifndef I2C0_CONFIG
#define I2C0_CONFIG \
{ \
.id = 0, \
.mode = I2C_HW_MODE,\
.phase = 15, \
}
#endif
#endif
#if defined (BSP_USING_TIMER_CH0)
#ifndef TIMER_CH0_CONFIG
#define TIMER_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.cnt_mode = TIMER_CNT_PRELOAD, \
.pl_trig_src = TIMER_PL_TRIG_COMP0, \
}
#endif
#endif
#if defined (BSP_USING_TIMER_CH1)
#ifndef TIMER_CH1_CONFIG
#define TIMER_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.cnt_mode = TIMER_CNT_PRELOAD, \
.pl_trig_src = TIMER_PL_TRIG_COMP0, \
}
#endif
#endif
#endif

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bsp/board/bl602_iot/pinmux_config.h Normal file
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/**
* @file pinmux_config.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _PINMUX_CONFIG_H
#define _PINMUX_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <q> GPIO0 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio0 function
#define CONFIG_GPIO0_FUNC GPIO_FUN_UNUSED
// <q> GPIO1 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio1 function
#define CONFIG_GPIO1_FUNC GPIO_FUN_UNUSED
// <q> GPIO2 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio2 function
#define CONFIG_GPIO2_FUNC GPIO_FUN_UNUSED
// <q> GPIO3 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_QDEC]
// <i> config gpio3 function
#define CONFIG_GPIO3_FUNC GPIO_FUN_UNUSED
// <q> GPIO4 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio4 function
#define CONFIG_GPIO4_FUNC GPIO_FUN_UNUSED
// <q> GPIO5 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_CTS//GPIO_FUN_UART1_CTS//GPIO_FUN_QDEC]
// <i> config gpio5 function
#define CONFIG_GPIO5_FUNC GPIO_FUN_UNUSED
// <q> GPIO6 <2> [GPIO_FUN_UNUSED//GPIO_FUN_CLK_OUT//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_TX//GPIO_FUN_UART1_TX//GPIO_FUN_QDEC]
// <i> config gpio6 function
#define CONFIG_GPIO6_FUNC GPIO_FUN_UNUSED
// <q> GPIO7 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RX//GPIO_FUN_UART1_RX//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio7 function
#define CONFIG_GPIO7_FUNC GPIO_FUN_UART0_RX
// <q> GPIO8 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_USB//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio8 function
#define CONFIG_GPIO8_FUNC GPIO_FUN_UNUSED
// <q> GPIO9 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio9 function
#define CONFIG_GPIO9_FUNC GPIO_FUN_UNUSED
// <q> GPIO10 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio10 function
#define CONFIG_GPIO10_FUNC GPIO_FUN_UNUSED
// <q> GPIO11 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio11 function
#define CONFIG_GPIO11_FUNC GPIO_FUN_UNUSED
// <q> GPIO12 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio12 function
#define CONFIG_GPIO12_FUNC GPIO_FUN_UNUSED
// <q> GPIO13 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio13 function
#define CONFIG_GPIO13_FUNC GPIO_FUN_UNUSED
// <q> GPIO14 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio14 function
#define CONFIG_GPIO14_FUNC GPIO_FUN_UNUSED
// <q> GPIO15 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio15 function
#define CONFIG_GPIO15_FUNC GPIO_FUN_UNUSED
// <q> GPIO16 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio16 function
#define CONFIG_GPIO16_FUNC GPIO_FUN_UART0_TX
// <q> GPIO17 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio17 function
#define CONFIG_GPIO17_FUNC GPIO_FUN_UNUSED
// <q> GPIO18 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio18 function
#define CONFIG_GPIO18_FUNC GPIO_FUN_UNUSED
// <q> GPIO19 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio19 function
#define CONFIG_GPIO19_FUNC GPIO_FUN_UNUSED
// <q> GPIO20 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio20 function
#define CONFIG_GPIO20_FUNC GPIO_FUN_UNUSED
// <q> GPIO21 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio21 function
#define CONFIG_GPIO21_FUNC GPIO_FUN_UNUSED
// <q> GPIO22 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio22 function
#define CONFIG_GPIO22_FUNC GPIO_FUN_UNUSED
// <q> GPIO23 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_ANALOG//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_QDEC]
// <i> config gpio23 function
#define CONFIG_GPIO23_FUNC GPIO_FUN_UNUSED
// <q> GPIO24 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio24 function
#define CONFIG_GPIO24_FUNC GPIO_FUN_UNUSED
// <q> GPIO25 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio25 function
#define CONFIG_GPIO25_FUNC GPIO_FUN_UNUSED
// <q> GPIO26 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio26 function
#define CONFIG_GPIO26_FUNC GPIO_FUN_UNUSED
// <q> GPIO27 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio27 function
#define CONFIG_GPIO27_FUNC GPIO_FUN_UNUSED
// <q> GPIO28 <2> [GPIO_FUN_UNUSED//GPIO_FUN_I2S//GPIO_FUN_SPI//GPIO_FUN_I2C//GPIO_FUN_PWM//GPIO_FUN_CAM//GPIO_FUN_UART0_RTS//GPIO_FUN_UART1_RTS//GPIO_FUN_ETHER_MAC//GPIO_FUN_QDEC]
// <i> config gpio28 function
#define CONFIG_GPIO28_FUNC GPIO_FUN_UNUSED
#endif

61
drivers/bl602_driver/CMakeLists.txt Normal file
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################# Add global include #################
list(APPEND ADD_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/startup"
"${CMAKE_CURRENT_SOURCE_DIR}/risc-v/Core/Include"
"${CMAKE_CURRENT_SOURCE_DIR}/regs"
)
#######################################################
################# Add private include #################
list(APPEND ADD_PRIVATE_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/default_config"
)
#######################################################
############## Add current dir source files ###########
file(GLOB_RECURSE sources
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/hal_drv/src/*.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/interrupt.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/system_bl602.c"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/entry.S"
"${CMAKE_CURRENT_SOURCE_DIR}/startup/GCC/start_load.c"
)
list(APPEND ADD_SRCS ${sources})
# aux_source_directory(src ADD_SRCS)
list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_mfg_efuse.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_mfg_media.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_mfg_flash.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl602_romdriver.c")
#######################################################
########### Add required/dependent components #########
list(APPEND ADD_REQUIREMENTS common)
#######################################################
############ Add static libs ##########################
# if(CONFIG_COMPONENT1_INCLUDE_STATIC_LIB)
# list(APPEND ADD_STATIC_LIB "lib/libtest.a")
# endif()
#######################################################
############ Add dynamic libs #########################
# list(APPEND ADD_DYNAMIC_LIB "lib/arch/v831/libmaix_nn.so"
# "lib/arch/v831/libmaix_cam.so"
# )
#######################################################
############ Add global compile option ################
#add components denpend on this component
list(APPEND ADD_DEFINITIONS -DARCH_RISCV)
#######################################################
############ Add private compile option ################
#add compile option for this component that won't affect other modules
# list(APPEND ADD_DEFINITIONS_PRIVATE -DAAAAA=1)
#######################################################
generate_library()

222
drivers/bl602_driver/bl602_flash.ld Normal file
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/****************************************************************************************
* @file map.txt
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2018
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(_enter)
StackSize = 0x0400; /* 1KB */
HeapSize = 0x1000; /* 4KB */
MEMORY
{
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42014000, LENGTH = 48K
ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 176K
}
SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(.text.metal.init.enter))
KEEP (*(SORT_NONE(.init)))
/* section information for finsh shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP(*(shellCommand))
_shell_command_end = .;
*(.text)
*(.text.*)
/*put .rodata**/
*(EXCLUDE_FILE( *bl602_glb.o \
*bl602_pds.o \
*bl602_common.o \
*bl602_sf_cfg.o \
*bl602_sf_ctrl.o \
*bl602_sflash.o \
*bl602_xip_sflash.o \
*bl602_ef_ctrl.o) .rodata*)
*(.rodata)
*(.rodata.*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code)
*(.tcm_const)
*(.sclock_rlt_code)
*(.sclock_rlt_const)
*bl602_glb.o*(.rodata*)
*bl602_pds.o*(.rodata*)
*bl602_common.o*(.rodata*)
*bl602_sf_cfg.o*(.rodata*)
*bl602_sf_ctrl.o*(.rodata*)
*bl602_sflash.o*(.rodata*)
*bl602_xip_sflash.o*(.rodata*)
*bl602_ef_ctrl.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/* .heap_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of heap sections, and assign
* values to heap symbols later */
.heap_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + HeapSize;
. = ALIGN(0x4);
} > dtcm_memory
_HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
_HeapSize = HeapSize;
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
}

14
drivers/bl602_driver/cpu_flags.cmake Normal file
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SET(CPU_ARCH "RISCV")
SET(MCPU "e24")
if(${SUPPORT_FLOAT} STREQUAL "y")
SET(MARCH "rv32imafc")
SET(MABI "ilp32f")
else()
SET(MARCH "rv32imac")
SET(MABI "ilp32")
endif()
list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})
SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl602_flash.ld)

5
drivers/bl602_driver/hal_drv/default_config/adc_config.h Normal file
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#ifndef _ADC_CONFIG_H
#define _ADC_CONFIG_H
#endif

6
drivers/bl602_driver/hal_drv/default_config/spi_config.h Normal file
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#ifndef _SPI_CONFIG_H
#define _SPI_CONFIG_H
#define SPI_DEGLITCH_ENABLE (0)
#define SPI_CONTINUE_TRANSFER_ENABLE (1)
#endif

12
drivers/bl602_driver/hal_drv/default_config/uart_config.h Normal file
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#ifndef _UART_CONFIG_H
#define _UART_CONFIG_H
#define UART_CLOCK_SOURCE_160M_ENABLE (1)
#define UART_CTS_FLOWCONTROL_ENABLE (0)
#define UART_RTS_FLOWCONTROL_ENABLE (0)
#define UART_RX_DEGLITCH_ENABLE (0)
#define UART_MSB_FIRST_ENABLE (0)
#define UART_FIFO_MAX_LEN 128
#define UART_DEFAULT_RTO_TIMEOUT 255
#endif

83
drivers/bl602_driver/hal_drv/inc/hal_clock.h Normal file
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/**
* @file hal_clock.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_CLOCK__H__
#define __HAL_CLOCK__H__
#include "drv_device.h"
#include "bl602_config.h"
#define EXTERNAL_XTAL_NONE 0
#define EXTERNAL_XTAL_24M 1
#define EXTERNAL_XTAL_32M 2
#define EXTERNAL_XTAL_38P4M 3
#define EXTERNAL_XTAL_40M 4
#define EXTERNAL_XTAL_26M 5
#define INTERAL_XTAL_RC32M 6
#define ROOT_CLOCK_SOURCE_RC_32K 0
#define ROOT_CLOCK_SOURCE_XTAL_32K 1
#define ROOT_CLOCK_SOURCE_RC_32M 2
#define ROOT_CLOCK_SOURCE_XTAL_32M 3
#define ROOT_CLOCK_SOURCE_PLL_48M 4
#define ROOT_CLOCK_SOURCE_PLL_120M 5
#define ROOT_CLOCK_SOURCE_PLL_160M 6
#define ROOT_CLOCK_SOURCE_PLL_192M 7
#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
#define ROOT_CLOCK_SOURCE_FCLK 8
#define ROOT_CLOCK_SOURCE_HCLK 8
#define ROOT_CLOCK_SOURCE_BCLK 9
#define ROOT_CLOCK_SOURCE_AUPLL 9
#define OUTPUT_REF_CLOCK_SOURCE_NONE 0
#define OUTPUT_REF_CLOCK_SOURCE_I2S 1
#if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 8)
#define CLOCK_XTAL EXTERNAL_XTAL_40M
#else
#define CLOCK_XTAL INTERAL_XTAL_RC32M
#endif
enum system_clock_type
{
SYSTEM_CLOCK_ROOT_CLOCK = 0,
SYSTEM_CLOCK_FCLK,
SYSTEM_CLOCK_BCLK,
SYSTEM_CLOCK_XCLK,
};
enum peripheral_clock_type
{
PERIPHERAL_CLOCK_UART = 0,
PERIPHERAL_CLOCK_SPI,
PERIPHERAL_CLOCK_I2C,
PERIPHERAL_CLOCK_ADC,
PERIPHERAL_CLOCK_DAC,
};
void system_clock_init(void);
void peripheral_clock_init(void);
uint32_t system_clock_get(enum system_clock_type type);
uint32_t peripheral_clock_get(enum peripheral_clock_type type);
#endif

193
drivers/bl602_driver/hal_drv/inc/hal_dma.h Normal file
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/**
* @file hal_dma.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_DMA__H__
#define __HAL_DMA__H__
#include "drv_device.h"
#include "bl602_config.h"
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
enum dma_index_type
{
#ifdef BSP_USING_DMA0_CH0
DMA0_CH0_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH1
DMA0_CH1_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH2
DMA0_CH2_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH3
DMA0_CH3_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH4
DMA0_CH4_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH5
DMA0_CH5_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH6
DMA0_CH6_INDEX,
#endif
#ifdef BSP_USING_DMA0_CH7
DMA0_CH7_INDEX,
#endif
DMA_MAX_INDEX
};
#define dma_channel_start(dev) device_control(dev,DMA_CHANNEL_START,NULL)
#define dma_channel_stop(dev) device_control(dev,DMA_CHANNEL_STOP,NULL)
#define dma_channel_update(dev,list) device_control(dev,DMA_CHANNEL_UPDATE,list)
#define dma_channel_check_busy(dev) device_control(dev,DMA_CHANNEL_GET_STATUS,NULL)
#define DMA_ADDR_UART0_TDR (0x4000A000+0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000+0x8C)
#define DMA_ADDR_UART1_TDR (0x4000A100+0x88)
#define DMA_ADDR_UART1_RDR (0x4000A100+0x8C)
#define DMA_ADDR_I2C_TDR (0x4000A300+0x88)
#define DMA_ADDR_I2C_RDR (0x4000A300+0x8C)
#define DMA_ADDR_SPI_TDR (0x4000A200+0x88)
#define DMA_ADDR_SPI_RDR (0x4000A200+0x8C)
#define DMA_ADDR_I2S_TDR (0x4000AA00+0x88)
#define DMA_ADDR_I2S_RDR (0x4000AA00+0x8C)
#define DMA_ADDR_ADC0_DR (0x40002000+0x04)
#define DMA_ADDR_ADC1_DR (0x40002000+0x04)
#define DMA_ADDR_DAC_TDR (0x40002048)
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE 1 /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE 0 /*!< Peripheral increment mode disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @brief DMA memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE 1 /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE 0 /*!< Memory increment mode disable */
#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */
#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */
#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX */
#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX */
#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX */
#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C RX */
#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C TX */
#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI RX */
#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */
#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */
#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */
#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC0 */
#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC1 */
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_TRANSFER_WIDTH_8BIT 0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
/**
* @brief DMA transfer direction type definition
*/
typedef enum {
DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer tyep:memory to memory */
DMA_MEMORY_TO_PERIPH, /*!< DMA transfer tyep:memory to peripheral */
DMA_PERIPH_TO_MEMORY, /*!< DMA transfer tyep:peripheral to memory */
DMA_PERIPH_TO_PERIPH, /*!< DMA transfer tyep:peripheral to peripheral */
}dma_transfer_dir_type;
typedef union
{
struct
{
uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */
uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */
uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */
uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */
uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */
uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */
uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */
uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */
uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */
uint32_t SI : 1; /* [ 26], r/w, 0x1 */
uint32_t DI : 1; /* [ 27], r/w, 0x1 */
uint32_t Prot : 3; /* [30:28], r/w, 0x0 */
uint32_t I : 1; /* [ 31], r/w, 0x0 */
} bits;
uint32_t WORD;
} dma_control_data_t;
typedef struct
{
uint32_t src_addr;
uint32_t dst_addr;
uint32_t nextlli;
dma_control_data_t cfg;
} dma_lli_ctrl_t;
typedef struct
{
uint8_t direction;
uint32_t src_req;
uint32_t dst_req;
} dma_ctrl_param_t;
typedef struct dma_device
{
struct device parent;
uint8_t id;
uint8_t ch;
uint8_t direction;
uint8_t transfer_mode;
uint32_t src_req;
uint32_t dst_req;
uint8_t src_burst_size;
uint8_t dst_burst_size;
uint8_t src_width;
uint8_t dst_width;
dma_lli_ctrl_t *lli_cfg;
} dma_device_t;
#define DMA_DEV(dev) ((dma_device_t*)dev)
int dma_register(enum dma_index_type, const char *name, uint16_t flag);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
int dma_allocate_register(const char *name, uint16_t flag);
#endif

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/**
* *****************************************************************************
* @file hal_gpio.h
* @version 0.1
* @date 2021-03-01
* @brief
* *****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************************************************************
*/
#ifndef __HAL_GPIO__H__
#define __HAL_GPIO__H__
#include "drv_device.h"
typedef enum
{
GPIO_PIN_0 = 0,
GPIO_PIN_1,
GPIO_PIN_2,
GPIO_PIN_3,
GPIO_PIN_4,
GPIO_PIN_5,
GPIO_PIN_6,
GPIO_PIN_7,
GPIO_PIN_8,
GPIO_PIN_9,
GPIO_PIN_10,
GPIO_PIN_11,
GPIO_PIN_12,
GPIO_PIN_13,
GPIO_PIN_14,
GPIO_PIN_15,
GPIO_PIN_16,
GPIO_PIN_17,
GPIO_PIN_18,
GPIO_PIN_19,
GPIO_PIN_20,
GPIO_PIN_21,
GPIO_PIN_22,
GPIO_PIN_23,
GPIO_PIN_24,
GPIO_PIN_25,
GPIO_PIN_26,
GPIO_PIN_27,
GPIO_PIN_28,
GPIO_PIN_29,
GPIO_PIN_30,
GPIO_PIN_31,
GPIO_PIN_32,
GPIO_PIN_33,
GPIO_PIN_34,
GPIO_PIN_35,
GPIO_PIN_36,
GPIO_PIN_37,
GPIO_PIN_MAX,
}gpio_pin_type;
#define GPIO_OUTPUT_MODE 0
#define GPIO_OUTPUT_PP_MODE 1
#define GPIO_OUTPUT_PD_MODE 2
#define GPIO_INPUT_MODE 3
#define GPIO_INPUT_PP_MODE 4
#define GPIO_INPUT_PD_MODE 5
#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6
#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7
#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8
#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9
#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10
#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11
#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 12
#define GPIO_SYNC_LOW_LEVEL_INT_MODE 13
typedef struct gpio_device
{
struct device parent;
} gpio_device_t;
void gpio_register(const char *name, uint16_t flag);
void gpio_set_mode(uint32_t pin, uint32_t mode);
void gpio_write(uint32_t pin, uint32_t value);
void gpio_toggle(uint32_t pin);
int gpio_read(uint32_t pin);
void gpio_attach_irq(uint32_t pin, void (*cbFun)(void));
void gpio_irq_enable(uint32_t pin,uint8_t enabled);
#endif

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#ifndef __HAL_MTIMER__H__
#define __HAL_MTIMER__H__
#include "stdint.h"
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void));
uint32_t mtimer_get_clk_src_div(void);
uint64_t mtimer_get_time_ms();
uint64_t mtimer_get_time_us();
void mtimer_delay_ms(uint32_t time);
void mtimer_delay_us(uint32_t time);
#endif

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/**
* *****************************************************************************
* @file hal_uart.h
* @version 0.1
* @date 2021-03-01
* @brief
* *****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************************************************************
*/
#ifndef __HAL_UART__H__
#define __HAL_UART__H__
#include "drv_device.h"
#include "bl602_config.h"
#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10
#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11
#define DEVICE_CTRL_UART_ATTACH_TX_DMA 0x12
#define DEVICE_CTRL_UART_ATTACH_RX_DMA 0x13
enum uart_index_type
{
#ifdef BSP_USING_UART0
UART0_INDEX,
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
#ifdef BSP_USING_UART2
UART2_INDEX,
#endif
#ifdef BSP_USING_UART3
UART3_INDEX,
#endif
#ifdef BSP_USING_UART4
UART4_INDEX,
#endif
UART_MAX_INDEX
};
/*!
* @brief UART data length settings
*
* This enumeration defines the UART data lengths.
*/
typedef enum
{
UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */
UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */
UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */
UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */
} uart_databits_t;
/*!
* @brief UART stop bit settings
*
* This enumeration defines the UART stop bits.
*/
typedef enum
{
UART_STOP_ONE = 0, /*!< One stop bit */
UART_STOP_ONE_D_FIVE = 0, /*!< 1.5 stop bit */
UART_STOP_TWO = 1 /*!< Two stop bits */
} uart_stopbits_t;
/*!
* @brief UART parity type settings
*
* This enumeration defines the UART parity types.
*/
typedef enum
{
UART_PAR_NONE = 0, /*!< No parity */
UART_PAR_ODD = 1, /*!< Parity bit is odd */
UART_PAR_EVEN = 2, /*!< Parity bit is even */
} uart_parity_t;
enum uart_event_type
{
UART_EVENT_TX_END,
UART_EVENT_TX_FIFO,
UART_EVENT_RX_END,
UART_EVENT_RX_FIFO,
UART_EVENT_RTO,
UART_EVENT_UNKNOWN
};
typedef struct
{
uint8_t tx;
uint8_t rx;
uint8_t cts;
uint8_t rts;
} uart_pin_t;
enum uart_it_type
{
UART_TX_END_IT = 1 << 0,
UART_RX_END_IT = 1 << 1,
UART_TX_FIFO_IT = 1 << 2,
UART_RX_FIFO_IT = 1 << 3,
UART_RTO_IT = 1 << 4,
UART_PCE_IT = 1 << 5,
UART_TX_FER_IT = 1 << 6,
UART_RX_FER_IT = 1 << 7,
UART_ALL_IT = 1 << 8
};
typedef struct
{
uint32_t baudrate;
uart_databits_t databits;
uart_stopbits_t stopbits;
uart_parity_t parity;
}uart_param_cfg_t;
typedef struct uart_device
{
struct device parent;
uint8_t id;
uint32_t baudrate;
uart_databits_t databits;
uart_stopbits_t stopbits;
uart_parity_t parity;
uint8_t fifo_threshold;
uart_pin_t pin;
void* tx_dma;
void* rx_dma;
} uart_device_t;
int uart_register(enum uart_index_type index, const char *name, uint16_t flag);
#endif

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#include "bl602_glb.h"
#include "hal_clock.h"
static uint32_t mtimer_get_clk_src_div(void)
{
return ((SystemCoreClockGet()/(GLB_Get_BCLK_Div() + 1))/1000/1000-1);
}
void system_clock_init(void)
{
/*select root clock*/
GLB_Set_System_CLK(CLOCK_XTAL,BSP_ROOT_CLOCK_SOURCE-2);
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_HCLK_DIV,BSP_BCLK_DIV);
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
}
void peripheral_clock_init(void)
{
#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1)
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M
GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_160M,BSP_UART_CLOCK_DIV);
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_FCLK,BSP_UART_CLOCK_DIV);
#endif
#endif
#if defined(BSP_USING_I2C0)
GLB_Set_I2C_CLK(ENABLE,BSP_I2C_CLOCK_DIV);
#endif
#if defined(BSP_USING_SPI0)
GLB_Set_SPI_CLK(ENABLE,BSP_SPI_CLOCK_DIV);
#endif
#if defined(BSP_USING_PWM)
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
#endif
#endif
#if defined(BSP_USING_IR)
GLB_Set_IR_CLK(ENABLE,0,BSP_IR_CLOCK_DIV);
#endif
#if defined(BSP_USING_ADC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_ADC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_ADC_CLOCK_DIV);
#endif
#endif
#if defined(BSP_USING_DAC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_DAC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_DAC_CLOCK_DIV);
#endif
#endif
}
uint32_t system_clock_get(enum system_clock_type type)
{
switch (type)
{
case SYSTEM_CLOCK_ROOT_CLOCK:
return SystemCoreClockGet();
case SYSTEM_CLOCK_FCLK:
return (SystemCoreClockGet()/(GLB_Get_HCLK_Div()+1));
case SYSTEM_CLOCK_BCLK:
return (SystemCoreClockGet()/((GLB_Get_HCLK_Div()+1)*(GLB_Get_BCLK_Div()+1)));
case SYSTEM_CLOCK_XCLK:
return 32000000;
default:
break;
}
return 0;
}
uint32_t peripheral_clock_get(enum peripheral_clock_type type)
{
uint32_t tmpVal;
uint32_t div;
switch (type)
{
case PERIPHERAL_CLOCK_UART:
#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1)
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M
return 160000000;
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
return system_clock_get(SYSTEM_CLOCK_FCLK)/(GLB_Get_HCLK_Div()+1));
#endif
#endif
case PERIPHERAL_CLOCK_SPI:
#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal,GLB_SPI_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1);
#endif
#endif
case PERIPHERAL_CLOCK_I2C:
#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal,GLB_I2C_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1);
#endif
#endif
case PERIPHERAL_CLOCK_ADC:
return 32000000;
default:
break;
}
(void)(tmpVal);
(void)(div);
return 0;
}

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/**
* @file hal_dma.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_dma.h"
#include "drv_mmheap.h"
#include "bl602_dma.h"
dma_control_data_t dma_ctrl_cfg;
void DMA0_IRQ(void);
dma_device_t dmax_device[DMA_MAX_INDEX] =
{
#ifdef BSP_USING_DMA0_CH0
DMA0_CH0_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH1
DMA0_CH1_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH2
DMA0_CH2_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH3
DMA0_CH3_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH4
DMA0_CH4_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH5
DMA0_CH5_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH6
DMA0_CH6_CONFIG,
#endif
#ifdef BSP_USING_DMA0_CH7
DMA0_CH7_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int dma_open(struct device *dev, uint16_t oflag)
{
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_LLI_Cfg_Type lliCfg = {0};
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
/* Enable uart interrupt*/
NVIC_DisableIRQ(DMA_ALL_IRQn);
DMA_Disable();
DMA_Channel_Disable(dma_device->ch);
lliCfg.dir = dma_device->direction;
lliCfg.srcPeriph = dma_device->src_req;
lliCfg.dstPeriph = dma_device->dst_req;
DMA_LLI_Init(dma_device->ch, &lliCfg);
dma_ctrl_cfg.bits.fix_cnt = 0;
dma_ctrl_cfg.bits.dst_min_mode = 0;
dma_ctrl_cfg.bits.dst_add_mode = 0;
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int dma_control(struct device *dev, int cmd, void *args)
{
dma_device_t *dma_device = (dma_device_t *)dev;
switch (cmd)
{
case DEVICE_CTRL_SET_INT /* constant-expression */:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
/* Enable uart interrupt*/
NVIC_EnableIRQ(DMA_ALL_IRQn);
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
/* Enable uart interrupt*/
NVIC_DisableIRQ(DMA_ALL_IRQn);
break;
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_CONFIG /* constant-expression */:
{
dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args;
DMA_LLI_Cfg_Type lliCfg = {0};
lliCfg.dir = cfg->direction;
lliCfg.srcPeriph = cfg->src_req;
lliCfg.dstPeriph = cfg->dst_req;
DMA_LLI_Init(dma_device->ch, &lliCfg);
break;
}
case DMA_CHANNEL_UPDATE:
DMA_LLI_Update(dma_device->ch, (uint32_t)args);
break;
case DMA_CHANNEL_GET_STATUS /* constant-expression */:
return DMA_Channel_Is_Busy(dma_device->ch);
case DMA_CHANNEL_START /* constant-expression */:
DMA_Channel_Enable(dma_device->ch);
break;
case DMA_CHANNEL_STOP /* constant-expression */:
DMA_Channel_Disable(dma_device->ch);
break;
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int dma_close(struct device *dev)
{
DMA_Disable();
return 0;
}
int dma_register(enum dma_index_type index, const char *name, uint16_t flag)
{
struct device *dev;
if (DMA_MAX_INDEX == 0)
return -DEVICE_EINVAL;
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name, flag);
}
static BL_Err_Type dma_scan_unregister_device(uint8_t * allocate_index){
struct device *dev;
dlist_t *node;
uint8_t dma_index=0;
uint32_t dma_handle[DMA_MAX_INDEX];
for(dma_index = 0;dma_index<DMA_MAX_INDEX;dma_index++){
dma_handle[dma_index] = 0xff;
}
/* get registered dma handle list*/
dlist_for_each(node, device_get_list_header())
{
dev = dlist_entry(node, struct device, list);
if(dev->type == DEVICE_CLASS_DMA){
dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
}
}
for(dma_index = 0;dma_index<DMA_MAX_INDEX;dma_index++){
if(dma_handle[dma_index]==0xff){
* allocate_index = dma_index;
return SUCCESS;
}
}
return ERROR;
}
int dma_allocate_register(const char *name, uint16_t flag)
{
struct device *dev;
uint8_t index;
if (DMA_MAX_INDEX == 0)
return -DEVICE_EINVAL;
if(dma_scan_unregister_device(&index) == ERROR){
return -DEVICE_ENOSPACE;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name, flag);
}
/**
* @brief
*
* @param dev
* @param src_addr
* @param dst_addr
* @param transfer_size
* @return int
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_Channel_Disable(dma_device->ch);
if (dma_device->direction == DMA_MEMORY_TO_MEMORY)
{
dma_ctrl_cfg.bits.SI = 1;
dma_ctrl_cfg.bits.DI = 1;
}
else if (dma_device->direction == DMA_MEMORY_TO_PERIPH)
{
dma_ctrl_cfg.bits.SI = 1;
dma_ctrl_cfg.bits.DI = 0;
}
else if (dma_device->direction == DMA_PERIPH_TO_MEMORY)
{
dma_ctrl_cfg.bits.SI = 0;
dma_ctrl_cfg.bits.DI = 1;
}
else if (dma_device->direction == DMA_PERIPH_TO_PERIPH)
{
dma_ctrl_cfg.bits.SI = 0;
dma_ctrl_cfg.bits.DI = 0;
}
dma_ctrl_cfg.bits.SBSize = dma_device->src_burst_size;
dma_ctrl_cfg.bits.DBSize = dma_device->dst_burst_size;
dma_ctrl_cfg.bits.SWidth = dma_device->src_width;
dma_ctrl_cfg.bits.DWidth = dma_device->dst_width;
if (dma_device->src_width == DMA_TRANSFER_WIDTH_8BIT)
{
actual_transfer_offset = 4095;
actual_transfer_len = transfer_size;
}
else if (dma_device->src_width == DMA_TRANSFER_WIDTH_16BIT)
{
if (transfer_size % 2)
return -1;
actual_transfer_offset = (4095 * 2);
actual_transfer_len = transfer_size/2;
}
else if (dma_device->src_width == DMA_TRANSFER_WIDTH_32BIT)
{
if (transfer_size % 4)
return -1;
actual_transfer_offset = (4095 * 4);
actual_transfer_len = transfer_size/4;
}
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
if (remain_len)
{
malloc_count++;
}
if(dma_device->lli_cfg)
{
mmheap_free(dma_device->lli_cfg);
dma_device->lli_cfg = (dma_lli_ctrl_t *)mmheap_alloc(sizeof(dma_lli_ctrl_t) * malloc_count);
}
else
{
dma_device->lli_cfg = (dma_lli_ctrl_t *)mmheap_alloc(sizeof(dma_lli_ctrl_t) * malloc_count);
}
if (dma_device->lli_cfg)
{
/*transfer_size will be 4095 or 4095*2 or 4095*4 in different transfer width*/
if ((!remain_len) && (malloc_count == 1))
{
dma_device->lli_cfg[0].src_addr = src_addr;
dma_device->lli_cfg[0].dst_addr = dst_addr;
dma_device->lli_cfg[0].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = remain_len;
dma_ctrl_cfg.bits.I = 1;
memcpy(&dma_device->lli_cfg[0].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
}
/*transfer_size will be 4095*n or 4095*2*n or 4095*4*n,(n>1) in different transfer width*/
else if ((!remain_len) && (malloc_count > 1))
{
for (uint32_t i = 0; i < malloc_count; i++)
{
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI)
src_addr += actual_transfer_offset;
if (dma_ctrl_cfg.bits.DI)
dst_addr += actual_transfer_offset;
if (i == malloc_count - 1)
{
dma_ctrl_cfg.bits.I = 1;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE)
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
}
if (i)
{
dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
}
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
}
}
else
{
for (uint32_t i = 0; i < malloc_count; i++)
{
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI)
src_addr += actual_transfer_offset;
if (dma_ctrl_cfg.bits.DI)
dst_addr += actual_transfer_offset;
if (i == malloc_count - 1)
{
dma_ctrl_cfg.bits.TransferSize = remain_len;
dma_ctrl_cfg.bits.I = 1;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE)
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
}
if (i)
{
dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
}
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
}
}
DMA_LLI_Update(dma_device->ch, (uint32_t)dma_device->lli_cfg);
}
else
{
return -2;
}
return 0;
}
/**
* @brief
*
* @param handle
*/
void dma_isr(dma_device_t *handle)
{
uint32_t tmpVal;
uint32_t intClr;
/* Get DMA register */
if (handle->id == 0)
{
uint32_t DMAChs = DMA_BASE;
for (uint8_t i = 0; i < DMA_CH_MAX; i++)
{
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0)
{
/* Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
intClr |= (1 << handle[i].ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
if (handle[i].parent.callback)
handle[i].parent.callback(&handle[i].parent, NULL, 0, DMA_INT_TCOMPLETED);
}
}
for (uint8_t i = 0; i < DMA_CH_MAX; i++)
{
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0)
{
/*Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
intClr |= (1 << handle[i].ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
if (handle[i].parent.callback)
handle[i].parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR);
}
}
}
else
{
}
}
/**
* @brief
*
*/
void DMA0_IRQ(void)
{
dma_isr(&dmax_device[0]);
}

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drivers/bl602_driver/hal_drv/src/hal_gpio.c Normal file
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/**
* *****************************************************************************
* @file hal_gpio.c
* @version 0.1
* @date 2021-03-01
* @brief
* *****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************************************************************
*/
#include "bl602_glb.h"
#include "bl602_gpio.h"
#include "hal_gpio.h"
gpio_device_t gpio_device;
/**
* @brief
*
* @param pin
* @param mode
*/
void gpio_set_mode(uint32_t pin, uint32_t mode)
{
GLB_GPIO_Cfg_Type gpio_cfg;
gpio_cfg.gpioFun = GPIO_FUN_GPIO;
gpio_cfg.gpioPin = pin;
gpio_cfg.drive = 0;
gpio_cfg.smtCtrl = 1;
switch (mode)
{
case GPIO_OUTPUT_MODE:
gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
gpio_cfg.pullType = GPIO_PULL_NONE;
break;
case GPIO_OUTPUT_PP_MODE:
gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
gpio_cfg.pullType = GPIO_PULL_UP;
break;
case GPIO_OUTPUT_PD_MODE:
gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
gpio_cfg.pullType = GPIO_PULL_DOWN;
break;
case GPIO_INPUT_MODE:
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_NONE;
break;
case GPIO_INPUT_PP_MODE:
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_UP;
break;
case GPIO_INPUT_PD_MODE:
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_DOWN;
break;
default:
NVIC_DisableIRQ(GPIO_INT0_IRQn);
GLB_GPIO_IntMask(pin, MASK);
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
GLB_GPIO_INT0_IRQHandler_Install();
if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
}
else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
}
else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
}
else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
}
else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
}
else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
}
else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_DOWN;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_POS_LEVEL);
}
else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_UP;
GLB_Set_GPIO_IntMod(pin, GLB_GPIO_INT_CONTROL_SYNC, GLB_GPIO_INT_TRIG_NEG_LEVEL);
}
else
return;
NVIC_EnableIRQ(GPIO_INT0_IRQn);
break;
}
GLB_GPIO_Init(&gpio_cfg);
}
/**
* @brief
*
* @param pin
* @param value
*/
void gpio_write(uint32_t pin, uint32_t value)
{
GLB_GPIO_Write(pin, value);
}
/**
* @brief
*
* @param pin
*/
void gpio_toggle(uint32_t pin)
{
}
/**
* @brief
*
* @param pin
* @return int
*/
int gpio_read(uint32_t pin)
{
return GLB_GPIO_Read(pin);
}
/**
* @brief
*
* @param pin
* @param cbFun
*/
void gpio_attach_irq(uint32_t pin, void (*cbFun)(void))
{
GLB_GPIO_INT0_Callback_Install(pin, cbFun);
}
/**
* @brief
*
* @param pin
* @param enabled
*/
void gpio_irq_enable(uint32_t pin, uint8_t enabled)
{
if (enabled)
{
GLB_GPIO_IntMask(pin, UNMASK);
}
else
{
GLB_GPIO_IntMask(pin, MASK);
}
}
void pin_register(const char *name, uint16_t flag)
{
struct device *dev;
dev = &(gpio_device.parent);
dev->open = NULL;
dev->close = NULL;
dev->control = NULL;
dev->write = NULL;
dev->read = NULL;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_GPIO;
dev->handle = NULL;
device_register(dev, name, flag);
}

147
drivers/bl602_driver/hal_drv/src/hal_mtimer.c Normal file
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/**
* @file hal_mtimer.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_mtimer.h"
#include "bl602_glb.h"
static void (*systick_callback)(void);
static uint64_t next_compare_tick = 0;
static uint64_t current_set_ticks = 0;
static void Systick_Handler(void)
{
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
systick_callback();
next_compare_tick += current_set_ticks;
}
/**
* @brief
*
* @param time
* @param interruptFun
*/
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void))
{
NVIC_DisableIRQ(MTIME_IRQn);
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME + 4 );
volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME );
volatile uint32_t ulHartId = 0;
current_set_ticks = ticks;
systick_callback = interruptfun;
__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
do
{
ulCurrentTimeHigh = *pulTimeHigh;
ulCurrentTimeLow = *pulTimeLow;
} while( ulCurrentTimeHigh != *pulTimeHigh );
next_compare_tick = ( uint64_t ) ulCurrentTimeHigh;
next_compare_tick <<= 32ULL;
next_compare_tick |= ( uint64_t ) ulCurrentTimeLow;
next_compare_tick += ( uint64_t ) current_set_ticks;
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
/* Prepare the time to use after the next tick interrupt. */
next_compare_tick += ( uint64_t ) current_set_ticks;
Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler);
NVIC_EnableIRQ(MTIME_IRQn);
}
/**
* @brief
*
* @return uint64_t
*/
uint64_t mtimer_get_time_ms()
{
return mtimer_get_time_us()/1000;
}
/**
* @brief
*
* @return uint64_t
*/
uint64_t mtimer_get_time_us()
{
uint32_t tmpValLow, tmpValHigh, tmpValHigh1;
do
{
tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME);
tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
} while (tmpValHigh != tmpValHigh1);
return (((uint64_t)tmpValHigh << 32) + tmpValLow);
}
/**
* @brief
*
* @param time
*/
void mtimer_delay_ms(uint32_t time)
{
uint64_t cnt = 0;
uint32_t clock = SystemCoreClockGet();
uint64_t startTime = mtimer_get_time_ms();
while (mtimer_get_time_ms() - startTime < time)
{
cnt++;
/* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
if (cnt > (time * (clock >> (10 + 5))) * 2)
{
break;
}
}
}
/**
* @brief
*
* @param time
*/
void mtimer_delay_us(uint32_t time)
{
uint64_t cnt = 0;
uint32_t clock = SystemCoreClockGet();
uint64_t startTime = mtimer_get_time_us();
while (mtimer_get_time_us() - startTime < time)
{
cnt++;
/* assume BFLB_BSP_Get_Time_Ms take 32 cycles*/
if (cnt > (time * (clock >> (10 + 5))) * 2)
{
break;
}
}
}

418
drivers/bl602_driver/hal_drv/src/hal_uart.c Normal file
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/**
* *****************************************************************************
* @file hal_uart.c
* @version 0.1
* @date 2021-03-01
* @brief
* *****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************************************************************
*/
#include "hal_uart.h"
#include "hal_dma.h"
#include "hal_gpio.h"
#include "hal_clock.h"
#include "bl602_uart.h"
#include "bl602_glb.h"
#include "uart_config.h"
#ifdef BSP_USING_UART0
void UART0_IRQ(void);
#endif
#ifdef BSP_USING_UART1
void UART1_IRQ(void);
#endif
uart_device_t uartx_device[UART_MAX_INDEX] =
{
#ifdef BSP_USING_UART0
UART0_CONFIG,
#endif
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
};
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int uart_open(struct device *dev, uint16_t oflag)
{
uart_device_t *uart_device = (uart_device_t *)dev;
UART_FifoCfg_Type fifoCfg = {0};
UART_CFG_Type uart_cfg = {0};
/* disable all interrupt */
UART_IntMask(uart_device->id, UART_INT_ALL, MASK);
/* disable uart before config */
UART_Disable(uart_device->id, UART_TXRX);
uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
uart_cfg.baudRate = uart_device->baudrate;
uart_cfg.dataBits = uart_device->databits;
uart_cfg.stopBits = uart_device->stopbits;
uart_cfg.parity = uart_device->parity;
uart_cfg.uartClk = uart_clk;
uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
/* uart init with default configuration */
UART_Init(uart_device->id, &uart_cfg);
/* Enable tx free run mode */
UART_TxFreeRun(uart_device->id, ENABLE);
/* Set rx time-out value */
UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT);
fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold;
fifoCfg.txFifoDmaEnable = DISABLE;
fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold;
fifoCfg.rxFifoDmaEnable = DISABLE;
if (oflag & DEVICE_OFLAG_STREAM_TX)
{
}
if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX))
{
#ifdef BSP_USING_UART0
if (uart_device->id == UART0_ID)
Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ);
#endif
#ifdef BSP_USING_UART1
if (uart_device->id == UART1_ID)
Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ);
#endif
}
if (oflag & DEVICE_OFLAG_DMA_TX)
{
fifoCfg.txFifoDmaEnable = ENABLE;
}
if (oflag & DEVICE_OFLAG_DMA_RX)
{
fifoCfg.rxFifoDmaEnable = ENABLE;
}
UART_FifoConfig(uart_device->id, &fifoCfg);
/* enable uart */
UART_Enable(uart_device->id, UART_TXRX);
return 0;
}
/**
* @brief
*
* @param dev
* @return int
*/
int uart_close(struct device *dev)
{
uart_device_t *uart_device = (uart_device_t *)dev;
UART_Disable(uart_device->id, UART_TXRX);
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int uart_control(struct device *dev, int cmd, void *args)
{
uart_device_t *uart_device = (uart_device_t *)dev;
switch (cmd)
{
case DEVICE_CTRL_SET_INT /* constant-expression */:
{
uint32_t offset = __builtin_ctz((uint32_t)args);
while ((0 <= offset) && (offset < 9))
{
if ((uint32_t)args & (1 << offset))
{
UART_IntMask(uart_device->id, offset, UNMASK);
}
offset++;
}
if (uart_device->id == UART0_ID)
NVIC_EnableIRQ(UART0_IRQn);
else if (uart_device->id == UART1_ID)
NVIC_EnableIRQ(UART1_IRQn);
break;
}
case DEVICE_CTRL_CLR_INT /* constant-expression */:
{
uint32_t offset = __builtin_ctz((uint32_t)args);
while ((0 <= offset) && (offset < 9))
{
if ((uint32_t)args & (1 << offset))
{
UART_IntMask(uart_device->id, offset, MASK);
}
offset++;
}
if (uart_device->id == UART0_ID)
NVIC_DisableIRQ(UART0_IRQn);
else if (uart_device->id == UART1_ID)
NVIC_DisableIRQ(UART1_IRQn);
break;
}
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_CONFIG /* constant-expression */:
{
uart_param_cfg_t* cfg = (uart_param_cfg_t *)args;
UART_CFG_Type uart_cfg = {0};
/* Disable uart before config */
UART_Disable(uart_device->id, UART_TXRX);
uart_cfg.uartClk = 160*1000*1000;
uart_cfg.baudRate = cfg->baudrate;
uart_cfg.stopBits = cfg->stopbits;
uart_cfg.parity = cfg->parity;
uart_cfg.dataBits = cfg->databits;
uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
UART_Init(uart_device->id, &uart_cfg);
#ifdef BSP_USING_UART0
if (uart_device->id == UART0_ID)
Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ);
#endif
#ifdef BSP_USING_UART1
if (uart_device->id == UART1_ID)
Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ);
#endif
/* Enable uart */
UART_Enable(uart_device->id, UART_TXRX);
break;
}
case DEVICE_CTRL_GET_CONFIG /* constant-expression */:
break;
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
uart_device->tx_dma = (struct device *)args;
break;
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
uart_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */:
return UART_GetTxFifoCount(uart_device->id);
case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */:
return UART_GetRxFifoCount(uart_device->id);
default:
break;
}
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX)
{
struct device *dma_ch = (struct device *)uart_device->tx_dma;
if (!dma_ch)
return -1;
if(uart_device->id == 0)
{
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
dma_channel_start(dma_ch);
}
else if(uart_device->id == 1)
{
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
dma_channel_start(dma_ch);
}
return 0;
}
return UART_SendData(uart_device->id, (uint8_t *)buffer, size);
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX)
{
struct device *dma_ch = (struct device *)uart_device->rx_dma;
if (!dma_ch)
return -1;
}
return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size);
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int uart_register(enum uart_index_type index, const char *name, uint16_t flag)
{
struct device *dev;
if(UART_MAX_INDEX == 0)
return -DEVICE_EINVAL;
dev = &(uartx_device[index].parent);
dev->open = uart_open;
dev->close = uart_close;
dev->control = uart_control;
dev->write = uart_write;
dev->read = uart_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_UART;
dev->handle = NULL;
return device_register(dev, name, flag);
}
/**
* @brief
*
* @param handle
*/
void uart_isr(uart_device_t *handle)
{
uint32_t tmpVal = 0;
uint32_t maskVal = 0;
uint32_t UARTx = (UART0_BASE + handle->id * 0x100);
tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
maskVal = BL_RD_REG(UARTx, UART_INT_MASK);
if (!handle->parent.callback)
return;
/* Length of uart tx data transfer arrived interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK))
{
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END);
}
/* Length of uart rx data transfer arrived interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK))
{
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2);
handle->parent.callback(&handle->parent,NULL, 0, UART_EVENT_RX_END);
}
/* Tx fifo ready interrupt,auto-cleared when data is pushed */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FIFO_MASK))
{
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO);
}
/* Rx fifo ready interrupt,auto-cleared when data is popped */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK))
{
uint8_t buffer[UART_FIFO_MAX_LEN];
UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
handle->parent.callback(&handle->parent, &buffer[0], handle->fifo_threshold, UART_EVENT_RX_FIFO);
}
/* Rx time-out interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK))
{
uint8_t buffer[UART_FIFO_MAX_LEN];
uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
}
/* Rx parity check error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK))
{
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);
handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT);
}
/* Tx fifo overflow/underflow error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK))
{
handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT);
}
/* Rx fifo overflow/underflow error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK))
{
handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT);
}
}
#ifdef BSP_USING_UART0
/**
* @brief
*
*/
void UART0_IRQ(void)
{
uart_isr(&uartx_device[UART0_INDEX]);
}
#endif
#ifdef BSP_USING_UART1
/**
* @brief
*
*/
void UART1_IRQ(void)
{
uart_isr(&uartx_device[UART1_INDEX]);
}
#endif

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#ifndef __BL602_H__
#define __BL602_H__
/** @addtogroup Configuration_section_for_RISCV
* @{
*/
/**
* @brief Configuration of the Processor and Core Peripherals
*/
#define SystemCoreClockSet(val) BL_WR_WORD(0x4000F108,val)
#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
#ifdef ARCH_ARM
#define IRQ_NUM_BASE 0
#endif
#ifdef ARCH_RISCV
#define IRQ_NUM_BASE 16
#endif
/**
* @brief BL602 Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
#ifdef ARCH_ARM
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
#endif
#ifdef ARCH_RISCV
MSOFT_IRQn =3, /*!< 3 RISCV machine software Interrupt */
MTIME_IRQn =7, /*!< 7 RISCV machine time Interrupt */
MEXT_IRQn =11, /*!< 11 RISCV external Interrupt */
CLIC_SOFT_PEND_IRQn =12, /*!< 12 RISCV CLIC software pending Interrupt */
#endif
/****** BL602 specific Interrupt Numbers **********************************************************************/
BMX_ERR_IRQn = IRQ_NUM_BASE+0, /*!< BMX Error Interrupt */
BMX_TO_IRQn = IRQ_NUM_BASE+1, /*!< BMX Timeout Interrupt */
L1C_BMX_ERR_IRQn = IRQ_NUM_BASE+2, /*!< L1C BMX Error Interrupt */
L1C_BMX_TO_IRQn = IRQ_NUM_BASE+3, /*!< L1C BMX Timeout Interrupt */
SEC_BMX_ERR_IRQn = IRQ_NUM_BASE+4, /*!< SEC BMX Error Interrupt */
RF_TOP_INT0_IRQn = IRQ_NUM_BASE+5, /*!< RF_TOP_INT0 Interrupt */
RF_TOP_INT1_IRQn = IRQ_NUM_BASE+6, /*!< RF_TOP_INT1 Interrupt */
SDIO_IRQn = IRQ_NUM_BASE+7, /*!< SDIO Interrupt */
DMA_BMX_ERR_IRQn = IRQ_NUM_BASE+8, /*!< DMA BMX Error Interrupt */
SEC_GMAC_IRQn = IRQ_NUM_BASE+9, /*!< SEC_ENG_GMAC_INT Interrupt */
SEC_CDET_IRQn = IRQ_NUM_BASE+10, /*!< SEC_ENG_CDET_INT Interrupt */
SEC_PKA_IRQn = IRQ_NUM_BASE+11, /*!< SEC_ENG_PKA_INT Interrupt */
SEC_TRNG_IRQn = IRQ_NUM_BASE+12, /*!< SEC_ENG_TRNG_INT Interrupt */
SEC_AES_IRQn = IRQ_NUM_BASE+13, /*!< SEC_ENG_AES_INT Interrupt */
SEC_SHA_IRQn = IRQ_NUM_BASE+14, /*!< SEC_ENG_SHA_INT Interrupt */
DMA_ALL_IRQn = IRQ_NUM_BASE+15, /*!< DMA ALL Interrupt */
RESERVED0 = IRQ_NUM_BASE+16, /*!< RESERVED Interrupt */
RESERVED1 = IRQ_NUM_BASE+17, /*!< RESERVED Interrupt */
RESERVED2 = IRQ_NUM_BASE+18, /*!< RESERVED Interrupt */
IRTX_IRQn = IRQ_NUM_BASE+19, /*!< IR TX Interrupt */
IRRX_IRQn = IRQ_NUM_BASE+20, /*!< IR RX Interrupt */
RESERVED3 = IRQ_NUM_BASE+21, /*!< RESERVED Interrupt */
RESERVED4 = IRQ_NUM_BASE+22, /*!< RESERVED Interrupt */
SF_CTRL_IRQn = IRQ_NUM_BASE+23, /*!< SF_CTRL Interrupt */
RESERVED5 = IRQ_NUM_BASE+24, /*!< RESERVED Interrupt */
GPADC_DMA_IRQn = IRQ_NUM_BASE+25, /*!< GPADC_DMA Interrupt */
EFUSE_IRQn = IRQ_NUM_BASE+26, /*!< Efuse Interrupt */
SPI_IRQn = IRQ_NUM_BASE+27, /*!< SPI Interrupt */
RESERVED6 = IRQ_NUM_BASE+28, /*!< RESERVED Interrupt */
UART0_IRQn = IRQ_NUM_BASE+29, /*!< UART Interrupt */
UART1_IRQn = IRQ_NUM_BASE+30, /*!< UART1 Interrupt */
RESERVED7 = IRQ_NUM_BASE+31, /*!< RESERVED Interrupt */
I2C_IRQn = IRQ_NUM_BASE+32, /*!< I2C Interrupt */
RESERVED8 = IRQ_NUM_BASE+33, /*!< RESERVED Interrupt */
PWM_IRQn = IRQ_NUM_BASE+34, /*!< PWM Interrupt */
RESERVED9 = IRQ_NUM_BASE+35, /*!< RESERVED Interrupt */
TIMER_CH0_IRQn = IRQ_NUM_BASE+36, /*!< Timer Channel 0 Interrupt */
TIMER_CH1_IRQn = IRQ_NUM_BASE+37, /*!< Timer Channel 1 Interrupt */
TIMER_WDT_IRQn = IRQ_NUM_BASE+38, /*!< Timer Watch Dog Interrupt */
RESERVED10 = IRQ_NUM_BASE+39, /*!< RESERVED Interrupt */
RESERVED11 = IRQ_NUM_BASE+40, /*!< RESERVED Interrupt */
RESERVED12 = IRQ_NUM_BASE+41, /*!< RESERVED Interrupt */
RESERVED13 = IRQ_NUM_BASE+42, /*!< RESERVED Interrupt */
RESERVED14 = IRQ_NUM_BASE+43, /*!< RESERVED Interrupt */
GPIO_INT0_IRQn = IRQ_NUM_BASE+44, /*!< RESERVED Interrupt */
RESERVED16 = IRQ_NUM_BASE+45, /*!< RESERVED Interrupt */
RESERVED17 = IRQ_NUM_BASE+46, /*!< RESERVED Interrupt */
RESERVED18 = IRQ_NUM_BASE+47, /*!< RESERVED Interrupt */
RESERVED19 = IRQ_NUM_BASE+48, /*!< RESERVED Interrupt */
RESERVED20 = IRQ_NUM_BASE+49, /*!< RESERVED Interrupt */
PDS_WAKEUP_IRQn = IRQ_NUM_BASE+50, /*!< PDS Wakeup Interrupt */
HBN_OUT0_IRQn = IRQ_NUM_BASE+51, /*!< Hibernate out 0 Interrupt */
HBN_OUT1_IRQn = IRQ_NUM_BASE+52, /*!< Hibernate out 1 Interrupt */
BOR_IRQn = IRQ_NUM_BASE+53, /*!< BOR Interrupt */
WIFI_IRQn = IRQ_NUM_BASE+54, /*!< WIFI To CPU Interrupt */
BZ_PHY_IRQn = IRQ_NUM_BASE+55, /*!< RESERVED Interrupt */
BLE_IRQn = IRQ_NUM_BASE+56, /*!< RESERVED Interrupt */
MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE+57, /*!< mac_int_tx_rx_timer Interrupt */
MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE+58, /*!< mac_int_tx_rx_misc Interrupt */
MAC_RX_TRG_IRQn = IRQ_NUM_BASE+59, /*!< mac_int_rx_trigger Interrupt */
MAC_TX_TRG_IRQn = IRQ_NUM_BASE+60, /*!< mac_int_tx_trigger Interrupt */
MAC_GEN_IRQn = IRQ_NUM_BASE+61, /*!< mac_int_gen Interrupt */
MAC_PORT_TRG_IRQn = IRQ_NUM_BASE+62, /*!< mac_int_port_trigger Interrupt */
WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE+63, /*!< wifi IPC public Interrupt */
IRQn_LAST,
} IRQn_Type;
/**
* @brief BL602 Memory Map Definitions
*/
#define BL602_FLASH_XIP_BASE 0x23000000
#define BL602_FLASH_XIP_END (0x23000000+16*1024*1024)
#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
#define BL602_FLASH_XIP_REMAP0_END (0x33000000+16*1024*1024)
#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
#define BL602_FLASH_XIP_REMAP1_END (0x43000000+16*1024*1024)
#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
#define BL602_FLASH_XIP_REMAP2_END (0x53000000+16*1024*1024)
#define BL602_WRAM_BASE 0x42020000
#define BL602_WRAM_END (0x42020000+176*1024)
#define BL602_WRAM_REMAP0_BASE 0x22020000
#define BL602_WRAM_REMAP0_END (0x22020000+176*1024)
#define BL602_WRAM_REMAP1_BASE 0x32020000
#define BL602_WRAM_REMAP1_END (0x32020000+176*1024)
#define BL602_WRAM_REMAP2_BASE 0x52020000
#define BL602_WRAM_REMAP2_END (0x52020000+176*1024)
#define BL602_TCM_BASE 0x22008000
#define BL602_TCM_END (0x22008000+(96+176)*1024)
#define BL602_TCM_REMAP0_BASE 0x32008000
#define BL602_TCM_REMAP0_END (0x32008000+(96+176)*1024)
#define BL602_TCM_REMAP1_BASE 0x42008000
#define BL602_TCM_REMAP1_END (0x42008000+(96+176)*1024)
#define BL602_TCM_REMAP2_BASE 0x52008000
#define BL602_TCM_REMAP2_END (0x52008000+(96+176)*1024)
/*@} end of group Memory_Map_Section */
/* BL602 peripherals base address */
#define GLB_BASE ((uint32_t)0x40000000)
#define RF_BASE ((uint32_t)0x40001000)
#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */
#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */
#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */
#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */
#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
#define EF_DATA_BASE ((uint32_t)0x40007000)
#define EF_CTRL_BASE ((uint32_t)0x40007000)
#define CCI_BASE ((uint32_t)0x40008000)
#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */
#define UART0_BASE ((uint32_t)0x4000A000)
#define UART1_BASE ((uint32_t)0x4000A100)
#define SPI_BASE ((uint32_t)0x4000A200)
#define I2C_BASE ((uint32_t)0x4000A300)
#define PWM_BASE ((uint32_t)0x4000A400)
#define TIMER_BASE ((uint32_t)0x4000A500)
#define IR_BASE ((uint32_t)0x4000A600)
#define SF_CTRL_BASE ((uint32_t)0x4000B000)
#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
#define DMA_BASE ((uint32_t)0x4000C000)
#define SDU_BASE ((uint32_t)0x4000D000)
#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */
#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */
#define HBN_RAM_BASE ((uint32_t)0x40010000)
typedef enum
{
BL_AHB_SLAVE1_GLB = 0x00,
BL_AHB_SLAVE1_RF = 0x01,
BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02,
BL_AHB_SLAVE1_SEC_DBG = 0x03,
BL_AHB_SLAVE1_SEC = 0x04,
BL_AHB_SLAVE1_TZ1 = 0x05,
BL_AHB_SLAVE1_TZ2 = 0x06,
BL_AHB_SLAVE1_EFUSE = 0x07,
BL_AHB_SLAVE1_CCI = 0x08,
BL_AHB_SLAVE1_L1C = 0x09,
BL_AHB_SLAVE1_RSVD0A = 0x0A,
BL_AHB_SLAVE1_SFC = 0x0B,
BL_AHB_SLAVE1_DMA = 0x0C,
BL_AHB_SLAVE1_SDU = 0x0D,
BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
BL_AHB_SLAVE1_RSVD0F = 0x0F,
BL_AHB_SLAVE1_UART0 = 0x10,
BL_AHB_SLAVE1_UART1 = 0x11,
BL_AHB_SLAVE1_SPI = 0x12,
BL_AHB_SLAVE1_I2C = 0x13,
BL_AHB_SLAVE1_PWM = 0x14,
BL_AHB_SLAVE1_TMR = 0x15,
BL_AHB_SLAVE1_IRR = 0x16,
BL_AHB_SLAVE1_CKS = 0x17,
BL_AHB_SLAVE1_MAX = 0x18,
}BL_AHB_Slave1_Type;
typedef enum
{
BL_AHB_SEC_ENG_AES0 = 0,
BL_AHB_SEC_ENG_AES1,
BL_AHB_SEC_ENG_SHA0,
BL_AHB_SEC_ENG_SHA1,
}BL_AHB_Sec_Eng_Type;
typedef enum
{
BL_AHB_DMA0_CH0 = 0,
BL_AHB_DMA0_CH1,
BL_AHB_DMA0_CH2,
BL_AHB_DMA0_CH3,
BL_AHB_DMA0_CH4,
}BL_AHB_DMA0_CHNL_Type;
typedef enum
{
BL_CORE_MASTER_IBUS_CPU = 0,
BL_CORE_MASTER_DBUS_CPU,
BL_CORE_MASTER_BUS_S2F,
BL_CORE_MASTER_MAX,
}BL_Core_Master_Type;
typedef enum
{
BL_CORE_SLAVE0_DTCM_CPU = 0,
BL_CORE_SLAVE0_MAX,
}BL_Core_Slave0_Type;
typedef enum
{
BL_CORE_SLAVE1_XIP_CPU = 0,
BL_CORE_SLAVE1_ITCM_CPU,
BL_CORE_SLAVE1_ROM,
BL_CORE_SLAVE1_MAX,
}BL_Core_Slave1_Type;
typedef enum
{
BL_CORE_SLAVE2_F2S = 0,
BL_CORE_SLAVE2_MAX,
}BL_Core_Slave2_Type;
/**
* @}
*/
#include <stdint.h>
#include <system_bl602.h>
/* ARM CPU include files */
#ifdef ARCH_ARM
#ifdef CPU_AP_CM4
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#endif
#ifdef CPU_NP_CM0
#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
#endif
#endif
/* RISCV CPU include files */
#ifdef ARCH_RISCV
#ifdef __GNUC__
#include "cmsis_compatible_gcc.h"
#include "clic.h"
#include "riscv_encoding.h"
#endif
#endif
/**
* @}
*/
#endif

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/**
******************************************************************************
* @file cci_reg.h
* @version V1.2
* @date 2019-11-12
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __CCI_REG_H__
#define __CCI_REG_H__
#include "bl602.h"
/* 0x0 : cci_cfg */
#define CCI_CFG_OFFSET (0x0)
#define CCI_EN CCI_EN
#define CCI_EN_POS (0U)
#define CCI_EN_LEN (1U)
#define CCI_EN_MSK (((1U<<CCI_EN_LEN)-1)<<CCI_EN_POS)
#define CCI_EN_UMSK (~(((1U<<CCI_EN_LEN)-1)<<CCI_EN_POS))
#define CCI_SLV_SEL_CCI2 CCI_SLV_SEL_CCI2
#define CCI_SLV_SEL_CCI2_POS (1U)
#define CCI_SLV_SEL_CCI2_LEN (1U)
#define CCI_SLV_SEL_CCI2_MSK (((1U<<CCI_SLV_SEL_CCI2_LEN)-1)<<CCI_SLV_SEL_CCI2_POS)
#define CCI_SLV_SEL_CCI2_UMSK (~(((1U<<CCI_SLV_SEL_CCI2_LEN)-1)<<CCI_SLV_SEL_CCI2_POS))
#define CCI_MAS_SEL_CCI2 CCI_MAS_SEL_CCI2
#define CCI_MAS_SEL_CCI2_POS (2U)
#define CCI_MAS_SEL_CCI2_LEN (1U)
#define CCI_MAS_SEL_CCI2_MSK (((1U<<CCI_MAS_SEL_CCI2_LEN)-1)<<CCI_MAS_SEL_CCI2_POS)
#define CCI_MAS_SEL_CCI2_UMSK (~(((1U<<CCI_MAS_SEL_CCI2_LEN)-1)<<CCI_MAS_SEL_CCI2_POS))
#define CCI_MAS_HW_MODE CCI_MAS_HW_MODE
#define CCI_MAS_HW_MODE_POS (3U)
#define CCI_MAS_HW_MODE_LEN (1U)
#define CCI_MAS_HW_MODE_MSK (((1U<<CCI_MAS_HW_MODE_LEN)-1)<<CCI_MAS_HW_MODE_POS)
#define CCI_MAS_HW_MODE_UMSK (~(((1U<<CCI_MAS_HW_MODE_LEN)-1)<<CCI_MAS_HW_MODE_POS))
#define CCI_REG_M_CCI_SCLK_EN CCI_REG_M_CCI_SCLK_EN
#define CCI_REG_M_CCI_SCLK_EN_POS (4U)
#define CCI_REG_M_CCI_SCLK_EN_LEN (1U)
#define CCI_REG_M_CCI_SCLK_EN_MSK (((1U<<CCI_REG_M_CCI_SCLK_EN_LEN)-1)<<CCI_REG_M_CCI_SCLK_EN_POS)
#define CCI_REG_M_CCI_SCLK_EN_UMSK (~(((1U<<CCI_REG_M_CCI_SCLK_EN_LEN)-1)<<CCI_REG_M_CCI_SCLK_EN_POS))
#define CCI_REG_DIV_M_CCI_SCLK CCI_REG_DIV_M_CCI_SCLK
#define CCI_REG_DIV_M_CCI_SCLK_POS (5U)
#define CCI_REG_DIV_M_CCI_SCLK_LEN (2U)
#define CCI_REG_DIV_M_CCI_SCLK_MSK (((1U<<CCI_REG_DIV_M_CCI_SCLK_LEN)-1)<<CCI_REG_DIV_M_CCI_SCLK_POS)
#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U<<CCI_REG_DIV_M_CCI_SCLK_LEN)-1)<<CCI_REG_DIV_M_CCI_SCLK_POS))
#define CCI_CFG_CCI1_PRE_READ CCI_CFG_CCI1_PRE_READ
#define CCI_CFG_CCI1_PRE_READ_POS (7U)
#define CCI_CFG_CCI1_PRE_READ_LEN (1U)
#define CCI_CFG_CCI1_PRE_READ_MSK (((1U<<CCI_CFG_CCI1_PRE_READ_LEN)-1)<<CCI_CFG_CCI1_PRE_READ_POS)
#define CCI_CFG_CCI1_PRE_READ_UMSK (~(((1U<<CCI_CFG_CCI1_PRE_READ_LEN)-1)<<CCI_CFG_CCI1_PRE_READ_POS))
#define CCI_REG_SCCI_CLK_INV CCI_REG_SCCI_CLK_INV
#define CCI_REG_SCCI_CLK_INV_POS (8U)
#define CCI_REG_SCCI_CLK_INV_LEN (1U)
#define CCI_REG_SCCI_CLK_INV_MSK (((1U<<CCI_REG_SCCI_CLK_INV_LEN)-1)<<CCI_REG_SCCI_CLK_INV_POS)
#define CCI_REG_SCCI_CLK_INV_UMSK (~(((1U<<CCI_REG_SCCI_CLK_INV_LEN)-1)<<CCI_REG_SCCI_CLK_INV_POS))
#define CCI_REG_MCCI_CLK_INV CCI_REG_MCCI_CLK_INV
#define CCI_REG_MCCI_CLK_INV_POS (9U)
#define CCI_REG_MCCI_CLK_INV_LEN (1U)
#define CCI_REG_MCCI_CLK_INV_MSK (((1U<<CCI_REG_MCCI_CLK_INV_LEN)-1)<<CCI_REG_MCCI_CLK_INV_POS)
#define CCI_REG_MCCI_CLK_INV_UMSK (~(((1U<<CCI_REG_MCCI_CLK_INV_LEN)-1)<<CCI_REG_MCCI_CLK_INV_POS))
/* 0x4 : cci_addr */
#define CCI_ADDR_OFFSET (0x4)
#define CCI_APB_CCI_ADDR CCI_APB_CCI_ADDR
#define CCI_APB_CCI_ADDR_POS (0U)
#define CCI_APB_CCI_ADDR_LEN (32U)
#define CCI_APB_CCI_ADDR_MSK (((1U<<CCI_APB_CCI_ADDR_LEN)-1)<<CCI_APB_CCI_ADDR_POS)
#define CCI_APB_CCI_ADDR_UMSK (~(((1U<<CCI_APB_CCI_ADDR_LEN)-1)<<CCI_APB_CCI_ADDR_POS))
/* 0x8 : cci_wdata */
#define CCI_WDATA_OFFSET (0x8)
#define CCI_APB_CCI_WDATA CCI_APB_CCI_WDATA
#define CCI_APB_CCI_WDATA_POS (0U)
#define CCI_APB_CCI_WDATA_LEN (32U)
#define CCI_APB_CCI_WDATA_MSK (((1U<<CCI_APB_CCI_WDATA_LEN)-1)<<CCI_APB_CCI_WDATA_POS)
#define CCI_APB_CCI_WDATA_UMSK (~(((1U<<CCI_APB_CCI_WDATA_LEN)-1)<<CCI_APB_CCI_WDATA_POS))
/* 0xC : cci_rdata */
#define CCI_RDATA_OFFSET (0xC)
#define CCI_APB_CCI_RDATA CCI_APB_CCI_RDATA
#define CCI_APB_CCI_RDATA_POS (0U)
#define CCI_APB_CCI_RDATA_LEN (32U)
#define CCI_APB_CCI_RDATA_MSK (((1U<<CCI_APB_CCI_RDATA_LEN)-1)<<CCI_APB_CCI_RDATA_POS)
#define CCI_APB_CCI_RDATA_UMSK (~(((1U<<CCI_APB_CCI_RDATA_LEN)-1)<<CCI_APB_CCI_RDATA_POS))
/* 0x10 : cci_ctl */
#define CCI_CTL_OFFSET (0x10)
#define CCI_WRITE_FLAG CCI_WRITE_FLAG
#define CCI_WRITE_FLAG_POS (0U)
#define CCI_WRITE_FLAG_LEN (1U)
#define CCI_WRITE_FLAG_MSK (((1U<<CCI_WRITE_FLAG_LEN)-1)<<CCI_WRITE_FLAG_POS)
#define CCI_WRITE_FLAG_UMSK (~(((1U<<CCI_WRITE_FLAG_LEN)-1)<<CCI_WRITE_FLAG_POS))
#define CCI_READ_FLAG CCI_READ_FLAG
#define CCI_READ_FLAG_POS (1U)
#define CCI_READ_FLAG_LEN (1U)
#define CCI_READ_FLAG_MSK (((1U<<CCI_READ_FLAG_LEN)-1)<<CCI_READ_FLAG_POS)
#define CCI_READ_FLAG_UMSK (~(((1U<<CCI_READ_FLAG_LEN)-1)<<CCI_READ_FLAG_POS))
#define CCI_AHB_STATE CCI_AHB_STATE
#define CCI_AHB_STATE_POS (2U)
#define CCI_AHB_STATE_LEN (2U)
#define CCI_AHB_STATE_MSK (((1U<<CCI_AHB_STATE_LEN)-1)<<CCI_AHB_STATE_POS)
#define CCI_AHB_STATE_UMSK (~(((1U<<CCI_AHB_STATE_LEN)-1)<<CCI_AHB_STATE_POS))
struct cci_reg {
/* 0x0 : cci_cfg */
union {
struct {
uint32_t cci_en : 1; /* [ 0], r/w, 0x1 */
uint32_t cci_slv_sel_cci2 : 1; /* [ 1], r/w, 0x0 */
uint32_t cci_mas_sel_cci2 : 1; /* [ 2], r/w, 0x0 */
uint32_t cci_mas_hw_mode : 1; /* [ 3], r/w, 0x0 */
uint32_t reg_m_cci_sclk_en : 1; /* [ 4], r/w, 0x0 */
uint32_t reg_div_m_cci_sclk : 2; /* [ 6: 5], r/w, 0x1 */
uint32_t cfg_cci1_pre_read : 1; /* [ 7], r/w, 0x0 */
uint32_t reg_scci_clk_inv : 1; /* [ 8], r/w, 0x0 */
uint32_t reg_mcci_clk_inv : 1; /* [ 9], r/w, 0x1 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
}BF;
uint32_t WORD;
} cci_cfg;
/* 0x4 : cci_addr */
union {
struct {
uint32_t apb_cci_addr : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} cci_addr;
/* 0x8 : cci_wdata */
union {
struct {
uint32_t apb_cci_wdata : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} cci_wdata;
/* 0xC : cci_rdata */
union {
struct {
uint32_t apb_cci_rdata : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} cci_rdata;
/* 0x10 : cci_ctl */
union {
struct {
uint32_t cci_write_flag : 1; /* [ 0], r, 0x0 */
uint32_t cci_read_flag : 1; /* [ 1], r, 0x0 */
uint32_t ahb_state : 2; /* [ 3: 2], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
}BF;
uint32_t WORD;
} cci_ctl;
};
typedef volatile struct cci_reg cci_reg_t;
#endif /* __CCI_REG_H__ */

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/**
******************************************************************************
* @file cks_reg.h
* @version V1.2
* @date 2019-11-08
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __CKS_REG_H__
#define __CKS_REG_H__
#include "bl602.h"
/* 0x0 : cks_config */
#define CKS_CONFIG_OFFSET (0x0)
#define CKS_CR_CKS_CLR CKS_CR_CKS_CLR
#define CKS_CR_CKS_CLR_POS (0U)
#define CKS_CR_CKS_CLR_LEN (1U)
#define CKS_CR_CKS_CLR_MSK (((1U<<CKS_CR_CKS_CLR_LEN)-1)<<CKS_CR_CKS_CLR_POS)
#define CKS_CR_CKS_CLR_UMSK (~(((1U<<CKS_CR_CKS_CLR_LEN)-1)<<CKS_CR_CKS_CLR_POS))
#define CKS_CR_CKS_BYTE_SWAP CKS_CR_CKS_BYTE_SWAP
#define CKS_CR_CKS_BYTE_SWAP_POS (1U)
#define CKS_CR_CKS_BYTE_SWAP_LEN (1U)
#define CKS_CR_CKS_BYTE_SWAP_MSK (((1U<<CKS_CR_CKS_BYTE_SWAP_LEN)-1)<<CKS_CR_CKS_BYTE_SWAP_POS)
#define CKS_CR_CKS_BYTE_SWAP_UMSK (~(((1U<<CKS_CR_CKS_BYTE_SWAP_LEN)-1)<<CKS_CR_CKS_BYTE_SWAP_POS))
/* 0x4 : data_in */
#define CKS_DATA_IN_OFFSET (0x4)
#define CKS_DATA_IN CKS_DATA_IN
#define CKS_DATA_IN_POS (0U)
#define CKS_DATA_IN_LEN (8U)
#define CKS_DATA_IN_MSK (((1U<<CKS_DATA_IN_LEN)-1)<<CKS_DATA_IN_POS)
#define CKS_DATA_IN_UMSK (~(((1U<<CKS_DATA_IN_LEN)-1)<<CKS_DATA_IN_POS))
/* 0x8 : cks_out */
#define CKS_OUT_OFFSET (0x8)
#define CKS_OUT CKS_OUT
#define CKS_OUT_POS (0U)
#define CKS_OUT_LEN (16U)
#define CKS_OUT_MSK (((1U<<CKS_OUT_LEN)-1)<<CKS_OUT_POS)
#define CKS_OUT_UMSK (~(((1U<<CKS_OUT_LEN)-1)<<CKS_OUT_POS))
struct cks_reg {
/* 0x0 : cks_config */
union {
struct {
uint32_t cr_cks_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t cr_cks_byte_swap : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
}BF;
uint32_t WORD;
} cks_config;
/* 0x4 : data_in */
union {
struct {
uint32_t data_in : 8; /* [ 7: 0], w, x */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} data_in;
/* 0x8 : cks_out */
union {
struct {
uint32_t cks_out : 16; /* [15: 0], r, 0xffff */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} cks_out;
};
typedef volatile struct cks_reg cks_reg_t;
#endif /* __CKS_REG_H__ */

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drivers/bl602_driver/regs/dma_reg.h Normal file
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drivers/bl602_driver/regs/ef_ctrl_reg.h Normal file
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/**
******************************************************************************
* @file ef_ctrl_reg.h
* @version V1.2
* @date 2019-11-22
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_CTRL_REG_H__
#define __EF_CTRL_REG_H__
#include "bl602.h"
/* 0x800 : ef_if_ctrl_0 */
#define EF_CTRL_EF_IF_CTRL_0_OFFSET (0x800)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS (0U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK (((1U<<EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN)-1)<<EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U<<EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN)-1)<<EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE EF_CTRL_EF_IF_0_AUTOLOAD_DONE
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN (1U)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK (((1U<<EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN)-1)<<EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK (~(((1U<<EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN)-1)<<EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
#define EF_CTRL_EF_IF_0_BUSY EF_CTRL_EF_IF_0_BUSY
#define EF_CTRL_EF_IF_0_BUSY_POS (2U)
#define EF_CTRL_EF_IF_0_BUSY_LEN (1U)
#define EF_CTRL_EF_IF_0_BUSY_MSK (((1U<<EF_CTRL_EF_IF_0_BUSY_LEN)-1)<<EF_CTRL_EF_IF_0_BUSY_POS)
#define EF_CTRL_EF_IF_0_BUSY_UMSK (~(((1U<<EF_CTRL_EF_IF_0_BUSY_LEN)-1)<<EF_CTRL_EF_IF_0_BUSY_POS))
#define EF_CTRL_EF_IF_0_RW EF_CTRL_EF_IF_0_RW
#define EF_CTRL_EF_IF_0_RW_POS (3U)
#define EF_CTRL_EF_IF_0_RW_LEN (1U)
#define EF_CTRL_EF_IF_0_RW_MSK (((1U<<EF_CTRL_EF_IF_0_RW_LEN)-1)<<EF_CTRL_EF_IF_0_RW_POS)
#define EF_CTRL_EF_IF_0_RW_UMSK (~(((1U<<EF_CTRL_EF_IF_0_RW_LEN)-1)<<EF_CTRL_EF_IF_0_RW_POS))
#define EF_CTRL_EF_IF_0_TRIG EF_CTRL_EF_IF_0_TRIG
#define EF_CTRL_EF_IF_0_TRIG_POS (4U)
#define EF_CTRL_EF_IF_0_TRIG_LEN (1U)
#define EF_CTRL_EF_IF_0_TRIG_MSK (((1U<<EF_CTRL_EF_IF_0_TRIG_LEN)-1)<<EF_CTRL_EF_IF_0_TRIG_POS)
#define EF_CTRL_EF_IF_0_TRIG_UMSK (~(((1U<<EF_CTRL_EF_IF_0_TRIG_LEN)-1)<<EF_CTRL_EF_IF_0_TRIG_POS))
#define EF_CTRL_EF_IF_0_MANUAL_EN EF_CTRL_EF_IF_0_MANUAL_EN
#define EF_CTRL_EF_IF_0_MANUAL_EN_POS (5U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN (1U)
#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK (((1U<<EF_CTRL_EF_IF_0_MANUAL_EN_LEN)-1)<<EF_CTRL_EF_IF_0_MANUAL_EN_POS)
#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK (~(((1U<<EF_CTRL_EF_IF_0_MANUAL_EN_LEN)-1)<<EF_CTRL_EF_IF_0_MANUAL_EN_POS))
#define EF_CTRL_EF_IF_0_CYC_MODIFY EF_CTRL_EF_IF_0_CYC_MODIFY
#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS (6U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN (1U)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK (((1U<<EF_CTRL_EF_IF_0_CYC_MODIFY_LEN)-1)<<EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK (~(((1U<<EF_CTRL_EF_IF_0_CYC_MODIFY_LEN)-1)<<EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL EF_CTRL_EF_CLK_SAHB_DATA_SEL
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS (7U)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN (1U)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK (((1U<<EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN)-1)<<EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK (~(((1U<<EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN)-1)<<EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CTRL EF_CTRL_EF_IF_PROT_CODE_CTRL
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK (((1U<<EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN)-1)<<EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK (~(((1U<<EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN)-1)<<EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
#define EF_CTRL_EF_IF_POR_DIG EF_CTRL_EF_IF_POR_DIG
#define EF_CTRL_EF_IF_POR_DIG_POS (16U)
#define EF_CTRL_EF_IF_POR_DIG_LEN (1U)
#define EF_CTRL_EF_IF_POR_DIG_MSK (((1U<<EF_CTRL_EF_IF_POR_DIG_LEN)-1)<<EF_CTRL_EF_IF_POR_DIG_POS)
#define EF_CTRL_EF_IF_POR_DIG_UMSK (~(((1U<<EF_CTRL_EF_IF_POR_DIG_LEN)-1)<<EF_CTRL_EF_IF_POR_DIG_POS))
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE EF_CTRL_EF_CLK_SAHB_DATA_GATE
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS (17U)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN (1U)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK (((1U<<EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN)-1)<<EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK (~(((1U<<EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN)-1)<<EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
#define EF_CTRL_EF_IF_AUTO_RD_EN EF_CTRL_EF_IF_AUTO_RD_EN
#define EF_CTRL_EF_IF_AUTO_RD_EN_POS (18U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN (1U)
#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK (((1U<<EF_CTRL_EF_IF_AUTO_RD_EN_LEN)-1)<<EF_CTRL_EF_IF_AUTO_RD_EN_POS)
#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK (~(((1U<<EF_CTRL_EF_IF_AUTO_RD_EN_LEN)-1)<<EF_CTRL_EF_IF_AUTO_RD_EN_POS))
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK EF_CTRL_EF_IF_CYC_MODIFY_LOCK
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS (19U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN (1U)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK (((1U<<EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN)-1)<<EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN)-1)<<EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
#define EF_CTRL_EF_IF_0_INT EF_CTRL_EF_IF_0_INT
#define EF_CTRL_EF_IF_0_INT_POS (20U)
#define EF_CTRL_EF_IF_0_INT_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_MSK (((1U<<EF_CTRL_EF_IF_0_INT_LEN)-1)<<EF_CTRL_EF_IF_0_INT_POS)
#define EF_CTRL_EF_IF_0_INT_UMSK (~(((1U<<EF_CTRL_EF_IF_0_INT_LEN)-1)<<EF_CTRL_EF_IF_0_INT_POS))
#define EF_CTRL_EF_IF_0_INT_CLR EF_CTRL_EF_IF_0_INT_CLR
#define EF_CTRL_EF_IF_0_INT_CLR_POS (21U)
#define EF_CTRL_EF_IF_0_INT_CLR_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_CLR_MSK (((1U<<EF_CTRL_EF_IF_0_INT_CLR_LEN)-1)<<EF_CTRL_EF_IF_0_INT_CLR_POS)
#define EF_CTRL_EF_IF_0_INT_CLR_UMSK (~(((1U<<EF_CTRL_EF_IF_0_INT_CLR_LEN)-1)<<EF_CTRL_EF_IF_0_INT_CLR_POS))
#define EF_CTRL_EF_IF_0_INT_SET EF_CTRL_EF_IF_0_INT_SET
#define EF_CTRL_EF_IF_0_INT_SET_POS (22U)
#define EF_CTRL_EF_IF_0_INT_SET_LEN (1U)
#define EF_CTRL_EF_IF_0_INT_SET_MSK (((1U<<EF_CTRL_EF_IF_0_INT_SET_LEN)-1)<<EF_CTRL_EF_IF_0_INT_SET_POS)
#define EF_CTRL_EF_IF_0_INT_SET_UMSK (~(((1U<<EF_CTRL_EF_IF_0_INT_SET_LEN)-1)<<EF_CTRL_EF_IF_0_INT_SET_POS))
#define EF_CTRL_EF_IF_PROT_CODE_CYC EF_CTRL_EF_IF_PROT_CODE_CYC
#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS (24U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK (((1U<<EF_CTRL_EF_IF_PROT_CODE_CYC_LEN)-1)<<EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK (~(((1U<<EF_CTRL_EF_IF_PROT_CODE_CYC_LEN)-1)<<EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
/* 0x804 : ef_if_cyc_0 */
#define EF_CTRL_EF_IF_CYC_0_OFFSET (0x804)
#define EF_CTRL_EF_IF_CYC_RD_DMY EF_CTRL_EF_IF_CYC_RD_DMY
#define EF_CTRL_EF_IF_CYC_RD_DMY_POS (0U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK (((1U<<EF_CTRL_EF_IF_CYC_RD_DMY_LEN)-1)<<EF_CTRL_EF_IF_CYC_RD_DMY_POS)
#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_RD_DMY_LEN)-1)<<EF_CTRL_EF_IF_CYC_RD_DMY_POS))
#define EF_CTRL_EF_IF_CYC_RD_DAT EF_CTRL_EF_IF_CYC_RD_DAT
#define EF_CTRL_EF_IF_CYC_RD_DAT_POS (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK (((1U<<EF_CTRL_EF_IF_CYC_RD_DAT_LEN)-1)<<EF_CTRL_EF_IF_CYC_RD_DAT_POS)
#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_RD_DAT_LEN)-1)<<EF_CTRL_EF_IF_CYC_RD_DAT_POS))
#define EF_CTRL_EF_IF_CYC_RD_ADR EF_CTRL_EF_IF_CYC_RD_ADR
#define EF_CTRL_EF_IF_CYC_RD_ADR_POS (12U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN (6U)
#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK (((1U<<EF_CTRL_EF_IF_CYC_RD_ADR_LEN)-1)<<EF_CTRL_EF_IF_CYC_RD_ADR_POS)
#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_RD_ADR_LEN)-1)<<EF_CTRL_EF_IF_CYC_RD_ADR_POS))
#define EF_CTRL_EF_IF_CYC_CS EF_CTRL_EF_IF_CYC_CS
#define EF_CTRL_EF_IF_CYC_CS_POS (18U)
#define EF_CTRL_EF_IF_CYC_CS_LEN (6U)
#define EF_CTRL_EF_IF_CYC_CS_MSK (((1U<<EF_CTRL_EF_IF_CYC_CS_LEN)-1)<<EF_CTRL_EF_IF_CYC_CS_POS)
#define EF_CTRL_EF_IF_CYC_CS_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_CS_LEN)-1)<<EF_CTRL_EF_IF_CYC_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_S EF_CTRL_EF_IF_CYC_PD_CS_S
#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS (24U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN (8U)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK (((1U<<EF_CTRL_EF_IF_CYC_PD_CS_S_LEN)-1)<<EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_PD_CS_S_LEN)-1)<<EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
/* 0x808 : ef_if_cyc_1 */
#define EF_CTRL_EF_IF_CYC_1_OFFSET (0x808)
#define EF_CTRL_EF_IF_CYC_PI EF_CTRL_EF_IF_CYC_PI
#define EF_CTRL_EF_IF_CYC_PI_POS (0U)
#define EF_CTRL_EF_IF_CYC_PI_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PI_MSK (((1U<<EF_CTRL_EF_IF_CYC_PI_LEN)-1)<<EF_CTRL_EF_IF_CYC_PI_POS)
#define EF_CTRL_EF_IF_CYC_PI_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_PI_LEN)-1)<<EF_CTRL_EF_IF_CYC_PI_POS))
#define EF_CTRL_EF_IF_CYC_PP EF_CTRL_EF_IF_CYC_PP
#define EF_CTRL_EF_IF_CYC_PP_POS (6U)
#define EF_CTRL_EF_IF_CYC_PP_LEN (8U)
#define EF_CTRL_EF_IF_CYC_PP_MSK (((1U<<EF_CTRL_EF_IF_CYC_PP_LEN)-1)<<EF_CTRL_EF_IF_CYC_PP_POS)
#define EF_CTRL_EF_IF_CYC_PP_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_PP_LEN)-1)<<EF_CTRL_EF_IF_CYC_PP_POS))
#define EF_CTRL_EF_IF_CYC_WR_ADR EF_CTRL_EF_IF_CYC_WR_ADR
#define EF_CTRL_EF_IF_CYC_WR_ADR_POS (14U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN (6U)
#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK (((1U<<EF_CTRL_EF_IF_CYC_WR_ADR_LEN)-1)<<EF_CTRL_EF_IF_CYC_WR_ADR_POS)
#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_WR_ADR_LEN)-1)<<EF_CTRL_EF_IF_CYC_WR_ADR_POS))
#define EF_CTRL_EF_IF_CYC_PS_CS EF_CTRL_EF_IF_CYC_PS_CS
#define EF_CTRL_EF_IF_CYC_PS_CS_POS (20U)
#define EF_CTRL_EF_IF_CYC_PS_CS_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PS_CS_MSK (((1U<<EF_CTRL_EF_IF_CYC_PS_CS_LEN)-1)<<EF_CTRL_EF_IF_CYC_PS_CS_POS)
#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_PS_CS_LEN)-1)<<EF_CTRL_EF_IF_CYC_PS_CS_POS))
#define EF_CTRL_EF_IF_CYC_PD_CS_H EF_CTRL_EF_IF_CYC_PD_CS_H
#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS (26U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN (6U)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK (((1U<<EF_CTRL_EF_IF_CYC_PD_CS_H_LEN)-1)<<EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U<<EF_CTRL_EF_IF_CYC_PD_CS_H_LEN)-1)<<EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
/* 0x80C : ef_if_0_manual */
#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C)
#define EF_CTRL_EF_IF_A EF_CTRL_EF_IF_A
#define EF_CTRL_EF_IF_A_POS (0U)
#define EF_CTRL_EF_IF_A_LEN (10U)
#define EF_CTRL_EF_IF_A_MSK (((1U<<EF_CTRL_EF_IF_A_LEN)-1)<<EF_CTRL_EF_IF_A_POS)
#define EF_CTRL_EF_IF_A_UMSK (~(((1U<<EF_CTRL_EF_IF_A_LEN)-1)<<EF_CTRL_EF_IF_A_POS))
#define EF_CTRL_EF_IF_PD EF_CTRL_EF_IF_PD
#define EF_CTRL_EF_IF_PD_POS (10U)
#define EF_CTRL_EF_IF_PD_LEN (1U)
#define EF_CTRL_EF_IF_PD_MSK (((1U<<EF_CTRL_EF_IF_PD_LEN)-1)<<EF_CTRL_EF_IF_PD_POS)
#define EF_CTRL_EF_IF_PD_UMSK (~(((1U<<EF_CTRL_EF_IF_PD_LEN)-1)<<EF_CTRL_EF_IF_PD_POS))
#define EF_CTRL_EF_IF_PS EF_CTRL_EF_IF_PS
#define EF_CTRL_EF_IF_PS_POS (11U)
#define EF_CTRL_EF_IF_PS_LEN (1U)
#define EF_CTRL_EF_IF_PS_MSK (((1U<<EF_CTRL_EF_IF_PS_LEN)-1)<<EF_CTRL_EF_IF_PS_POS)
#define EF_CTRL_EF_IF_PS_UMSK (~(((1U<<EF_CTRL_EF_IF_PS_LEN)-1)<<EF_CTRL_EF_IF_PS_POS))
#define EF_CTRL_EF_IF_STROBE EF_CTRL_EF_IF_STROBE
#define EF_CTRL_EF_IF_STROBE_POS (12U)
#define EF_CTRL_EF_IF_STROBE_LEN (1U)
#define EF_CTRL_EF_IF_STROBE_MSK (((1U<<EF_CTRL_EF_IF_STROBE_LEN)-1)<<EF_CTRL_EF_IF_STROBE_POS)
#define EF_CTRL_EF_IF_STROBE_UMSK (~(((1U<<EF_CTRL_EF_IF_STROBE_LEN)-1)<<EF_CTRL_EF_IF_STROBE_POS))
#define EF_CTRL_EF_IF_PGENB EF_CTRL_EF_IF_PGENB
#define EF_CTRL_EF_IF_PGENB_POS (13U)
#define EF_CTRL_EF_IF_PGENB_LEN (1U)
#define EF_CTRL_EF_IF_PGENB_MSK (((1U<<EF_CTRL_EF_IF_PGENB_LEN)-1)<<EF_CTRL_EF_IF_PGENB_POS)
#define EF_CTRL_EF_IF_PGENB_UMSK (~(((1U<<EF_CTRL_EF_IF_PGENB_LEN)-1)<<EF_CTRL_EF_IF_PGENB_POS))
#define EF_CTRL_EF_IF_LOAD EF_CTRL_EF_IF_LOAD
#define EF_CTRL_EF_IF_LOAD_POS (14U)
#define EF_CTRL_EF_IF_LOAD_LEN (1U)
#define EF_CTRL_EF_IF_LOAD_MSK (((1U<<EF_CTRL_EF_IF_LOAD_LEN)-1)<<EF_CTRL_EF_IF_LOAD_POS)
#define EF_CTRL_EF_IF_LOAD_UMSK (~(((1U<<EF_CTRL_EF_IF_LOAD_LEN)-1)<<EF_CTRL_EF_IF_LOAD_POS))
#define EF_CTRL_EF_IF_CSB EF_CTRL_EF_IF_CSB
#define EF_CTRL_EF_IF_CSB_POS (15U)
#define EF_CTRL_EF_IF_CSB_LEN (1U)
#define EF_CTRL_EF_IF_CSB_MSK (((1U<<EF_CTRL_EF_IF_CSB_LEN)-1)<<EF_CTRL_EF_IF_CSB_POS)
#define EF_CTRL_EF_IF_CSB_UMSK (~(((1U<<EF_CTRL_EF_IF_CSB_LEN)-1)<<EF_CTRL_EF_IF_CSB_POS))
#define EF_CTRL_EF_IF_0_Q EF_CTRL_EF_IF_0_Q
#define EF_CTRL_EF_IF_0_Q_POS (16U)
#define EF_CTRL_EF_IF_0_Q_LEN (8U)
#define EF_CTRL_EF_IF_0_Q_MSK (((1U<<EF_CTRL_EF_IF_0_Q_LEN)-1)<<EF_CTRL_EF_IF_0_Q_POS)
#define EF_CTRL_EF_IF_0_Q_UMSK (~(((1U<<EF_CTRL_EF_IF_0_Q_LEN)-1)<<EF_CTRL_EF_IF_0_Q_POS))
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL EF_CTRL_EF_IF_PROT_CODE_MANUAL
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS (24U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN (8U)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK (((1U<<EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN)-1)<<EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U<<EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN)-1)<<EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
/* 0x810 : ef_if_0_status */
#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
#define EF_CTRL_EF_IF_0_STATUS EF_CTRL_EF_IF_0_STATUS
#define EF_CTRL_EF_IF_0_STATUS_POS (0U)
#define EF_CTRL_EF_IF_0_STATUS_LEN (32U)
#define EF_CTRL_EF_IF_0_STATUS_MSK (((1U<<EF_CTRL_EF_IF_0_STATUS_LEN)-1)<<EF_CTRL_EF_IF_0_STATUS_POS)
#define EF_CTRL_EF_IF_0_STATUS_UMSK (~(((1U<<EF_CTRL_EF_IF_0_STATUS_LEN)-1)<<EF_CTRL_EF_IF_0_STATUS_POS))
/* 0x814 : ef_if_cfg_0 */
#define EF_CTRL_EF_IF_CFG_0_OFFSET (0x814)
#define EF_CTRL_EF_IF_SF_AES_MODE EF_CTRL_EF_IF_SF_AES_MODE
#define EF_CTRL_EF_IF_SF_AES_MODE_POS (0U)
#define EF_CTRL_EF_IF_SF_AES_MODE_LEN (2U)
#define EF_CTRL_EF_IF_SF_AES_MODE_MSK (((1U<<EF_CTRL_EF_IF_SF_AES_MODE_LEN)-1)<<EF_CTRL_EF_IF_SF_AES_MODE_POS)
#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK (~(((1U<<EF_CTRL_EF_IF_SF_AES_MODE_LEN)-1)<<EF_CTRL_EF_IF_SF_AES_MODE_POS))
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE EF_CTRL_EF_IF_SBOOT_SIGN_MODE
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS (2U)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK (((1U<<EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN)-1)<<EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)
#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U<<EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN)-1)<<EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS))
#define EF_CTRL_EF_IF_SBOOT_EN EF_CTRL_EF_IF_SBOOT_EN
#define EF_CTRL_EF_IF_SBOOT_EN_POS (4U)
#define EF_CTRL_EF_IF_SBOOT_EN_LEN (2U)
#define EF_CTRL_EF_IF_SBOOT_EN_MSK (((1U<<EF_CTRL_EF_IF_SBOOT_EN_LEN)-1)<<EF_CTRL_EF_IF_SBOOT_EN_POS)
#define EF_CTRL_EF_IF_SBOOT_EN_UMSK (~(((1U<<EF_CTRL_EF_IF_SBOOT_EN_LEN)-1)<<EF_CTRL_EF_IF_SBOOT_EN_POS))
#define EF_CTRL_EF_IF_CPU1_ENC_EN EF_CTRL_EF_IF_CPU1_ENC_EN
#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS (6U)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK (((1U<<EF_CTRL_EF_IF_CPU1_ENC_EN_LEN)-1)<<EF_CTRL_EF_IF_CPU1_ENC_EN_POS)
#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK (~(((1U<<EF_CTRL_EF_IF_CPU1_ENC_EN_LEN)-1)<<EF_CTRL_EF_IF_CPU1_ENC_EN_POS))
#define EF_CTRL_EF_IF_CPU0_ENC_EN EF_CTRL_EF_IF_CPU0_ENC_EN
#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS (7U)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK (((1U<<EF_CTRL_EF_IF_CPU0_ENC_EN_LEN)-1)<<EF_CTRL_EF_IF_CPU0_ENC_EN_POS)
#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK (~(((1U<<EF_CTRL_EF_IF_CPU0_ENC_EN_LEN)-1)<<EF_CTRL_EF_IF_CPU0_ENC_EN_POS))
#define EF_CTRL_EF_IF_BOOT_SEL EF_CTRL_EF_IF_BOOT_SEL
#define EF_CTRL_EF_IF_BOOT_SEL_POS (8U)
#define EF_CTRL_EF_IF_BOOT_SEL_LEN (4U)
#define EF_CTRL_EF_IF_BOOT_SEL_MSK (((1U<<EF_CTRL_EF_IF_BOOT_SEL_LEN)-1)<<EF_CTRL_EF_IF_BOOT_SEL_POS)
#define EF_CTRL_EF_IF_BOOT_SEL_UMSK (~(((1U<<EF_CTRL_EF_IF_BOOT_SEL_LEN)-1)<<EF_CTRL_EF_IF_BOOT_SEL_POS))
#define EF_CTRL_EF_IF_SW_USAGE_1 EF_CTRL_EF_IF_SW_USAGE_1
#define EF_CTRL_EF_IF_SW_USAGE_1_POS (12U)
#define EF_CTRL_EF_IF_SW_USAGE_1_LEN (2U)
#define EF_CTRL_EF_IF_SW_USAGE_1_MSK (((1U<<EF_CTRL_EF_IF_SW_USAGE_1_LEN)-1)<<EF_CTRL_EF_IF_SW_USAGE_1_POS)
#define EF_CTRL_EF_IF_SW_USAGE_1_UMSK (~(((1U<<EF_CTRL_EF_IF_SW_USAGE_1_LEN)-1)<<EF_CTRL_EF_IF_SW_USAGE_1_POS))
#define EF_CTRL_EF_IF_SDU_DIS EF_CTRL_EF_IF_SDU_DIS
#define EF_CTRL_EF_IF_SDU_DIS_POS (14U)
#define EF_CTRL_EF_IF_SDU_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SDU_DIS_MSK (((1U<<EF_CTRL_EF_IF_SDU_DIS_LEN)-1)<<EF_CTRL_EF_IF_SDU_DIS_POS)
#define EF_CTRL_EF_IF_SDU_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_SDU_DIS_LEN)-1)<<EF_CTRL_EF_IF_SDU_DIS_POS))
#define EF_CTRL_EF_IF_BLE_DIS EF_CTRL_EF_IF_BLE_DIS
#define EF_CTRL_EF_IF_BLE_DIS_POS (15U)
#define EF_CTRL_EF_IF_BLE_DIS_LEN (1U)
#define EF_CTRL_EF_IF_BLE_DIS_MSK (((1U<<EF_CTRL_EF_IF_BLE_DIS_LEN)-1)<<EF_CTRL_EF_IF_BLE_DIS_POS)
#define EF_CTRL_EF_IF_BLE_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_BLE_DIS_LEN)-1)<<EF_CTRL_EF_IF_BLE_DIS_POS))
#define EF_CTRL_EF_IF_WIFI_DIS EF_CTRL_EF_IF_WIFI_DIS
#define EF_CTRL_EF_IF_WIFI_DIS_POS (16U)
#define EF_CTRL_EF_IF_WIFI_DIS_LEN (1U)
#define EF_CTRL_EF_IF_WIFI_DIS_MSK (((1U<<EF_CTRL_EF_IF_WIFI_DIS_LEN)-1)<<EF_CTRL_EF_IF_WIFI_DIS_POS)
#define EF_CTRL_EF_IF_WIFI_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_WIFI_DIS_LEN)-1)<<EF_CTRL_EF_IF_WIFI_DIS_POS))
#define EF_CTRL_EF_IF_0_KEY_ENC_EN EF_CTRL_EF_IF_0_KEY_ENC_EN
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS (17U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN (1U)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK (((1U<<EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN)-1)<<EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK (~(((1U<<EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN)-1)<<EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_IF_CAM_DIS EF_CTRL_EF_IF_CAM_DIS
#define EF_CTRL_EF_IF_CAM_DIS_POS (18U)
#define EF_CTRL_EF_IF_CAM_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CAM_DIS_MSK (((1U<<EF_CTRL_EF_IF_CAM_DIS_LEN)-1)<<EF_CTRL_EF_IF_CAM_DIS_POS)
#define EF_CTRL_EF_IF_CAM_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_CAM_DIS_LEN)-1)<<EF_CTRL_EF_IF_CAM_DIS_POS))
#define EF_CTRL_EF_IF_SF_DIS EF_CTRL_EF_IF_SF_DIS
#define EF_CTRL_EF_IF_SF_DIS_POS (19U)
#define EF_CTRL_EF_IF_SF_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SF_DIS_MSK (((1U<<EF_CTRL_EF_IF_SF_DIS_LEN)-1)<<EF_CTRL_EF_IF_SF_DIS_POS)
#define EF_CTRL_EF_IF_SF_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_SF_DIS_LEN)-1)<<EF_CTRL_EF_IF_SF_DIS_POS))
#define EF_CTRL_EF_IF_CPU1_DIS EF_CTRL_EF_IF_CPU1_DIS
#define EF_CTRL_EF_IF_CPU1_DIS_POS (20U)
#define EF_CTRL_EF_IF_CPU1_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU1_DIS_MSK (((1U<<EF_CTRL_EF_IF_CPU1_DIS_LEN)-1)<<EF_CTRL_EF_IF_CPU1_DIS_POS)
#define EF_CTRL_EF_IF_CPU1_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_CPU1_DIS_LEN)-1)<<EF_CTRL_EF_IF_CPU1_DIS_POS))
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS EF_CTRL_EF_IF_CPU_RST_DBG_DIS
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS (21U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK (((1U<<EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN)-1)<<EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN)-1)<<EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_IF_SE_DBG_DIS EF_CTRL_EF_IF_SE_DBG_DIS
#define EF_CTRL_EF_IF_SE_DBG_DIS_POS (22U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK (((1U<<EF_CTRL_EF_IF_SE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_IF_SE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_SE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_IF_SE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS EF_CTRL_EF_IF_EFUSE_DBG_DIS
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS (23U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK (((1U<<EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS EF_CTRL_EF_IF_DBG_JTAG_1_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS (24U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK (((1U<<EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN)-1)<<EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN)-1)<<EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS EF_CTRL_EF_IF_DBG_JTAG_0_DIS
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS (26U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK (((1U<<EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN)-1)<<EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK (~(((1U<<EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN)-1)<<EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_IF_DBG_MODE EF_CTRL_EF_IF_DBG_MODE
#define EF_CTRL_EF_IF_DBG_MODE_POS (28U)
#define EF_CTRL_EF_IF_DBG_MODE_LEN (4U)
#define EF_CTRL_EF_IF_DBG_MODE_MSK (((1U<<EF_CTRL_EF_IF_DBG_MODE_LEN)-1)<<EF_CTRL_EF_IF_DBG_MODE_POS)
#define EF_CTRL_EF_IF_DBG_MODE_UMSK (~(((1U<<EF_CTRL_EF_IF_DBG_MODE_LEN)-1)<<EF_CTRL_EF_IF_DBG_MODE_POS))
/* 0x818 : ef_sw_cfg_0 */
#define EF_CTRL_EF_SW_CFG_0_OFFSET (0x818)
#define EF_CTRL_EF_SW_SF_AES_MODE EF_CTRL_EF_SW_SF_AES_MODE
#define EF_CTRL_EF_SW_SF_AES_MODE_POS (0U)
#define EF_CTRL_EF_SW_SF_AES_MODE_LEN (2U)
#define EF_CTRL_EF_SW_SF_AES_MODE_MSK (((1U<<EF_CTRL_EF_SW_SF_AES_MODE_LEN)-1)<<EF_CTRL_EF_SW_SF_AES_MODE_POS)
#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK (~(((1U<<EF_CTRL_EF_SW_SF_AES_MODE_LEN)-1)<<EF_CTRL_EF_SW_SF_AES_MODE_POS))
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE EF_CTRL_EF_SW_SBOOT_SIGN_MODE
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS (2U)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN (2U)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK (((1U<<EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN)-1)<<EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)
#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U<<EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN)-1)<<EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS))
#define EF_CTRL_EF_SW_SBOOT_EN EF_CTRL_EF_SW_SBOOT_EN
#define EF_CTRL_EF_SW_SBOOT_EN_POS (4U)
#define EF_CTRL_EF_SW_SBOOT_EN_LEN (2U)
#define EF_CTRL_EF_SW_SBOOT_EN_MSK (((1U<<EF_CTRL_EF_SW_SBOOT_EN_LEN)-1)<<EF_CTRL_EF_SW_SBOOT_EN_POS)
#define EF_CTRL_EF_SW_SBOOT_EN_UMSK (~(((1U<<EF_CTRL_EF_SW_SBOOT_EN_LEN)-1)<<EF_CTRL_EF_SW_SBOOT_EN_POS))
#define EF_CTRL_EF_SW_CPU1_ENC_EN EF_CTRL_EF_SW_CPU1_ENC_EN
#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS (6U)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK (((1U<<EF_CTRL_EF_SW_CPU1_ENC_EN_LEN)-1)<<EF_CTRL_EF_SW_CPU1_ENC_EN_POS)
#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK (~(((1U<<EF_CTRL_EF_SW_CPU1_ENC_EN_LEN)-1)<<EF_CTRL_EF_SW_CPU1_ENC_EN_POS))
#define EF_CTRL_EF_SW_CPU0_ENC_EN EF_CTRL_EF_SW_CPU0_ENC_EN
#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS (7U)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK (((1U<<EF_CTRL_EF_SW_CPU0_ENC_EN_LEN)-1)<<EF_CTRL_EF_SW_CPU0_ENC_EN_POS)
#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK (~(((1U<<EF_CTRL_EF_SW_CPU0_ENC_EN_LEN)-1)<<EF_CTRL_EF_SW_CPU0_ENC_EN_POS))
#define EF_CTRL_EF_SW_SW_USAGE_1 EF_CTRL_EF_SW_SW_USAGE_1
#define EF_CTRL_EF_SW_SW_USAGE_1_POS (12U)
#define EF_CTRL_EF_SW_SW_USAGE_1_LEN (2U)
#define EF_CTRL_EF_SW_SW_USAGE_1_MSK (((1U<<EF_CTRL_EF_SW_SW_USAGE_1_LEN)-1)<<EF_CTRL_EF_SW_SW_USAGE_1_POS)
#define EF_CTRL_EF_SW_SW_USAGE_1_UMSK (~(((1U<<EF_CTRL_EF_SW_SW_USAGE_1_LEN)-1)<<EF_CTRL_EF_SW_SW_USAGE_1_POS))
#define EF_CTRL_EF_SW_SDU_DIS EF_CTRL_EF_SW_SDU_DIS
#define EF_CTRL_EF_SW_SDU_DIS_POS (14U)
#define EF_CTRL_EF_SW_SDU_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SDU_DIS_MSK (((1U<<EF_CTRL_EF_SW_SDU_DIS_LEN)-1)<<EF_CTRL_EF_SW_SDU_DIS_POS)
#define EF_CTRL_EF_SW_SDU_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_SDU_DIS_LEN)-1)<<EF_CTRL_EF_SW_SDU_DIS_POS))
#define EF_CTRL_EF_SW_BLE_DIS EF_CTRL_EF_SW_BLE_DIS
#define EF_CTRL_EF_SW_BLE_DIS_POS (15U)
#define EF_CTRL_EF_SW_BLE_DIS_LEN (1U)
#define EF_CTRL_EF_SW_BLE_DIS_MSK (((1U<<EF_CTRL_EF_SW_BLE_DIS_LEN)-1)<<EF_CTRL_EF_SW_BLE_DIS_POS)
#define EF_CTRL_EF_SW_BLE_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_BLE_DIS_LEN)-1)<<EF_CTRL_EF_SW_BLE_DIS_POS))
#define EF_CTRL_EF_SW_WIFI_DIS EF_CTRL_EF_SW_WIFI_DIS
#define EF_CTRL_EF_SW_WIFI_DIS_POS (16U)
#define EF_CTRL_EF_SW_WIFI_DIS_LEN (1U)
#define EF_CTRL_EF_SW_WIFI_DIS_MSK (((1U<<EF_CTRL_EF_SW_WIFI_DIS_LEN)-1)<<EF_CTRL_EF_SW_WIFI_DIS_POS)
#define EF_CTRL_EF_SW_WIFI_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_WIFI_DIS_LEN)-1)<<EF_CTRL_EF_SW_WIFI_DIS_POS))
#define EF_CTRL_EF_SW_0_KEY_ENC_EN EF_CTRL_EF_SW_0_KEY_ENC_EN
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS (17U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN (1U)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK (((1U<<EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN)-1)<<EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK (~(((1U<<EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN)-1)<<EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
#define EF_CTRL_EF_SW_CAM_DIS EF_CTRL_EF_SW_CAM_DIS
#define EF_CTRL_EF_SW_CAM_DIS_POS (18U)
#define EF_CTRL_EF_SW_CAM_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CAM_DIS_MSK (((1U<<EF_CTRL_EF_SW_CAM_DIS_LEN)-1)<<EF_CTRL_EF_SW_CAM_DIS_POS)
#define EF_CTRL_EF_SW_CAM_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_CAM_DIS_LEN)-1)<<EF_CTRL_EF_SW_CAM_DIS_POS))
#define EF_CTRL_EF_SW_SF_DIS EF_CTRL_EF_SW_SF_DIS
#define EF_CTRL_EF_SW_SF_DIS_POS (19U)
#define EF_CTRL_EF_SW_SF_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SF_DIS_MSK (((1U<<EF_CTRL_EF_SW_SF_DIS_LEN)-1)<<EF_CTRL_EF_SW_SF_DIS_POS)
#define EF_CTRL_EF_SW_SF_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_SF_DIS_LEN)-1)<<EF_CTRL_EF_SW_SF_DIS_POS))
#define EF_CTRL_EF_SW_CPU1_DIS EF_CTRL_EF_SW_CPU1_DIS
#define EF_CTRL_EF_SW_CPU1_DIS_POS (20U)
#define EF_CTRL_EF_SW_CPU1_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU1_DIS_MSK (((1U<<EF_CTRL_EF_SW_CPU1_DIS_LEN)-1)<<EF_CTRL_EF_SW_CPU1_DIS_POS)
#define EF_CTRL_EF_SW_CPU1_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_CPU1_DIS_LEN)-1)<<EF_CTRL_EF_SW_CPU1_DIS_POS))
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS EF_CTRL_EF_SW_CPU_RST_DBG_DIS
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS (21U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK (((1U<<EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN)-1)<<EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN)-1)<<EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
#define EF_CTRL_EF_SW_SE_DBG_DIS EF_CTRL_EF_SW_SE_DBG_DIS
#define EF_CTRL_EF_SW_SE_DBG_DIS_POS (22U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK (((1U<<EF_CTRL_EF_SW_SE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_SW_SE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_SE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_SW_SE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS EF_CTRL_EF_SW_EFUSE_DBG_DIS
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS (23U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN (1U)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK (((1U<<EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN)-1)<<EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS EF_CTRL_EF_SW_DBG_JTAG_1_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS (24U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK (((1U<<EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN)-1)<<EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN)-1)<<EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS EF_CTRL_EF_SW_DBG_JTAG_0_DIS
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS (26U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN (2U)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK (((1U<<EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN)-1)<<EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK (~(((1U<<EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN)-1)<<EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
#define EF_CTRL_EF_SW_DBG_MODE EF_CTRL_EF_SW_DBG_MODE
#define EF_CTRL_EF_SW_DBG_MODE_POS (28U)
#define EF_CTRL_EF_SW_DBG_MODE_LEN (4U)
#define EF_CTRL_EF_SW_DBG_MODE_MSK (((1U<<EF_CTRL_EF_SW_DBG_MODE_LEN)-1)<<EF_CTRL_EF_SW_DBG_MODE_POS)
#define EF_CTRL_EF_SW_DBG_MODE_UMSK (~(((1U<<EF_CTRL_EF_SW_DBG_MODE_LEN)-1)<<EF_CTRL_EF_SW_DBG_MODE_POS))
/* 0x81C : ef_reserved */
#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
#define EF_CTRL_EF_RESERVED EF_CTRL_EF_RESERVED
#define EF_CTRL_EF_RESERVED_POS (0U)
#define EF_CTRL_EF_RESERVED_LEN (32U)
#define EF_CTRL_EF_RESERVED_MSK (((1U<<EF_CTRL_EF_RESERVED_LEN)-1)<<EF_CTRL_EF_RESERVED_POS)
#define EF_CTRL_EF_RESERVED_UMSK (~(((1U<<EF_CTRL_EF_RESERVED_LEN)-1)<<EF_CTRL_EF_RESERVED_POS))
/* 0x820 : ef_if_ana_trim_0 */
#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820)
#define EF_CTRL_EF_IF_ANA_TRIM_0 EF_CTRL_EF_IF_ANA_TRIM_0
#define EF_CTRL_EF_IF_ANA_TRIM_0_POS (0U)
#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN (32U)
#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK (((1U<<EF_CTRL_EF_IF_ANA_TRIM_0_LEN)-1)<<EF_CTRL_EF_IF_ANA_TRIM_0_POS)
#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK (~(((1U<<EF_CTRL_EF_IF_ANA_TRIM_0_LEN)-1)<<EF_CTRL_EF_IF_ANA_TRIM_0_POS))
/* 0x824 : ef_if_sw_usage_0 */
#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824)
#define EF_CTRL_EF_IF_SW_USAGE_0 EF_CTRL_EF_IF_SW_USAGE_0
#define EF_CTRL_EF_IF_SW_USAGE_0_POS (0U)
#define EF_CTRL_EF_IF_SW_USAGE_0_LEN (32U)
#define EF_CTRL_EF_IF_SW_USAGE_0_MSK (((1U<<EF_CTRL_EF_IF_SW_USAGE_0_LEN)-1)<<EF_CTRL_EF_IF_SW_USAGE_0_POS)
#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK (~(((1U<<EF_CTRL_EF_IF_SW_USAGE_0_LEN)-1)<<EF_CTRL_EF_IF_SW_USAGE_0_POS))
/* 0xA00 : ef_crc_ctrl_0 */
#define EF_CTRL_EF_CRC_CTRL_0_OFFSET (0xA00)
#define EF_CTRL_EF_CRC_BUSY EF_CTRL_EF_CRC_BUSY
#define EF_CTRL_EF_CRC_BUSY_POS (0U)
#define EF_CTRL_EF_CRC_BUSY_LEN (1U)
#define EF_CTRL_EF_CRC_BUSY_MSK (((1U<<EF_CTRL_EF_CRC_BUSY_LEN)-1)<<EF_CTRL_EF_CRC_BUSY_POS)
#define EF_CTRL_EF_CRC_BUSY_UMSK (~(((1U<<EF_CTRL_EF_CRC_BUSY_LEN)-1)<<EF_CTRL_EF_CRC_BUSY_POS))
#define EF_CTRL_EF_CRC_TRIG EF_CTRL_EF_CRC_TRIG
#define EF_CTRL_EF_CRC_TRIG_POS (1U)
#define EF_CTRL_EF_CRC_TRIG_LEN (1U)
#define EF_CTRL_EF_CRC_TRIG_MSK (((1U<<EF_CTRL_EF_CRC_TRIG_LEN)-1)<<EF_CTRL_EF_CRC_TRIG_POS)
#define EF_CTRL_EF_CRC_TRIG_UMSK (~(((1U<<EF_CTRL_EF_CRC_TRIG_LEN)-1)<<EF_CTRL_EF_CRC_TRIG_POS))
#define EF_CTRL_EF_CRC_EN EF_CTRL_EF_CRC_EN
#define EF_CTRL_EF_CRC_EN_POS (2U)
#define EF_CTRL_EF_CRC_EN_LEN (1U)
#define EF_CTRL_EF_CRC_EN_MSK (((1U<<EF_CTRL_EF_CRC_EN_LEN)-1)<<EF_CTRL_EF_CRC_EN_POS)
#define EF_CTRL_EF_CRC_EN_UMSK (~(((1U<<EF_CTRL_EF_CRC_EN_LEN)-1)<<EF_CTRL_EF_CRC_EN_POS))
#define EF_CTRL_EF_CRC_MODE EF_CTRL_EF_CRC_MODE
#define EF_CTRL_EF_CRC_MODE_POS (3U)
#define EF_CTRL_EF_CRC_MODE_LEN (1U)
#define EF_CTRL_EF_CRC_MODE_MSK (((1U<<EF_CTRL_EF_CRC_MODE_LEN)-1)<<EF_CTRL_EF_CRC_MODE_POS)
#define EF_CTRL_EF_CRC_MODE_UMSK (~(((1U<<EF_CTRL_EF_CRC_MODE_LEN)-1)<<EF_CTRL_EF_CRC_MODE_POS))
#define EF_CTRL_EF_CRC_ERROR EF_CTRL_EF_CRC_ERROR
#define EF_CTRL_EF_CRC_ERROR_POS (4U)
#define EF_CTRL_EF_CRC_ERROR_LEN (1U)
#define EF_CTRL_EF_CRC_ERROR_MSK (((1U<<EF_CTRL_EF_CRC_ERROR_LEN)-1)<<EF_CTRL_EF_CRC_ERROR_POS)
#define EF_CTRL_EF_CRC_ERROR_UMSK (~(((1U<<EF_CTRL_EF_CRC_ERROR_LEN)-1)<<EF_CTRL_EF_CRC_ERROR_POS))
#define EF_CTRL_EF_CRC_DOUT_INV_EN EF_CTRL_EF_CRC_DOUT_INV_EN
#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS (5U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN (1U)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK (((1U<<EF_CTRL_EF_CRC_DOUT_INV_EN_LEN)-1)<<EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U<<EF_CTRL_EF_CRC_DOUT_INV_EN_LEN)-1)<<EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
#define EF_CTRL_EF_CRC_DOUT_ENDIAN EF_CTRL_EF_CRC_DOUT_ENDIAN
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS (6U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN (1U)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK (((1U<<EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN)-1)<<EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U<<EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN)-1)<<EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
#define EF_CTRL_EF_CRC_DIN_ENDIAN EF_CTRL_EF_CRC_DIN_ENDIAN
#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS (7U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN (1U)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK (((1U<<EF_CTRL_EF_CRC_DIN_ENDIAN_LEN)-1)<<EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK (~(((1U<<EF_CTRL_EF_CRC_DIN_ENDIAN_LEN)-1)<<EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
#define EF_CTRL_EF_CRC_INT EF_CTRL_EF_CRC_INT
#define EF_CTRL_EF_CRC_INT_POS (8U)
#define EF_CTRL_EF_CRC_INT_LEN (1U)
#define EF_CTRL_EF_CRC_INT_MSK (((1U<<EF_CTRL_EF_CRC_INT_LEN)-1)<<EF_CTRL_EF_CRC_INT_POS)
#define EF_CTRL_EF_CRC_INT_UMSK (~(((1U<<EF_CTRL_EF_CRC_INT_LEN)-1)<<EF_CTRL_EF_CRC_INT_POS))
#define EF_CTRL_EF_CRC_INT_CLR EF_CTRL_EF_CRC_INT_CLR
#define EF_CTRL_EF_CRC_INT_CLR_POS (9U)
#define EF_CTRL_EF_CRC_INT_CLR_LEN (1U)
#define EF_CTRL_EF_CRC_INT_CLR_MSK (((1U<<EF_CTRL_EF_CRC_INT_CLR_LEN)-1)<<EF_CTRL_EF_CRC_INT_CLR_POS)
#define EF_CTRL_EF_CRC_INT_CLR_UMSK (~(((1U<<EF_CTRL_EF_CRC_INT_CLR_LEN)-1)<<EF_CTRL_EF_CRC_INT_CLR_POS))
#define EF_CTRL_EF_CRC_INT_SET EF_CTRL_EF_CRC_INT_SET
#define EF_CTRL_EF_CRC_INT_SET_POS (10U)
#define EF_CTRL_EF_CRC_INT_SET_LEN (1U)
#define EF_CTRL_EF_CRC_INT_SET_MSK (((1U<<EF_CTRL_EF_CRC_INT_SET_LEN)-1)<<EF_CTRL_EF_CRC_INT_SET_POS)
#define EF_CTRL_EF_CRC_INT_SET_UMSK (~(((1U<<EF_CTRL_EF_CRC_INT_SET_LEN)-1)<<EF_CTRL_EF_CRC_INT_SET_POS))
#define EF_CTRL_EF_CRC_LOCK EF_CTRL_EF_CRC_LOCK
#define EF_CTRL_EF_CRC_LOCK_POS (11U)
#define EF_CTRL_EF_CRC_LOCK_LEN (1U)
#define EF_CTRL_EF_CRC_LOCK_MSK (((1U<<EF_CTRL_EF_CRC_LOCK_LEN)-1)<<EF_CTRL_EF_CRC_LOCK_POS)
#define EF_CTRL_EF_CRC_LOCK_UMSK (~(((1U<<EF_CTRL_EF_CRC_LOCK_LEN)-1)<<EF_CTRL_EF_CRC_LOCK_POS))
#define EF_CTRL_EF_CRC_SLP_N EF_CTRL_EF_CRC_SLP_N
#define EF_CTRL_EF_CRC_SLP_N_POS (16U)
#define EF_CTRL_EF_CRC_SLP_N_LEN (16U)
#define EF_CTRL_EF_CRC_SLP_N_MSK (((1U<<EF_CTRL_EF_CRC_SLP_N_LEN)-1)<<EF_CTRL_EF_CRC_SLP_N_POS)
#define EF_CTRL_EF_CRC_SLP_N_UMSK (~(((1U<<EF_CTRL_EF_CRC_SLP_N_LEN)-1)<<EF_CTRL_EF_CRC_SLP_N_POS))
/* 0xA04 : ef_crc_ctrl_1 */
#define EF_CTRL_EF_CRC_CTRL_1_OFFSET (0xA04)
#define EF_CTRL_EF_CRC_DATA_0_EN EF_CTRL_EF_CRC_DATA_0_EN
#define EF_CTRL_EF_CRC_DATA_0_EN_POS (0U)
#define EF_CTRL_EF_CRC_DATA_0_EN_LEN (32U)
#define EF_CTRL_EF_CRC_DATA_0_EN_MSK (((1U<<EF_CTRL_EF_CRC_DATA_0_EN_LEN)-1)<<EF_CTRL_EF_CRC_DATA_0_EN_POS)
#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U<<EF_CTRL_EF_CRC_DATA_0_EN_LEN)-1)<<EF_CTRL_EF_CRC_DATA_0_EN_POS))
/* 0xA08 : ef_crc_ctrl_2 */
#define EF_CTRL_EF_CRC_CTRL_2_OFFSET (0xA08)
#define EF_CTRL_EF_CRC_DATA_1_EN EF_CTRL_EF_CRC_DATA_1_EN
#define EF_CTRL_EF_CRC_DATA_1_EN_POS (0U)
#define EF_CTRL_EF_CRC_DATA_1_EN_LEN (32U)
#define EF_CTRL_EF_CRC_DATA_1_EN_MSK (((1U<<EF_CTRL_EF_CRC_DATA_1_EN_LEN)-1)<<EF_CTRL_EF_CRC_DATA_1_EN_POS)
#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U<<EF_CTRL_EF_CRC_DATA_1_EN_LEN)-1)<<EF_CTRL_EF_CRC_DATA_1_EN_POS))
/* 0xA0C : ef_crc_ctrl_3 */
#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
#define EF_CTRL_EF_CRC_IV EF_CTRL_EF_CRC_IV
#define EF_CTRL_EF_CRC_IV_POS (0U)
#define EF_CTRL_EF_CRC_IV_LEN (32U)
#define EF_CTRL_EF_CRC_IV_MSK (((1U<<EF_CTRL_EF_CRC_IV_LEN)-1)<<EF_CTRL_EF_CRC_IV_POS)
#define EF_CTRL_EF_CRC_IV_UMSK (~(((1U<<EF_CTRL_EF_CRC_IV_LEN)-1)<<EF_CTRL_EF_CRC_IV_POS))
/* 0xA10 : ef_crc_ctrl_4 */
#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
#define EF_CTRL_EF_CRC_GOLDEN EF_CTRL_EF_CRC_GOLDEN
#define EF_CTRL_EF_CRC_GOLDEN_POS (0U)
#define EF_CTRL_EF_CRC_GOLDEN_LEN (32U)
#define EF_CTRL_EF_CRC_GOLDEN_MSK (((1U<<EF_CTRL_EF_CRC_GOLDEN_LEN)-1)<<EF_CTRL_EF_CRC_GOLDEN_POS)
#define EF_CTRL_EF_CRC_GOLDEN_UMSK (~(((1U<<EF_CTRL_EF_CRC_GOLDEN_LEN)-1)<<EF_CTRL_EF_CRC_GOLDEN_POS))
/* 0xA14 : ef_crc_ctrl_5 */
#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
#define EF_CTRL_EF_CRC_DOUT EF_CTRL_EF_CRC_DOUT
#define EF_CTRL_EF_CRC_DOUT_POS (0U)
#define EF_CTRL_EF_CRC_DOUT_LEN (32U)
#define EF_CTRL_EF_CRC_DOUT_MSK (((1U<<EF_CTRL_EF_CRC_DOUT_LEN)-1)<<EF_CTRL_EF_CRC_DOUT_POS)
#define EF_CTRL_EF_CRC_DOUT_UMSK (~(((1U<<EF_CTRL_EF_CRC_DOUT_LEN)-1)<<EF_CTRL_EF_CRC_DOUT_POS))
struct ef_ctrl_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[2048];
/* 0x800 : ef_if_ctrl_0 */
union {
struct {
uint32_t ef_if_0_autoload_p1_done : 1; /* [ 0], r, 0x1 */
uint32_t ef_if_0_autoload_done : 1; /* [ 1], r, 0x1 */
uint32_t ef_if_0_busy : 1; /* [ 2], r, 0x0 */
uint32_t ef_if_0_rw : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_if_0_trig : 1; /* [ 4], r/w, 0x0 */
uint32_t ef_if_0_manual_en : 1; /* [ 5], r/w, 0x0 */
uint32_t ef_if_0_cyc_modify : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_clk_sahb_data_sel : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_if_prot_code_ctrl : 8; /* [15: 8], r/w, 0x0 */
uint32_t ef_if_por_dig : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_clk_sahb_data_gate : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_if_auto_rd_en : 1; /* [ 18], r/w, 0x1 */
uint32_t ef_if_cyc_modify_lock : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_if_0_int : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_0_int_clr : 1; /* [ 21], r/w, 0x1 */
uint32_t ef_if_0_int_set : 1; /* [ 22], r/w, 0x0 */
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
uint32_t ef_if_prot_code_cyc : 8; /* [31:24], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_if_ctrl_0;
/* 0x804 : ef_if_cyc_0 */
union {
struct {
uint32_t ef_if_cyc_rd_dmy : 6; /* [ 5: 0], r/w, 0x0 */
uint32_t ef_if_cyc_rd_dat : 6; /* [11: 6], r/w, 0x1 */
uint32_t ef_if_cyc_rd_adr : 6; /* [17:12], r/w, 0x0 */
uint32_t ef_if_cyc_cs : 6; /* [23:18], r/w, 0x0 */
uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24], r/w, 0x16 */
}BF;
uint32_t WORD;
} ef_if_cyc_0;
/* 0x808 : ef_if_cyc_1 */
union {
struct {
uint32_t ef_if_cyc_pi : 6; /* [ 5: 0], r/w, 0x9 */
uint32_t ef_if_cyc_pp : 8; /* [13: 6], r/w, 0x98 */
uint32_t ef_if_cyc_wr_adr : 6; /* [19:14], r/w, 0x1 */
uint32_t ef_if_cyc_ps_cs : 6; /* [25:20], r/w, 0x2 */
uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_if_cyc_1;
/* 0x80C : ef_if_0_manual */
union {
struct {
uint32_t ef_if_a : 10; /* [ 9: 0], r/w, 0x0 */
uint32_t ef_if_pd : 1; /* [ 10], r/w, 0x1 */
uint32_t ef_if_ps : 1; /* [ 11], r/w, 0x0 */
uint32_t ef_if_strobe : 1; /* [ 12], r/w, 0x0 */
uint32_t ef_if_pgenb : 1; /* [ 13], r/w, 0x1 */
uint32_t ef_if_load : 1; /* [ 14], r/w, 0x1 */
uint32_t ef_if_csb : 1; /* [ 15], r/w, 0x1 */
uint32_t ef_if_0_q : 8; /* [23:16], r, 0x0 */
uint32_t ef_if_prot_code_manual : 8; /* [31:24], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_if_0_manual;
/* 0x810 : ef_if_0_status */
union {
struct {
uint32_t ef_if_0_status : 32; /* [31: 0], r, 0xe400 */
}BF;
uint32_t WORD;
} ef_if_0_status;
/* 0x814 : ef_if_cfg_0 */
union {
struct {
uint32_t ef_if_sf_aes_mode : 2; /* [ 1: 0], r, 0x0 */
uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2], r, 0x0 */
uint32_t ef_if_sboot_en : 2; /* [ 5: 4], r, 0x0 */
uint32_t ef_if_cpu1_enc_en : 1; /* [ 6], r, 0x0 */
uint32_t ef_if_cpu0_enc_en : 1; /* [ 7], r, 0x0 */
uint32_t ef_if_boot_sel : 4; /* [11: 8], r, 0x0 */
uint32_t ef_if_sw_usage_1 : 2; /* [13:12], r, 0x0 */
uint32_t ef_if_sdu_dis : 1; /* [ 14], r, 0x0 */
uint32_t ef_if_ble_dis : 1; /* [ 15], r, 0x0 */
uint32_t ef_if_wifi_dis : 1; /* [ 16], r, 0x0 */
uint32_t ef_if_0_key_enc_en : 1; /* [ 17], r, 0x0 */
uint32_t ef_if_cam_dis : 1; /* [ 18], r, 0x0 */
uint32_t ef_if_sf_dis : 1; /* [ 19], r, 0x0 */
uint32_t ef_if_cpu1_dis : 1; /* [ 20], r, 0x0 */
uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [ 21], r, 0x0 */
uint32_t ef_if_se_dbg_dis : 1; /* [ 22], r, 0x0 */
uint32_t ef_if_efuse_dbg_dis : 1; /* [ 23], r, 0x0 */
uint32_t ef_if_dbg_jtag_1_dis : 2; /* [25:24], r, 0x0 */
uint32_t ef_if_dbg_jtag_0_dis : 2; /* [27:26], r, 0x0 */
uint32_t ef_if_dbg_mode : 4; /* [31:28], r, 0x0 */
}BF;
uint32_t WORD;
} ef_if_cfg_0;
/* 0x818 : ef_sw_cfg_0 */
union {
struct {
uint32_t ef_sw_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t ef_sw_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t ef_sw_cpu1_enc_en : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_sw_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */
uint32_t ef_sw_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */
uint32_t ef_sw_sdu_dis : 1; /* [ 14], r/w, 0x0 */
uint32_t ef_sw_ble_dis : 1; /* [ 15], r/w, 0x0 */
uint32_t ef_sw_wifi_dis : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_sw_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t ef_sw_cam_dis : 1; /* [ 18], r/w, 0x0 */
uint32_t ef_sw_sf_dis : 1; /* [ 19], r/w, 0x0 */
uint32_t ef_sw_cpu1_dis : 1; /* [ 20], r/w, 0x0 */
uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
uint32_t ef_sw_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
uint32_t ef_sw_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
uint32_t ef_sw_dbg_jtag_1_dis : 2; /* [25:24], r/w, 0x0 */
uint32_t ef_sw_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_sw_dbg_mode : 4; /* [31:28], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_sw_cfg_0;
/* 0x81C : ef_reserved */
union {
struct {
uint32_t ef_reserved : 32; /* [31: 0], r/w, 0xffff */
}BF;
uint32_t WORD;
} ef_reserved;
/* 0x820 : ef_if_ana_trim_0 */
union {
struct {
uint32_t ef_if_ana_trim_0 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} ef_if_ana_trim_0;
/* 0x824 : ef_if_sw_usage_0 */
union {
struct {
uint32_t ef_if_sw_usage_0 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} ef_if_sw_usage_0;
/* 0x828 reserved */
uint8_t RESERVED0x828[472];
/* 0xA00 : ef_crc_ctrl_0 */
union {
struct {
uint32_t ef_crc_busy : 1; /* [ 0], r, 0x0 */
uint32_t ef_crc_trig : 1; /* [ 1], r/w, 0x0 */
uint32_t ef_crc_en : 1; /* [ 2], r/w, 0x1 */
uint32_t ef_crc_mode : 1; /* [ 3], r/w, 0x0 */
uint32_t ef_crc_error : 1; /* [ 4], r, 0x0 */
uint32_t ef_crc_dout_inv_en : 1; /* [ 5], r/w, 0x1 */
uint32_t ef_crc_dout_endian : 1; /* [ 6], r/w, 0x0 */
uint32_t ef_crc_din_endian : 1; /* [ 7], r/w, 0x0 */
uint32_t ef_crc_int : 1; /* [ 8], r, 0x0 */
uint32_t ef_crc_int_clr : 1; /* [ 9], r/w, 0x1 */
uint32_t ef_crc_int_set : 1; /* [ 10], r/w, 0x0 */
uint32_t ef_crc_lock : 1; /* [ 11], r/w, 0x0 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t ef_crc_slp_n : 16; /* [31:16], r/w, 0xff */
}BF;
uint32_t WORD;
} ef_crc_ctrl_0;
/* 0xA04 : ef_crc_ctrl_1 */
union {
struct {
uint32_t ef_crc_data_0_en : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} ef_crc_ctrl_1;
/* 0xA08 : ef_crc_ctrl_2 */
union {
struct {
uint32_t ef_crc_data_1_en : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} ef_crc_ctrl_2;
/* 0xA0C : ef_crc_ctrl_3 */
union {
struct {
uint32_t ef_crc_iv : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} ef_crc_ctrl_3;
/* 0xA10 : ef_crc_ctrl_4 */
union {
struct {
uint32_t ef_crc_golden : 32; /* [31: 0], r/w, 0xc2a8fa9dL */
}BF;
uint32_t WORD;
} ef_crc_ctrl_4;
/* 0xA14 : ef_crc_ctrl_5 */
union {
struct {
uint32_t ef_crc_dout : 32; /* [31: 0], r, 0xffffffffL */
}BF;
uint32_t WORD;
} ef_crc_ctrl_5;
};
typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;
#endif /* __EF_CTRL_REG_H__ */

768
drivers/bl602_driver/regs/ef_data_0_reg.h Normal file
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@ -0,0 +1,768 @@
/**
******************************************************************************
* @file ef_data_0_reg.h
* @version V1.2
* @date 2019-11-22
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_0_REG_H__
#define __EF_DATA_0_REG_H__
#include "bl602.h"
/* 0x0 : ef_cfg_0 */
#define EF_DATA_0_EF_CFG_0_OFFSET (0x0)
#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE
#define EF_DATA_0_EF_SF_AES_MODE_POS (0U)
#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U)
#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U<<EF_DATA_0_EF_SF_AES_MODE_LEN)-1)<<EF_DATA_0_EF_SF_AES_MODE_POS)
#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U<<EF_DATA_0_EF_SF_AES_MODE_LEN)-1)<<EF_DATA_0_EF_SF_AES_MODE_POS))
#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U<<EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN)-1)<<EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U<<EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN)-1)<<EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN
#define EF_DATA_0_EF_SBOOT_EN_POS (4U)
#define EF_DATA_0_EF_SBOOT_EN_LEN (2U)
#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U<<EF_DATA_0_EF_SBOOT_EN_LEN)-1)<<EF_DATA_0_EF_SBOOT_EN_POS)
#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U<<EF_DATA_0_EF_SBOOT_EN_LEN)-1)<<EF_DATA_0_EF_SBOOT_EN_POS))
#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN
#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U)
#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U<<EF_DATA_0_EF_CPU0_ENC_EN_LEN)-1)<<EF_DATA_0_EF_CPU0_ENC_EN_POS)
#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U<<EF_DATA_0_EF_CPU0_ENC_EN_LEN)-1)<<EF_DATA_0_EF_CPU0_ENC_EN_POS))
#define EF_DATA_0_EF_TRIM_EN EF_DATA_0_EF_TRIM_EN
#define EF_DATA_0_EF_TRIM_EN_POS (12U)
#define EF_DATA_0_EF_TRIM_EN_LEN (1U)
#define EF_DATA_0_EF_TRIM_EN_MSK (((1U<<EF_DATA_0_EF_TRIM_EN_LEN)-1)<<EF_DATA_0_EF_TRIM_EN_POS)
#define EF_DATA_0_EF_TRIM_EN_UMSK (~(((1U<<EF_DATA_0_EF_TRIM_EN_LEN)-1)<<EF_DATA_0_EF_TRIM_EN_POS))
#define EF_DATA_0_EF_NO_HD_BOOT_EN EF_DATA_0_EF_NO_HD_BOOT_EN
#define EF_DATA_0_EF_NO_HD_BOOT_EN_POS (13U)
#define EF_DATA_0_EF_NO_HD_BOOT_EN_LEN (1U)
#define EF_DATA_0_EF_NO_HD_BOOT_EN_MSK (((1U<<EF_DATA_0_EF_NO_HD_BOOT_EN_LEN)-1)<<EF_DATA_0_EF_NO_HD_BOOT_EN_POS)
#define EF_DATA_0_EF_NO_HD_BOOT_EN_UMSK (~(((1U<<EF_DATA_0_EF_NO_HD_BOOT_EN_LEN)-1)<<EF_DATA_0_EF_NO_HD_BOOT_EN_POS))
#define EF_DATA_0_EF_SDU_DIS EF_DATA_0_EF_SDU_DIS
#define EF_DATA_0_EF_SDU_DIS_POS (14U)
#define EF_DATA_0_EF_SDU_DIS_LEN (1U)
#define EF_DATA_0_EF_SDU_DIS_MSK (((1U<<EF_DATA_0_EF_SDU_DIS_LEN)-1)<<EF_DATA_0_EF_SDU_DIS_POS)
#define EF_DATA_0_EF_SDU_DIS_UMSK (~(((1U<<EF_DATA_0_EF_SDU_DIS_LEN)-1)<<EF_DATA_0_EF_SDU_DIS_POS))
#define EF_DATA_0_EF_BLE_DIS EF_DATA_0_EF_BLE_DIS
#define EF_DATA_0_EF_BLE_DIS_POS (15U)
#define EF_DATA_0_EF_BLE_DIS_LEN (1U)
#define EF_DATA_0_EF_BLE_DIS_MSK (((1U<<EF_DATA_0_EF_BLE_DIS_LEN)-1)<<EF_DATA_0_EF_BLE_DIS_POS)
#define EF_DATA_0_EF_BLE_DIS_UMSK (~(((1U<<EF_DATA_0_EF_BLE_DIS_LEN)-1)<<EF_DATA_0_EF_BLE_DIS_POS))
#define EF_DATA_0_EF_WIFI_DIS EF_DATA_0_EF_WIFI_DIS
#define EF_DATA_0_EF_WIFI_DIS_POS (16U)
#define EF_DATA_0_EF_WIFI_DIS_LEN (1U)
#define EF_DATA_0_EF_WIFI_DIS_MSK (((1U<<EF_DATA_0_EF_WIFI_DIS_LEN)-1)<<EF_DATA_0_EF_WIFI_DIS_POS)
#define EF_DATA_0_EF_WIFI_DIS_UMSK (~(((1U<<EF_DATA_0_EF_WIFI_DIS_LEN)-1)<<EF_DATA_0_EF_WIFI_DIS_POS))
#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN
#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U<<EF_DATA_0_EF_0_KEY_ENC_EN_LEN)-1)<<EF_DATA_0_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U<<EF_DATA_0_EF_0_KEY_ENC_EN_LEN)-1)<<EF_DATA_0_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_0_EF_SF_DIS EF_DATA_0_EF_SF_DIS
#define EF_DATA_0_EF_SF_DIS_POS (19U)
#define EF_DATA_0_EF_SF_DIS_LEN (1U)
#define EF_DATA_0_EF_SF_DIS_MSK (((1U<<EF_DATA_0_EF_SF_DIS_LEN)-1)<<EF_DATA_0_EF_SF_DIS_POS)
#define EF_DATA_0_EF_SF_DIS_UMSK (~(((1U<<EF_DATA_0_EF_SF_DIS_LEN)-1)<<EF_DATA_0_EF_SF_DIS_POS))
#define EF_DATA_0_EF_CPU_RST_DBG_DIS EF_DATA_0_EF_CPU_RST_DBG_DIS
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_POS (21U)
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN (1U)
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_MSK (((1U<<EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN)-1)<<EF_DATA_0_EF_CPU_RST_DBG_DIS_POS)
#define EF_DATA_0_EF_CPU_RST_DBG_DIS_UMSK (~(((1U<<EF_DATA_0_EF_CPU_RST_DBG_DIS_LEN)-1)<<EF_DATA_0_EF_CPU_RST_DBG_DIS_POS))
#define EF_DATA_0_EF_SE_DBG_DIS EF_DATA_0_EF_SE_DBG_DIS
#define EF_DATA_0_EF_SE_DBG_DIS_POS (22U)
#define EF_DATA_0_EF_SE_DBG_DIS_LEN (1U)
#define EF_DATA_0_EF_SE_DBG_DIS_MSK (((1U<<EF_DATA_0_EF_SE_DBG_DIS_LEN)-1)<<EF_DATA_0_EF_SE_DBG_DIS_POS)
#define EF_DATA_0_EF_SE_DBG_DIS_UMSK (~(((1U<<EF_DATA_0_EF_SE_DBG_DIS_LEN)-1)<<EF_DATA_0_EF_SE_DBG_DIS_POS))
#define EF_DATA_0_EF_EFUSE_DBG_DIS EF_DATA_0_EF_EFUSE_DBG_DIS
#define EF_DATA_0_EF_EFUSE_DBG_DIS_POS (23U)
#define EF_DATA_0_EF_EFUSE_DBG_DIS_LEN (1U)
#define EF_DATA_0_EF_EFUSE_DBG_DIS_MSK (((1U<<EF_DATA_0_EF_EFUSE_DBG_DIS_LEN)-1)<<EF_DATA_0_EF_EFUSE_DBG_DIS_POS)
#define EF_DATA_0_EF_EFUSE_DBG_DIS_UMSK (~(((1U<<EF_DATA_0_EF_EFUSE_DBG_DIS_LEN)-1)<<EF_DATA_0_EF_EFUSE_DBG_DIS_POS))
#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U<<EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN)-1)<<EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U<<EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN)-1)<<EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE
#define EF_DATA_0_EF_DBG_MODE_POS (28U)
#define EF_DATA_0_EF_DBG_MODE_LEN (4U)
#define EF_DATA_0_EF_DBG_MODE_MSK (((1U<<EF_DATA_0_EF_DBG_MODE_LEN)-1)<<EF_DATA_0_EF_DBG_MODE_POS)
#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U<<EF_DATA_0_EF_DBG_MODE_LEN)-1)<<EF_DATA_0_EF_DBG_MODE_POS))
/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW
#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U<<EF_DATA_0_EF_DBG_PWD_LOW_LEN)-1)<<EF_DATA_0_EF_DBG_PWD_LOW_POS)
#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U<<EF_DATA_0_EF_DBG_PWD_LOW_LEN)-1)<<EF_DATA_0_EF_DBG_PWD_LOW_POS))
/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH
#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U<<EF_DATA_0_EF_DBG_PWD_HIGH_LEN)-1)<<EF_DATA_0_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U<<EF_DATA_0_EF_DBG_PWD_HIGH_LEN)-1)<<EF_DATA_0_EF_DBG_PWD_HIGH_POS))
/* 0xC : ef_ana_trim_0 */
#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC)
#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0
#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U)
#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U)
#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U<<EF_DATA_0_EF_ANA_TRIM_0_LEN)-1)<<EF_DATA_0_EF_ANA_TRIM_0_POS)
#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U<<EF_DATA_0_EF_ANA_TRIM_0_LEN)-1)<<EF_DATA_0_EF_ANA_TRIM_0_POS))
/* 0x10 : ef_sw_usage_0 */
#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10)
#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0
#define EF_DATA_0_EF_SW_USAGE_0_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U<<EF_DATA_0_EF_SW_USAGE_0_LEN)-1)<<EF_DATA_0_EF_SW_USAGE_0_POS)
#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U<<EF_DATA_0_EF_SW_USAGE_0_LEN)-1)<<EF_DATA_0_EF_SW_USAGE_0_POS))
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW
#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U<<EF_DATA_0_EF_WIFI_MAC_LOW_LEN)-1)<<EF_DATA_0_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U<<EF_DATA_0_EF_WIFI_MAC_LOW_LEN)-1)<<EF_DATA_0_EF_WIFI_MAC_LOW_POS))
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH
#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U<<EF_DATA_0_EF_WIFI_MAC_HIGH_LEN)-1)<<EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U<<EF_DATA_0_EF_WIFI_MAC_HIGH_LEN)-1)<<EF_DATA_0_EF_WIFI_MAC_HIGH_POS))
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0
#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_0_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_0_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W0_POS))
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1
#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_0_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_0_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W1_POS))
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2
#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_0_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_0_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W2_POS))
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3
#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_0_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_0_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_0_W3_POS))
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0
#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_1_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_1_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W0_POS))
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1
#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_1_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_1_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W1_POS))
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2
#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_1_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_1_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W2_POS))
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3
#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_1_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_1_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_1_W3_POS))
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0
#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_2_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_2_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W0_POS))
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1
#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_2_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_2_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W1_POS))
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2
#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_2_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_2_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W2_POS))
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3
#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_2_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_2_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_2_W3_POS))
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0
#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_3_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_3_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W0_POS))
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1
#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_3_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_3_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W1_POS))
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2
#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_3_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_3_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W2_POS))
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3
#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_3_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_3_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_3_W3_POS))
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0
#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_4_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_4_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W0_POS))
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60)
#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1
#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_4_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_4_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W1_POS))
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64)
#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2
#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_4_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_4_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W2_POS))
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68)
#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3
#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_4_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_4_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_4_W3_POS))
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0
#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_5_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_5_W0_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W0_POS))
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70)
#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1
#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_5_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_5_W1_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W1_POS))
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74)
#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2
#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_5_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_5_W2_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W2_POS))
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78)
#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3
#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U<<EF_DATA_0_EF_KEY_SLOT_5_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U<<EF_DATA_0_EF_KEY_SLOT_5_W3_LEN)-1)<<EF_DATA_0_EF_KEY_SLOT_5_W3_POS))
/* 0x7C : ef_data_0_lock */
#define EF_DATA_0_LOCK_OFFSET (0x7C)
#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1
#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U)
#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U)
#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U<<EF_DATA_0_EF_ANA_TRIM_1_LEN)-1)<<EF_DATA_0_EF_ANA_TRIM_1_POS)
#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U<<EF_DATA_0_EF_ANA_TRIM_1_LEN)-1)<<EF_DATA_0_EF_ANA_TRIM_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS))
#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE
#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U<<EF_DATA_0_WR_LOCK_BOOT_MODE_LEN)-1)<<EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_BOOT_MODE_LEN)-1)<<EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD
#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U<<EF_DATA_0_WR_LOCK_DBG_PWD_LEN)-1)<<EF_DATA_0_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_DBG_PWD_LEN)-1)<<EF_DATA_0_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U<<EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN)-1)<<EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN)-1)<<EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC
#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U<<EF_DATA_0_WR_LOCK_WIFI_MAC_LEN)-1)<<EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_WIFI_MAC_LEN)-1)<<EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN)-1)<<EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS))
#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD
#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U<<EF_DATA_0_RD_LOCK_DBG_PWD_LEN)-1)<<EF_DATA_0_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_DBG_PWD_LEN)-1)<<EF_DATA_0_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U<<EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN)-1)<<EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS))
struct ef_data_0_reg {
/* 0x0 : ef_cfg_0 */
union {
struct {
uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */
uint32_t ef_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */
uint32_t ef_sdu_dis : 1; /* [ 14], r/w, 0x0 */
uint32_t ef_ble_dis : 1; /* [ 15], r/w, 0x0 */
uint32_t ef_wifi_dis : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t ef_sf_dis : 1; /* [ 19], r/w, 0x0 */
uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
uint32_t ef_cpu_rst_dbg_dis : 1; /* [ 21], r/w, 0x0 */
uint32_t ef_se_dbg_dis : 1; /* [ 22], r/w, 0x0 */
uint32_t ef_efuse_dbg_dis : 1; /* [ 23], r/w, 0x0 */
uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */
uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_cfg_0;
/* 0x4 : ef_dbg_pwd_low */
union {
struct {
uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_dbg_pwd_low;
/* 0x8 : ef_dbg_pwd_high */
union {
struct {
uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_dbg_pwd_high;
/* 0xC : ef_ana_trim_0 */
union {
struct {
uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_ana_trim_0;
/* 0x10 : ef_sw_usage_0 */
union {
struct {
uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_sw_usage_0;
/* 0x14 : ef_wifi_mac_low */
union {
struct {
uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_wifi_mac_low;
/* 0x18 : ef_wifi_mac_high */
union {
struct {
uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_wifi_mac_high;
/* 0x1C : ef_key_slot_0_w0 */
union {
struct {
uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_0_w0;
/* 0x20 : ef_key_slot_0_w1 */
union {
struct {
uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_0_w1;
/* 0x24 : ef_key_slot_0_w2 */
union {
struct {
uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_0_w2;
/* 0x28 : ef_key_slot_0_w3 */
union {
struct {
uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_0_w3;
/* 0x2C : ef_key_slot_1_w0 */
union {
struct {
uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_1_w0;
/* 0x30 : ef_key_slot_1_w1 */
union {
struct {
uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_1_w1;
/* 0x34 : ef_key_slot_1_w2 */
union {
struct {
uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_1_w2;
/* 0x38 : ef_key_slot_1_w3 */
union {
struct {
uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_1_w3;
/* 0x3C : ef_key_slot_2_w0 */
union {
struct {
uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_2_w0;
/* 0x40 : ef_key_slot_2_w1 */
union {
struct {
uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_2_w1;
/* 0x44 : ef_key_slot_2_w2 */
union {
struct {
uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_2_w2;
/* 0x48 : ef_key_slot_2_w3 */
union {
struct {
uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_2_w3;
/* 0x4C : ef_key_slot_3_w0 */
union {
struct {
uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_3_w0;
/* 0x50 : ef_key_slot_3_w1 */
union {
struct {
uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_3_w1;
/* 0x54 : ef_key_slot_3_w2 */
union {
struct {
uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_3_w2;
/* 0x58 : ef_key_slot_3_w3 */
union {
struct {
uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_3_w3;
/* 0x5C : ef_key_slot_4_w0 */
union {
struct {
uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_4_w0;
/* 0x60 : ef_key_slot_4_w1 */
union {
struct {
uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_4_w1;
/* 0x64 : ef_key_slot_4_w2 */
union {
struct {
uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_4_w2;
/* 0x68 : ef_key_slot_4_w3 */
union {
struct {
uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_4_w3;
/* 0x6C : ef_key_slot_5_w0 */
union {
struct {
uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_5_w0;
/* 0x70 : ef_key_slot_5_w1 */
union {
struct {
uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_5_w1;
/* 0x74 : ef_key_slot_5_w2 */
union {
struct {
uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_5_w2;
/* 0x78 : ef_key_slot_5_w3 */
union {
struct {
uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_key_slot_5_w3;
/* 0x7C : ef_data_0_lock */
union {
struct {
uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */
uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */
uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */
}BF;
uint32_t WORD;
} ef_data_0_lock;
};
typedef volatile struct ef_data_0_reg ef_data_0_reg_t;
#endif /* __EF_DATA_0_REG_H__ */

457
drivers/bl602_driver/regs/ef_data_1_reg.h Normal file
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@ -0,0 +1,457 @@
/**
******************************************************************************
* @file ef_data_1_reg.h
* @version V1.2
* @date 2019-11-22
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_1_REG_H__
#define __EF_DATA_1_REG_H__
#include "bl602.h"
/* 0x80 : reg_key_slot_6_w0 */
#define EF_DATA_1_REG_KEY_SLOT_6_W0_OFFSET (0x80)
#define EF_DATA_1_REG_KEY_SLOT_6_W0 EF_DATA_1_REG_KEY_SLOT_6_W0
#define EF_DATA_1_REG_KEY_SLOT_6_W0_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_6_W0_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_6_W0_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_6_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W0_POS)
#define EF_DATA_1_REG_KEY_SLOT_6_W0_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_6_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W0_POS))
/* 0x84 : reg_key_slot_6_w1 */
#define EF_DATA_1_REG_KEY_SLOT_6_W1_OFFSET (0x84)
#define EF_DATA_1_REG_KEY_SLOT_6_W1 EF_DATA_1_REG_KEY_SLOT_6_W1
#define EF_DATA_1_REG_KEY_SLOT_6_W1_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_6_W1_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_6_W1_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_6_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W1_POS)
#define EF_DATA_1_REG_KEY_SLOT_6_W1_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_6_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W1_POS))
/* 0x88 : reg_key_slot_6_w2 */
#define EF_DATA_1_REG_KEY_SLOT_6_W2_OFFSET (0x88)
#define EF_DATA_1_REG_KEY_SLOT_6_W2 EF_DATA_1_REG_KEY_SLOT_6_W2
#define EF_DATA_1_REG_KEY_SLOT_6_W2_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_6_W2_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_6_W2_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_6_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W2_POS)
#define EF_DATA_1_REG_KEY_SLOT_6_W2_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_6_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W2_POS))
/* 0x8C : reg_key_slot_6_w3 */
#define EF_DATA_1_REG_KEY_SLOT_6_W3_OFFSET (0x8C)
#define EF_DATA_1_REG_KEY_SLOT_6_W3 EF_DATA_1_REG_KEY_SLOT_6_W3
#define EF_DATA_1_REG_KEY_SLOT_6_W3_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_6_W3_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_6_W3_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_6_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W3_POS)
#define EF_DATA_1_REG_KEY_SLOT_6_W3_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_6_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_6_W3_POS))
/* 0x90 : reg_key_slot_7_w0 */
#define EF_DATA_1_REG_KEY_SLOT_7_W0_OFFSET (0x90)
#define EF_DATA_1_REG_KEY_SLOT_7_W0 EF_DATA_1_REG_KEY_SLOT_7_W0
#define EF_DATA_1_REG_KEY_SLOT_7_W0_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_7_W0_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_7_W0_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_7_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W0_POS)
#define EF_DATA_1_REG_KEY_SLOT_7_W0_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_7_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W0_POS))
/* 0x94 : reg_key_slot_7_w1 */
#define EF_DATA_1_REG_KEY_SLOT_7_W1_OFFSET (0x94)
#define EF_DATA_1_REG_KEY_SLOT_7_W1 EF_DATA_1_REG_KEY_SLOT_7_W1
#define EF_DATA_1_REG_KEY_SLOT_7_W1_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_7_W1_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_7_W1_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_7_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W1_POS)
#define EF_DATA_1_REG_KEY_SLOT_7_W1_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_7_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W1_POS))
/* 0x98 : reg_key_slot_7_w2 */
#define EF_DATA_1_REG_KEY_SLOT_7_W2_OFFSET (0x98)
#define EF_DATA_1_REG_KEY_SLOT_7_W2 EF_DATA_1_REG_KEY_SLOT_7_W2
#define EF_DATA_1_REG_KEY_SLOT_7_W2_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_7_W2_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_7_W2_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_7_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W2_POS)
#define EF_DATA_1_REG_KEY_SLOT_7_W2_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_7_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W2_POS))
/* 0x9C : reg_key_slot_7_w3 */
#define EF_DATA_1_REG_KEY_SLOT_7_W3_OFFSET (0x9C)
#define EF_DATA_1_REG_KEY_SLOT_7_W3 EF_DATA_1_REG_KEY_SLOT_7_W3
#define EF_DATA_1_REG_KEY_SLOT_7_W3_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_7_W3_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_7_W3_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_7_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W3_POS)
#define EF_DATA_1_REG_KEY_SLOT_7_W3_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_7_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_7_W3_POS))
/* 0xA0 : reg_key_slot_8_w0 */
#define EF_DATA_1_REG_KEY_SLOT_8_W0_OFFSET (0xA0)
#define EF_DATA_1_REG_KEY_SLOT_8_W0 EF_DATA_1_REG_KEY_SLOT_8_W0
#define EF_DATA_1_REG_KEY_SLOT_8_W0_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_8_W0_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_8_W0_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_8_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W0_POS)
#define EF_DATA_1_REG_KEY_SLOT_8_W0_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_8_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W0_POS))
/* 0xA4 : reg_key_slot_8_w1 */
#define EF_DATA_1_REG_KEY_SLOT_8_W1_OFFSET (0xA4)
#define EF_DATA_1_REG_KEY_SLOT_8_W1 EF_DATA_1_REG_KEY_SLOT_8_W1
#define EF_DATA_1_REG_KEY_SLOT_8_W1_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_8_W1_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_8_W1_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_8_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W1_POS)
#define EF_DATA_1_REG_KEY_SLOT_8_W1_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_8_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W1_POS))
/* 0xA8 : reg_key_slot_8_w2 */
#define EF_DATA_1_REG_KEY_SLOT_8_W2_OFFSET (0xA8)
#define EF_DATA_1_REG_KEY_SLOT_8_W2 EF_DATA_1_REG_KEY_SLOT_8_W2
#define EF_DATA_1_REG_KEY_SLOT_8_W2_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_8_W2_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_8_W2_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_8_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W2_POS)
#define EF_DATA_1_REG_KEY_SLOT_8_W2_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_8_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W2_POS))
/* 0xAC : reg_key_slot_8_w3 */
#define EF_DATA_1_REG_KEY_SLOT_8_W3_OFFSET (0xAC)
#define EF_DATA_1_REG_KEY_SLOT_8_W3 EF_DATA_1_REG_KEY_SLOT_8_W3
#define EF_DATA_1_REG_KEY_SLOT_8_W3_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_8_W3_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_8_W3_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_8_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W3_POS)
#define EF_DATA_1_REG_KEY_SLOT_8_W3_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_8_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_8_W3_POS))
/* 0xB0 : reg_key_slot_9_w0 */
#define EF_DATA_1_REG_KEY_SLOT_9_W0_OFFSET (0xB0)
#define EF_DATA_1_REG_KEY_SLOT_9_W0 EF_DATA_1_REG_KEY_SLOT_9_W0
#define EF_DATA_1_REG_KEY_SLOT_9_W0_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_9_W0_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_9_W0_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_9_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W0_POS)
#define EF_DATA_1_REG_KEY_SLOT_9_W0_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_9_W0_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W0_POS))
/* 0xB4 : reg_key_slot_9_w1 */
#define EF_DATA_1_REG_KEY_SLOT_9_W1_OFFSET (0xB4)
#define EF_DATA_1_REG_KEY_SLOT_9_W1 EF_DATA_1_REG_KEY_SLOT_9_W1
#define EF_DATA_1_REG_KEY_SLOT_9_W1_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_9_W1_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_9_W1_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_9_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W1_POS)
#define EF_DATA_1_REG_KEY_SLOT_9_W1_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_9_W1_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W1_POS))
/* 0xB8 : reg_key_slot_9_w2 */
#define EF_DATA_1_REG_KEY_SLOT_9_W2_OFFSET (0xB8)
#define EF_DATA_1_REG_KEY_SLOT_9_W2 EF_DATA_1_REG_KEY_SLOT_9_W2
#define EF_DATA_1_REG_KEY_SLOT_9_W2_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_9_W2_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_9_W2_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_9_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W2_POS)
#define EF_DATA_1_REG_KEY_SLOT_9_W2_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_9_W2_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W2_POS))
/* 0xBC : reg_key_slot_9_w3 */
#define EF_DATA_1_REG_KEY_SLOT_9_W3_OFFSET (0xBC)
#define EF_DATA_1_REG_KEY_SLOT_9_W3 EF_DATA_1_REG_KEY_SLOT_9_W3
#define EF_DATA_1_REG_KEY_SLOT_9_W3_POS (0U)
#define EF_DATA_1_REG_KEY_SLOT_9_W3_LEN (32U)
#define EF_DATA_1_REG_KEY_SLOT_9_W3_MSK (((1U<<EF_DATA_1_REG_KEY_SLOT_9_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W3_POS)
#define EF_DATA_1_REG_KEY_SLOT_9_W3_UMSK (~(((1U<<EF_DATA_1_REG_KEY_SLOT_9_W3_LEN)-1)<<EF_DATA_1_REG_KEY_SLOT_9_W3_POS))
/* 0xC0 : reg_key_slot_10_w0 */
#define EF_DATA_1_REG_KEY_SLOT_10_W0_OFFSET (0xC0)
/* 0xC4 : reg_key_slot_10_w1 */
#define EF_DATA_1_REG_KEY_SLOT_10_W1_OFFSET (0xC4)
/* 0xC8 : reg_key_slot_10_w2 */
#define EF_DATA_1_REG_KEY_SLOT_10_W2_OFFSET (0xC8)
/* 0xCC : reg_key_slot_10_w3 */
#define EF_DATA_1_REG_KEY_SLOT_10_W3_OFFSET (0xCC)
/* 0xD0 : reg_key_slot_11_w0 */
#define EF_DATA_1_REG_KEY_SLOT_11_W0_OFFSET (0xD0)
/* 0xD4 : reg_key_slot_11_w1 */
#define EF_DATA_1_REG_KEY_SLOT_11_W1_OFFSET (0xD4)
/* 0xD8 : reg_key_slot_11_w2 */
#define EF_DATA_1_REG_KEY_SLOT_11_W2_OFFSET (0xD8)
/* 0xDC : reg_key_slot_11_w3 */
#define EF_DATA_1_REG_KEY_SLOT_11_W3_OFFSET (0xDC)
/* 0xE0 : reg_data_1_lock */
#define EF_DATA_1_REG_DATA_1_LOCK_OFFSET (0xE0)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6 EF_DATA_1_WR_LOCK_KEY_SLOT_6
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS (10U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_MSK (((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_6_UMSK (~(((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_6_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_6_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7 EF_DATA_1_WR_LOCK_KEY_SLOT_7
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS (11U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_MSK (((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_7_UMSK (~(((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_7_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_7_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8 EF_DATA_1_WR_LOCK_KEY_SLOT_8
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS (12U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_MSK (((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_8_UMSK (~(((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_8_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_8_POS))
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9 EF_DATA_1_WR_LOCK_KEY_SLOT_9
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS (13U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN (1U)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_MSK (((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS)
#define EF_DATA_1_WR_LOCK_KEY_SLOT_9_UMSK (~(((1U<<EF_DATA_1_WR_LOCK_KEY_SLOT_9_LEN)-1)<<EF_DATA_1_WR_LOCK_KEY_SLOT_9_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6 EF_DATA_1_RD_LOCK_KEY_SLOT_6
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS (26U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_MSK (((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_6_UMSK (~(((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_6_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_6_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7 EF_DATA_1_RD_LOCK_KEY_SLOT_7
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS (27U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_MSK (((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_7_UMSK (~(((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_7_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_7_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8 EF_DATA_1_RD_LOCK_KEY_SLOT_8
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS (28U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_MSK (((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_8_UMSK (~(((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_8_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_8_POS))
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9 EF_DATA_1_RD_LOCK_KEY_SLOT_9
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS (29U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN (1U)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_MSK (((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS)
#define EF_DATA_1_RD_LOCK_KEY_SLOT_9_UMSK (~(((1U<<EF_DATA_1_RD_LOCK_KEY_SLOT_9_LEN)-1)<<EF_DATA_1_RD_LOCK_KEY_SLOT_9_POS))
struct ef_data_1_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[128];
/* 0x80 : reg_key_slot_6_w0 */
union {
struct {
uint32_t reg_key_slot_6_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_6_w0;
/* 0x84 : reg_key_slot_6_w1 */
union {
struct {
uint32_t reg_key_slot_6_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_6_w1;
/* 0x88 : reg_key_slot_6_w2 */
union {
struct {
uint32_t reg_key_slot_6_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_6_w2;
/* 0x8C : reg_key_slot_6_w3 */
union {
struct {
uint32_t reg_key_slot_6_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_6_w3;
/* 0x90 : reg_key_slot_7_w0 */
union {
struct {
uint32_t reg_key_slot_7_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_7_w0;
/* 0x94 : reg_key_slot_7_w1 */
union {
struct {
uint32_t reg_key_slot_7_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_7_w1;
/* 0x98 : reg_key_slot_7_w2 */
union {
struct {
uint32_t reg_key_slot_7_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_7_w2;
/* 0x9C : reg_key_slot_7_w3 */
union {
struct {
uint32_t reg_key_slot_7_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_7_w3;
/* 0xA0 : reg_key_slot_8_w0 */
union {
struct {
uint32_t reg_key_slot_8_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_8_w0;
/* 0xA4 : reg_key_slot_8_w1 */
union {
struct {
uint32_t reg_key_slot_8_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_8_w1;
/* 0xA8 : reg_key_slot_8_w2 */
union {
struct {
uint32_t reg_key_slot_8_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_8_w2;
/* 0xAC : reg_key_slot_8_w3 */
union {
struct {
uint32_t reg_key_slot_8_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_8_w3;
/* 0xB0 : reg_key_slot_9_w0 */
union {
struct {
uint32_t reg_key_slot_9_w0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_9_w0;
/* 0xB4 : reg_key_slot_9_w1 */
union {
struct {
uint32_t reg_key_slot_9_w1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_9_w1;
/* 0xB8 : reg_key_slot_9_w2 */
union {
struct {
uint32_t reg_key_slot_9_w2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_9_w2;
/* 0xBC : reg_key_slot_9_w3 */
union {
struct {
uint32_t reg_key_slot_9_w3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_9_w3;
/* 0xC0 : reg_key_slot_10_w0 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_10_w0;
/* 0xC4 : reg_key_slot_10_w1 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_10_w1;
/* 0xC8 : reg_key_slot_10_w2 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_10_w2;
/* 0xCC : reg_key_slot_10_w3 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_10_w3;
/* 0xD0 : reg_key_slot_11_w0 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_11_w0;
/* 0xD4 : reg_key_slot_11_w1 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_11_w1;
/* 0xD8 : reg_key_slot_11_w2 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_11_w2;
/* 0xDC : reg_key_slot_11_w3 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_key_slot_11_w3;
/* 0xE0 : reg_data_1_lock */
union {
struct {
uint32_t RESERVED_9_0 : 10; /* [ 9: 0], rsvd, 0x0 */
uint32_t wr_lock_key_slot_6 : 1; /* [ 10], r/w, 0x0 */
uint32_t wr_lock_key_slot_7 : 1; /* [ 11], r/w, 0x0 */
uint32_t wr_lock_key_slot_8 : 1; /* [ 12], r/w, 0x0 */
uint32_t wr_lock_key_slot_9 : 1; /* [ 13], r/w, 0x0 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t RESERVED_25_16 : 10; /* [25:16], rsvd, 0x0 */
uint32_t rd_lock_key_slot_6 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_7 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_8 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_9 : 1; /* [ 29], r/w, 0x0 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
}BF;
uint32_t WORD;
} reg_data_1_lock;
};
typedef volatile struct ef_data_1_reg ef_data_1_reg_t;
#endif /* __EF_DATA_1_REG_H__ */

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drivers/bl602_driver/regs/glb_reg.h Normal file
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drivers/bl602_driver/regs/gpip_reg.h Normal file
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/**
******************************************************************************
* @file gpip_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __GPIP_REG_H__
#define __GPIP_REG_H__
#include "bl602.h"
/* 0x0 : gpadc_config */
#define GPIP_GPADC_CONFIG_OFFSET (0x0)
#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN
#define GPIP_GPADC_DMA_EN_POS (0U)
#define GPIP_GPADC_DMA_EN_LEN (1U)
#define GPIP_GPADC_DMA_EN_MSK (((1U<<GPIP_GPADC_DMA_EN_LEN)-1)<<GPIP_GPADC_DMA_EN_POS)
#define GPIP_GPADC_DMA_EN_UMSK (~(((1U<<GPIP_GPADC_DMA_EN_LEN)-1)<<GPIP_GPADC_DMA_EN_POS))
#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR
#define GPIP_GPADC_FIFO_CLR_POS (1U)
#define GPIP_GPADC_FIFO_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_CLR_MSK (((1U<<GPIP_GPADC_FIFO_CLR_LEN)-1)<<GPIP_GPADC_FIFO_CLR_POS)
#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U<<GPIP_GPADC_FIFO_CLR_LEN)-1)<<GPIP_GPADC_FIFO_CLR_POS))
#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE
#define GPIP_GPADC_FIFO_NE_POS (2U)
#define GPIP_GPADC_FIFO_NE_LEN (1U)
#define GPIP_GPADC_FIFO_NE_MSK (((1U<<GPIP_GPADC_FIFO_NE_LEN)-1)<<GPIP_GPADC_FIFO_NE_POS)
#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U<<GPIP_GPADC_FIFO_NE_LEN)-1)<<GPIP_GPADC_FIFO_NE_POS))
#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL
#define GPIP_GPADC_FIFO_FULL_POS (3U)
#define GPIP_GPADC_FIFO_FULL_LEN (1U)
#define GPIP_GPADC_FIFO_FULL_MSK (((1U<<GPIP_GPADC_FIFO_FULL_LEN)-1)<<GPIP_GPADC_FIFO_FULL_POS)
#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U<<GPIP_GPADC_FIFO_FULL_LEN)-1)<<GPIP_GPADC_FIFO_FULL_POS))
#define GPIP_GPADC_RDY GPIP_GPADC_RDY
#define GPIP_GPADC_RDY_POS (4U)
#define GPIP_GPADC_RDY_LEN (1U)
#define GPIP_GPADC_RDY_MSK (((1U<<GPIP_GPADC_RDY_LEN)-1)<<GPIP_GPADC_RDY_POS)
#define GPIP_GPADC_RDY_UMSK (~(((1U<<GPIP_GPADC_RDY_LEN)-1)<<GPIP_GPADC_RDY_POS))
#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN
#define GPIP_GPADC_FIFO_OVERRUN_POS (5U)
#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U<<GPIP_GPADC_FIFO_OVERRUN_LEN)-1)<<GPIP_GPADC_FIFO_OVERRUN_POS)
#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U<<GPIP_GPADC_FIFO_OVERRUN_LEN)-1)<<GPIP_GPADC_FIFO_OVERRUN_POS))
#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN
#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U)
#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U<<GPIP_GPADC_FIFO_UNDERRUN_LEN)-1)<<GPIP_GPADC_FIFO_UNDERRUN_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U<<GPIP_GPADC_FIFO_UNDERRUN_LEN)-1)<<GPIP_GPADC_FIFO_UNDERRUN_POS))
#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR
#define GPIP_GPADC_RDY_CLR_POS (8U)
#define GPIP_GPADC_RDY_CLR_LEN (1U)
#define GPIP_GPADC_RDY_CLR_MSK (((1U<<GPIP_GPADC_RDY_CLR_LEN)-1)<<GPIP_GPADC_RDY_CLR_POS)
#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U<<GPIP_GPADC_RDY_CLR_LEN)-1)<<GPIP_GPADC_RDY_CLR_POS))
#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR
#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U<<GPIP_GPADC_FIFO_OVERRUN_CLR_LEN)-1)<<GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U<<GPIP_GPADC_FIFO_OVERRUN_CLR_LEN)-1)<<GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U<<GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN)-1)<<GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U<<GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN)-1)<<GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK
#define GPIP_GPADC_RDY_MASK_POS (12U)
#define GPIP_GPADC_RDY_MASK_LEN (1U)
#define GPIP_GPADC_RDY_MASK_MSK (((1U<<GPIP_GPADC_RDY_MASK_LEN)-1)<<GPIP_GPADC_RDY_MASK_POS)
#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U<<GPIP_GPADC_RDY_MASK_LEN)-1)<<GPIP_GPADC_RDY_MASK_POS))
#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK
#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U<<GPIP_GPADC_FIFO_OVERRUN_MASK_LEN)-1)<<GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U<<GPIP_GPADC_FIFO_OVERRUN_MASK_LEN)-1)<<GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U<<GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN)-1)<<GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U<<GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN)-1)<<GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT
#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U)
#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U)
#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U<<GPIP_GPADC_FIFO_DATA_COUNT_LEN)-1)<<GPIP_GPADC_FIFO_DATA_COUNT_POS)
#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U<<GPIP_GPADC_FIFO_DATA_COUNT_LEN)-1)<<GPIP_GPADC_FIFO_DATA_COUNT_POS))
#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL
#define GPIP_GPADC_FIFO_THL_POS (22U)
#define GPIP_GPADC_FIFO_THL_LEN (2U)
#define GPIP_GPADC_FIFO_THL_MSK (((1U<<GPIP_GPADC_FIFO_THL_LEN)-1)<<GPIP_GPADC_FIFO_THL_POS)
#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U<<GPIP_GPADC_FIFO_THL_LEN)-1)<<GPIP_GPADC_FIFO_THL_POS))
/* 0x4 : gpadc_dma_rdata */
#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA
#define GPIP_GPADC_DMA_RDATA_POS (0U)
#define GPIP_GPADC_DMA_RDATA_LEN (26U)
#define GPIP_GPADC_DMA_RDATA_MSK (((1U<<GPIP_GPADC_DMA_RDATA_LEN)-1)<<GPIP_GPADC_DMA_RDATA_POS)
#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U<<GPIP_GPADC_DMA_RDATA_LEN)-1)<<GPIP_GPADC_DMA_RDATA_POS))
/* 0x40 : gpdac_config */
#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
#define GPIP_GPDAC_EN GPIP_GPDAC_EN
#define GPIP_GPDAC_EN_POS (0U)
#define GPIP_GPDAC_EN_LEN (1U)
#define GPIP_GPDAC_EN_MSK (((1U<<GPIP_GPDAC_EN_LEN)-1)<<GPIP_GPDAC_EN_POS)
#define GPIP_GPDAC_EN_UMSK (~(((1U<<GPIP_GPDAC_EN_LEN)-1)<<GPIP_GPDAC_EN_POS))
#define GPIP_GPDAC_EN2 GPIP_GPDAC_EN2
#define GPIP_GPDAC_EN2_POS (1U)
#define GPIP_GPDAC_EN2_LEN (1U)
#define GPIP_GPDAC_EN2_MSK (((1U<<GPIP_GPDAC_EN2_LEN)-1)<<GPIP_GPDAC_EN2_POS)
#define GPIP_GPDAC_EN2_UMSK (~(((1U<<GPIP_GPDAC_EN2_LEN)-1)<<GPIP_GPDAC_EN2_POS))
#define GPIP_DSM_MODE GPIP_DSM_MODE
#define GPIP_DSM_MODE_POS (4U)
#define GPIP_DSM_MODE_LEN (2U)
#define GPIP_DSM_MODE_MSK (((1U<<GPIP_DSM_MODE_LEN)-1)<<GPIP_DSM_MODE_POS)
#define GPIP_DSM_MODE_UMSK (~(((1U<<GPIP_DSM_MODE_LEN)-1)<<GPIP_DSM_MODE_POS))
#define GPIP_GPDAC_MODE GPIP_GPDAC_MODE
#define GPIP_GPDAC_MODE_POS (8U)
#define GPIP_GPDAC_MODE_LEN (3U)
#define GPIP_GPDAC_MODE_MSK (((1U<<GPIP_GPDAC_MODE_LEN)-1)<<GPIP_GPDAC_MODE_POS)
#define GPIP_GPDAC_MODE_UMSK (~(((1U<<GPIP_GPDAC_MODE_LEN)-1)<<GPIP_GPDAC_MODE_POS))
#define GPIP_GPDAC_CH_A_SEL GPIP_GPDAC_CH_A_SEL
#define GPIP_GPDAC_CH_A_SEL_POS (16U)
#define GPIP_GPDAC_CH_A_SEL_LEN (4U)
#define GPIP_GPDAC_CH_A_SEL_MSK (((1U<<GPIP_GPDAC_CH_A_SEL_LEN)-1)<<GPIP_GPDAC_CH_A_SEL_POS)
#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U<<GPIP_GPDAC_CH_A_SEL_LEN)-1)<<GPIP_GPDAC_CH_A_SEL_POS))
#define GPIP_GPDAC_CH_B_SEL GPIP_GPDAC_CH_B_SEL
#define GPIP_GPDAC_CH_B_SEL_POS (20U)
#define GPIP_GPDAC_CH_B_SEL_LEN (4U)
#define GPIP_GPDAC_CH_B_SEL_MSK (((1U<<GPIP_GPDAC_CH_B_SEL_LEN)-1)<<GPIP_GPDAC_CH_B_SEL_POS)
#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U<<GPIP_GPDAC_CH_B_SEL_LEN)-1)<<GPIP_GPDAC_CH_B_SEL_POS))
/* 0x44 : gpdac_dma_config */
#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
#define GPIP_GPDAC_DMA_TX_EN GPIP_GPDAC_DMA_TX_EN
#define GPIP_GPDAC_DMA_TX_EN_POS (0U)
#define GPIP_GPDAC_DMA_TX_EN_LEN (1U)
#define GPIP_GPDAC_DMA_TX_EN_MSK (((1U<<GPIP_GPDAC_DMA_TX_EN_LEN)-1)<<GPIP_GPDAC_DMA_TX_EN_POS)
#define GPIP_GPDAC_DMA_TX_EN_UMSK (~(((1U<<GPIP_GPDAC_DMA_TX_EN_LEN)-1)<<GPIP_GPDAC_DMA_TX_EN_POS))
#define GPIP_GPDAC_DMA_FORMAT GPIP_GPDAC_DMA_FORMAT
#define GPIP_GPDAC_DMA_FORMAT_POS (4U)
#define GPIP_GPDAC_DMA_FORMAT_LEN (2U)
#define GPIP_GPDAC_DMA_FORMAT_MSK (((1U<<GPIP_GPDAC_DMA_FORMAT_LEN)-1)<<GPIP_GPDAC_DMA_FORMAT_POS)
#define GPIP_GPDAC_DMA_FORMAT_UMSK (~(((1U<<GPIP_GPDAC_DMA_FORMAT_LEN)-1)<<GPIP_GPDAC_DMA_FORMAT_POS))
/* 0x48 : gpdac_dma_wdata */
#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
#define GPIP_GPDAC_DMA_WDATA GPIP_GPDAC_DMA_WDATA
#define GPIP_GPDAC_DMA_WDATA_POS (0U)
#define GPIP_GPDAC_DMA_WDATA_LEN (32U)
#define GPIP_GPDAC_DMA_WDATA_MSK (((1U<<GPIP_GPDAC_DMA_WDATA_LEN)-1)<<GPIP_GPDAC_DMA_WDATA_POS)
#define GPIP_GPDAC_DMA_WDATA_UMSK (~(((1U<<GPIP_GPDAC_DMA_WDATA_LEN)-1)<<GPIP_GPDAC_DMA_WDATA_POS))
/* 0x4C : gpdac_tx_fifo_status */
#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
#define GPIP_TX_FIFO_EMPTY GPIP_TX_FIFO_EMPTY
#define GPIP_TX_FIFO_EMPTY_POS (0U)
#define GPIP_TX_FIFO_EMPTY_LEN (1U)
#define GPIP_TX_FIFO_EMPTY_MSK (((1U<<GPIP_TX_FIFO_EMPTY_LEN)-1)<<GPIP_TX_FIFO_EMPTY_POS)
#define GPIP_TX_FIFO_EMPTY_UMSK (~(((1U<<GPIP_TX_FIFO_EMPTY_LEN)-1)<<GPIP_TX_FIFO_EMPTY_POS))
#define GPIP_TX_FIFO_FULL GPIP_TX_FIFO_FULL
#define GPIP_TX_FIFO_FULL_POS (1U)
#define GPIP_TX_FIFO_FULL_LEN (1U)
#define GPIP_TX_FIFO_FULL_MSK (((1U<<GPIP_TX_FIFO_FULL_LEN)-1)<<GPIP_TX_FIFO_FULL_POS)
#define GPIP_TX_FIFO_FULL_UMSK (~(((1U<<GPIP_TX_FIFO_FULL_LEN)-1)<<GPIP_TX_FIFO_FULL_POS))
#define GPIP_TX_CS GPIP_TX_CS
#define GPIP_TX_CS_POS (2U)
#define GPIP_TX_CS_LEN (2U)
#define GPIP_TX_CS_MSK (((1U<<GPIP_TX_CS_LEN)-1)<<GPIP_TX_CS_POS)
#define GPIP_TX_CS_UMSK (~(((1U<<GPIP_TX_CS_LEN)-1)<<GPIP_TX_CS_POS))
#define GPIP_TXFIFORDPTR GPIP_TXFIFORDPTR
#define GPIP_TXFIFORDPTR_POS (4U)
#define GPIP_TXFIFORDPTR_LEN (3U)
#define GPIP_TXFIFORDPTR_MSK (((1U<<GPIP_TXFIFORDPTR_LEN)-1)<<GPIP_TXFIFORDPTR_POS)
#define GPIP_TXFIFORDPTR_UMSK (~(((1U<<GPIP_TXFIFORDPTR_LEN)-1)<<GPIP_TXFIFORDPTR_POS))
#define GPIP_TXFIFOWRPTR GPIP_TXFIFOWRPTR
#define GPIP_TXFIFOWRPTR_POS (8U)
#define GPIP_TXFIFOWRPTR_LEN (2U)
#define GPIP_TXFIFOWRPTR_MSK (((1U<<GPIP_TXFIFOWRPTR_LEN)-1)<<GPIP_TXFIFOWRPTR_POS)
#define GPIP_TXFIFOWRPTR_UMSK (~(((1U<<GPIP_TXFIFOWRPTR_LEN)-1)<<GPIP_TXFIFOWRPTR_POS))
struct gpip_reg {
/* 0x0 : gpadc_config */
union {
struct {
uint32_t gpadc_dma_en : 1; /* [ 0], r/w, 0x0 */
uint32_t gpadc_fifo_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t gpadc_fifo_ne : 1; /* [ 2], r, 0x0 */
uint32_t gpadc_fifo_full : 1; /* [ 3], r, 0x0 */
uint32_t gpadc_rdy : 1; /* [ 4], r, 0x0 */
uint32_t gpadc_fifo_overrun : 1; /* [ 5], r, 0x0 */
uint32_t gpadc_fifo_underrun : 1; /* [ 6], r, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t gpadc_rdy_clr : 1; /* [ 8], r/w, 0x0 */
uint32_t gpadc_fifo_overrun_clr : 1; /* [ 9], r/w, 0x0 */
uint32_t gpadc_fifo_underrun_clr : 1; /* [ 10], r/w, 0x0 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t gpadc_rdy_mask : 1; /* [ 12], r/w, 0x0 */
uint32_t gpadc_fifo_overrun_mask : 1; /* [ 13], r/w, 0x0 */
uint32_t gpadc_fifo_underrun_mask : 1; /* [ 14], r/w, 0x0 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t gpadc_fifo_data_count : 6; /* [21:16], r, 0x0 */
uint32_t gpadc_fifo_thl : 2; /* [23:22], r/w, 0x0 */
uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0x0 */
}BF;
uint32_t WORD;
} gpadc_config;
/* 0x4 : gpadc_dma_rdata */
union {
struct {
uint32_t gpadc_dma_rdata : 26; /* [25: 0], r, 0x0 */
uint32_t rsvd_31_26 : 6; /* [31:26], rsvd, 0x0 */
}BF;
uint32_t WORD;
} gpadc_dma_rdata;
/* 0x8 reserved */
uint8_t RESERVED0x8[56];
/* 0x40 : gpdac_config */
union {
struct {
uint32_t gpdac_en : 1; /* [ 0], r/w, 0x0 */
uint32_t gpdac_en2 : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
uint32_t dsm_mode : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t gpdac_mode : 3; /* [10: 8], r/w, 0x0 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t gpdac_ch_a_sel : 4; /* [19:16], r/w, 0x0 */
uint32_t gpdac_ch_b_sel : 4; /* [23:20], r/w, 0x0 */
uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0xd */
}BF;
uint32_t WORD;
} gpdac_config;
/* 0x44 : gpdac_dma_config */
union {
struct {
uint32_t gpdac_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
uint32_t gpdac_dma_format : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
}BF;
uint32_t WORD;
} gpdac_dma_config;
/* 0x48 : gpdac_dma_wdata */
union {
struct {
uint32_t gpdac_dma_wdata : 32; /* [31: 0], w, x */
}BF;
uint32_t WORD;
} gpdac_dma_wdata;
/* 0x4C : gpdac_tx_fifo_status */
union {
struct {
uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */
uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */
uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */
uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
}BF;
uint32_t WORD;
} gpdac_tx_fifo_status;
};
typedef volatile struct gpip_reg gpip_reg_t;
#endif /* __GPIP_REG_H__ */

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drivers/bl602_driver/regs/hbn_reg.h Normal file
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@ -0,0 +1,743 @@
/**
******************************************************************************
* @file hbn_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HBN_REG_H__
#define __HBN_REG_H__
#include "bl602.h"
/* 0x0 : HBN_CTL */
#define HBN_CTL_OFFSET (0x0)
#define HBN_RTC_CTL HBN_RTC_CTL
#define HBN_RTC_CTL_POS (0U)
#define HBN_RTC_CTL_LEN (7U)
#define HBN_RTC_CTL_MSK (((1U<<HBN_RTC_CTL_LEN)-1)<<HBN_RTC_CTL_POS)
#define HBN_RTC_CTL_UMSK (~(((1U<<HBN_RTC_CTL_LEN)-1)<<HBN_RTC_CTL_POS))
#define HBN_MODE HBN_MODE
#define HBN_MODE_POS (7U)
#define HBN_MODE_LEN (1U)
#define HBN_MODE_MSK (((1U<<HBN_MODE_LEN)-1)<<HBN_MODE_POS)
#define HBN_MODE_UMSK (~(((1U<<HBN_MODE_LEN)-1)<<HBN_MODE_POS))
#define HBN_TRAP_MODE HBN_TRAP_MODE
#define HBN_TRAP_MODE_POS (8U)
#define HBN_TRAP_MODE_LEN (1U)
#define HBN_TRAP_MODE_MSK (((1U<<HBN_TRAP_MODE_LEN)-1)<<HBN_TRAP_MODE_POS)
#define HBN_TRAP_MODE_UMSK (~(((1U<<HBN_TRAP_MODE_LEN)-1)<<HBN_TRAP_MODE_POS))
#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE
#define HBN_PWRDN_HBN_CORE_POS (9U)
#define HBN_PWRDN_HBN_CORE_LEN (1U)
#define HBN_PWRDN_HBN_CORE_MSK (((1U<<HBN_PWRDN_HBN_CORE_LEN)-1)<<HBN_PWRDN_HBN_CORE_POS)
#define HBN_PWRDN_HBN_CORE_UMSK (~(((1U<<HBN_PWRDN_HBN_CORE_LEN)-1)<<HBN_PWRDN_HBN_CORE_POS))
#define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC
#define HBN_PWRDN_HBN_RTC_POS (11U)
#define HBN_PWRDN_HBN_RTC_LEN (1U)
#define HBN_PWRDN_HBN_RTC_MSK (((1U<<HBN_PWRDN_HBN_RTC_LEN)-1)<<HBN_PWRDN_HBN_RTC_POS)
#define HBN_PWRDN_HBN_RTC_UMSK (~(((1U<<HBN_PWRDN_HBN_RTC_LEN)-1)<<HBN_PWRDN_HBN_RTC_POS))
#define HBN_SW_RST HBN_SW_RST
#define HBN_SW_RST_POS (12U)
#define HBN_SW_RST_LEN (1U)
#define HBN_SW_RST_MSK (((1U<<HBN_SW_RST_LEN)-1)<<HBN_SW_RST_POS)
#define HBN_SW_RST_UMSK (~(((1U<<HBN_SW_RST_LEN)-1)<<HBN_SW_RST_POS))
#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11
#define HBN_DIS_PWR_OFF_LDO11_POS (13U)
#define HBN_DIS_PWR_OFF_LDO11_LEN (1U)
#define HBN_DIS_PWR_OFF_LDO11_MSK (((1U<<HBN_DIS_PWR_OFF_LDO11_LEN)-1)<<HBN_DIS_PWR_OFF_LDO11_POS)
#define HBN_DIS_PWR_OFF_LDO11_UMSK (~(((1U<<HBN_DIS_PWR_OFF_LDO11_LEN)-1)<<HBN_DIS_PWR_OFF_LDO11_POS))
#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT
#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U)
#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U)
#define HBN_DIS_PWR_OFF_LDO11_RT_MSK (((1U<<HBN_DIS_PWR_OFF_LDO11_RT_LEN)-1)<<HBN_DIS_PWR_OFF_LDO11_RT_POS)
#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U<<HBN_DIS_PWR_OFF_LDO11_RT_LEN)-1)<<HBN_DIS_PWR_OFF_LDO11_RT_POS))
#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL
#define HBN_LDO11_RT_VOUT_SEL_POS (15U)
#define HBN_LDO11_RT_VOUT_SEL_LEN (4U)
#define HBN_LDO11_RT_VOUT_SEL_MSK (((1U<<HBN_LDO11_RT_VOUT_SEL_LEN)-1)<<HBN_LDO11_RT_VOUT_SEL_POS)
#define HBN_LDO11_RT_VOUT_SEL_UMSK (~(((1U<<HBN_LDO11_RT_VOUT_SEL_LEN)-1)<<HBN_LDO11_RT_VOUT_SEL_POS))
#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL
#define HBN_LDO11_AON_VOUT_SEL_POS (19U)
#define HBN_LDO11_AON_VOUT_SEL_LEN (4U)
#define HBN_LDO11_AON_VOUT_SEL_MSK (((1U<<HBN_LDO11_AON_VOUT_SEL_LEN)-1)<<HBN_LDO11_AON_VOUT_SEL_POS)
#define HBN_LDO11_AON_VOUT_SEL_UMSK (~(((1U<<HBN_LDO11_AON_VOUT_SEL_LEN)-1)<<HBN_LDO11_AON_VOUT_SEL_POS))
#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON
#define HBN_PU_DCDC18_AON_POS (23U)
#define HBN_PU_DCDC18_AON_LEN (1U)
#define HBN_PU_DCDC18_AON_MSK (((1U<<HBN_PU_DCDC18_AON_LEN)-1)<<HBN_PU_DCDC18_AON_POS)
#define HBN_PU_DCDC18_AON_UMSK (~(((1U<<HBN_PU_DCDC18_AON_LEN)-1)<<HBN_PU_DCDC18_AON_POS))
#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION
#define HBN_RTC_DLY_OPTION_POS (24U)
#define HBN_RTC_DLY_OPTION_LEN (1U)
#define HBN_RTC_DLY_OPTION_MSK (((1U<<HBN_RTC_DLY_OPTION_LEN)-1)<<HBN_RTC_DLY_OPTION_POS)
#define HBN_RTC_DLY_OPTION_UMSK (~(((1U<<HBN_RTC_DLY_OPTION_LEN)-1)<<HBN_RTC_DLY_OPTION_POS))
#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION
#define HBN_PWR_ON_OPTION_POS (25U)
#define HBN_PWR_ON_OPTION_LEN (1U)
#define HBN_PWR_ON_OPTION_MSK (((1U<<HBN_PWR_ON_OPTION_LEN)-1)<<HBN_PWR_ON_OPTION_POS)
#define HBN_PWR_ON_OPTION_UMSK (~(((1U<<HBN_PWR_ON_OPTION_LEN)-1)<<HBN_PWR_ON_OPTION_POS))
#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION
#define HBN_SRAM_SLP_OPTION_POS (26U)
#define HBN_SRAM_SLP_OPTION_LEN (1U)
#define HBN_SRAM_SLP_OPTION_MSK (((1U<<HBN_SRAM_SLP_OPTION_LEN)-1)<<HBN_SRAM_SLP_OPTION_POS)
#define HBN_SRAM_SLP_OPTION_UMSK (~(((1U<<HBN_SRAM_SLP_OPTION_LEN)-1)<<HBN_SRAM_SLP_OPTION_POS))
#define HBN_SRAM_SLP HBN_SRAM_SLP
#define HBN_SRAM_SLP_POS (27U)
#define HBN_SRAM_SLP_LEN (1U)
#define HBN_SRAM_SLP_MSK (((1U<<HBN_SRAM_SLP_LEN)-1)<<HBN_SRAM_SLP_POS)
#define HBN_SRAM_SLP_UMSK (~(((1U<<HBN_SRAM_SLP_LEN)-1)<<HBN_SRAM_SLP_POS))
#define HBN_STATE HBN_STATE
#define HBN_STATE_POS (28U)
#define HBN_STATE_LEN (4U)
#define HBN_STATE_MSK (((1U<<HBN_STATE_LEN)-1)<<HBN_STATE_POS)
#define HBN_STATE_UMSK (~(((1U<<HBN_STATE_LEN)-1)<<HBN_STATE_POS))
/* 0x4 : HBN_TIME_L */
#define HBN_TIME_L_OFFSET (0x4)
#define HBN_TIME_L HBN_TIME_L
#define HBN_TIME_L_POS (0U)
#define HBN_TIME_L_LEN (32U)
#define HBN_TIME_L_MSK (((1U<<HBN_TIME_L_LEN)-1)<<HBN_TIME_L_POS)
#define HBN_TIME_L_UMSK (~(((1U<<HBN_TIME_L_LEN)-1)<<HBN_TIME_L_POS))
/* 0x8 : HBN_TIME_H */
#define HBN_TIME_H_OFFSET (0x8)
#define HBN_TIME_H HBN_TIME_H
#define HBN_TIME_H_POS (0U)
#define HBN_TIME_H_LEN (8U)
#define HBN_TIME_H_MSK (((1U<<HBN_TIME_H_LEN)-1)<<HBN_TIME_H_POS)
#define HBN_TIME_H_UMSK (~(((1U<<HBN_TIME_H_LEN)-1)<<HBN_TIME_H_POS))
/* 0xC : RTC_TIME_L */
#define HBN_RTC_TIME_L_OFFSET (0xC)
#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L
#define HBN_RTC_TIME_LATCH_L_POS (0U)
#define HBN_RTC_TIME_LATCH_L_LEN (32U)
#define HBN_RTC_TIME_LATCH_L_MSK (((1U<<HBN_RTC_TIME_LATCH_L_LEN)-1)<<HBN_RTC_TIME_LATCH_L_POS)
#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U<<HBN_RTC_TIME_LATCH_L_LEN)-1)<<HBN_RTC_TIME_LATCH_L_POS))
/* 0x10 : RTC_TIME_H */
#define HBN_RTC_TIME_H_OFFSET (0x10)
#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H
#define HBN_RTC_TIME_LATCH_H_POS (0U)
#define HBN_RTC_TIME_LATCH_H_LEN (8U)
#define HBN_RTC_TIME_LATCH_H_MSK (((1U<<HBN_RTC_TIME_LATCH_H_LEN)-1)<<HBN_RTC_TIME_LATCH_H_POS)
#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U<<HBN_RTC_TIME_LATCH_H_LEN)-1)<<HBN_RTC_TIME_LATCH_H_POS))
#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH
#define HBN_RTC_TIME_LATCH_POS (31U)
#define HBN_RTC_TIME_LATCH_LEN (1U)
#define HBN_RTC_TIME_LATCH_MSK (((1U<<HBN_RTC_TIME_LATCH_LEN)-1)<<HBN_RTC_TIME_LATCH_POS)
#define HBN_RTC_TIME_LATCH_UMSK (~(((1U<<HBN_RTC_TIME_LATCH_LEN)-1)<<HBN_RTC_TIME_LATCH_POS))
/* 0x14 : HBN_IRQ_MODE */
#define HBN_IRQ_MODE_OFFSET (0x14)
#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE
#define HBN_PIN_WAKEUP_MODE_POS (0U)
#define HBN_PIN_WAKEUP_MODE_LEN (3U)
#define HBN_PIN_WAKEUP_MODE_MSK (((1U<<HBN_PIN_WAKEUP_MODE_LEN)-1)<<HBN_PIN_WAKEUP_MODE_POS)
#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U<<HBN_PIN_WAKEUP_MODE_LEN)-1)<<HBN_PIN_WAKEUP_MODE_POS))
#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK
#define HBN_PIN_WAKEUP_MASK_POS (3U)
#define HBN_PIN_WAKEUP_MASK_LEN (2U)
#define HBN_PIN_WAKEUP_MASK_MSK (((1U<<HBN_PIN_WAKEUP_MASK_LEN)-1)<<HBN_PIN_WAKEUP_MASK_POS)
#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U<<HBN_PIN_WAKEUP_MASK_LEN)-1)<<HBN_PIN_WAKEUP_MASK_POS))
#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT
#define HBN_REG_AON_PAD_IE_SMT_POS (8U)
#define HBN_REG_AON_PAD_IE_SMT_LEN (1U)
#define HBN_REG_AON_PAD_IE_SMT_MSK (((1U<<HBN_REG_AON_PAD_IE_SMT_LEN)-1)<<HBN_REG_AON_PAD_IE_SMT_POS)
#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U<<HBN_REG_AON_PAD_IE_SMT_LEN)-1)<<HBN_REG_AON_PAD_IE_SMT_POS))
#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD
#define HBN_REG_EN_HW_PU_PD_POS (16U)
#define HBN_REG_EN_HW_PU_PD_LEN (1U)
#define HBN_REG_EN_HW_PU_PD_MSK (((1U<<HBN_REG_EN_HW_PU_PD_LEN)-1)<<HBN_REG_EN_HW_PU_PD_POS)
#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U<<HBN_REG_EN_HW_PU_PD_LEN)-1)<<HBN_REG_EN_HW_PU_PD_POS))
#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN
#define HBN_IRQ_BOR_EN_POS (18U)
#define HBN_IRQ_BOR_EN_LEN (1U)
#define HBN_IRQ_BOR_EN_MSK (((1U<<HBN_IRQ_BOR_EN_LEN)-1)<<HBN_IRQ_BOR_EN_POS)
#define HBN_IRQ_BOR_EN_UMSK (~(((1U<<HBN_IRQ_BOR_EN_LEN)-1)<<HBN_IRQ_BOR_EN_POS))
#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN
#define HBN_IRQ_ACOMP0_EN_POS (20U)
#define HBN_IRQ_ACOMP0_EN_LEN (2U)
#define HBN_IRQ_ACOMP0_EN_MSK (((1U<<HBN_IRQ_ACOMP0_EN_LEN)-1)<<HBN_IRQ_ACOMP0_EN_POS)
#define HBN_IRQ_ACOMP0_EN_UMSK (~(((1U<<HBN_IRQ_ACOMP0_EN_LEN)-1)<<HBN_IRQ_ACOMP0_EN_POS))
#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN
#define HBN_IRQ_ACOMP1_EN_POS (22U)
#define HBN_IRQ_ACOMP1_EN_LEN (2U)
#define HBN_IRQ_ACOMP1_EN_MSK (((1U<<HBN_IRQ_ACOMP1_EN_LEN)-1)<<HBN_IRQ_ACOMP1_EN_POS)
#define HBN_IRQ_ACOMP1_EN_UMSK (~(((1U<<HBN_IRQ_ACOMP1_EN_LEN)-1)<<HBN_IRQ_ACOMP1_EN_POS))
#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL
#define HBN_PIN_WAKEUP_SEL_POS (24U)
#define HBN_PIN_WAKEUP_SEL_LEN (3U)
#define HBN_PIN_WAKEUP_SEL_MSK (((1U<<HBN_PIN_WAKEUP_SEL_LEN)-1)<<HBN_PIN_WAKEUP_SEL_POS)
#define HBN_PIN_WAKEUP_SEL_UMSK (~(((1U<<HBN_PIN_WAKEUP_SEL_LEN)-1)<<HBN_PIN_WAKEUP_SEL_POS))
#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN
#define HBN_PIN_WAKEUP_EN_POS (27U)
#define HBN_PIN_WAKEUP_EN_LEN (1U)
#define HBN_PIN_WAKEUP_EN_MSK (((1U<<HBN_PIN_WAKEUP_EN_LEN)-1)<<HBN_PIN_WAKEUP_EN_POS)
#define HBN_PIN_WAKEUP_EN_UMSK (~(((1U<<HBN_PIN_WAKEUP_EN_LEN)-1)<<HBN_PIN_WAKEUP_EN_POS))
/* 0x18 : HBN_IRQ_STAT */
#define HBN_IRQ_STAT_OFFSET (0x18)
#define HBN_IRQ_STAT HBN_IRQ_STAT
#define HBN_IRQ_STAT_POS (0U)
#define HBN_IRQ_STAT_LEN (32U)
#define HBN_IRQ_STAT_MSK (((1U<<HBN_IRQ_STAT_LEN)-1)<<HBN_IRQ_STAT_POS)
#define HBN_IRQ_STAT_UMSK (~(((1U<<HBN_IRQ_STAT_LEN)-1)<<HBN_IRQ_STAT_POS))
/* 0x1C : HBN_IRQ_CLR */
#define HBN_IRQ_CLR_OFFSET (0x1C)
#define HBN_IRQ_CLR HBN_IRQ_CLR
#define HBN_IRQ_CLR_POS (0U)
#define HBN_IRQ_CLR_LEN (32U)
#define HBN_IRQ_CLR_MSK (((1U<<HBN_IRQ_CLR_LEN)-1)<<HBN_IRQ_CLR_POS)
#define HBN_IRQ_CLR_UMSK (~(((1U<<HBN_IRQ_CLR_LEN)-1)<<HBN_IRQ_CLR_POS))
/* 0x20 : HBN_PIR_CFG */
#define HBN_PIR_CFG_OFFSET (0x20)
#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL
#define HBN_PIR_HPF_SEL_POS (0U)
#define HBN_PIR_HPF_SEL_LEN (2U)
#define HBN_PIR_HPF_SEL_MSK (((1U<<HBN_PIR_HPF_SEL_LEN)-1)<<HBN_PIR_HPF_SEL_POS)
#define HBN_PIR_HPF_SEL_UMSK (~(((1U<<HBN_PIR_HPF_SEL_LEN)-1)<<HBN_PIR_HPF_SEL_POS))
#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL
#define HBN_PIR_LPF_SEL_POS (2U)
#define HBN_PIR_LPF_SEL_LEN (1U)
#define HBN_PIR_LPF_SEL_MSK (((1U<<HBN_PIR_LPF_SEL_LEN)-1)<<HBN_PIR_LPF_SEL_POS)
#define HBN_PIR_LPF_SEL_UMSK (~(((1U<<HBN_PIR_LPF_SEL_LEN)-1)<<HBN_PIR_LPF_SEL_POS))
#define HBN_PIR_DIS HBN_PIR_DIS
#define HBN_PIR_DIS_POS (4U)
#define HBN_PIR_DIS_LEN (2U)
#define HBN_PIR_DIS_MSK (((1U<<HBN_PIR_DIS_LEN)-1)<<HBN_PIR_DIS_POS)
#define HBN_PIR_DIS_UMSK (~(((1U<<HBN_PIR_DIS_LEN)-1)<<HBN_PIR_DIS_POS))
#define HBN_PIR_EN HBN_PIR_EN
#define HBN_PIR_EN_POS (7U)
#define HBN_PIR_EN_LEN (1U)
#define HBN_PIR_EN_MSK (((1U<<HBN_PIR_EN_LEN)-1)<<HBN_PIR_EN_POS)
#define HBN_PIR_EN_UMSK (~(((1U<<HBN_PIR_EN_LEN)-1)<<HBN_PIR_EN_POS))
#define HBN_GPADC_CGEN HBN_GPADC_CGEN
#define HBN_GPADC_CGEN_POS (8U)
#define HBN_GPADC_CGEN_LEN (1U)
#define HBN_GPADC_CGEN_MSK (((1U<<HBN_GPADC_CGEN_LEN)-1)<<HBN_GPADC_CGEN_POS)
#define HBN_GPADC_CGEN_UMSK (~(((1U<<HBN_GPADC_CGEN_LEN)-1)<<HBN_GPADC_CGEN_POS))
#define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC
#define HBN_GPADC_NOSYNC_POS (9U)
#define HBN_GPADC_NOSYNC_LEN (1U)
#define HBN_GPADC_NOSYNC_MSK (((1U<<HBN_GPADC_NOSYNC_LEN)-1)<<HBN_GPADC_NOSYNC_POS)
#define HBN_GPADC_NOSYNC_UMSK (~(((1U<<HBN_GPADC_NOSYNC_LEN)-1)<<HBN_GPADC_NOSYNC_POS))
/* 0x24 : HBN_PIR_VTH */
#define HBN_PIR_VTH_OFFSET (0x24)
#define HBN_PIR_VTH HBN_PIR_VTH
#define HBN_PIR_VTH_POS (0U)
#define HBN_PIR_VTH_LEN (14U)
#define HBN_PIR_VTH_MSK (((1U<<HBN_PIR_VTH_LEN)-1)<<HBN_PIR_VTH_POS)
#define HBN_PIR_VTH_UMSK (~(((1U<<HBN_PIR_VTH_LEN)-1)<<HBN_PIR_VTH_POS))
/* 0x28 : HBN_PIR_INTERVAL */
#define HBN_PIR_INTERVAL_OFFSET (0x28)
#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL
#define HBN_PIR_INTERVAL_POS (0U)
#define HBN_PIR_INTERVAL_LEN (12U)
#define HBN_PIR_INTERVAL_MSK (((1U<<HBN_PIR_INTERVAL_LEN)-1)<<HBN_PIR_INTERVAL_POS)
#define HBN_PIR_INTERVAL_UMSK (~(((1U<<HBN_PIR_INTERVAL_LEN)-1)<<HBN_PIR_INTERVAL_POS))
/* 0x2C : HBN_BOR_CFG */
#define HBN_BOR_CFG_OFFSET (0x2C)
#define HBN_BOR_SEL HBN_BOR_SEL
#define HBN_BOR_SEL_POS (0U)
#define HBN_BOR_SEL_LEN (1U)
#define HBN_BOR_SEL_MSK (((1U<<HBN_BOR_SEL_LEN)-1)<<HBN_BOR_SEL_POS)
#define HBN_BOR_SEL_UMSK (~(((1U<<HBN_BOR_SEL_LEN)-1)<<HBN_BOR_SEL_POS))
#define HBN_BOR_VTH HBN_BOR_VTH
#define HBN_BOR_VTH_POS (1U)
#define HBN_BOR_VTH_LEN (1U)
#define HBN_BOR_VTH_MSK (((1U<<HBN_BOR_VTH_LEN)-1)<<HBN_BOR_VTH_POS)
#define HBN_BOR_VTH_UMSK (~(((1U<<HBN_BOR_VTH_LEN)-1)<<HBN_BOR_VTH_POS))
#define HBN_PU_BOR HBN_PU_BOR
#define HBN_PU_BOR_POS (2U)
#define HBN_PU_BOR_LEN (1U)
#define HBN_PU_BOR_MSK (((1U<<HBN_PU_BOR_LEN)-1)<<HBN_PU_BOR_POS)
#define HBN_PU_BOR_UMSK (~(((1U<<HBN_PU_BOR_LEN)-1)<<HBN_PU_BOR_POS))
#define HBN_R_BOR_OUT HBN_R_BOR_OUT
#define HBN_R_BOR_OUT_POS (3U)
#define HBN_R_BOR_OUT_LEN (1U)
#define HBN_R_BOR_OUT_MSK (((1U<<HBN_R_BOR_OUT_LEN)-1)<<HBN_R_BOR_OUT_POS)
#define HBN_R_BOR_OUT_UMSK (~(((1U<<HBN_R_BOR_OUT_LEN)-1)<<HBN_R_BOR_OUT_POS))
/* 0x30 : HBN_GLB */
#define HBN_GLB_OFFSET (0x30)
#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL
#define HBN_ROOT_CLK_SEL_POS (0U)
#define HBN_ROOT_CLK_SEL_LEN (2U)
#define HBN_ROOT_CLK_SEL_MSK (((1U<<HBN_ROOT_CLK_SEL_LEN)-1)<<HBN_ROOT_CLK_SEL_POS)
#define HBN_ROOT_CLK_SEL_UMSK (~(((1U<<HBN_ROOT_CLK_SEL_LEN)-1)<<HBN_ROOT_CLK_SEL_POS))
#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL
#define HBN_UART_CLK_SEL_POS (2U)
#define HBN_UART_CLK_SEL_LEN (1U)
#define HBN_UART_CLK_SEL_MSK (((1U<<HBN_UART_CLK_SEL_LEN)-1)<<HBN_UART_CLK_SEL_POS)
#define HBN_UART_CLK_SEL_UMSK (~(((1U<<HBN_UART_CLK_SEL_LEN)-1)<<HBN_UART_CLK_SEL_POS))
#define HBN_F32K_SEL HBN_F32K_SEL
#define HBN_F32K_SEL_POS (3U)
#define HBN_F32K_SEL_LEN (2U)
#define HBN_F32K_SEL_MSK (((1U<<HBN_F32K_SEL_LEN)-1)<<HBN_F32K_SEL_POS)
#define HBN_F32K_SEL_UMSK (~(((1U<<HBN_F32K_SEL_LEN)-1)<<HBN_F32K_SEL_POS))
#define HBN_PU_RC32K HBN_PU_RC32K
#define HBN_PU_RC32K_POS (5U)
#define HBN_PU_RC32K_LEN (1U)
#define HBN_PU_RC32K_MSK (((1U<<HBN_PU_RC32K_LEN)-1)<<HBN_PU_RC32K_POS)
#define HBN_PU_RC32K_UMSK (~(((1U<<HBN_PU_RC32K_LEN)-1)<<HBN_PU_RC32K_POS))
#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK (((1U<<HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN)-1)<<HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U<<HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN)-1)<<HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL
#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U)
#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U)
#define HBN_SW_LDO11_RT_VOUT_SEL_MSK (((1U<<HBN_SW_LDO11_RT_VOUT_SEL_LEN)-1)<<HBN_SW_LDO11_RT_VOUT_SEL_POS)
#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK (~(((1U<<HBN_SW_LDO11_RT_VOUT_SEL_LEN)-1)<<HBN_SW_LDO11_RT_VOUT_SEL_POS))
#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL
#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U)
#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U)
#define HBN_SW_LDO11_AON_VOUT_SEL_MSK (((1U<<HBN_SW_LDO11_AON_VOUT_SEL_LEN)-1)<<HBN_SW_LDO11_AON_VOUT_SEL_POS)
#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK (~(((1U<<HBN_SW_LDO11_AON_VOUT_SEL_LEN)-1)<<HBN_SW_LDO11_AON_VOUT_SEL_POS))
/* 0x34 : HBN_SRAM */
#define HBN_SRAM_OFFSET (0x34)
#define HBN_RETRAM_RET HBN_RETRAM_RET
#define HBN_RETRAM_RET_POS (6U)
#define HBN_RETRAM_RET_LEN (1U)
#define HBN_RETRAM_RET_MSK (((1U<<HBN_RETRAM_RET_LEN)-1)<<HBN_RETRAM_RET_POS)
#define HBN_RETRAM_RET_UMSK (~(((1U<<HBN_RETRAM_RET_LEN)-1)<<HBN_RETRAM_RET_POS))
#define HBN_RETRAM_SLP HBN_RETRAM_SLP
#define HBN_RETRAM_SLP_POS (7U)
#define HBN_RETRAM_SLP_LEN (1U)
#define HBN_RETRAM_SLP_MSK (((1U<<HBN_RETRAM_SLP_LEN)-1)<<HBN_RETRAM_SLP_POS)
#define HBN_RETRAM_SLP_UMSK (~(((1U<<HBN_RETRAM_SLP_LEN)-1)<<HBN_RETRAM_SLP_POS))
/* 0x100 : HBN_RSV0 */
#define HBN_RSV0_OFFSET (0x100)
#define HBN_RSV0 HBN_RSV0
#define HBN_RSV0_POS (0U)
#define HBN_RSV0_LEN (32U)
#define HBN_RSV0_MSK (((1U<<HBN_RSV0_LEN)-1)<<HBN_RSV0_POS)
#define HBN_RSV0_UMSK (~(((1U<<HBN_RSV0_LEN)-1)<<HBN_RSV0_POS))
/* 0x104 : HBN_RSV1 */
#define HBN_RSV1_OFFSET (0x104)
#define HBN_RSV1 HBN_RSV1
#define HBN_RSV1_POS (0U)
#define HBN_RSV1_LEN (32U)
#define HBN_RSV1_MSK (((1U<<HBN_RSV1_LEN)-1)<<HBN_RSV1_POS)
#define HBN_RSV1_UMSK (~(((1U<<HBN_RSV1_LEN)-1)<<HBN_RSV1_POS))
/* 0x108 : HBN_RSV2 */
#define HBN_RSV2_OFFSET (0x108)
#define HBN_RSV2 HBN_RSV2
#define HBN_RSV2_POS (0U)
#define HBN_RSV2_LEN (32U)
#define HBN_RSV2_MSK (((1U<<HBN_RSV2_LEN)-1)<<HBN_RSV2_POS)
#define HBN_RSV2_UMSK (~(((1U<<HBN_RSV2_LEN)-1)<<HBN_RSV2_POS))
/* 0x10C : HBN_RSV3 */
#define HBN_RSV3_OFFSET (0x10C)
#define HBN_RSV3 HBN_RSV3
#define HBN_RSV3_POS (0U)
#define HBN_RSV3_LEN (32U)
#define HBN_RSV3_MSK (((1U<<HBN_RSV3_LEN)-1)<<HBN_RSV3_POS)
#define HBN_RSV3_UMSK (~(((1U<<HBN_RSV3_LEN)-1)<<HBN_RSV3_POS))
/* 0x200 : rc32k_ctrl0 */
#define HBN_RC32K_CTRL0_OFFSET (0x200)
#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE
#define HBN_RC32K_CAL_DONE_POS (0U)
#define HBN_RC32K_CAL_DONE_LEN (1U)
#define HBN_RC32K_CAL_DONE_MSK (((1U<<HBN_RC32K_CAL_DONE_LEN)-1)<<HBN_RC32K_CAL_DONE_POS)
#define HBN_RC32K_CAL_DONE_UMSK (~(((1U<<HBN_RC32K_CAL_DONE_LEN)-1)<<HBN_RC32K_CAL_DONE_POS))
#define HBN_RC32K_RDY HBN_RC32K_RDY
#define HBN_RC32K_RDY_POS (1U)
#define HBN_RC32K_RDY_LEN (1U)
#define HBN_RC32K_RDY_MSK (((1U<<HBN_RC32K_RDY_LEN)-1)<<HBN_RC32K_RDY_POS)
#define HBN_RC32K_RDY_UMSK (~(((1U<<HBN_RC32K_RDY_LEN)-1)<<HBN_RC32K_RDY_POS))
#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS
#define HBN_RC32K_CAL_INPROGRESS_POS (2U)
#define HBN_RC32K_CAL_INPROGRESS_LEN (1U)
#define HBN_RC32K_CAL_INPROGRESS_MSK (((1U<<HBN_RC32K_CAL_INPROGRESS_LEN)-1)<<HBN_RC32K_CAL_INPROGRESS_POS)
#define HBN_RC32K_CAL_INPROGRESS_UMSK (~(((1U<<HBN_RC32K_CAL_INPROGRESS_LEN)-1)<<HBN_RC32K_CAL_INPROGRESS_POS))
#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV
#define HBN_RC32K_CAL_DIV_POS (3U)
#define HBN_RC32K_CAL_DIV_LEN (2U)
#define HBN_RC32K_CAL_DIV_MSK (((1U<<HBN_RC32K_CAL_DIV_LEN)-1)<<HBN_RC32K_CAL_DIV_POS)
#define HBN_RC32K_CAL_DIV_UMSK (~(((1U<<HBN_RC32K_CAL_DIV_LEN)-1)<<HBN_RC32K_CAL_DIV_POS))
#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE
#define HBN_RC32K_CAL_PRECHARGE_POS (5U)
#define HBN_RC32K_CAL_PRECHARGE_LEN (1U)
#define HBN_RC32K_CAL_PRECHARGE_MSK (((1U<<HBN_RC32K_CAL_PRECHARGE_LEN)-1)<<HBN_RC32K_CAL_PRECHARGE_POS)
#define HBN_RC32K_CAL_PRECHARGE_UMSK (~(((1U<<HBN_RC32K_CAL_PRECHARGE_LEN)-1)<<HBN_RC32K_CAL_PRECHARGE_POS))
#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL
#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U)
#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U)
#define HBN_RC32K_DIG_CODE_FR_CAL_MSK (((1U<<HBN_RC32K_DIG_CODE_FR_CAL_LEN)-1)<<HBN_RC32K_DIG_CODE_FR_CAL_POS)
#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U<<HBN_RC32K_DIG_CODE_FR_CAL_LEN)-1)<<HBN_RC32K_DIG_CODE_FR_CAL_POS))
#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY
#define HBN_RC32K_VREF_DLY_POS (16U)
#define HBN_RC32K_VREF_DLY_LEN (2U)
#define HBN_RC32K_VREF_DLY_MSK (((1U<<HBN_RC32K_VREF_DLY_LEN)-1)<<HBN_RC32K_VREF_DLY_POS)
#define HBN_RC32K_VREF_DLY_UMSK (~(((1U<<HBN_RC32K_VREF_DLY_LEN)-1)<<HBN_RC32K_VREF_DLY_POS))
#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL
#define HBN_RC32K_ALLOW_CAL_POS (18U)
#define HBN_RC32K_ALLOW_CAL_LEN (1U)
#define HBN_RC32K_ALLOW_CAL_MSK (((1U<<HBN_RC32K_ALLOW_CAL_LEN)-1)<<HBN_RC32K_ALLOW_CAL_POS)
#define HBN_RC32K_ALLOW_CAL_UMSK (~(((1U<<HBN_RC32K_ALLOW_CAL_LEN)-1)<<HBN_RC32K_ALLOW_CAL_POS))
#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN
#define HBN_RC32K_EXT_CODE_EN_POS (19U)
#define HBN_RC32K_EXT_CODE_EN_LEN (1U)
#define HBN_RC32K_EXT_CODE_EN_MSK (((1U<<HBN_RC32K_EXT_CODE_EN_LEN)-1)<<HBN_RC32K_EXT_CODE_EN_POS)
#define HBN_RC32K_EXT_CODE_EN_UMSK (~(((1U<<HBN_RC32K_EXT_CODE_EN_LEN)-1)<<HBN_RC32K_EXT_CODE_EN_POS))
#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN
#define HBN_RC32K_CAL_EN_POS (20U)
#define HBN_RC32K_CAL_EN_LEN (1U)
#define HBN_RC32K_CAL_EN_MSK (((1U<<HBN_RC32K_CAL_EN_LEN)-1)<<HBN_RC32K_CAL_EN_POS)
#define HBN_RC32K_CAL_EN_UMSK (~(((1U<<HBN_RC32K_CAL_EN_LEN)-1)<<HBN_RC32K_CAL_EN_POS))
#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT
#define HBN_RC32K_CODE_FR_EXT_POS (22U)
#define HBN_RC32K_CODE_FR_EXT_LEN (10U)
#define HBN_RC32K_CODE_FR_EXT_MSK (((1U<<HBN_RC32K_CODE_FR_EXT_LEN)-1)<<HBN_RC32K_CODE_FR_EXT_POS)
#define HBN_RC32K_CODE_FR_EXT_UMSK (~(((1U<<HBN_RC32K_CODE_FR_EXT_LEN)-1)<<HBN_RC32K_CODE_FR_EXT_POS))
/* 0x204 : xtal32k */
#define HBN_XTAL32K_OFFSET (0x204)
#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL
#define HBN_XTAL32K_EXT_SEL_POS (2U)
#define HBN_XTAL32K_EXT_SEL_LEN (1U)
#define HBN_XTAL32K_EXT_SEL_MSK (((1U<<HBN_XTAL32K_EXT_SEL_LEN)-1)<<HBN_XTAL32K_EXT_SEL_POS)
#define HBN_XTAL32K_EXT_SEL_UMSK (~(((1U<<HBN_XTAL32K_EXT_SEL_LEN)-1)<<HBN_XTAL32K_EXT_SEL_POS))
#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL
#define HBN_XTAL32K_AMP_CTRL_POS (3U)
#define HBN_XTAL32K_AMP_CTRL_LEN (2U)
#define HBN_XTAL32K_AMP_CTRL_MSK (((1U<<HBN_XTAL32K_AMP_CTRL_LEN)-1)<<HBN_XTAL32K_AMP_CTRL_POS)
#define HBN_XTAL32K_AMP_CTRL_UMSK (~(((1U<<HBN_XTAL32K_AMP_CTRL_LEN)-1)<<HBN_XTAL32K_AMP_CTRL_POS))
#define HBN_XTAL32K_REG HBN_XTAL32K_REG
#define HBN_XTAL32K_REG_POS (5U)
#define HBN_XTAL32K_REG_LEN (2U)
#define HBN_XTAL32K_REG_MSK (((1U<<HBN_XTAL32K_REG_LEN)-1)<<HBN_XTAL32K_REG_POS)
#define HBN_XTAL32K_REG_UMSK (~(((1U<<HBN_XTAL32K_REG_LEN)-1)<<HBN_XTAL32K_REG_POS))
#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE
#define HBN_XTAL32K_OUTBUF_STRE_POS (7U)
#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U)
#define HBN_XTAL32K_OUTBUF_STRE_MSK (((1U<<HBN_XTAL32K_OUTBUF_STRE_LEN)-1)<<HBN_XTAL32K_OUTBUF_STRE_POS)
#define HBN_XTAL32K_OUTBUF_STRE_UMSK (~(((1U<<HBN_XTAL32K_OUTBUF_STRE_LEN)-1)<<HBN_XTAL32K_OUTBUF_STRE_POS))
#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT
#define HBN_XTAL32K_OTF_SHORT_POS (8U)
#define HBN_XTAL32K_OTF_SHORT_LEN (1U)
#define HBN_XTAL32K_OTF_SHORT_MSK (((1U<<HBN_XTAL32K_OTF_SHORT_LEN)-1)<<HBN_XTAL32K_OTF_SHORT_POS)
#define HBN_XTAL32K_OTF_SHORT_UMSK (~(((1U<<HBN_XTAL32K_OTF_SHORT_LEN)-1)<<HBN_XTAL32K_OTF_SHORT_POS))
#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE
#define HBN_XTAL32K_INV_STRE_POS (9U)
#define HBN_XTAL32K_INV_STRE_LEN (2U)
#define HBN_XTAL32K_INV_STRE_MSK (((1U<<HBN_XTAL32K_INV_STRE_LEN)-1)<<HBN_XTAL32K_INV_STRE_POS)
#define HBN_XTAL32K_INV_STRE_UMSK (~(((1U<<HBN_XTAL32K_INV_STRE_LEN)-1)<<HBN_XTAL32K_INV_STRE_POS))
#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK
#define HBN_XTAL32K_CAPBANK_POS (11U)
#define HBN_XTAL32K_CAPBANK_LEN (6U)
#define HBN_XTAL32K_CAPBANK_MSK (((1U<<HBN_XTAL32K_CAPBANK_LEN)-1)<<HBN_XTAL32K_CAPBANK_POS)
#define HBN_XTAL32K_CAPBANK_UMSK (~(((1U<<HBN_XTAL32K_CAPBANK_LEN)-1)<<HBN_XTAL32K_CAPBANK_POS))
#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT
#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U)
#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U)
#define HBN_XTAL32K_AC_CAP_SHORT_MSK (((1U<<HBN_XTAL32K_AC_CAP_SHORT_LEN)-1)<<HBN_XTAL32K_AC_CAP_SHORT_POS)
#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U<<HBN_XTAL32K_AC_CAP_SHORT_LEN)-1)<<HBN_XTAL32K_AC_CAP_SHORT_POS))
#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF
#define HBN_PU_XTAL32K_BUF_POS (18U)
#define HBN_PU_XTAL32K_BUF_LEN (1U)
#define HBN_PU_XTAL32K_BUF_MSK (((1U<<HBN_PU_XTAL32K_BUF_LEN)-1)<<HBN_PU_XTAL32K_BUF_POS)
#define HBN_PU_XTAL32K_BUF_UMSK (~(((1U<<HBN_PU_XTAL32K_BUF_LEN)-1)<<HBN_PU_XTAL32K_BUF_POS))
#define HBN_PU_XTAL32K HBN_PU_XTAL32K
#define HBN_PU_XTAL32K_POS (19U)
#define HBN_PU_XTAL32K_LEN (1U)
#define HBN_PU_XTAL32K_MSK (((1U<<HBN_PU_XTAL32K_LEN)-1)<<HBN_PU_XTAL32K_POS)
#define HBN_PU_XTAL32K_UMSK (~(((1U<<HBN_PU_XTAL32K_LEN)-1)<<HBN_PU_XTAL32K_POS))
struct hbn_reg {
/* 0x0 : HBN_CTL */
union {
struct {
uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */
uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */
uint32_t trap_mode : 1; /* [ 8], r, 0x0 */
uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */
uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */
uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */
uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */
uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */
uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */
uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */
uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */
uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */
uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */
uint32_t sram_slp : 1; /* [ 27], r, 0x0 */
uint32_t hbn_state : 4; /* [31:28], r, 0x0 */
}BF;
uint32_t WORD;
} HBN_CTL;
/* 0x4 : HBN_TIME_L */
union {
struct {
uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} HBN_TIME_L;
/* 0x8 : HBN_TIME_H */
union {
struct {
uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_TIME_H;
/* 0xC : RTC_TIME_L */
union {
struct {
uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} RTC_TIME_L;
/* 0x10 : RTC_TIME_H */
union {
struct {
uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */
uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */
uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */
}BF;
uint32_t WORD;
} RTC_TIME_H;
/* 0x14 : HBN_IRQ_MODE */
union {
struct {
uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */
uint32_t hbn_pin_wakeup_mask : 2; /* [ 4: 3], r/w, 0x0 */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t reg_aon_pad_ie_smt : 1; /* [ 8], r/w, 0x1 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */
uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */
uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */
uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */
uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */
uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_IRQ_MODE;
/* 0x18 : HBN_IRQ_STAT */
union {
struct {
uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} HBN_IRQ_STAT;
/* 0x1C : HBN_IRQ_CLR */
union {
struct {
uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */
}BF;
uint32_t WORD;
} HBN_IRQ_CLR;
/* 0x20 : HBN_PIR_CFG */
union {
struct {
uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */
uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */
uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_PIR_CFG;
/* 0x24 : HBN_PIR_VTH */
union {
struct {
uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */
uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_PIR_VTH;
/* 0x28 : HBN_PIR_INTERVAL */
union {
struct {
uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_PIR_INTERVAL;
/* 0x2C : HBN_BOR_CFG */
union {
struct {
uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */
uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */
uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */
uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_BOR_CFG;
/* 0x30 : HBN_GLB */
union {
struct {
uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */
uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */
uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */
uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */
}BF;
uint32_t WORD;
} HBN_GLB;
/* 0x34 : HBN_SRAM */
union {
struct {
uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */
uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */
uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} HBN_SRAM;
/* 0x38 reserved */
uint8_t RESERVED0x38[200];
/* 0x100 : HBN_RSV0 */
union {
struct {
uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} HBN_RSV0;
/* 0x104 : HBN_RSV1 */
union {
struct {
uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} HBN_RSV1;
/* 0x108 : HBN_RSV2 */
union {
struct {
uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} HBN_RSV2;
/* 0x10C : HBN_RSV3 */
union {
struct {
uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} HBN_RSV3;
/* 0x110 reserved */
uint8_t RESERVED0x110[240];
/* 0x200 : rc32k_ctrl0 */
union {
struct {
uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */
uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */
uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */
uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */
uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */
uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */
uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */
uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */
uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */
uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x140 */
}BF;
uint32_t WORD;
} rc32k_ctrl0;
/* 0x204 : xtal32k */
union {
struct {
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */
uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */
uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */
uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */
uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */
uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */
uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */
uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */
uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */
uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
}BF;
uint32_t WORD;
} xtal32k;
};
typedef volatile struct hbn_reg hbn_reg_t;
#endif /* __HBN_REG_H__ */

549
drivers/bl602_driver/regs/i2c_reg.h Normal file
View file

@ -0,0 +1,549 @@
/**
******************************************************************************
* @file i2c_reg.h
* @version V1.2
* @date 2019-10-21
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __I2C_REG_H__
#define __I2C_REG_H__
#include "bl602.h"
/* 0x0 : i2c_config */
#define I2C_CONFIG_OFFSET (0x0)
#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN
#define I2C_CR_I2C_M_EN_POS (0U)
#define I2C_CR_I2C_M_EN_LEN (1U)
#define I2C_CR_I2C_M_EN_MSK (((1U<<I2C_CR_I2C_M_EN_LEN)-1)<<I2C_CR_I2C_M_EN_POS)
#define I2C_CR_I2C_M_EN_UMSK (~(((1U<<I2C_CR_I2C_M_EN_LEN)-1)<<I2C_CR_I2C_M_EN_POS))
#define I2C_CR_I2C_PKT_DIR I2C_CR_I2C_PKT_DIR
#define I2C_CR_I2C_PKT_DIR_POS (1U)
#define I2C_CR_I2C_PKT_DIR_LEN (1U)
#define I2C_CR_I2C_PKT_DIR_MSK (((1U<<I2C_CR_I2C_PKT_DIR_LEN)-1)<<I2C_CR_I2C_PKT_DIR_POS)
#define I2C_CR_I2C_PKT_DIR_UMSK (~(((1U<<I2C_CR_I2C_PKT_DIR_LEN)-1)<<I2C_CR_I2C_PKT_DIR_POS))
#define I2C_CR_I2C_DEG_EN I2C_CR_I2C_DEG_EN
#define I2C_CR_I2C_DEG_EN_POS (2U)
#define I2C_CR_I2C_DEG_EN_LEN (1U)
#define I2C_CR_I2C_DEG_EN_MSK (((1U<<I2C_CR_I2C_DEG_EN_LEN)-1)<<I2C_CR_I2C_DEG_EN_POS)
#define I2C_CR_I2C_DEG_EN_UMSK (~(((1U<<I2C_CR_I2C_DEG_EN_LEN)-1)<<I2C_CR_I2C_DEG_EN_POS))
#define I2C_CR_I2C_SCL_SYNC_EN I2C_CR_I2C_SCL_SYNC_EN
#define I2C_CR_I2C_SCL_SYNC_EN_POS (3U)
#define I2C_CR_I2C_SCL_SYNC_EN_LEN (1U)
#define I2C_CR_I2C_SCL_SYNC_EN_MSK (((1U<<I2C_CR_I2C_SCL_SYNC_EN_LEN)-1)<<I2C_CR_I2C_SCL_SYNC_EN_POS)
#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U<<I2C_CR_I2C_SCL_SYNC_EN_LEN)-1)<<I2C_CR_I2C_SCL_SYNC_EN_POS))
#define I2C_CR_I2C_SUB_ADDR_EN I2C_CR_I2C_SUB_ADDR_EN
#define I2C_CR_I2C_SUB_ADDR_EN_POS (4U)
#define I2C_CR_I2C_SUB_ADDR_EN_LEN (1U)
#define I2C_CR_I2C_SUB_ADDR_EN_MSK (((1U<<I2C_CR_I2C_SUB_ADDR_EN_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_EN_POS)
#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U<<I2C_CR_I2C_SUB_ADDR_EN_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_EN_POS))
#define I2C_CR_I2C_SUB_ADDR_BC I2C_CR_I2C_SUB_ADDR_BC
#define I2C_CR_I2C_SUB_ADDR_BC_POS (5U)
#define I2C_CR_I2C_SUB_ADDR_BC_LEN (2U)
#define I2C_CR_I2C_SUB_ADDR_BC_MSK (((1U<<I2C_CR_I2C_SUB_ADDR_BC_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_BC_POS)
#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U<<I2C_CR_I2C_SUB_ADDR_BC_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_BC_POS))
#define I2C_CR_I2C_SLV_ADDR I2C_CR_I2C_SLV_ADDR
#define I2C_CR_I2C_SLV_ADDR_POS (8U)
#define I2C_CR_I2C_SLV_ADDR_LEN (7U)
#define I2C_CR_I2C_SLV_ADDR_MSK (((1U<<I2C_CR_I2C_SLV_ADDR_LEN)-1)<<I2C_CR_I2C_SLV_ADDR_POS)
#define I2C_CR_I2C_SLV_ADDR_UMSK (~(((1U<<I2C_CR_I2C_SLV_ADDR_LEN)-1)<<I2C_CR_I2C_SLV_ADDR_POS))
#define I2C_CR_I2C_PKT_LEN I2C_CR_I2C_PKT_LEN
#define I2C_CR_I2C_PKT_LEN_POS (16U)
#define I2C_CR_I2C_PKT_LEN_LEN (8U)
#define I2C_CR_I2C_PKT_LEN_MSK (((1U<<I2C_CR_I2C_PKT_LEN_LEN)-1)<<I2C_CR_I2C_PKT_LEN_POS)
#define I2C_CR_I2C_PKT_LEN_UMSK (~(((1U<<I2C_CR_I2C_PKT_LEN_LEN)-1)<<I2C_CR_I2C_PKT_LEN_POS))
#define I2C_CR_I2C_DEG_CNT I2C_CR_I2C_DEG_CNT
#define I2C_CR_I2C_DEG_CNT_POS (28U)
#define I2C_CR_I2C_DEG_CNT_LEN (4U)
#define I2C_CR_I2C_DEG_CNT_MSK (((1U<<I2C_CR_I2C_DEG_CNT_LEN)-1)<<I2C_CR_I2C_DEG_CNT_POS)
#define I2C_CR_I2C_DEG_CNT_UMSK (~(((1U<<I2C_CR_I2C_DEG_CNT_LEN)-1)<<I2C_CR_I2C_DEG_CNT_POS))
/* 0x4 : i2c_int_sts */
#define I2C_INT_STS_OFFSET (0x4)
#define I2C_END_INT I2C_END_INT
#define I2C_END_INT_POS (0U)
#define I2C_END_INT_LEN (1U)
#define I2C_END_INT_MSK (((1U<<I2C_END_INT_LEN)-1)<<I2C_END_INT_POS)
#define I2C_END_INT_UMSK (~(((1U<<I2C_END_INT_LEN)-1)<<I2C_END_INT_POS))
#define I2C_TXF_INT I2C_TXF_INT
#define I2C_TXF_INT_POS (1U)
#define I2C_TXF_INT_LEN (1U)
#define I2C_TXF_INT_MSK (((1U<<I2C_TXF_INT_LEN)-1)<<I2C_TXF_INT_POS)
#define I2C_TXF_INT_UMSK (~(((1U<<I2C_TXF_INT_LEN)-1)<<I2C_TXF_INT_POS))
#define I2C_RXF_INT I2C_RXF_INT
#define I2C_RXF_INT_POS (2U)
#define I2C_RXF_INT_LEN (1U)
#define I2C_RXF_INT_MSK (((1U<<I2C_RXF_INT_LEN)-1)<<I2C_RXF_INT_POS)
#define I2C_RXF_INT_UMSK (~(((1U<<I2C_RXF_INT_LEN)-1)<<I2C_RXF_INT_POS))
#define I2C_NAK_INT I2C_NAK_INT
#define I2C_NAK_INT_POS (3U)
#define I2C_NAK_INT_LEN (1U)
#define I2C_NAK_INT_MSK (((1U<<I2C_NAK_INT_LEN)-1)<<I2C_NAK_INT_POS)
#define I2C_NAK_INT_UMSK (~(((1U<<I2C_NAK_INT_LEN)-1)<<I2C_NAK_INT_POS))
#define I2C_ARB_INT I2C_ARB_INT
#define I2C_ARB_INT_POS (4U)
#define I2C_ARB_INT_LEN (1U)
#define I2C_ARB_INT_MSK (((1U<<I2C_ARB_INT_LEN)-1)<<I2C_ARB_INT_POS)
#define I2C_ARB_INT_UMSK (~(((1U<<I2C_ARB_INT_LEN)-1)<<I2C_ARB_INT_POS))
#define I2C_FER_INT I2C_FER_INT
#define I2C_FER_INT_POS (5U)
#define I2C_FER_INT_LEN (1U)
#define I2C_FER_INT_MSK (((1U<<I2C_FER_INT_LEN)-1)<<I2C_FER_INT_POS)
#define I2C_FER_INT_UMSK (~(((1U<<I2C_FER_INT_LEN)-1)<<I2C_FER_INT_POS))
#define I2C_CR_I2C_END_MASK I2C_CR_I2C_END_MASK
#define I2C_CR_I2C_END_MASK_POS (8U)
#define I2C_CR_I2C_END_MASK_LEN (1U)
#define I2C_CR_I2C_END_MASK_MSK (((1U<<I2C_CR_I2C_END_MASK_LEN)-1)<<I2C_CR_I2C_END_MASK_POS)
#define I2C_CR_I2C_END_MASK_UMSK (~(((1U<<I2C_CR_I2C_END_MASK_LEN)-1)<<I2C_CR_I2C_END_MASK_POS))
#define I2C_CR_I2C_TXF_MASK I2C_CR_I2C_TXF_MASK
#define I2C_CR_I2C_TXF_MASK_POS (9U)
#define I2C_CR_I2C_TXF_MASK_LEN (1U)
#define I2C_CR_I2C_TXF_MASK_MSK (((1U<<I2C_CR_I2C_TXF_MASK_LEN)-1)<<I2C_CR_I2C_TXF_MASK_POS)
#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U<<I2C_CR_I2C_TXF_MASK_LEN)-1)<<I2C_CR_I2C_TXF_MASK_POS))
#define I2C_CR_I2C_RXF_MASK I2C_CR_I2C_RXF_MASK
#define I2C_CR_I2C_RXF_MASK_POS (10U)
#define I2C_CR_I2C_RXF_MASK_LEN (1U)
#define I2C_CR_I2C_RXF_MASK_MSK (((1U<<I2C_CR_I2C_RXF_MASK_LEN)-1)<<I2C_CR_I2C_RXF_MASK_POS)
#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U<<I2C_CR_I2C_RXF_MASK_LEN)-1)<<I2C_CR_I2C_RXF_MASK_POS))
#define I2C_CR_I2C_NAK_MASK I2C_CR_I2C_NAK_MASK
#define I2C_CR_I2C_NAK_MASK_POS (11U)
#define I2C_CR_I2C_NAK_MASK_LEN (1U)
#define I2C_CR_I2C_NAK_MASK_MSK (((1U<<I2C_CR_I2C_NAK_MASK_LEN)-1)<<I2C_CR_I2C_NAK_MASK_POS)
#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U<<I2C_CR_I2C_NAK_MASK_LEN)-1)<<I2C_CR_I2C_NAK_MASK_POS))
#define I2C_CR_I2C_ARB_MASK I2C_CR_I2C_ARB_MASK
#define I2C_CR_I2C_ARB_MASK_POS (12U)
#define I2C_CR_I2C_ARB_MASK_LEN (1U)
#define I2C_CR_I2C_ARB_MASK_MSK (((1U<<I2C_CR_I2C_ARB_MASK_LEN)-1)<<I2C_CR_I2C_ARB_MASK_POS)
#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U<<I2C_CR_I2C_ARB_MASK_LEN)-1)<<I2C_CR_I2C_ARB_MASK_POS))
#define I2C_CR_I2C_FER_MASK I2C_CR_I2C_FER_MASK
#define I2C_CR_I2C_FER_MASK_POS (13U)
#define I2C_CR_I2C_FER_MASK_LEN (1U)
#define I2C_CR_I2C_FER_MASK_MSK (((1U<<I2C_CR_I2C_FER_MASK_LEN)-1)<<I2C_CR_I2C_FER_MASK_POS)
#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U<<I2C_CR_I2C_FER_MASK_LEN)-1)<<I2C_CR_I2C_FER_MASK_POS))
#define I2C_CR_I2C_END_CLR I2C_CR_I2C_END_CLR
#define I2C_CR_I2C_END_CLR_POS (16U)
#define I2C_CR_I2C_END_CLR_LEN (1U)
#define I2C_CR_I2C_END_CLR_MSK (((1U<<I2C_CR_I2C_END_CLR_LEN)-1)<<I2C_CR_I2C_END_CLR_POS)
#define I2C_CR_I2C_END_CLR_UMSK (~(((1U<<I2C_CR_I2C_END_CLR_LEN)-1)<<I2C_CR_I2C_END_CLR_POS))
#define I2C_CR_I2C_NAK_CLR I2C_CR_I2C_NAK_CLR
#define I2C_CR_I2C_NAK_CLR_POS (19U)
#define I2C_CR_I2C_NAK_CLR_LEN (1U)
#define I2C_CR_I2C_NAK_CLR_MSK (((1U<<I2C_CR_I2C_NAK_CLR_LEN)-1)<<I2C_CR_I2C_NAK_CLR_POS)
#define I2C_CR_I2C_NAK_CLR_UMSK (~(((1U<<I2C_CR_I2C_NAK_CLR_LEN)-1)<<I2C_CR_I2C_NAK_CLR_POS))
#define I2C_CR_I2C_ARB_CLR I2C_CR_I2C_ARB_CLR
#define I2C_CR_I2C_ARB_CLR_POS (20U)
#define I2C_CR_I2C_ARB_CLR_LEN (1U)
#define I2C_CR_I2C_ARB_CLR_MSK (((1U<<I2C_CR_I2C_ARB_CLR_LEN)-1)<<I2C_CR_I2C_ARB_CLR_POS)
#define I2C_CR_I2C_ARB_CLR_UMSK (~(((1U<<I2C_CR_I2C_ARB_CLR_LEN)-1)<<I2C_CR_I2C_ARB_CLR_POS))
#define I2C_CR_I2C_END_EN I2C_CR_I2C_END_EN
#define I2C_CR_I2C_END_EN_POS (24U)
#define I2C_CR_I2C_END_EN_LEN (1U)
#define I2C_CR_I2C_END_EN_MSK (((1U<<I2C_CR_I2C_END_EN_LEN)-1)<<I2C_CR_I2C_END_EN_POS)
#define I2C_CR_I2C_END_EN_UMSK (~(((1U<<I2C_CR_I2C_END_EN_LEN)-1)<<I2C_CR_I2C_END_EN_POS))
#define I2C_CR_I2C_TXF_EN I2C_CR_I2C_TXF_EN
#define I2C_CR_I2C_TXF_EN_POS (25U)
#define I2C_CR_I2C_TXF_EN_LEN (1U)
#define I2C_CR_I2C_TXF_EN_MSK (((1U<<I2C_CR_I2C_TXF_EN_LEN)-1)<<I2C_CR_I2C_TXF_EN_POS)
#define I2C_CR_I2C_TXF_EN_UMSK (~(((1U<<I2C_CR_I2C_TXF_EN_LEN)-1)<<I2C_CR_I2C_TXF_EN_POS))
#define I2C_CR_I2C_RXF_EN I2C_CR_I2C_RXF_EN
#define I2C_CR_I2C_RXF_EN_POS (26U)
#define I2C_CR_I2C_RXF_EN_LEN (1U)
#define I2C_CR_I2C_RXF_EN_MSK (((1U<<I2C_CR_I2C_RXF_EN_LEN)-1)<<I2C_CR_I2C_RXF_EN_POS)
#define I2C_CR_I2C_RXF_EN_UMSK (~(((1U<<I2C_CR_I2C_RXF_EN_LEN)-1)<<I2C_CR_I2C_RXF_EN_POS))
#define I2C_CR_I2C_NAK_EN I2C_CR_I2C_NAK_EN
#define I2C_CR_I2C_NAK_EN_POS (27U)
#define I2C_CR_I2C_NAK_EN_LEN (1U)
#define I2C_CR_I2C_NAK_EN_MSK (((1U<<I2C_CR_I2C_NAK_EN_LEN)-1)<<I2C_CR_I2C_NAK_EN_POS)
#define I2C_CR_I2C_NAK_EN_UMSK (~(((1U<<I2C_CR_I2C_NAK_EN_LEN)-1)<<I2C_CR_I2C_NAK_EN_POS))
#define I2C_CR_I2C_ARB_EN I2C_CR_I2C_ARB_EN
#define I2C_CR_I2C_ARB_EN_POS (28U)
#define I2C_CR_I2C_ARB_EN_LEN (1U)
#define I2C_CR_I2C_ARB_EN_MSK (((1U<<I2C_CR_I2C_ARB_EN_LEN)-1)<<I2C_CR_I2C_ARB_EN_POS)
#define I2C_CR_I2C_ARB_EN_UMSK (~(((1U<<I2C_CR_I2C_ARB_EN_LEN)-1)<<I2C_CR_I2C_ARB_EN_POS))
#define I2C_CR_I2C_FER_EN I2C_CR_I2C_FER_EN
#define I2C_CR_I2C_FER_EN_POS (29U)
#define I2C_CR_I2C_FER_EN_LEN (1U)
#define I2C_CR_I2C_FER_EN_MSK (((1U<<I2C_CR_I2C_FER_EN_LEN)-1)<<I2C_CR_I2C_FER_EN_POS)
#define I2C_CR_I2C_FER_EN_UMSK (~(((1U<<I2C_CR_I2C_FER_EN_LEN)-1)<<I2C_CR_I2C_FER_EN_POS))
/* 0x8 : i2c_sub_addr */
#define I2C_SUB_ADDR_OFFSET (0x8)
#define I2C_CR_I2C_SUB_ADDR_B0 I2C_CR_I2C_SUB_ADDR_B0
#define I2C_CR_I2C_SUB_ADDR_B0_POS (0U)
#define I2C_CR_I2C_SUB_ADDR_B0_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B0_MSK (((1U<<I2C_CR_I2C_SUB_ADDR_B0_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B0_POS)
#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U<<I2C_CR_I2C_SUB_ADDR_B0_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B0_POS))
#define I2C_CR_I2C_SUB_ADDR_B1 I2C_CR_I2C_SUB_ADDR_B1
#define I2C_CR_I2C_SUB_ADDR_B1_POS (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B1_MSK (((1U<<I2C_CR_I2C_SUB_ADDR_B1_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B1_POS)
#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U<<I2C_CR_I2C_SUB_ADDR_B1_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B1_POS))
#define I2C_CR_I2C_SUB_ADDR_B2 I2C_CR_I2C_SUB_ADDR_B2
#define I2C_CR_I2C_SUB_ADDR_B2_POS (16U)
#define I2C_CR_I2C_SUB_ADDR_B2_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B2_MSK (((1U<<I2C_CR_I2C_SUB_ADDR_B2_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B2_POS)
#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U<<I2C_CR_I2C_SUB_ADDR_B2_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B2_POS))
#define I2C_CR_I2C_SUB_ADDR_B3 I2C_CR_I2C_SUB_ADDR_B3
#define I2C_CR_I2C_SUB_ADDR_B3_POS (24U)
#define I2C_CR_I2C_SUB_ADDR_B3_LEN (8U)
#define I2C_CR_I2C_SUB_ADDR_B3_MSK (((1U<<I2C_CR_I2C_SUB_ADDR_B3_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B3_POS)
#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U<<I2C_CR_I2C_SUB_ADDR_B3_LEN)-1)<<I2C_CR_I2C_SUB_ADDR_B3_POS))
/* 0xC : i2c_bus_busy */
#define I2C_BUS_BUSY_OFFSET (0xC)
#define I2C_STS_I2C_BUS_BUSY I2C_STS_I2C_BUS_BUSY
#define I2C_STS_I2C_BUS_BUSY_POS (0U)
#define I2C_STS_I2C_BUS_BUSY_LEN (1U)
#define I2C_STS_I2C_BUS_BUSY_MSK (((1U<<I2C_STS_I2C_BUS_BUSY_LEN)-1)<<I2C_STS_I2C_BUS_BUSY_POS)
#define I2C_STS_I2C_BUS_BUSY_UMSK (~(((1U<<I2C_STS_I2C_BUS_BUSY_LEN)-1)<<I2C_STS_I2C_BUS_BUSY_POS))
#define I2C_CR_I2C_BUS_BUSY_CLR I2C_CR_I2C_BUS_BUSY_CLR
#define I2C_CR_I2C_BUS_BUSY_CLR_POS (1U)
#define I2C_CR_I2C_BUS_BUSY_CLR_LEN (1U)
#define I2C_CR_I2C_BUS_BUSY_CLR_MSK (((1U<<I2C_CR_I2C_BUS_BUSY_CLR_LEN)-1)<<I2C_CR_I2C_BUS_BUSY_CLR_POS)
#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U<<I2C_CR_I2C_BUS_BUSY_CLR_LEN)-1)<<I2C_CR_I2C_BUS_BUSY_CLR_POS))
/* 0x10 : i2c_prd_start */
#define I2C_PRD_START_OFFSET (0x10)
#define I2C_CR_I2C_PRD_S_PH_0 I2C_CR_I2C_PRD_S_PH_0
#define I2C_CR_I2C_PRD_S_PH_0_POS (0U)
#define I2C_CR_I2C_PRD_S_PH_0_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_0_MSK (((1U<<I2C_CR_I2C_PRD_S_PH_0_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_0_POS)
#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U<<I2C_CR_I2C_PRD_S_PH_0_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_0_POS))
#define I2C_CR_I2C_PRD_S_PH_1 I2C_CR_I2C_PRD_S_PH_1
#define I2C_CR_I2C_PRD_S_PH_1_POS (8U)
#define I2C_CR_I2C_PRD_S_PH_1_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_1_MSK (((1U<<I2C_CR_I2C_PRD_S_PH_1_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_1_POS)
#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U<<I2C_CR_I2C_PRD_S_PH_1_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_1_POS))
#define I2C_CR_I2C_PRD_S_PH_2 I2C_CR_I2C_PRD_S_PH_2
#define I2C_CR_I2C_PRD_S_PH_2_POS (16U)
#define I2C_CR_I2C_PRD_S_PH_2_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_2_MSK (((1U<<I2C_CR_I2C_PRD_S_PH_2_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_2_POS)
#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U<<I2C_CR_I2C_PRD_S_PH_2_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_2_POS))
#define I2C_CR_I2C_PRD_S_PH_3 I2C_CR_I2C_PRD_S_PH_3
#define I2C_CR_I2C_PRD_S_PH_3_POS (24U)
#define I2C_CR_I2C_PRD_S_PH_3_LEN (8U)
#define I2C_CR_I2C_PRD_S_PH_3_MSK (((1U<<I2C_CR_I2C_PRD_S_PH_3_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_3_POS)
#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U<<I2C_CR_I2C_PRD_S_PH_3_LEN)-1)<<I2C_CR_I2C_PRD_S_PH_3_POS))
/* 0x14 : i2c_prd_stop */
#define I2C_PRD_STOP_OFFSET (0x14)
#define I2C_CR_I2C_PRD_P_PH_0 I2C_CR_I2C_PRD_P_PH_0
#define I2C_CR_I2C_PRD_P_PH_0_POS (0U)
#define I2C_CR_I2C_PRD_P_PH_0_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_0_MSK (((1U<<I2C_CR_I2C_PRD_P_PH_0_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_0_POS)
#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U<<I2C_CR_I2C_PRD_P_PH_0_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_0_POS))
#define I2C_CR_I2C_PRD_P_PH_1 I2C_CR_I2C_PRD_P_PH_1
#define I2C_CR_I2C_PRD_P_PH_1_POS (8U)
#define I2C_CR_I2C_PRD_P_PH_1_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_1_MSK (((1U<<I2C_CR_I2C_PRD_P_PH_1_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_1_POS)
#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U<<I2C_CR_I2C_PRD_P_PH_1_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_1_POS))
#define I2C_CR_I2C_PRD_P_PH_2 I2C_CR_I2C_PRD_P_PH_2
#define I2C_CR_I2C_PRD_P_PH_2_POS (16U)
#define I2C_CR_I2C_PRD_P_PH_2_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_2_MSK (((1U<<I2C_CR_I2C_PRD_P_PH_2_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_2_POS)
#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U<<I2C_CR_I2C_PRD_P_PH_2_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_2_POS))
#define I2C_CR_I2C_PRD_P_PH_3 I2C_CR_I2C_PRD_P_PH_3
#define I2C_CR_I2C_PRD_P_PH_3_POS (24U)
#define I2C_CR_I2C_PRD_P_PH_3_LEN (8U)
#define I2C_CR_I2C_PRD_P_PH_3_MSK (((1U<<I2C_CR_I2C_PRD_P_PH_3_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_3_POS)
#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U<<I2C_CR_I2C_PRD_P_PH_3_LEN)-1)<<I2C_CR_I2C_PRD_P_PH_3_POS))
/* 0x18 : i2c_prd_data */
#define I2C_PRD_DATA_OFFSET (0x18)
#define I2C_CR_I2C_PRD_D_PH_0 I2C_CR_I2C_PRD_D_PH_0
#define I2C_CR_I2C_PRD_D_PH_0_POS (0U)
#define I2C_CR_I2C_PRD_D_PH_0_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_0_MSK (((1U<<I2C_CR_I2C_PRD_D_PH_0_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_0_POS)
#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U<<I2C_CR_I2C_PRD_D_PH_0_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_0_POS))
#define I2C_CR_I2C_PRD_D_PH_1 I2C_CR_I2C_PRD_D_PH_1
#define I2C_CR_I2C_PRD_D_PH_1_POS (8U)
#define I2C_CR_I2C_PRD_D_PH_1_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_1_MSK (((1U<<I2C_CR_I2C_PRD_D_PH_1_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_1_POS)
#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U<<I2C_CR_I2C_PRD_D_PH_1_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_1_POS))
#define I2C_CR_I2C_PRD_D_PH_2 I2C_CR_I2C_PRD_D_PH_2
#define I2C_CR_I2C_PRD_D_PH_2_POS (16U)
#define I2C_CR_I2C_PRD_D_PH_2_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_2_MSK (((1U<<I2C_CR_I2C_PRD_D_PH_2_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_2_POS)
#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U<<I2C_CR_I2C_PRD_D_PH_2_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_2_POS))
#define I2C_CR_I2C_PRD_D_PH_3 I2C_CR_I2C_PRD_D_PH_3
#define I2C_CR_I2C_PRD_D_PH_3_POS (24U)
#define I2C_CR_I2C_PRD_D_PH_3_LEN (8U)
#define I2C_CR_I2C_PRD_D_PH_3_MSK (((1U<<I2C_CR_I2C_PRD_D_PH_3_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_3_POS)
#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U<<I2C_CR_I2C_PRD_D_PH_3_LEN)-1)<<I2C_CR_I2C_PRD_D_PH_3_POS))
/* 0x80 : i2c_fifo_config_0 */
#define I2C_FIFO_CONFIG_0_OFFSET (0x80)
#define I2C_DMA_TX_EN I2C_DMA_TX_EN
#define I2C_DMA_TX_EN_POS (0U)
#define I2C_DMA_TX_EN_LEN (1U)
#define I2C_DMA_TX_EN_MSK (((1U<<I2C_DMA_TX_EN_LEN)-1)<<I2C_DMA_TX_EN_POS)
#define I2C_DMA_TX_EN_UMSK (~(((1U<<I2C_DMA_TX_EN_LEN)-1)<<I2C_DMA_TX_EN_POS))
#define I2C_DMA_RX_EN I2C_DMA_RX_EN
#define I2C_DMA_RX_EN_POS (1U)
#define I2C_DMA_RX_EN_LEN (1U)
#define I2C_DMA_RX_EN_MSK (((1U<<I2C_DMA_RX_EN_LEN)-1)<<I2C_DMA_RX_EN_POS)
#define I2C_DMA_RX_EN_UMSK (~(((1U<<I2C_DMA_RX_EN_LEN)-1)<<I2C_DMA_RX_EN_POS))
#define I2C_TX_FIFO_CLR I2C_TX_FIFO_CLR
#define I2C_TX_FIFO_CLR_POS (2U)
#define I2C_TX_FIFO_CLR_LEN (1U)
#define I2C_TX_FIFO_CLR_MSK (((1U<<I2C_TX_FIFO_CLR_LEN)-1)<<I2C_TX_FIFO_CLR_POS)
#define I2C_TX_FIFO_CLR_UMSK (~(((1U<<I2C_TX_FIFO_CLR_LEN)-1)<<I2C_TX_FIFO_CLR_POS))
#define I2C_RX_FIFO_CLR I2C_RX_FIFO_CLR
#define I2C_RX_FIFO_CLR_POS (3U)
#define I2C_RX_FIFO_CLR_LEN (1U)
#define I2C_RX_FIFO_CLR_MSK (((1U<<I2C_RX_FIFO_CLR_LEN)-1)<<I2C_RX_FIFO_CLR_POS)
#define I2C_RX_FIFO_CLR_UMSK (~(((1U<<I2C_RX_FIFO_CLR_LEN)-1)<<I2C_RX_FIFO_CLR_POS))
#define I2C_TX_FIFO_OVERFLOW I2C_TX_FIFO_OVERFLOW
#define I2C_TX_FIFO_OVERFLOW_POS (4U)
#define I2C_TX_FIFO_OVERFLOW_LEN (1U)
#define I2C_TX_FIFO_OVERFLOW_MSK (((1U<<I2C_TX_FIFO_OVERFLOW_LEN)-1)<<I2C_TX_FIFO_OVERFLOW_POS)
#define I2C_TX_FIFO_OVERFLOW_UMSK (~(((1U<<I2C_TX_FIFO_OVERFLOW_LEN)-1)<<I2C_TX_FIFO_OVERFLOW_POS))
#define I2C_TX_FIFO_UNDERFLOW I2C_TX_FIFO_UNDERFLOW
#define I2C_TX_FIFO_UNDERFLOW_POS (5U)
#define I2C_TX_FIFO_UNDERFLOW_LEN (1U)
#define I2C_TX_FIFO_UNDERFLOW_MSK (((1U<<I2C_TX_FIFO_UNDERFLOW_LEN)-1)<<I2C_TX_FIFO_UNDERFLOW_POS)
#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U<<I2C_TX_FIFO_UNDERFLOW_LEN)-1)<<I2C_TX_FIFO_UNDERFLOW_POS))
#define I2C_RX_FIFO_OVERFLOW I2C_RX_FIFO_OVERFLOW
#define I2C_RX_FIFO_OVERFLOW_POS (6U)
#define I2C_RX_FIFO_OVERFLOW_LEN (1U)
#define I2C_RX_FIFO_OVERFLOW_MSK (((1U<<I2C_RX_FIFO_OVERFLOW_LEN)-1)<<I2C_RX_FIFO_OVERFLOW_POS)
#define I2C_RX_FIFO_OVERFLOW_UMSK (~(((1U<<I2C_RX_FIFO_OVERFLOW_LEN)-1)<<I2C_RX_FIFO_OVERFLOW_POS))
#define I2C_RX_FIFO_UNDERFLOW I2C_RX_FIFO_UNDERFLOW
#define I2C_RX_FIFO_UNDERFLOW_POS (7U)
#define I2C_RX_FIFO_UNDERFLOW_LEN (1U)
#define I2C_RX_FIFO_UNDERFLOW_MSK (((1U<<I2C_RX_FIFO_UNDERFLOW_LEN)-1)<<I2C_RX_FIFO_UNDERFLOW_POS)
#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U<<I2C_RX_FIFO_UNDERFLOW_LEN)-1)<<I2C_RX_FIFO_UNDERFLOW_POS))
/* 0x84 : i2c_fifo_config_1 */
#define I2C_FIFO_CONFIG_1_OFFSET (0x84)
#define I2C_TX_FIFO_CNT I2C_TX_FIFO_CNT
#define I2C_TX_FIFO_CNT_POS (0U)
#define I2C_TX_FIFO_CNT_LEN (2U)
#define I2C_TX_FIFO_CNT_MSK (((1U<<I2C_TX_FIFO_CNT_LEN)-1)<<I2C_TX_FIFO_CNT_POS)
#define I2C_TX_FIFO_CNT_UMSK (~(((1U<<I2C_TX_FIFO_CNT_LEN)-1)<<I2C_TX_FIFO_CNT_POS))
#define I2C_RX_FIFO_CNT I2C_RX_FIFO_CNT
#define I2C_RX_FIFO_CNT_POS (8U)
#define I2C_RX_FIFO_CNT_LEN (2U)
#define I2C_RX_FIFO_CNT_MSK (((1U<<I2C_RX_FIFO_CNT_LEN)-1)<<I2C_RX_FIFO_CNT_POS)
#define I2C_RX_FIFO_CNT_UMSK (~(((1U<<I2C_RX_FIFO_CNT_LEN)-1)<<I2C_RX_FIFO_CNT_POS))
#define I2C_TX_FIFO_TH I2C_TX_FIFO_TH
#define I2C_TX_FIFO_TH_POS (16U)
#define I2C_TX_FIFO_TH_LEN (1U)
#define I2C_TX_FIFO_TH_MSK (((1U<<I2C_TX_FIFO_TH_LEN)-1)<<I2C_TX_FIFO_TH_POS)
#define I2C_TX_FIFO_TH_UMSK (~(((1U<<I2C_TX_FIFO_TH_LEN)-1)<<I2C_TX_FIFO_TH_POS))
#define I2C_RX_FIFO_TH I2C_RX_FIFO_TH
#define I2C_RX_FIFO_TH_POS (24U)
#define I2C_RX_FIFO_TH_LEN (1U)
#define I2C_RX_FIFO_TH_MSK (((1U<<I2C_RX_FIFO_TH_LEN)-1)<<I2C_RX_FIFO_TH_POS)
#define I2C_RX_FIFO_TH_UMSK (~(((1U<<I2C_RX_FIFO_TH_LEN)-1)<<I2C_RX_FIFO_TH_POS))
/* 0x88 : i2c_fifo_wdata */
#define I2C_FIFO_WDATA_OFFSET (0x88)
#define I2C_FIFO_WDATA I2C_FIFO_WDATA
#define I2C_FIFO_WDATA_POS (0U)
#define I2C_FIFO_WDATA_LEN (32U)
#define I2C_FIFO_WDATA_MSK (((1U<<I2C_FIFO_WDATA_LEN)-1)<<I2C_FIFO_WDATA_POS)
#define I2C_FIFO_WDATA_UMSK (~(((1U<<I2C_FIFO_WDATA_LEN)-1)<<I2C_FIFO_WDATA_POS))
/* 0x8C : i2c_fifo_rdata */
#define I2C_FIFO_RDATA_OFFSET (0x8C)
#define I2C_FIFO_RDATA I2C_FIFO_RDATA
#define I2C_FIFO_RDATA_POS (0U)
#define I2C_FIFO_RDATA_LEN (32U)
#define I2C_FIFO_RDATA_MSK (((1U<<I2C_FIFO_RDATA_LEN)-1)<<I2C_FIFO_RDATA_POS)
#define I2C_FIFO_RDATA_UMSK (~(((1U<<I2C_FIFO_RDATA_LEN)-1)<<I2C_FIFO_RDATA_POS))
struct i2c_reg {
/* 0x0 : i2c_config */
union {
struct {
uint32_t cr_i2c_m_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_i2c_pkt_dir : 1; /* [ 1], r/w, 0x1 */
uint32_t cr_i2c_deg_en : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_i2c_scl_sync_en : 1; /* [ 3], r/w, 0x1 */
uint32_t cr_i2c_sub_addr_en : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5], r/w, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t cr_i2c_slv_addr : 7; /* [14: 8], r/w, 0x0 */
uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
uint32_t cr_i2c_pkt_len : 8; /* [23:16], r/w, 0x0 */
uint32_t reserved_24_27 : 4; /* [27:24], rsvd, 0x0 */
uint32_t cr_i2c_deg_cnt : 4; /* [31:28], r/w, 0x0 */
}BF;
uint32_t WORD;
} i2c_config;
/* 0x4 : i2c_int_sts */
union {
struct {
uint32_t i2c_end_int : 1; /* [ 0], r, 0x0 */
uint32_t i2c_txf_int : 1; /* [ 1], r, 0x0 */
uint32_t i2c_rxf_int : 1; /* [ 2], r, 0x0 */
uint32_t i2c_nak_int : 1; /* [ 3], r, 0x0 */
uint32_t i2c_arb_int : 1; /* [ 4], r, 0x0 */
uint32_t i2c_fer_int : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t cr_i2c_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_i2c_txf_mask : 1; /* [ 9], r/w, 0x1 */
uint32_t cr_i2c_rxf_mask : 1; /* [ 10], r/w, 0x1 */
uint32_t cr_i2c_nak_mask : 1; /* [ 11], r/w, 0x1 */
uint32_t cr_i2c_arb_mask : 1; /* [ 12], r/w, 0x1 */
uint32_t cr_i2c_fer_mask : 1; /* [ 13], r/w, 0x1 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t cr_i2c_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t cr_i2c_nak_clr : 1; /* [ 19], w1c, 0x0 */
uint32_t cr_i2c_arb_clr : 1; /* [ 20], w1c, 0x0 */
uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
uint32_t cr_i2c_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t cr_i2c_txf_en : 1; /* [ 25], r/w, 0x1 */
uint32_t cr_i2c_rxf_en : 1; /* [ 26], r/w, 0x1 */
uint32_t cr_i2c_nak_en : 1; /* [ 27], r/w, 0x1 */
uint32_t cr_i2c_arb_en : 1; /* [ 28], r/w, 0x1 */
uint32_t cr_i2c_fer_en : 1; /* [ 29], r/w, 0x1 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
}BF;
uint32_t WORD;
} i2c_int_sts;
/* 0x8 : i2c_sub_addr */
union {
struct {
uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16], r/w, 0x0 */
uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24], r/w, 0x0 */
}BF;
uint32_t WORD;
} i2c_sub_addr;
/* 0xC : i2c_bus_busy */
union {
struct {
uint32_t sts_i2c_bus_busy : 1; /* [ 0], r, 0x0 */
uint32_t cr_i2c_bus_busy_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
}BF;
uint32_t WORD;
} i2c_bus_busy;
/* 0x10 : i2c_prd_start */
union {
struct {
uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24], r/w, 0xf */
}BF;
uint32_t WORD;
} i2c_prd_start;
/* 0x14 : i2c_prd_stop */
union {
struct {
uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24], r/w, 0xf */
}BF;
uint32_t WORD;
} i2c_prd_stop;
/* 0x18 : i2c_prd_data */
union {
struct {
uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24], r/w, 0xf */
}BF;
uint32_t WORD;
} i2c_prd_data;
/* 0x1c reserved */
uint8_t RESERVED0x1c[100];
/* 0x80 : i2c_fifo_config_0 */
union {
struct {
uint32_t i2c_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t i2c_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} i2c_fifo_config_0;
/* 0x84 : i2c_fifo_config_1 */
union {
struct {
uint32_t tx_fifo_cnt : 2; /* [ 1: 0], r, 0x2 */
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
uint32_t rx_fifo_cnt : 2; /* [ 9: 8], r, 0x0 */
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
uint32_t tx_fifo_th : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t rx_fifo_th : 1; /* [ 24], r/w, 0x0 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
}BF;
uint32_t WORD;
} i2c_fifo_config_1;
/* 0x88 : i2c_fifo_wdata */
union {
struct {
uint32_t i2c_fifo_wdata : 32; /* [31: 0], w, x */
}BF;
uint32_t WORD;
} i2c_fifo_wdata;
/* 0x8C : i2c_fifo_rdata */
union {
struct {
uint32_t i2c_fifo_rdata : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} i2c_fifo_rdata;
};
typedef volatile struct i2c_reg i2c_reg_t;
#endif /* __I2C_REG_H__ */

633
drivers/bl602_driver/regs/ir_reg.h Normal file
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@ -0,0 +1,633 @@
/**
******************************************************************************
* @file ir_reg.h
* @version V1.2
* @date 2019-10-21
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __IR_REG_H__
#define __IR_REG_H__
#include "bl602.h"
/* 0x0 : irtx_config */
#define IRTX_CONFIG_OFFSET (0x0)
#define IR_CR_IRTX_EN IR_CR_IRTX_EN
#define IR_CR_IRTX_EN_POS (0U)
#define IR_CR_IRTX_EN_LEN (1U)
#define IR_CR_IRTX_EN_MSK (((1U<<IR_CR_IRTX_EN_LEN)-1)<<IR_CR_IRTX_EN_POS)
#define IR_CR_IRTX_EN_UMSK (~(((1U<<IR_CR_IRTX_EN_LEN)-1)<<IR_CR_IRTX_EN_POS))
#define IR_CR_IRTX_OUT_INV IR_CR_IRTX_OUT_INV
#define IR_CR_IRTX_OUT_INV_POS (1U)
#define IR_CR_IRTX_OUT_INV_LEN (1U)
#define IR_CR_IRTX_OUT_INV_MSK (((1U<<IR_CR_IRTX_OUT_INV_LEN)-1)<<IR_CR_IRTX_OUT_INV_POS)
#define IR_CR_IRTX_OUT_INV_UMSK (~(((1U<<IR_CR_IRTX_OUT_INV_LEN)-1)<<IR_CR_IRTX_OUT_INV_POS))
#define IR_CR_IRTX_MOD_EN IR_CR_IRTX_MOD_EN
#define IR_CR_IRTX_MOD_EN_POS (2U)
#define IR_CR_IRTX_MOD_EN_LEN (1U)
#define IR_CR_IRTX_MOD_EN_MSK (((1U<<IR_CR_IRTX_MOD_EN_LEN)-1)<<IR_CR_IRTX_MOD_EN_POS)
#define IR_CR_IRTX_MOD_EN_UMSK (~(((1U<<IR_CR_IRTX_MOD_EN_LEN)-1)<<IR_CR_IRTX_MOD_EN_POS))
#define IR_CR_IRTX_SWM_EN IR_CR_IRTX_SWM_EN
#define IR_CR_IRTX_SWM_EN_POS (3U)
#define IR_CR_IRTX_SWM_EN_LEN (1U)
#define IR_CR_IRTX_SWM_EN_MSK (((1U<<IR_CR_IRTX_SWM_EN_LEN)-1)<<IR_CR_IRTX_SWM_EN_POS)
#define IR_CR_IRTX_SWM_EN_UMSK (~(((1U<<IR_CR_IRTX_SWM_EN_LEN)-1)<<IR_CR_IRTX_SWM_EN_POS))
#define IR_CR_IRTX_DATA_EN IR_CR_IRTX_DATA_EN
#define IR_CR_IRTX_DATA_EN_POS (4U)
#define IR_CR_IRTX_DATA_EN_LEN (1U)
#define IR_CR_IRTX_DATA_EN_MSK (((1U<<IR_CR_IRTX_DATA_EN_LEN)-1)<<IR_CR_IRTX_DATA_EN_POS)
#define IR_CR_IRTX_DATA_EN_UMSK (~(((1U<<IR_CR_IRTX_DATA_EN_LEN)-1)<<IR_CR_IRTX_DATA_EN_POS))
#define IR_CR_IRTX_LOGIC0_HL_INV IR_CR_IRTX_LOGIC0_HL_INV
#define IR_CR_IRTX_LOGIC0_HL_INV_POS (5U)
#define IR_CR_IRTX_LOGIC0_HL_INV_LEN (1U)
#define IR_CR_IRTX_LOGIC0_HL_INV_MSK (((1U<<IR_CR_IRTX_LOGIC0_HL_INV_LEN)-1)<<IR_CR_IRTX_LOGIC0_HL_INV_POS)
#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U<<IR_CR_IRTX_LOGIC0_HL_INV_LEN)-1)<<IR_CR_IRTX_LOGIC0_HL_INV_POS))
#define IR_CR_IRTX_LOGIC1_HL_INV IR_CR_IRTX_LOGIC1_HL_INV
#define IR_CR_IRTX_LOGIC1_HL_INV_POS (6U)
#define IR_CR_IRTX_LOGIC1_HL_INV_LEN (1U)
#define IR_CR_IRTX_LOGIC1_HL_INV_MSK (((1U<<IR_CR_IRTX_LOGIC1_HL_INV_LEN)-1)<<IR_CR_IRTX_LOGIC1_HL_INV_POS)
#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U<<IR_CR_IRTX_LOGIC1_HL_INV_LEN)-1)<<IR_CR_IRTX_LOGIC1_HL_INV_POS))
#define IR_CR_IRTX_HEAD_EN IR_CR_IRTX_HEAD_EN
#define IR_CR_IRTX_HEAD_EN_POS (8U)
#define IR_CR_IRTX_HEAD_EN_LEN (1U)
#define IR_CR_IRTX_HEAD_EN_MSK (((1U<<IR_CR_IRTX_HEAD_EN_LEN)-1)<<IR_CR_IRTX_HEAD_EN_POS)
#define IR_CR_IRTX_HEAD_EN_UMSK (~(((1U<<IR_CR_IRTX_HEAD_EN_LEN)-1)<<IR_CR_IRTX_HEAD_EN_POS))
#define IR_CR_IRTX_HEAD_HL_INV IR_CR_IRTX_HEAD_HL_INV
#define IR_CR_IRTX_HEAD_HL_INV_POS (9U)
#define IR_CR_IRTX_HEAD_HL_INV_LEN (1U)
#define IR_CR_IRTX_HEAD_HL_INV_MSK (((1U<<IR_CR_IRTX_HEAD_HL_INV_LEN)-1)<<IR_CR_IRTX_HEAD_HL_INV_POS)
#define IR_CR_IRTX_HEAD_HL_INV_UMSK (~(((1U<<IR_CR_IRTX_HEAD_HL_INV_LEN)-1)<<IR_CR_IRTX_HEAD_HL_INV_POS))
#define IR_CR_IRTX_TAIL_EN IR_CR_IRTX_TAIL_EN
#define IR_CR_IRTX_TAIL_EN_POS (10U)
#define IR_CR_IRTX_TAIL_EN_LEN (1U)
#define IR_CR_IRTX_TAIL_EN_MSK (((1U<<IR_CR_IRTX_TAIL_EN_LEN)-1)<<IR_CR_IRTX_TAIL_EN_POS)
#define IR_CR_IRTX_TAIL_EN_UMSK (~(((1U<<IR_CR_IRTX_TAIL_EN_LEN)-1)<<IR_CR_IRTX_TAIL_EN_POS))
#define IR_CR_IRTX_TAIL_HL_INV IR_CR_IRTX_TAIL_HL_INV
#define IR_CR_IRTX_TAIL_HL_INV_POS (11U)
#define IR_CR_IRTX_TAIL_HL_INV_LEN (1U)
#define IR_CR_IRTX_TAIL_HL_INV_MSK (((1U<<IR_CR_IRTX_TAIL_HL_INV_LEN)-1)<<IR_CR_IRTX_TAIL_HL_INV_POS)
#define IR_CR_IRTX_TAIL_HL_INV_UMSK (~(((1U<<IR_CR_IRTX_TAIL_HL_INV_LEN)-1)<<IR_CR_IRTX_TAIL_HL_INV_POS))
#define IR_CR_IRTX_DATA_NUM IR_CR_IRTX_DATA_NUM
#define IR_CR_IRTX_DATA_NUM_POS (12U)
#define IR_CR_IRTX_DATA_NUM_LEN (6U)
#define IR_CR_IRTX_DATA_NUM_MSK (((1U<<IR_CR_IRTX_DATA_NUM_LEN)-1)<<IR_CR_IRTX_DATA_NUM_POS)
#define IR_CR_IRTX_DATA_NUM_UMSK (~(((1U<<IR_CR_IRTX_DATA_NUM_LEN)-1)<<IR_CR_IRTX_DATA_NUM_POS))
/* 0x4 : irtx_int_sts */
#define IRTX_INT_STS_OFFSET (0x4)
#define IRTX_END_INT IRTX_END_INT
#define IRTX_END_INT_POS (0U)
#define IRTX_END_INT_LEN (1U)
#define IRTX_END_INT_MSK (((1U<<IRTX_END_INT_LEN)-1)<<IRTX_END_INT_POS)
#define IRTX_END_INT_UMSK (~(((1U<<IRTX_END_INT_LEN)-1)<<IRTX_END_INT_POS))
#define IR_CR_IRTX_END_MASK IR_CR_IRTX_END_MASK
#define IR_CR_IRTX_END_MASK_POS (8U)
#define IR_CR_IRTX_END_MASK_LEN (1U)
#define IR_CR_IRTX_END_MASK_MSK (((1U<<IR_CR_IRTX_END_MASK_LEN)-1)<<IR_CR_IRTX_END_MASK_POS)
#define IR_CR_IRTX_END_MASK_UMSK (~(((1U<<IR_CR_IRTX_END_MASK_LEN)-1)<<IR_CR_IRTX_END_MASK_POS))
#define IR_CR_IRTX_END_CLR IR_CR_IRTX_END_CLR
#define IR_CR_IRTX_END_CLR_POS (16U)
#define IR_CR_IRTX_END_CLR_LEN (1U)
#define IR_CR_IRTX_END_CLR_MSK (((1U<<IR_CR_IRTX_END_CLR_LEN)-1)<<IR_CR_IRTX_END_CLR_POS)
#define IR_CR_IRTX_END_CLR_UMSK (~(((1U<<IR_CR_IRTX_END_CLR_LEN)-1)<<IR_CR_IRTX_END_CLR_POS))
#define IR_CR_IRTX_END_EN IR_CR_IRTX_END_EN
#define IR_CR_IRTX_END_EN_POS (24U)
#define IR_CR_IRTX_END_EN_LEN (1U)
#define IR_CR_IRTX_END_EN_MSK (((1U<<IR_CR_IRTX_END_EN_LEN)-1)<<IR_CR_IRTX_END_EN_POS)
#define IR_CR_IRTX_END_EN_UMSK (~(((1U<<IR_CR_IRTX_END_EN_LEN)-1)<<IR_CR_IRTX_END_EN_POS))
/* 0x8 : irtx_data_word0 */
#define IRTX_DATA_WORD0_OFFSET (0x8)
#define IR_CR_IRTX_DATA_WORD0 IR_CR_IRTX_DATA_WORD0
#define IR_CR_IRTX_DATA_WORD0_POS (0U)
#define IR_CR_IRTX_DATA_WORD0_LEN (32U)
#define IR_CR_IRTX_DATA_WORD0_MSK (((1U<<IR_CR_IRTX_DATA_WORD0_LEN)-1)<<IR_CR_IRTX_DATA_WORD0_POS)
#define IR_CR_IRTX_DATA_WORD0_UMSK (~(((1U<<IR_CR_IRTX_DATA_WORD0_LEN)-1)<<IR_CR_IRTX_DATA_WORD0_POS))
/* 0xC : irtx_data_word1 */
#define IRTX_DATA_WORD1_OFFSET (0xC)
#define IR_CR_IRTX_DATA_WORD1 IR_CR_IRTX_DATA_WORD1
#define IR_CR_IRTX_DATA_WORD1_POS (0U)
#define IR_CR_IRTX_DATA_WORD1_LEN (32U)
#define IR_CR_IRTX_DATA_WORD1_MSK (((1U<<IR_CR_IRTX_DATA_WORD1_LEN)-1)<<IR_CR_IRTX_DATA_WORD1_POS)
#define IR_CR_IRTX_DATA_WORD1_UMSK (~(((1U<<IR_CR_IRTX_DATA_WORD1_LEN)-1)<<IR_CR_IRTX_DATA_WORD1_POS))
/* 0x10 : irtx_pulse_width */
#define IRTX_PULSE_WIDTH_OFFSET (0x10)
#define IR_CR_IRTX_PW_UNIT IR_CR_IRTX_PW_UNIT
#define IR_CR_IRTX_PW_UNIT_POS (0U)
#define IR_CR_IRTX_PW_UNIT_LEN (12U)
#define IR_CR_IRTX_PW_UNIT_MSK (((1U<<IR_CR_IRTX_PW_UNIT_LEN)-1)<<IR_CR_IRTX_PW_UNIT_POS)
#define IR_CR_IRTX_PW_UNIT_UMSK (~(((1U<<IR_CR_IRTX_PW_UNIT_LEN)-1)<<IR_CR_IRTX_PW_UNIT_POS))
#define IR_CR_IRTX_MOD_PH0_W IR_CR_IRTX_MOD_PH0_W
#define IR_CR_IRTX_MOD_PH0_W_POS (16U)
#define IR_CR_IRTX_MOD_PH0_W_LEN (8U)
#define IR_CR_IRTX_MOD_PH0_W_MSK (((1U<<IR_CR_IRTX_MOD_PH0_W_LEN)-1)<<IR_CR_IRTX_MOD_PH0_W_POS)
#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U<<IR_CR_IRTX_MOD_PH0_W_LEN)-1)<<IR_CR_IRTX_MOD_PH0_W_POS))
#define IR_CR_IRTX_MOD_PH1_W IR_CR_IRTX_MOD_PH1_W
#define IR_CR_IRTX_MOD_PH1_W_POS (24U)
#define IR_CR_IRTX_MOD_PH1_W_LEN (8U)
#define IR_CR_IRTX_MOD_PH1_W_MSK (((1U<<IR_CR_IRTX_MOD_PH1_W_LEN)-1)<<IR_CR_IRTX_MOD_PH1_W_POS)
#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U<<IR_CR_IRTX_MOD_PH1_W_LEN)-1)<<IR_CR_IRTX_MOD_PH1_W_POS))
/* 0x14 : irtx_pw */
#define IRTX_PW_OFFSET (0x14)
#define IR_CR_IRTX_LOGIC0_PH0_W IR_CR_IRTX_LOGIC0_PH0_W
#define IR_CR_IRTX_LOGIC0_PH0_W_POS (0U)
#define IR_CR_IRTX_LOGIC0_PH0_W_LEN (4U)
#define IR_CR_IRTX_LOGIC0_PH0_W_MSK (((1U<<IR_CR_IRTX_LOGIC0_PH0_W_LEN)-1)<<IR_CR_IRTX_LOGIC0_PH0_W_POS)
#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U<<IR_CR_IRTX_LOGIC0_PH0_W_LEN)-1)<<IR_CR_IRTX_LOGIC0_PH0_W_POS))
#define IR_CR_IRTX_LOGIC0_PH1_W IR_CR_IRTX_LOGIC0_PH1_W
#define IR_CR_IRTX_LOGIC0_PH1_W_POS (4U)
#define IR_CR_IRTX_LOGIC0_PH1_W_LEN (4U)
#define IR_CR_IRTX_LOGIC0_PH1_W_MSK (((1U<<IR_CR_IRTX_LOGIC0_PH1_W_LEN)-1)<<IR_CR_IRTX_LOGIC0_PH1_W_POS)
#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U<<IR_CR_IRTX_LOGIC0_PH1_W_LEN)-1)<<IR_CR_IRTX_LOGIC0_PH1_W_POS))
#define IR_CR_IRTX_LOGIC1_PH0_W IR_CR_IRTX_LOGIC1_PH0_W
#define IR_CR_IRTX_LOGIC1_PH0_W_POS (8U)
#define IR_CR_IRTX_LOGIC1_PH0_W_LEN (4U)
#define IR_CR_IRTX_LOGIC1_PH0_W_MSK (((1U<<IR_CR_IRTX_LOGIC1_PH0_W_LEN)-1)<<IR_CR_IRTX_LOGIC1_PH0_W_POS)
#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U<<IR_CR_IRTX_LOGIC1_PH0_W_LEN)-1)<<IR_CR_IRTX_LOGIC1_PH0_W_POS))
#define IR_CR_IRTX_LOGIC1_PH1_W IR_CR_IRTX_LOGIC1_PH1_W
#define IR_CR_IRTX_LOGIC1_PH1_W_POS (12U)
#define IR_CR_IRTX_LOGIC1_PH1_W_LEN (4U)
#define IR_CR_IRTX_LOGIC1_PH1_W_MSK (((1U<<IR_CR_IRTX_LOGIC1_PH1_W_LEN)-1)<<IR_CR_IRTX_LOGIC1_PH1_W_POS)
#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U<<IR_CR_IRTX_LOGIC1_PH1_W_LEN)-1)<<IR_CR_IRTX_LOGIC1_PH1_W_POS))
#define IR_CR_IRTX_HEAD_PH0_W IR_CR_IRTX_HEAD_PH0_W
#define IR_CR_IRTX_HEAD_PH0_W_POS (16U)
#define IR_CR_IRTX_HEAD_PH0_W_LEN (4U)
#define IR_CR_IRTX_HEAD_PH0_W_MSK (((1U<<IR_CR_IRTX_HEAD_PH0_W_LEN)-1)<<IR_CR_IRTX_HEAD_PH0_W_POS)
#define IR_CR_IRTX_HEAD_PH0_W_UMSK (~(((1U<<IR_CR_IRTX_HEAD_PH0_W_LEN)-1)<<IR_CR_IRTX_HEAD_PH0_W_POS))
#define IR_CR_IRTX_HEAD_PH1_W IR_CR_IRTX_HEAD_PH1_W
#define IR_CR_IRTX_HEAD_PH1_W_POS (20U)
#define IR_CR_IRTX_HEAD_PH1_W_LEN (4U)
#define IR_CR_IRTX_HEAD_PH1_W_MSK (((1U<<IR_CR_IRTX_HEAD_PH1_W_LEN)-1)<<IR_CR_IRTX_HEAD_PH1_W_POS)
#define IR_CR_IRTX_HEAD_PH1_W_UMSK (~(((1U<<IR_CR_IRTX_HEAD_PH1_W_LEN)-1)<<IR_CR_IRTX_HEAD_PH1_W_POS))
#define IR_CR_IRTX_TAIL_PH0_W IR_CR_IRTX_TAIL_PH0_W
#define IR_CR_IRTX_TAIL_PH0_W_POS (24U)
#define IR_CR_IRTX_TAIL_PH0_W_LEN (4U)
#define IR_CR_IRTX_TAIL_PH0_W_MSK (((1U<<IR_CR_IRTX_TAIL_PH0_W_LEN)-1)<<IR_CR_IRTX_TAIL_PH0_W_POS)
#define IR_CR_IRTX_TAIL_PH0_W_UMSK (~(((1U<<IR_CR_IRTX_TAIL_PH0_W_LEN)-1)<<IR_CR_IRTX_TAIL_PH0_W_POS))
#define IR_CR_IRTX_TAIL_PH1_W IR_CR_IRTX_TAIL_PH1_W
#define IR_CR_IRTX_TAIL_PH1_W_POS (28U)
#define IR_CR_IRTX_TAIL_PH1_W_LEN (4U)
#define IR_CR_IRTX_TAIL_PH1_W_MSK (((1U<<IR_CR_IRTX_TAIL_PH1_W_LEN)-1)<<IR_CR_IRTX_TAIL_PH1_W_POS)
#define IR_CR_IRTX_TAIL_PH1_W_UMSK (~(((1U<<IR_CR_IRTX_TAIL_PH1_W_LEN)-1)<<IR_CR_IRTX_TAIL_PH1_W_POS))
/* 0x40 : irtx_swm_pw_0 */
#define IRTX_SWM_PW_0_OFFSET (0x40)
#define IR_CR_IRTX_SWM_PW_0 IR_CR_IRTX_SWM_PW_0
#define IR_CR_IRTX_SWM_PW_0_POS (0U)
#define IR_CR_IRTX_SWM_PW_0_LEN (32U)
#define IR_CR_IRTX_SWM_PW_0_MSK (((1U<<IR_CR_IRTX_SWM_PW_0_LEN)-1)<<IR_CR_IRTX_SWM_PW_0_POS)
#define IR_CR_IRTX_SWM_PW_0_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_0_LEN)-1)<<IR_CR_IRTX_SWM_PW_0_POS))
/* 0x44 : irtx_swm_pw_1 */
#define IRTX_SWM_PW_1_OFFSET (0x44)
#define IR_CR_IRTX_SWM_PW_1 IR_CR_IRTX_SWM_PW_1
#define IR_CR_IRTX_SWM_PW_1_POS (0U)
#define IR_CR_IRTX_SWM_PW_1_LEN (32U)
#define IR_CR_IRTX_SWM_PW_1_MSK (((1U<<IR_CR_IRTX_SWM_PW_1_LEN)-1)<<IR_CR_IRTX_SWM_PW_1_POS)
#define IR_CR_IRTX_SWM_PW_1_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_1_LEN)-1)<<IR_CR_IRTX_SWM_PW_1_POS))
/* 0x48 : irtx_swm_pw_2 */
#define IRTX_SWM_PW_2_OFFSET (0x48)
#define IR_CR_IRTX_SWM_PW_2 IR_CR_IRTX_SWM_PW_2
#define IR_CR_IRTX_SWM_PW_2_POS (0U)
#define IR_CR_IRTX_SWM_PW_2_LEN (32U)
#define IR_CR_IRTX_SWM_PW_2_MSK (((1U<<IR_CR_IRTX_SWM_PW_2_LEN)-1)<<IR_CR_IRTX_SWM_PW_2_POS)
#define IR_CR_IRTX_SWM_PW_2_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_2_LEN)-1)<<IR_CR_IRTX_SWM_PW_2_POS))
/* 0x4C : irtx_swm_pw_3 */
#define IRTX_SWM_PW_3_OFFSET (0x4C)
#define IR_CR_IRTX_SWM_PW_3 IR_CR_IRTX_SWM_PW_3
#define IR_CR_IRTX_SWM_PW_3_POS (0U)
#define IR_CR_IRTX_SWM_PW_3_LEN (32U)
#define IR_CR_IRTX_SWM_PW_3_MSK (((1U<<IR_CR_IRTX_SWM_PW_3_LEN)-1)<<IR_CR_IRTX_SWM_PW_3_POS)
#define IR_CR_IRTX_SWM_PW_3_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_3_LEN)-1)<<IR_CR_IRTX_SWM_PW_3_POS))
/* 0x50 : irtx_swm_pw_4 */
#define IRTX_SWM_PW_4_OFFSET (0x50)
#define IR_CR_IRTX_SWM_PW_4 IR_CR_IRTX_SWM_PW_4
#define IR_CR_IRTX_SWM_PW_4_POS (0U)
#define IR_CR_IRTX_SWM_PW_4_LEN (32U)
#define IR_CR_IRTX_SWM_PW_4_MSK (((1U<<IR_CR_IRTX_SWM_PW_4_LEN)-1)<<IR_CR_IRTX_SWM_PW_4_POS)
#define IR_CR_IRTX_SWM_PW_4_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_4_LEN)-1)<<IR_CR_IRTX_SWM_PW_4_POS))
/* 0x54 : irtx_swm_pw_5 */
#define IRTX_SWM_PW_5_OFFSET (0x54)
#define IR_CR_IRTX_SWM_PW_5 IR_CR_IRTX_SWM_PW_5
#define IR_CR_IRTX_SWM_PW_5_POS (0U)
#define IR_CR_IRTX_SWM_PW_5_LEN (32U)
#define IR_CR_IRTX_SWM_PW_5_MSK (((1U<<IR_CR_IRTX_SWM_PW_5_LEN)-1)<<IR_CR_IRTX_SWM_PW_5_POS)
#define IR_CR_IRTX_SWM_PW_5_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_5_LEN)-1)<<IR_CR_IRTX_SWM_PW_5_POS))
/* 0x58 : irtx_swm_pw_6 */
#define IRTX_SWM_PW_6_OFFSET (0x58)
#define IR_CR_IRTX_SWM_PW_6 IR_CR_IRTX_SWM_PW_6
#define IR_CR_IRTX_SWM_PW_6_POS (0U)
#define IR_CR_IRTX_SWM_PW_6_LEN (32U)
#define IR_CR_IRTX_SWM_PW_6_MSK (((1U<<IR_CR_IRTX_SWM_PW_6_LEN)-1)<<IR_CR_IRTX_SWM_PW_6_POS)
#define IR_CR_IRTX_SWM_PW_6_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_6_LEN)-1)<<IR_CR_IRTX_SWM_PW_6_POS))
/* 0x5C : irtx_swm_pw_7 */
#define IRTX_SWM_PW_7_OFFSET (0x5C)
#define IR_CR_IRTX_SWM_PW_7 IR_CR_IRTX_SWM_PW_7
#define IR_CR_IRTX_SWM_PW_7_POS (0U)
#define IR_CR_IRTX_SWM_PW_7_LEN (32U)
#define IR_CR_IRTX_SWM_PW_7_MSK (((1U<<IR_CR_IRTX_SWM_PW_7_LEN)-1)<<IR_CR_IRTX_SWM_PW_7_POS)
#define IR_CR_IRTX_SWM_PW_7_UMSK (~(((1U<<IR_CR_IRTX_SWM_PW_7_LEN)-1)<<IR_CR_IRTX_SWM_PW_7_POS))
/* 0x80 : irrx_config */
#define IRRX_CONFIG_OFFSET (0x80)
#define IR_CR_IRRX_EN IR_CR_IRRX_EN
#define IR_CR_IRRX_EN_POS (0U)
#define IR_CR_IRRX_EN_LEN (1U)
#define IR_CR_IRRX_EN_MSK (((1U<<IR_CR_IRRX_EN_LEN)-1)<<IR_CR_IRRX_EN_POS)
#define IR_CR_IRRX_EN_UMSK (~(((1U<<IR_CR_IRRX_EN_LEN)-1)<<IR_CR_IRRX_EN_POS))
#define IR_CR_IRRX_IN_INV IR_CR_IRRX_IN_INV
#define IR_CR_IRRX_IN_INV_POS (1U)
#define IR_CR_IRRX_IN_INV_LEN (1U)
#define IR_CR_IRRX_IN_INV_MSK (((1U<<IR_CR_IRRX_IN_INV_LEN)-1)<<IR_CR_IRRX_IN_INV_POS)
#define IR_CR_IRRX_IN_INV_UMSK (~(((1U<<IR_CR_IRRX_IN_INV_LEN)-1)<<IR_CR_IRRX_IN_INV_POS))
#define IR_CR_IRRX_MODE IR_CR_IRRX_MODE
#define IR_CR_IRRX_MODE_POS (2U)
#define IR_CR_IRRX_MODE_LEN (2U)
#define IR_CR_IRRX_MODE_MSK (((1U<<IR_CR_IRRX_MODE_LEN)-1)<<IR_CR_IRRX_MODE_POS)
#define IR_CR_IRRX_MODE_UMSK (~(((1U<<IR_CR_IRRX_MODE_LEN)-1)<<IR_CR_IRRX_MODE_POS))
#define IR_CR_IRRX_DEG_EN IR_CR_IRRX_DEG_EN
#define IR_CR_IRRX_DEG_EN_POS (4U)
#define IR_CR_IRRX_DEG_EN_LEN (1U)
#define IR_CR_IRRX_DEG_EN_MSK (((1U<<IR_CR_IRRX_DEG_EN_LEN)-1)<<IR_CR_IRRX_DEG_EN_POS)
#define IR_CR_IRRX_DEG_EN_UMSK (~(((1U<<IR_CR_IRRX_DEG_EN_LEN)-1)<<IR_CR_IRRX_DEG_EN_POS))
#define IR_CR_IRRX_DEG_CNT IR_CR_IRRX_DEG_CNT
#define IR_CR_IRRX_DEG_CNT_POS (8U)
#define IR_CR_IRRX_DEG_CNT_LEN (4U)
#define IR_CR_IRRX_DEG_CNT_MSK (((1U<<IR_CR_IRRX_DEG_CNT_LEN)-1)<<IR_CR_IRRX_DEG_CNT_POS)
#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U<<IR_CR_IRRX_DEG_CNT_LEN)-1)<<IR_CR_IRRX_DEG_CNT_POS))
/* 0x84 : irrx_int_sts */
#define IRRX_INT_STS_OFFSET (0x84)
#define IRRX_END_INT IRRX_END_INT
#define IRRX_END_INT_POS (0U)
#define IRRX_END_INT_LEN (1U)
#define IRRX_END_INT_MSK (((1U<<IRRX_END_INT_LEN)-1)<<IRRX_END_INT_POS)
#define IRRX_END_INT_UMSK (~(((1U<<IRRX_END_INT_LEN)-1)<<IRRX_END_INT_POS))
#define IR_CR_IRRX_END_MASK IR_CR_IRRX_END_MASK
#define IR_CR_IRRX_END_MASK_POS (8U)
#define IR_CR_IRRX_END_MASK_LEN (1U)
#define IR_CR_IRRX_END_MASK_MSK (((1U<<IR_CR_IRRX_END_MASK_LEN)-1)<<IR_CR_IRRX_END_MASK_POS)
#define IR_CR_IRRX_END_MASK_UMSK (~(((1U<<IR_CR_IRRX_END_MASK_LEN)-1)<<IR_CR_IRRX_END_MASK_POS))
#define IR_CR_IRRX_END_CLR IR_CR_IRRX_END_CLR
#define IR_CR_IRRX_END_CLR_POS (16U)
#define IR_CR_IRRX_END_CLR_LEN (1U)
#define IR_CR_IRRX_END_CLR_MSK (((1U<<IR_CR_IRRX_END_CLR_LEN)-1)<<IR_CR_IRRX_END_CLR_POS)
#define IR_CR_IRRX_END_CLR_UMSK (~(((1U<<IR_CR_IRRX_END_CLR_LEN)-1)<<IR_CR_IRRX_END_CLR_POS))
#define IR_CR_IRRX_END_EN IR_CR_IRRX_END_EN
#define IR_CR_IRRX_END_EN_POS (24U)
#define IR_CR_IRRX_END_EN_LEN (1U)
#define IR_CR_IRRX_END_EN_MSK (((1U<<IR_CR_IRRX_END_EN_LEN)-1)<<IR_CR_IRRX_END_EN_POS)
#define IR_CR_IRRX_END_EN_UMSK (~(((1U<<IR_CR_IRRX_END_EN_LEN)-1)<<IR_CR_IRRX_END_EN_POS))
/* 0x88 : irrx_pw_config */
#define IRRX_PW_CONFIG_OFFSET (0x88)
#define IR_CR_IRRX_DATA_TH IR_CR_IRRX_DATA_TH
#define IR_CR_IRRX_DATA_TH_POS (0U)
#define IR_CR_IRRX_DATA_TH_LEN (16U)
#define IR_CR_IRRX_DATA_TH_MSK (((1U<<IR_CR_IRRX_DATA_TH_LEN)-1)<<IR_CR_IRRX_DATA_TH_POS)
#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U<<IR_CR_IRRX_DATA_TH_LEN)-1)<<IR_CR_IRRX_DATA_TH_POS))
#define IR_CR_IRRX_END_TH IR_CR_IRRX_END_TH
#define IR_CR_IRRX_END_TH_POS (16U)
#define IR_CR_IRRX_END_TH_LEN (16U)
#define IR_CR_IRRX_END_TH_MSK (((1U<<IR_CR_IRRX_END_TH_LEN)-1)<<IR_CR_IRRX_END_TH_POS)
#define IR_CR_IRRX_END_TH_UMSK (~(((1U<<IR_CR_IRRX_END_TH_LEN)-1)<<IR_CR_IRRX_END_TH_POS))
/* 0x90 : irrx_data_count */
#define IRRX_DATA_COUNT_OFFSET (0x90)
#define IR_STS_IRRX_DATA_CNT IR_STS_IRRX_DATA_CNT
#define IR_STS_IRRX_DATA_CNT_POS (0U)
#define IR_STS_IRRX_DATA_CNT_LEN (7U)
#define IR_STS_IRRX_DATA_CNT_MSK (((1U<<IR_STS_IRRX_DATA_CNT_LEN)-1)<<IR_STS_IRRX_DATA_CNT_POS)
#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U<<IR_STS_IRRX_DATA_CNT_LEN)-1)<<IR_STS_IRRX_DATA_CNT_POS))
/* 0x94 : irrx_data_word0 */
#define IRRX_DATA_WORD0_OFFSET (0x94)
#define IR_STS_IRRX_DATA_WORD0 IR_STS_IRRX_DATA_WORD0
#define IR_STS_IRRX_DATA_WORD0_POS (0U)
#define IR_STS_IRRX_DATA_WORD0_LEN (32U)
#define IR_STS_IRRX_DATA_WORD0_MSK (((1U<<IR_STS_IRRX_DATA_WORD0_LEN)-1)<<IR_STS_IRRX_DATA_WORD0_POS)
#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U<<IR_STS_IRRX_DATA_WORD0_LEN)-1)<<IR_STS_IRRX_DATA_WORD0_POS))
/* 0x98 : irrx_data_word1 */
#define IRRX_DATA_WORD1_OFFSET (0x98)
#define IR_STS_IRRX_DATA_WORD1 IR_STS_IRRX_DATA_WORD1
#define IR_STS_IRRX_DATA_WORD1_POS (0U)
#define IR_STS_IRRX_DATA_WORD1_LEN (32U)
#define IR_STS_IRRX_DATA_WORD1_MSK (((1U<<IR_STS_IRRX_DATA_WORD1_LEN)-1)<<IR_STS_IRRX_DATA_WORD1_POS)
#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U<<IR_STS_IRRX_DATA_WORD1_LEN)-1)<<IR_STS_IRRX_DATA_WORD1_POS))
/* 0xC0 : irrx_swm_fifo_config_0 */
#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0)
#define IR_RX_FIFO_CLR IR_RX_FIFO_CLR
#define IR_RX_FIFO_CLR_POS (0U)
#define IR_RX_FIFO_CLR_LEN (1U)
#define IR_RX_FIFO_CLR_MSK (((1U<<IR_RX_FIFO_CLR_LEN)-1)<<IR_RX_FIFO_CLR_POS)
#define IR_RX_FIFO_CLR_UMSK (~(((1U<<IR_RX_FIFO_CLR_LEN)-1)<<IR_RX_FIFO_CLR_POS))
#define IR_RX_FIFO_OVERFLOW IR_RX_FIFO_OVERFLOW
#define IR_RX_FIFO_OVERFLOW_POS (2U)
#define IR_RX_FIFO_OVERFLOW_LEN (1U)
#define IR_RX_FIFO_OVERFLOW_MSK (((1U<<IR_RX_FIFO_OVERFLOW_LEN)-1)<<IR_RX_FIFO_OVERFLOW_POS)
#define IR_RX_FIFO_OVERFLOW_UMSK (~(((1U<<IR_RX_FIFO_OVERFLOW_LEN)-1)<<IR_RX_FIFO_OVERFLOW_POS))
#define IR_RX_FIFO_UNDERFLOW IR_RX_FIFO_UNDERFLOW
#define IR_RX_FIFO_UNDERFLOW_POS (3U)
#define IR_RX_FIFO_UNDERFLOW_LEN (1U)
#define IR_RX_FIFO_UNDERFLOW_MSK (((1U<<IR_RX_FIFO_UNDERFLOW_LEN)-1)<<IR_RX_FIFO_UNDERFLOW_POS)
#define IR_RX_FIFO_UNDERFLOW_UMSK (~(((1U<<IR_RX_FIFO_UNDERFLOW_LEN)-1)<<IR_RX_FIFO_UNDERFLOW_POS))
#define IR_RX_FIFO_CNT IR_RX_FIFO_CNT
#define IR_RX_FIFO_CNT_POS (4U)
#define IR_RX_FIFO_CNT_LEN (7U)
#define IR_RX_FIFO_CNT_MSK (((1U<<IR_RX_FIFO_CNT_LEN)-1)<<IR_RX_FIFO_CNT_POS)
#define IR_RX_FIFO_CNT_UMSK (~(((1U<<IR_RX_FIFO_CNT_LEN)-1)<<IR_RX_FIFO_CNT_POS))
/* 0xC4 : irrx_swm_fifo_rdata */
#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4)
#define IR_RX_FIFO_RDATA IR_RX_FIFO_RDATA
#define IR_RX_FIFO_RDATA_POS (0U)
#define IR_RX_FIFO_RDATA_LEN (16U)
#define IR_RX_FIFO_RDATA_MSK (((1U<<IR_RX_FIFO_RDATA_LEN)-1)<<IR_RX_FIFO_RDATA_POS)
#define IR_RX_FIFO_RDATA_UMSK (~(((1U<<IR_RX_FIFO_RDATA_LEN)-1)<<IR_RX_FIFO_RDATA_POS))
struct ir_reg {
/* 0x0 : irtx_config */
union {
struct {
uint32_t cr_irtx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_irtx_out_inv : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_irtx_mod_en : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_irtx_swm_en : 1; /* [ 3], r/w, 0x0 */
uint32_t cr_irtx_data_en : 1; /* [ 4], r/w, 0x1 */
uint32_t cr_irtx_logic0_hl_inv : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_irtx_logic1_hl_inv : 1; /* [ 6], r/w, 0x0 */
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t cr_irtx_head_en : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_irtx_head_hl_inv : 1; /* [ 9], r/w, 0x0 */
uint32_t cr_irtx_tail_en : 1; /* [ 10], r/w, 0x1 */
uint32_t cr_irtx_tail_hl_inv : 1; /* [ 11], r/w, 0x0 */
uint32_t cr_irtx_data_num : 6; /* [17:12], r/w, 0x1f */
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irtx_config;
/* 0x4 : irtx_int_sts */
union {
struct {
uint32_t irtx_end_int : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
uint32_t cr_irtx_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t cr_irtx_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t cr_irtx_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irtx_int_sts;
/* 0x8 : irtx_data_word0 */
union {
struct {
uint32_t cr_irtx_data_word0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_data_word0;
/* 0xC : irtx_data_word1 */
union {
struct {
uint32_t cr_irtx_data_word1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_data_word1;
/* 0x10 : irtx_pulse_width */
union {
struct {
uint32_t cr_irtx_pw_unit : 12; /* [11: 0], r/w, 0x464 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t cr_irtx_mod_ph0_w : 8; /* [23:16], r/w, 0x11 */
uint32_t cr_irtx_mod_ph1_w : 8; /* [31:24], r/w, 0x22 */
}BF;
uint32_t WORD;
} irtx_pulse_width;
/* 0x14 : irtx_pw */
union {
struct {
uint32_t cr_irtx_logic0_ph0_w : 4; /* [ 3: 0], r/w, 0x0 */
uint32_t cr_irtx_logic0_ph1_w : 4; /* [ 7: 4], r/w, 0x0 */
uint32_t cr_irtx_logic1_ph0_w : 4; /* [11: 8], r/w, 0x0 */
uint32_t cr_irtx_logic1_ph1_w : 4; /* [15:12], r/w, 0x2 */
uint32_t cr_irtx_head_ph0_w : 4; /* [19:16], r/w, 0xf */
uint32_t cr_irtx_head_ph1_w : 4; /* [23:20], r/w, 0x7 */
uint32_t cr_irtx_tail_ph0_w : 4; /* [27:24], r/w, 0x0 */
uint32_t cr_irtx_tail_ph1_w : 4; /* [31:28], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_pw;
/* 0x18 reserved */
uint8_t RESERVED0x18[40];
/* 0x40 : irtx_swm_pw_0 */
union {
struct {
uint32_t cr_irtx_swm_pw_0 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_0;
/* 0x44 : irtx_swm_pw_1 */
union {
struct {
uint32_t cr_irtx_swm_pw_1 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_1;
/* 0x48 : irtx_swm_pw_2 */
union {
struct {
uint32_t cr_irtx_swm_pw_2 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_2;
/* 0x4C : irtx_swm_pw_3 */
union {
struct {
uint32_t cr_irtx_swm_pw_3 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_3;
/* 0x50 : irtx_swm_pw_4 */
union {
struct {
uint32_t cr_irtx_swm_pw_4 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_4;
/* 0x54 : irtx_swm_pw_5 */
union {
struct {
uint32_t cr_irtx_swm_pw_5 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_5;
/* 0x58 : irtx_swm_pw_6 */
union {
struct {
uint32_t cr_irtx_swm_pw_6 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_6;
/* 0x5C : irtx_swm_pw_7 */
union {
struct {
uint32_t cr_irtx_swm_pw_7 : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} irtx_swm_pw_7;
/* 0x60 reserved */
uint8_t RESERVED0x60[32];
/* 0x80 : irrx_config */
union {
struct {
uint32_t cr_irrx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_irrx_in_inv : 1; /* [ 1], r/w, 0x1 */
uint32_t cr_irrx_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t cr_irrx_deg_en : 1; /* [ 4], r/w, 0x0 */
uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
uint32_t cr_irrx_deg_cnt : 4; /* [11: 8], r/w, 0x0 */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irrx_config;
/* 0x84 : irrx_int_sts */
union {
struct {
uint32_t irrx_end_int : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */
uint32_t cr_irrx_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
uint32_t cr_irrx_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */
uint32_t cr_irrx_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irrx_int_sts;
/* 0x88 : irrx_pw_config */
union {
struct {
uint32_t cr_irrx_data_th : 16; /* [15: 0], r/w, 0xd47 */
uint32_t cr_irrx_end_th : 16; /* [31:16], r/w, 0x2327 */
}BF;
uint32_t WORD;
} irrx_pw_config;
/* 0x8c reserved */
uint8_t RESERVED0x8c[4];
/* 0x90 : irrx_data_count */
union {
struct {
uint32_t sts_irrx_data_cnt : 7; /* [ 6: 0], r, 0x0 */
uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irrx_data_count;
/* 0x94 : irrx_data_word0 */
union {
struct {
uint32_t sts_irrx_data_word0 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} irrx_data_word0;
/* 0x98 : irrx_data_word1 */
union {
struct {
uint32_t sts_irrx_data_word1 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} irrx_data_word1;
/* 0x9c reserved */
uint8_t RESERVED0x9c[36];
/* 0xC0 : irrx_swm_fifo_config_0 */
union {
struct {
uint32_t rx_fifo_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 2], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 3], r, 0x0 */
uint32_t rx_fifo_cnt : 7; /* [10: 4], r, 0x0 */
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irrx_swm_fifo_config_0;
/* 0xC4 : irrx_swm_fifo_rdata */
union {
struct {
uint32_t rx_fifo_rdata : 16; /* [15: 0], r, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irrx_swm_fifo_rdata;
};
typedef volatile struct ir_reg ir_reg_t;
#endif /* __IR_REG_H__ */

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/**
******************************************************************************
* @file l1c_reg.h
* @version V1.2
* @date 2019-11-22
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __L1C_REG_H__
#define __L1C_REG_H__
#include "bl602.h"
/* 0x0 : l1c_config */
#define L1C_CONFIG_OFFSET (0x0)
#define L1C_CACHEABLE L1C_CACHEABLE
#define L1C_CACHEABLE_POS (0U)
#define L1C_CACHEABLE_LEN (1U)
#define L1C_CACHEABLE_MSK (((1U<<L1C_CACHEABLE_LEN)-1)<<L1C_CACHEABLE_POS)
#define L1C_CACHEABLE_UMSK (~(((1U<<L1C_CACHEABLE_LEN)-1)<<L1C_CACHEABLE_POS))
#define L1C_CNT_EN L1C_CNT_EN
#define L1C_CNT_EN_POS (1U)
#define L1C_CNT_EN_LEN (1U)
#define L1C_CNT_EN_MSK (((1U<<L1C_CNT_EN_LEN)-1)<<L1C_CNT_EN_POS)
#define L1C_CNT_EN_UMSK (~(((1U<<L1C_CNT_EN_LEN)-1)<<L1C_CNT_EN_POS))
#define L1C_INVALID_EN L1C_INVALID_EN
#define L1C_INVALID_EN_POS (2U)
#define L1C_INVALID_EN_LEN (1U)
#define L1C_INVALID_EN_MSK (((1U<<L1C_INVALID_EN_LEN)-1)<<L1C_INVALID_EN_POS)
#define L1C_INVALID_EN_UMSK (~(((1U<<L1C_INVALID_EN_LEN)-1)<<L1C_INVALID_EN_POS))
#define L1C_INVALID_DONE L1C_INVALID_DONE
#define L1C_INVALID_DONE_POS (3U)
#define L1C_INVALID_DONE_LEN (1U)
#define L1C_INVALID_DONE_MSK (((1U<<L1C_INVALID_DONE_LEN)-1)<<L1C_INVALID_DONE_POS)
#define L1C_INVALID_DONE_UMSK (~(((1U<<L1C_INVALID_DONE_LEN)-1)<<L1C_INVALID_DONE_POS))
#define L1C_WAY_DIS L1C_WAY_DIS
#define L1C_WAY_DIS_POS (8U)
#define L1C_WAY_DIS_LEN (4U)
#define L1C_WAY_DIS_MSK (((1U<<L1C_WAY_DIS_LEN)-1)<<L1C_WAY_DIS_POS)
#define L1C_WAY_DIS_UMSK (~(((1U<<L1C_WAY_DIS_LEN)-1)<<L1C_WAY_DIS_POS))
#define L1C_IROM_2T_ACCESS L1C_IROM_2T_ACCESS
#define L1C_IROM_2T_ACCESS_POS (12U)
#define L1C_IROM_2T_ACCESS_LEN (1U)
#define L1C_IROM_2T_ACCESS_MSK (((1U<<L1C_IROM_2T_ACCESS_LEN)-1)<<L1C_IROM_2T_ACCESS_POS)
#define L1C_IROM_2T_ACCESS_UMSK (~(((1U<<L1C_IROM_2T_ACCESS_LEN)-1)<<L1C_IROM_2T_ACCESS_POS))
#define L1C_BYPASS L1C_BYPASS
#define L1C_BYPASS_POS (14U)
#define L1C_BYPASS_LEN (1U)
#define L1C_BYPASS_MSK (((1U<<L1C_BYPASS_LEN)-1)<<L1C_BYPASS_POS)
#define L1C_BYPASS_UMSK (~(((1U<<L1C_BYPASS_LEN)-1)<<L1C_BYPASS_POS))
#define L1C_BMX_ERR_EN L1C_BMX_ERR_EN
#define L1C_BMX_ERR_EN_POS (15U)
#define L1C_BMX_ERR_EN_LEN (1U)
#define L1C_BMX_ERR_EN_MSK (((1U<<L1C_BMX_ERR_EN_LEN)-1)<<L1C_BMX_ERR_EN_POS)
#define L1C_BMX_ERR_EN_UMSK (~(((1U<<L1C_BMX_ERR_EN_LEN)-1)<<L1C_BMX_ERR_EN_POS))
#define L1C_BMX_ARB_MODE L1C_BMX_ARB_MODE
#define L1C_BMX_ARB_MODE_POS (16U)
#define L1C_BMX_ARB_MODE_LEN (2U)
#define L1C_BMX_ARB_MODE_MSK (((1U<<L1C_BMX_ARB_MODE_LEN)-1)<<L1C_BMX_ARB_MODE_POS)
#define L1C_BMX_ARB_MODE_UMSK (~(((1U<<L1C_BMX_ARB_MODE_LEN)-1)<<L1C_BMX_ARB_MODE_POS))
#define L1C_BMX_TIMEOUT_EN L1C_BMX_TIMEOUT_EN
#define L1C_BMX_TIMEOUT_EN_POS (20U)
#define L1C_BMX_TIMEOUT_EN_LEN (4U)
#define L1C_BMX_TIMEOUT_EN_MSK (((1U<<L1C_BMX_TIMEOUT_EN_LEN)-1)<<L1C_BMX_TIMEOUT_EN_POS)
#define L1C_BMX_TIMEOUT_EN_UMSK (~(((1U<<L1C_BMX_TIMEOUT_EN_LEN)-1)<<L1C_BMX_TIMEOUT_EN_POS))
#define L1C_BMX_BUSY_OPTION_DIS L1C_BMX_BUSY_OPTION_DIS
#define L1C_BMX_BUSY_OPTION_DIS_POS (24U)
#define L1C_BMX_BUSY_OPTION_DIS_LEN (1U)
#define L1C_BMX_BUSY_OPTION_DIS_MSK (((1U<<L1C_BMX_BUSY_OPTION_DIS_LEN)-1)<<L1C_BMX_BUSY_OPTION_DIS_POS)
#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U<<L1C_BMX_BUSY_OPTION_DIS_LEN)-1)<<L1C_BMX_BUSY_OPTION_DIS_POS))
#define L1C_EARLY_RESP_DIS L1C_EARLY_RESP_DIS
#define L1C_EARLY_RESP_DIS_POS (25U)
#define L1C_EARLY_RESP_DIS_LEN (1U)
#define L1C_EARLY_RESP_DIS_MSK (((1U<<L1C_EARLY_RESP_DIS_LEN)-1)<<L1C_EARLY_RESP_DIS_POS)
#define L1C_EARLY_RESP_DIS_UMSK (~(((1U<<L1C_EARLY_RESP_DIS_LEN)-1)<<L1C_EARLY_RESP_DIS_POS))
#define L1C_WRAP_DIS L1C_WRAP_DIS
#define L1C_WRAP_DIS_POS (26U)
#define L1C_WRAP_DIS_LEN (1U)
#define L1C_WRAP_DIS_MSK (((1U<<L1C_WRAP_DIS_LEN)-1)<<L1C_WRAP_DIS_POS)
#define L1C_WRAP_DIS_UMSK (~(((1U<<L1C_WRAP_DIS_LEN)-1)<<L1C_WRAP_DIS_POS))
/* 0x4 : hit_cnt_lsb */
#define L1C_HIT_CNT_LSB_OFFSET (0x4)
#define L1C_HIT_CNT_LSB L1C_HIT_CNT_LSB
#define L1C_HIT_CNT_LSB_POS (0U)
#define L1C_HIT_CNT_LSB_LEN (32U)
#define L1C_HIT_CNT_LSB_MSK (((1U<<L1C_HIT_CNT_LSB_LEN)-1)<<L1C_HIT_CNT_LSB_POS)
#define L1C_HIT_CNT_LSB_UMSK (~(((1U<<L1C_HIT_CNT_LSB_LEN)-1)<<L1C_HIT_CNT_LSB_POS))
/* 0x8 : hit_cnt_msb */
#define L1C_HIT_CNT_MSB_OFFSET (0x8)
#define L1C_HIT_CNT_MSB L1C_HIT_CNT_MSB
#define L1C_HIT_CNT_MSB_POS (0U)
#define L1C_HIT_CNT_MSB_LEN (32U)
#define L1C_HIT_CNT_MSB_MSK (((1U<<L1C_HIT_CNT_MSB_LEN)-1)<<L1C_HIT_CNT_MSB_POS)
#define L1C_HIT_CNT_MSB_UMSK (~(((1U<<L1C_HIT_CNT_MSB_LEN)-1)<<L1C_HIT_CNT_MSB_POS))
/* 0xC : miss_cnt */
#define L1C_MISS_CNT_OFFSET (0xC)
#define L1C_MISS_CNT L1C_MISS_CNT
#define L1C_MISS_CNT_POS (0U)
#define L1C_MISS_CNT_LEN (32U)
#define L1C_MISS_CNT_MSK (((1U<<L1C_MISS_CNT_LEN)-1)<<L1C_MISS_CNT_POS)
#define L1C_MISS_CNT_UMSK (~(((1U<<L1C_MISS_CNT_LEN)-1)<<L1C_MISS_CNT_POS))
/* 0x10 : l1c_range */
#define L1C_RANGE_OFFSET (0x10)
/* 0x200 : l1c_bmx_err_addr_en */
#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
#define L1C_BMX_ERR_ADDR_DIS L1C_BMX_ERR_ADDR_DIS
#define L1C_BMX_ERR_ADDR_DIS_POS (0U)
#define L1C_BMX_ERR_ADDR_DIS_LEN (1U)
#define L1C_BMX_ERR_ADDR_DIS_MSK (((1U<<L1C_BMX_ERR_ADDR_DIS_LEN)-1)<<L1C_BMX_ERR_ADDR_DIS_POS)
#define L1C_BMX_ERR_ADDR_DIS_UMSK (~(((1U<<L1C_BMX_ERR_ADDR_DIS_LEN)-1)<<L1C_BMX_ERR_ADDR_DIS_POS))
#define L1C_BMX_ERR_DEC L1C_BMX_ERR_DEC
#define L1C_BMX_ERR_DEC_POS (4U)
#define L1C_BMX_ERR_DEC_LEN (1U)
#define L1C_BMX_ERR_DEC_MSK (((1U<<L1C_BMX_ERR_DEC_LEN)-1)<<L1C_BMX_ERR_DEC_POS)
#define L1C_BMX_ERR_DEC_UMSK (~(((1U<<L1C_BMX_ERR_DEC_LEN)-1)<<L1C_BMX_ERR_DEC_POS))
#define L1C_BMX_ERR_TZ L1C_BMX_ERR_TZ
#define L1C_BMX_ERR_TZ_POS (5U)
#define L1C_BMX_ERR_TZ_LEN (1U)
#define L1C_BMX_ERR_TZ_MSK (((1U<<L1C_BMX_ERR_TZ_LEN)-1)<<L1C_BMX_ERR_TZ_POS)
#define L1C_BMX_ERR_TZ_UMSK (~(((1U<<L1C_BMX_ERR_TZ_LEN)-1)<<L1C_BMX_ERR_TZ_POS))
#define L1C_HSEL_OPTION L1C_HSEL_OPTION
#define L1C_HSEL_OPTION_POS (16U)
#define L1C_HSEL_OPTION_LEN (4U)
#define L1C_HSEL_OPTION_MSK (((1U<<L1C_HSEL_OPTION_LEN)-1)<<L1C_HSEL_OPTION_POS)
#define L1C_HSEL_OPTION_UMSK (~(((1U<<L1C_HSEL_OPTION_LEN)-1)<<L1C_HSEL_OPTION_POS))
/* 0x204 : l1c_bmx_err_addr */
#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
#define L1C_BMX_ERR_ADDR L1C_BMX_ERR_ADDR
#define L1C_BMX_ERR_ADDR_POS (0U)
#define L1C_BMX_ERR_ADDR_LEN (32U)
#define L1C_BMX_ERR_ADDR_MSK (((1U<<L1C_BMX_ERR_ADDR_LEN)-1)<<L1C_BMX_ERR_ADDR_POS)
#define L1C_BMX_ERR_ADDR_UMSK (~(((1U<<L1C_BMX_ERR_ADDR_LEN)-1)<<L1C_BMX_ERR_ADDR_POS))
/* 0x208 : irom1_misr_dataout_0 */
#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
#define L1C_IROM1_MISR_DATAOUT_0 L1C_IROM1_MISR_DATAOUT_0
#define L1C_IROM1_MISR_DATAOUT_0_POS (0U)
#define L1C_IROM1_MISR_DATAOUT_0_LEN (32U)
#define L1C_IROM1_MISR_DATAOUT_0_MSK (((1U<<L1C_IROM1_MISR_DATAOUT_0_LEN)-1)<<L1C_IROM1_MISR_DATAOUT_0_POS)
#define L1C_IROM1_MISR_DATAOUT_0_UMSK (~(((1U<<L1C_IROM1_MISR_DATAOUT_0_LEN)-1)<<L1C_IROM1_MISR_DATAOUT_0_POS))
/* 0x20C : irom1_misr_dataout_1 */
#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
/* 0x210 : cpu_clk_gate */
#define L1C_CPU_CLK_GATE_OFFSET (0x210)
#define L1C_FORCE_E21_CLOCK_ON_0 L1C_FORCE_E21_CLOCK_ON_0
#define L1C_FORCE_E21_CLOCK_ON_0_POS (0U)
#define L1C_FORCE_E21_CLOCK_ON_0_LEN (1U)
#define L1C_FORCE_E21_CLOCK_ON_0_MSK (((1U<<L1C_FORCE_E21_CLOCK_ON_0_LEN)-1)<<L1C_FORCE_E21_CLOCK_ON_0_POS)
#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U<<L1C_FORCE_E21_CLOCK_ON_0_LEN)-1)<<L1C_FORCE_E21_CLOCK_ON_0_POS))
#define L1C_FORCE_E21_CLOCK_ON_1 L1C_FORCE_E21_CLOCK_ON_1
#define L1C_FORCE_E21_CLOCK_ON_1_POS (1U)
#define L1C_FORCE_E21_CLOCK_ON_1_LEN (1U)
#define L1C_FORCE_E21_CLOCK_ON_1_MSK (((1U<<L1C_FORCE_E21_CLOCK_ON_1_LEN)-1)<<L1C_FORCE_E21_CLOCK_ON_1_POS)
#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U<<L1C_FORCE_E21_CLOCK_ON_1_LEN)-1)<<L1C_FORCE_E21_CLOCK_ON_1_POS))
#define L1C_FORCE_E21_CLOCK_ON_2 L1C_FORCE_E21_CLOCK_ON_2
#define L1C_FORCE_E21_CLOCK_ON_2_POS (2U)
#define L1C_FORCE_E21_CLOCK_ON_2_LEN (1U)
#define L1C_FORCE_E21_CLOCK_ON_2_MSK (((1U<<L1C_FORCE_E21_CLOCK_ON_2_LEN)-1)<<L1C_FORCE_E21_CLOCK_ON_2_POS)
#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U<<L1C_FORCE_E21_CLOCK_ON_2_LEN)-1)<<L1C_FORCE_E21_CLOCK_ON_2_POS))
struct l1c_reg {
/* 0x0 : l1c_config */
union {
struct {
uint32_t l1c_cacheable : 1; /* [ 0], r/w, 0x0 */
uint32_t l1c_cnt_en : 1; /* [ 1], r/w, 0x0 */
uint32_t l1c_invalid_en : 1; /* [ 2], r/w, 0x0 */
uint32_t l1c_invalid_done : 1; /* [ 3], r, 0x0 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t l1c_way_dis : 4; /* [11: 8], r/w, 0xf */
uint32_t irom_2t_access : 1; /* [ 12], r/w, 0x0 */
uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */
uint32_t l1c_bypass : 1; /* [ 14], r/w, 0x0 */
uint32_t l1c_bmx_err_en : 1; /* [ 15], r/w, 0x0 */
uint32_t l1c_bmx_arb_mode : 2; /* [17:16], r/w, 0x0 */
uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
uint32_t l1c_bmx_timeout_en : 4; /* [23:20], r/w, 0x0 */
uint32_t l1c_bmx_busy_option_dis : 1; /* [ 24], r/w, 0x0 */
uint32_t early_resp_dis : 1; /* [ 25], r/w, 0x1 */
uint32_t wrap_dis : 1; /* [ 26], r/w, 0x1 */
uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
}BF;
uint32_t WORD;
} l1c_config;
/* 0x4 : hit_cnt_lsb */
union {
struct {
uint32_t hit_cnt_lsb : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} hit_cnt_lsb;
/* 0x8 : hit_cnt_msb */
union {
struct {
uint32_t hit_cnt_msb : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} hit_cnt_msb;
/* 0xC : miss_cnt */
union {
struct {
uint32_t miss_cnt : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} miss_cnt;
/* 0x10 : l1c_range */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} l1c_range;
/* 0x14 reserved */
uint8_t RESERVED0x14[492];
/* 0x200 : l1c_bmx_err_addr_en */
union {
struct {
uint32_t l1c_bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
uint32_t l1c_bmx_err_dec : 1; /* [ 4], r, 0x0 */
uint32_t l1c_bmx_err_tz : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
uint32_t l1c_hsel_option : 4; /* [19:16], r/w, 0x0 */
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
}BF;
uint32_t WORD;
} l1c_bmx_err_addr_en;
/* 0x204 : l1c_bmx_err_addr */
union {
struct {
uint32_t l1c_bmx_err_addr : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} l1c_bmx_err_addr;
/* 0x208 : irom1_misr_dataout_0 */
union {
struct {
uint32_t irom1_misr_dataout_0 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} irom1_misr_dataout_0;
/* 0x20C : irom1_misr_dataout_1 */
union {
struct {
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
}BF;
uint32_t WORD;
} irom1_misr_dataout_1;
/* 0x210 : cpu_clk_gate */
union {
struct {
uint32_t force_e21_clock_on_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t force_e21_clock_on_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t force_e21_clock_on_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} cpu_clk_gate;
};
typedef volatile struct l1c_reg l1c_reg_t;
#endif /* __L1C_REG_H__ */

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/**
******************************************************************************
* @file pwm_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __PWM_REG_H__
#define __PWM_REG_H__
#include "bl602.h"
/* 0x0 : pwm_int_config */
#define PWM_INT_CONFIG_OFFSET (0x0)
#define PWM_INTERRUPT_STS PWM_INTERRUPT_STS
#define PWM_INTERRUPT_STS_POS (0U)
#define PWM_INTERRUPT_STS_LEN (6U)
#define PWM_INTERRUPT_STS_MSK (((1U<<PWM_INTERRUPT_STS_LEN)-1)<<PWM_INTERRUPT_STS_POS)
#define PWM_INTERRUPT_STS_UMSK (~(((1U<<PWM_INTERRUPT_STS_LEN)-1)<<PWM_INTERRUPT_STS_POS))
#define PWM_INT_CLEAR PWM_INT_CLEAR
#define PWM_INT_CLEAR_POS (8U)
#define PWM_INT_CLEAR_LEN (6U)
#define PWM_INT_CLEAR_MSK (((1U<<PWM_INT_CLEAR_LEN)-1)<<PWM_INT_CLEAR_POS)
#define PWM_INT_CLEAR_UMSK (~(((1U<<PWM_INT_CLEAR_LEN)-1)<<PWM_INT_CLEAR_POS))
/* 0x20 : pwm0_clkdiv */
#define PWM0_CLKDIV_OFFSET (0x20)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS))
/* 0x24 : pwm0_thre1 */
#define PWM0_THRE1_OFFSET (0x24)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS))
/* 0x28 : pwm0_thre2 */
#define PWM0_THRE2_OFFSET (0x28)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS))
/* 0x2C : pwm0_period */
#define PWM0_PERIOD_OFFSET (0x2C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS))
/* 0x30 : pwm0_config */
#define PWM0_CONFIG_OFFSET (0x30)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS))
/* 0x34 : pwm0_interrupt */
#define PWM0_INTERRUPT_OFFSET (0x34)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS))
/* 0x40 : pwm1_clkdiv */
#define PWM1_CLKDIV_OFFSET (0x40)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS))
/* 0x44 : pwm1_thre1 */
#define PWM1_THRE1_OFFSET (0x44)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS))
/* 0x48 : pwm1_thre2 */
#define PWM1_THRE2_OFFSET (0x48)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS))
/* 0x4C : pwm1_period */
#define PWM1_PERIOD_OFFSET (0x4C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS))
/* 0x50 : pwm1_config */
#define PWM1_CONFIG_OFFSET (0x50)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS))
/* 0x54 : pwm1_interrupt */
#define PWM1_INTERRUPT_OFFSET (0x54)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS))
/* 0x60 : pwm2_clkdiv */
#define PWM2_CLKDIV_OFFSET (0x60)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS))
/* 0x64 : pwm2_thre1 */
#define PWM2_THRE1_OFFSET (0x64)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS))
/* 0x68 : pwm2_thre2 */
#define PWM2_THRE2_OFFSET (0x68)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS))
/* 0x6C : pwm2_period */
#define PWM2_PERIOD_OFFSET (0x6C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS))
/* 0x70 : pwm2_config */
#define PWM2_CONFIG_OFFSET (0x70)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS))
/* 0x74 : pwm2_interrupt */
#define PWM2_INTERRUPT_OFFSET (0x74)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS))
/* 0x80 : pwm3_clkdiv */
#define PWM3_CLKDIV_OFFSET (0x80)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS))
/* 0x84 : pwm3_thre1 */
#define PWM3_THRE1_OFFSET (0x84)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS))
/* 0x88 : pwm3_thre2 */
#define PWM3_THRE2_OFFSET (0x88)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS))
/* 0x8C : pwm3_period */
#define PWM3_PERIOD_OFFSET (0x8C)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS))
/* 0x90 : pwm3_config */
#define PWM3_CONFIG_OFFSET (0x90)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS))
/* 0x94 : pwm3_interrupt */
#define PWM3_INTERRUPT_OFFSET (0x94)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS))
/* 0xA0 : pwm4_clkdiv */
#define PWM4_CLKDIV_OFFSET (0xA0)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS))
/* 0xA4 : pwm4_thre1 */
#define PWM4_THRE1_OFFSET (0xA4)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS))
/* 0xA8 : pwm4_thre2 */
#define PWM4_THRE2_OFFSET (0xA8)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS))
/* 0xAC : pwm4_period */
#define PWM4_PERIOD_OFFSET (0xAC)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS))
/* 0xB0 : pwm4_config */
#define PWM4_CONFIG_OFFSET (0xB0)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS))
/* 0xB4 : pwm4_interrupt */
#define PWM4_INTERRUPT_OFFSET (0xB4)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS))
struct pwm_reg {
/* 0x0 : pwm_int_config */
union {
struct {
uint32_t pwm_interrupt_sts : 6; /* [ 5: 0], r, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t pwm_int_clear : 6; /* [13: 8], w, 0x0 */
uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_int_config;
/* 0x4 reserved */
uint8_t RESERVED0x4[28];
/* 0x20 : pwm0_clkdiv */
union {
struct {
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm0_clkdiv;
/* 0x24 : pwm0_thre1 */
union {
struct {
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm0_thre1;
/* 0x28 : pwm0_thre2 */
union {
struct {
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm0_thre2;
/* 0x2C : pwm0_period */
union {
struct {
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm0_period;
/* 0x30 : pwm0_config */
union {
struct {
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm0_config;
/* 0x34 : pwm0_interrupt */
union {
struct {
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm0_interrupt;
/* 0x38 reserved */
uint8_t RESERVED0x38[8];
/* 0x40 : pwm1_clkdiv */
union {
struct {
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm1_clkdiv;
/* 0x44 : pwm1_thre1 */
union {
struct {
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm1_thre1;
/* 0x48 : pwm1_thre2 */
union {
struct {
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm1_thre2;
/* 0x4C : pwm1_period */
union {
struct {
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm1_period;
/* 0x50 : pwm1_config */
union {
struct {
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm1_config;
/* 0x54 : pwm1_interrupt */
union {
struct {
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm1_interrupt;
/* 0x58 reserved */
uint8_t RESERVED0x58[8];
/* 0x60 : pwm2_clkdiv */
union {
struct {
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm2_clkdiv;
/* 0x64 : pwm2_thre1 */
union {
struct {
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm2_thre1;
/* 0x68 : pwm2_thre2 */
union {
struct {
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm2_thre2;
/* 0x6C : pwm2_period */
union {
struct {
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm2_period;
/* 0x70 : pwm2_config */
union {
struct {
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm2_config;
/* 0x74 : pwm2_interrupt */
union {
struct {
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm2_interrupt;
/* 0x78 reserved */
uint8_t RESERVED0x78[8];
/* 0x80 : pwm3_clkdiv */
union {
struct {
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm3_clkdiv;
/* 0x84 : pwm3_thre1 */
union {
struct {
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm3_thre1;
/* 0x88 : pwm3_thre2 */
union {
struct {
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm3_thre2;
/* 0x8C : pwm3_period */
union {
struct {
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm3_period;
/* 0x90 : pwm3_config */
union {
struct {
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm3_config;
/* 0x94 : pwm3_interrupt */
union {
struct {
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm3_interrupt;
/* 0x98 reserved */
uint8_t RESERVED0x98[8];
/* 0xA0 : pwm4_clkdiv */
union {
struct {
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm4_clkdiv;
/* 0xA4 : pwm4_thre1 */
union {
struct {
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm4_thre1;
/* 0xA8 : pwm4_thre2 */
union {
struct {
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm4_thre2;
/* 0xAC : pwm4_period */
union {
struct {
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm4_period;
/* 0xB0 : pwm4_config */
union {
struct {
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm4_config;
/* 0xB4 : pwm4_interrupt */
union {
struct {
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm4_interrupt;
};
typedef volatile struct pwm_reg pwm_reg_t;
/*Following is reg patch*/
/* 0x0 : pwm_clkdiv */
#define PWM_CLKDIV_OFFSET (0x0)
#define PWM_CLK_DIV PWM_CLK_DIV
#define PWM_CLK_DIV_POS (0U)
#define PWM_CLK_DIV_LEN (16U)
#define PWM_CLK_DIV_MSK (((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS)
#define PWM_CLK_DIV_UMSK (~(((1U<<PWM_CLK_DIV_LEN)-1)<<PWM_CLK_DIV_POS))
/* 0x4 : pwm_thre1 */
#define PWM_THRE1_OFFSET (0x4)
#define PWM_THRE1 PWM_THRE1
#define PWM_THRE1_POS (0U)
#define PWM_THRE1_LEN (16U)
#define PWM_THRE1_MSK (((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS)
#define PWM_THRE1_UMSK (~(((1U<<PWM_THRE1_LEN)-1)<<PWM_THRE1_POS))
/* 0x8 : pwm_thre2 */
#define PWM_THRE2_OFFSET (0x8)
#define PWM_THRE2 PWM_THRE2
#define PWM_THRE2_POS (0U)
#define PWM_THRE2_LEN (16U)
#define PWM_THRE2_MSK (((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS)
#define PWM_THRE2_UMSK (~(((1U<<PWM_THRE2_LEN)-1)<<PWM_THRE2_POS))
/* 0xc : pwm_period */
#define PWM_PERIOD_OFFSET (0xc)
#define PWM_PERIOD PWM_PERIOD
#define PWM_PERIOD_POS (0U)
#define PWM_PERIOD_LEN (16U)
#define PWM_PERIOD_MSK (((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS)
#define PWM_PERIOD_UMSK (~(((1U<<PWM_PERIOD_LEN)-1)<<PWM_PERIOD_POS))
/* 0x10 : pwm_config */
#define PWM_CONFIG_OFFSET (0x10)
#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL
#define PWM_REG_CLK_SEL_POS (0U)
#define PWM_REG_CLK_SEL_LEN (2U)
#define PWM_REG_CLK_SEL_MSK (((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS)
#define PWM_REG_CLK_SEL_UMSK (~(((1U<<PWM_REG_CLK_SEL_LEN)-1)<<PWM_REG_CLK_SEL_POS))
#define PWM_OUT_INV PWM_OUT_INV
#define PWM_OUT_INV_POS (2U)
#define PWM_OUT_INV_LEN (1U)
#define PWM_OUT_INV_MSK (((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS)
#define PWM_OUT_INV_UMSK (~(((1U<<PWM_OUT_INV_LEN)-1)<<PWM_OUT_INV_POS))
#define PWM_STOP_MODE PWM_STOP_MODE
#define PWM_STOP_MODE_POS (3U)
#define PWM_STOP_MODE_LEN (1U)
#define PWM_STOP_MODE_MSK (((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS)
#define PWM_STOP_MODE_UMSK (~(((1U<<PWM_STOP_MODE_LEN)-1)<<PWM_STOP_MODE_POS))
#define PWM_SW_FORCE_VAL PWM_SW_FORCE_VAL
#define PWM_SW_FORCE_VAL_POS (4U)
#define PWM_SW_FORCE_VAL_LEN (1U)
#define PWM_SW_FORCE_VAL_MSK (((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS)
#define PWM_SW_FORCE_VAL_UMSK (~(((1U<<PWM_SW_FORCE_VAL_LEN)-1)<<PWM_SW_FORCE_VAL_POS))
#define PWM_SW_MODE PWM_SW_MODE
#define PWM_SW_MODE_POS (5U)
#define PWM_SW_MODE_LEN (1U)
#define PWM_SW_MODE_MSK (((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS)
#define PWM_SW_MODE_UMSK (~(((1U<<PWM_SW_MODE_LEN)-1)<<PWM_SW_MODE_POS))
#define PWM_STOP_EN PWM_STOP_EN
#define PWM_STOP_EN_POS (6U)
#define PWM_STOP_EN_LEN (1U)
#define PWM_STOP_EN_MSK (((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS)
#define PWM_STOP_EN_UMSK (~(((1U<<PWM_STOP_EN_LEN)-1)<<PWM_STOP_EN_POS))
#define PWM_STS_TOP PWM_STS_TOP
#define PWM_STS_TOP_POS (7U)
#define PWM_STS_TOP_LEN (1U)
#define PWM_STS_TOP_MSK (((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS)
#define PWM_STS_TOP_UMSK (~(((1U<<PWM_STS_TOP_LEN)-1)<<PWM_STS_TOP_POS))
/* 0x14 : pwm_interrupt */
#define PWM_INTERRUPT_OFFSET (0x14)
#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT
#define PWM_INT_PERIOD_CNT_POS (0U)
#define PWM_INT_PERIOD_CNT_LEN (16U)
#define PWM_INT_PERIOD_CNT_MSK (((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS)
#define PWM_INT_PERIOD_CNT_UMSK (~(((1U<<PWM_INT_PERIOD_CNT_LEN)-1)<<PWM_INT_PERIOD_CNT_POS))
#define PWM_INT_ENABLE PWM_INT_ENABLE
#define PWM_INT_ENABLE_POS (16U)
#define PWM_INT_ENABLE_LEN (1U)
#define PWM_INT_ENABLE_MSK (((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS)
#define PWM_INT_ENABLE_UMSK (~(((1U<<PWM_INT_ENABLE_LEN)-1)<<PWM_INT_ENABLE_POS))
struct pwm_channel_reg {
/* 0x0 : pwm_clkdiv */
union {
struct {
uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_clkdiv;
/* 0x4 : pwm_thre1 */
union {
struct {
uint32_t pwm_thre1 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_thre1;
/* 0x8 : pwm_thre2 */
union {
struct {
uint32_t pwm_thre2 : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_thre2;
/* 0xc : pwm_period */
union {
struct {
uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_period;
/* 0x10 : pwm_config */
union {
struct {
uint32_t reg_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t pwm_out_inv : 1; /* [ 2], r/w, 0x0 */
uint32_t pwm_stop_mode : 1; /* [ 3], r/w, 0x1 */
uint32_t pwm_sw_force_val : 1; /* [ 4], r/w, 0x0 */
uint32_t pwm_sw_mode : 1; /* [ 5], r/w, 0x0 */
uint32_t pwm_stop_en : 1; /* [ 6], r/w, 0x0 */
uint32_t pwm_sts_top : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_config;
/* 0x14 : pwm_interrupt */
union {
struct {
uint32_t pwm_int_period_cnt : 16; /* [15: 0], r/w, 0x0 */
uint32_t pwm_int_enable : 1; /* [ 16], r/w, 0x0 */
uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */
}BF;
uint32_t WORD;
} pwm_interrupt;
};
typedef volatile struct pwm_channel_reg pwm_channel_reg_t;
#define PWM_CHANNEL_OFFSET 0x20
#endif /* __PWM_REG_H__ */

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/**
******************************************************************************
* @file sec_dbg_reg.h
* @version V1.2
* @date 2019-11-04
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __SEC_DBG_REG_H__
#define __SEC_DBG_REG_H__
#include "bl602.h"
/* 0x0 : sd_chip_id_low */
#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0)
#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW
#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U)
#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U)
#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U<<SEC_DBG_SD_CHIP_ID_LOW_LEN)-1)<<SEC_DBG_SD_CHIP_ID_LOW_POS)
#define SEC_DBG_SD_CHIP_ID_LOW_UMSK (~(((1U<<SEC_DBG_SD_CHIP_ID_LOW_LEN)-1)<<SEC_DBG_SD_CHIP_ID_LOW_POS))
/* 0x4 : sd_chip_id_high */
#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4)
#define SEC_DBG_SD_CHIP_ID_HIGH SEC_DBG_SD_CHIP_ID_HIGH
#define SEC_DBG_SD_CHIP_ID_HIGH_POS (0U)
#define SEC_DBG_SD_CHIP_ID_HIGH_LEN (32U)
#define SEC_DBG_SD_CHIP_ID_HIGH_MSK (((1U<<SEC_DBG_SD_CHIP_ID_HIGH_LEN)-1)<<SEC_DBG_SD_CHIP_ID_HIGH_POS)
#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK (~(((1U<<SEC_DBG_SD_CHIP_ID_HIGH_LEN)-1)<<SEC_DBG_SD_CHIP_ID_HIGH_POS))
/* 0x8 : sd_wifi_mac_low */
#define SEC_DBG_SD_WIFI_MAC_LOW_OFFSET (0x8)
#define SEC_DBG_SD_WIFI_MAC_LOW SEC_DBG_SD_WIFI_MAC_LOW
#define SEC_DBG_SD_WIFI_MAC_LOW_POS (0U)
#define SEC_DBG_SD_WIFI_MAC_LOW_LEN (32U)
#define SEC_DBG_SD_WIFI_MAC_LOW_MSK (((1U<<SEC_DBG_SD_WIFI_MAC_LOW_LEN)-1)<<SEC_DBG_SD_WIFI_MAC_LOW_POS)
#define SEC_DBG_SD_WIFI_MAC_LOW_UMSK (~(((1U<<SEC_DBG_SD_WIFI_MAC_LOW_LEN)-1)<<SEC_DBG_SD_WIFI_MAC_LOW_POS))
/* 0xC : sd_wifi_mac_high */
#define SEC_DBG_SD_WIFI_MAC_HIGH_OFFSET (0xC)
#define SEC_DBG_SD_WIFI_MAC_HIGH SEC_DBG_SD_WIFI_MAC_HIGH
#define SEC_DBG_SD_WIFI_MAC_HIGH_POS (0U)
#define SEC_DBG_SD_WIFI_MAC_HIGH_LEN (32U)
#define SEC_DBG_SD_WIFI_MAC_HIGH_MSK (((1U<<SEC_DBG_SD_WIFI_MAC_HIGH_LEN)-1)<<SEC_DBG_SD_WIFI_MAC_HIGH_POS)
#define SEC_DBG_SD_WIFI_MAC_HIGH_UMSK (~(((1U<<SEC_DBG_SD_WIFI_MAC_HIGH_LEN)-1)<<SEC_DBG_SD_WIFI_MAC_HIGH_POS))
/* 0x10 : sd_dbg_pwd_low */
#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x10)
#define SEC_DBG_SD_DBG_PWD_LOW SEC_DBG_SD_DBG_PWD_LOW
#define SEC_DBG_SD_DBG_PWD_LOW_POS (0U)
#define SEC_DBG_SD_DBG_PWD_LOW_LEN (32U)
#define SEC_DBG_SD_DBG_PWD_LOW_MSK (((1U<<SEC_DBG_SD_DBG_PWD_LOW_LEN)-1)<<SEC_DBG_SD_DBG_PWD_LOW_POS)
#define SEC_DBG_SD_DBG_PWD_LOW_UMSK (~(((1U<<SEC_DBG_SD_DBG_PWD_LOW_LEN)-1)<<SEC_DBG_SD_DBG_PWD_LOW_POS))
/* 0x14 : sd_dbg_pwd_high */
#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0x14)
#define SEC_DBG_SD_DBG_PWD_HIGH SEC_DBG_SD_DBG_PWD_HIGH
#define SEC_DBG_SD_DBG_PWD_HIGH_POS (0U)
#define SEC_DBG_SD_DBG_PWD_HIGH_LEN (32U)
#define SEC_DBG_SD_DBG_PWD_HIGH_MSK (((1U<<SEC_DBG_SD_DBG_PWD_HIGH_LEN)-1)<<SEC_DBG_SD_DBG_PWD_HIGH_POS)
#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK (~(((1U<<SEC_DBG_SD_DBG_PWD_HIGH_LEN)-1)<<SEC_DBG_SD_DBG_PWD_HIGH_POS))
/* 0x18 : sd_status */
#define SEC_DBG_SD_STATUS_OFFSET (0x18)
#define SEC_DBG_SD_DBG_PWD_BUSY SEC_DBG_SD_DBG_PWD_BUSY
#define SEC_DBG_SD_DBG_PWD_BUSY_POS (0U)
#define SEC_DBG_SD_DBG_PWD_BUSY_LEN (1U)
#define SEC_DBG_SD_DBG_PWD_BUSY_MSK (((1U<<SEC_DBG_SD_DBG_PWD_BUSY_LEN)-1)<<SEC_DBG_SD_DBG_PWD_BUSY_POS)
#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK (~(((1U<<SEC_DBG_SD_DBG_PWD_BUSY_LEN)-1)<<SEC_DBG_SD_DBG_PWD_BUSY_POS))
#define SEC_DBG_SD_DBG_PWD_TRIG SEC_DBG_SD_DBG_PWD_TRIG
#define SEC_DBG_SD_DBG_PWD_TRIG_POS (1U)
#define SEC_DBG_SD_DBG_PWD_TRIG_LEN (1U)
#define SEC_DBG_SD_DBG_PWD_TRIG_MSK (((1U<<SEC_DBG_SD_DBG_PWD_TRIG_LEN)-1)<<SEC_DBG_SD_DBG_PWD_TRIG_POS)
#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK (~(((1U<<SEC_DBG_SD_DBG_PWD_TRIG_LEN)-1)<<SEC_DBG_SD_DBG_PWD_TRIG_POS))
#define SEC_DBG_SD_DBG_CCI_READ_EN SEC_DBG_SD_DBG_CCI_READ_EN
#define SEC_DBG_SD_DBG_CCI_READ_EN_POS (2U)
#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN (1U)
#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK (((1U<<SEC_DBG_SD_DBG_CCI_READ_EN_LEN)-1)<<SEC_DBG_SD_DBG_CCI_READ_EN_POS)
#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U<<SEC_DBG_SD_DBG_CCI_READ_EN_LEN)-1)<<SEC_DBG_SD_DBG_CCI_READ_EN_POS))
#define SEC_DBG_SD_DBG_CCI_CLK_SEL SEC_DBG_SD_DBG_CCI_CLK_SEL
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS (3U)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN (1U)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK (((1U<<SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN)-1)<<SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)
#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U<<SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN)-1)<<SEC_DBG_SD_DBG_CCI_CLK_SEL_POS))
#define SEC_DBG_SD_DBG_PWD_CNT SEC_DBG_SD_DBG_PWD_CNT
#define SEC_DBG_SD_DBG_PWD_CNT_POS (4U)
#define SEC_DBG_SD_DBG_PWD_CNT_LEN (20U)
#define SEC_DBG_SD_DBG_PWD_CNT_MSK (((1U<<SEC_DBG_SD_DBG_PWD_CNT_LEN)-1)<<SEC_DBG_SD_DBG_PWD_CNT_POS)
#define SEC_DBG_SD_DBG_PWD_CNT_UMSK (~(((1U<<SEC_DBG_SD_DBG_PWD_CNT_LEN)-1)<<SEC_DBG_SD_DBG_PWD_CNT_POS))
#define SEC_DBG_SD_DBG_MODE SEC_DBG_SD_DBG_MODE
#define SEC_DBG_SD_DBG_MODE_POS (24U)
#define SEC_DBG_SD_DBG_MODE_LEN (4U)
#define SEC_DBG_SD_DBG_MODE_MSK (((1U<<SEC_DBG_SD_DBG_MODE_LEN)-1)<<SEC_DBG_SD_DBG_MODE_POS)
#define SEC_DBG_SD_DBG_MODE_UMSK (~(((1U<<SEC_DBG_SD_DBG_MODE_LEN)-1)<<SEC_DBG_SD_DBG_MODE_POS))
#define SEC_DBG_SD_DBG_ENA SEC_DBG_SD_DBG_ENA
#define SEC_DBG_SD_DBG_ENA_POS (28U)
#define SEC_DBG_SD_DBG_ENA_LEN (4U)
#define SEC_DBG_SD_DBG_ENA_MSK (((1U<<SEC_DBG_SD_DBG_ENA_LEN)-1)<<SEC_DBG_SD_DBG_ENA_POS)
#define SEC_DBG_SD_DBG_ENA_UMSK (~(((1U<<SEC_DBG_SD_DBG_ENA_LEN)-1)<<SEC_DBG_SD_DBG_ENA_POS))
/* 0x1C : sd_dbg_reserved */
#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C)
#define SEC_DBG_SD_DBG_RESERVED SEC_DBG_SD_DBG_RESERVED
#define SEC_DBG_SD_DBG_RESERVED_POS (0U)
#define SEC_DBG_SD_DBG_RESERVED_LEN (32U)
#define SEC_DBG_SD_DBG_RESERVED_MSK (((1U<<SEC_DBG_SD_DBG_RESERVED_LEN)-1)<<SEC_DBG_SD_DBG_RESERVED_POS)
#define SEC_DBG_SD_DBG_RESERVED_UMSK (~(((1U<<SEC_DBG_SD_DBG_RESERVED_LEN)-1)<<SEC_DBG_SD_DBG_RESERVED_POS))
struct sec_dbg_reg {
/* 0x0 : sd_chip_id_low */
union {
struct {
uint32_t sd_chip_id_low : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} sd_chip_id_low;
/* 0x4 : sd_chip_id_high */
union {
struct {
uint32_t sd_chip_id_high : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} sd_chip_id_high;
/* 0x8 : sd_wifi_mac_low */
union {
struct {
uint32_t sd_wifi_mac_low : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} sd_wifi_mac_low;
/* 0xC : sd_wifi_mac_high */
union {
struct {
uint32_t sd_wifi_mac_high : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} sd_wifi_mac_high;
/* 0x10 : sd_dbg_pwd_low */
union {
struct {
uint32_t sd_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} sd_dbg_pwd_low;
/* 0x14 : sd_dbg_pwd_high */
union {
struct {
uint32_t sd_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} sd_dbg_pwd_high;
/* 0x18 : sd_status */
union {
struct {
uint32_t sd_dbg_pwd_busy : 1; /* [ 0], r, 0x0 */
uint32_t sd_dbg_pwd_trig : 1; /* [ 1], r/w, 0x0 */
uint32_t sd_dbg_cci_read_en : 1; /* [ 2], r/w, 0x0 */
uint32_t sd_dbg_cci_clk_sel : 1; /* [ 3], r/w, 0x0 */
uint32_t sd_dbg_pwd_cnt : 20; /* [23: 4], r, 0x0 */
uint32_t sd_dbg_mode : 4; /* [27:24], r, 0x0 */
uint32_t sd_dbg_ena : 4; /* [31:28], r, 0x0 */
}BF;
uint32_t WORD;
} sd_status;
/* 0x1C : sd_dbg_reserved */
union {
struct {
uint32_t sd_dbg_reserved : 32; /* [31: 0], r/w, 0xffff */
}BF;
uint32_t WORD;
} sd_dbg_reserved;
};
typedef volatile struct sec_dbg_reg sec_dbg_reg_t;
#endif /* __SEC_DBG_REG_H__ */

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/**
******************************************************************************
* @file spi_reg.h
* @version V1.2
* @date 2019-10-21
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __SPI_REG_H__
#define __SPI_REG_H__
#include "bl602.h"
/* 0x0 : spi_config */
#define SPI_CONFIG_OFFSET (0x0)
#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN
#define SPI_CR_SPI_M_EN_POS (0U)
#define SPI_CR_SPI_M_EN_LEN (1U)
#define SPI_CR_SPI_M_EN_MSK (((1U<<SPI_CR_SPI_M_EN_LEN)-1)<<SPI_CR_SPI_M_EN_POS)
#define SPI_CR_SPI_M_EN_UMSK (~(((1U<<SPI_CR_SPI_M_EN_LEN)-1)<<SPI_CR_SPI_M_EN_POS))
#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN
#define SPI_CR_SPI_S_EN_POS (1U)
#define SPI_CR_SPI_S_EN_LEN (1U)
#define SPI_CR_SPI_S_EN_MSK (((1U<<SPI_CR_SPI_S_EN_LEN)-1)<<SPI_CR_SPI_S_EN_POS)
#define SPI_CR_SPI_S_EN_UMSK (~(((1U<<SPI_CR_SPI_S_EN_LEN)-1)<<SPI_CR_SPI_S_EN_POS))
#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE
#define SPI_CR_SPI_FRAME_SIZE_POS (2U)
#define SPI_CR_SPI_FRAME_SIZE_LEN (2U)
#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U<<SPI_CR_SPI_FRAME_SIZE_LEN)-1)<<SPI_CR_SPI_FRAME_SIZE_POS)
#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U<<SPI_CR_SPI_FRAME_SIZE_LEN)-1)<<SPI_CR_SPI_FRAME_SIZE_POS))
#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL
#define SPI_CR_SPI_SCLK_POL_POS (4U)
#define SPI_CR_SPI_SCLK_POL_LEN (1U)
#define SPI_CR_SPI_SCLK_POL_MSK (((1U<<SPI_CR_SPI_SCLK_POL_LEN)-1)<<SPI_CR_SPI_SCLK_POL_POS)
#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U<<SPI_CR_SPI_SCLK_POL_LEN)-1)<<SPI_CR_SPI_SCLK_POL_POS))
#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH
#define SPI_CR_SPI_SCLK_PH_POS (5U)
#define SPI_CR_SPI_SCLK_PH_LEN (1U)
#define SPI_CR_SPI_SCLK_PH_MSK (((1U<<SPI_CR_SPI_SCLK_PH_LEN)-1)<<SPI_CR_SPI_SCLK_PH_POS)
#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U<<SPI_CR_SPI_SCLK_PH_LEN)-1)<<SPI_CR_SPI_SCLK_PH_POS))
#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV
#define SPI_CR_SPI_BIT_INV_POS (6U)
#define SPI_CR_SPI_BIT_INV_LEN (1U)
#define SPI_CR_SPI_BIT_INV_MSK (((1U<<SPI_CR_SPI_BIT_INV_LEN)-1)<<SPI_CR_SPI_BIT_INV_POS)
#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U<<SPI_CR_SPI_BIT_INV_LEN)-1)<<SPI_CR_SPI_BIT_INV_POS))
#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV
#define SPI_CR_SPI_BYTE_INV_POS (7U)
#define SPI_CR_SPI_BYTE_INV_LEN (1U)
#define SPI_CR_SPI_BYTE_INV_MSK (((1U<<SPI_CR_SPI_BYTE_INV_LEN)-1)<<SPI_CR_SPI_BYTE_INV_POS)
#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U<<SPI_CR_SPI_BYTE_INV_LEN)-1)<<SPI_CR_SPI_BYTE_INV_POS))
#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN
#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U)
#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U)
#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U<<SPI_CR_SPI_RXD_IGNR_EN_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_EN_POS)
#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U<<SPI_CR_SPI_RXD_IGNR_EN_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_EN_POS))
#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN
#define SPI_CR_SPI_M_CONT_EN_POS (9U)
#define SPI_CR_SPI_M_CONT_EN_LEN (1U)
#define SPI_CR_SPI_M_CONT_EN_MSK (((1U<<SPI_CR_SPI_M_CONT_EN_LEN)-1)<<SPI_CR_SPI_M_CONT_EN_POS)
#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U<<SPI_CR_SPI_M_CONT_EN_LEN)-1)<<SPI_CR_SPI_M_CONT_EN_POS))
#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN
#define SPI_CR_SPI_DEG_EN_POS (11U)
#define SPI_CR_SPI_DEG_EN_LEN (1U)
#define SPI_CR_SPI_DEG_EN_MSK (((1U<<SPI_CR_SPI_DEG_EN_LEN)-1)<<SPI_CR_SPI_DEG_EN_POS)
#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U<<SPI_CR_SPI_DEG_EN_LEN)-1)<<SPI_CR_SPI_DEG_EN_POS))
#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT
#define SPI_CR_SPI_DEG_CNT_POS (12U)
#define SPI_CR_SPI_DEG_CNT_LEN (4U)
#define SPI_CR_SPI_DEG_CNT_MSK (((1U<<SPI_CR_SPI_DEG_CNT_LEN)-1)<<SPI_CR_SPI_DEG_CNT_POS)
#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U<<SPI_CR_SPI_DEG_CNT_LEN)-1)<<SPI_CR_SPI_DEG_CNT_POS))
/* 0x4 : spi_int_sts */
#define SPI_INT_STS_OFFSET (0x4)
#define SPI_END_INT SPI_END_INT
#define SPI_END_INT_POS (0U)
#define SPI_END_INT_LEN (1U)
#define SPI_END_INT_MSK (((1U<<SPI_END_INT_LEN)-1)<<SPI_END_INT_POS)
#define SPI_END_INT_UMSK (~(((1U<<SPI_END_INT_LEN)-1)<<SPI_END_INT_POS))
#define SPI_TXF_INT SPI_TXF_INT
#define SPI_TXF_INT_POS (1U)
#define SPI_TXF_INT_LEN (1U)
#define SPI_TXF_INT_MSK (((1U<<SPI_TXF_INT_LEN)-1)<<SPI_TXF_INT_POS)
#define SPI_TXF_INT_UMSK (~(((1U<<SPI_TXF_INT_LEN)-1)<<SPI_TXF_INT_POS))
#define SPI_RXF_INT SPI_RXF_INT
#define SPI_RXF_INT_POS (2U)
#define SPI_RXF_INT_LEN (1U)
#define SPI_RXF_INT_MSK (((1U<<SPI_RXF_INT_LEN)-1)<<SPI_RXF_INT_POS)
#define SPI_RXF_INT_UMSK (~(((1U<<SPI_RXF_INT_LEN)-1)<<SPI_RXF_INT_POS))
#define SPI_STO_INT SPI_STO_INT
#define SPI_STO_INT_POS (3U)
#define SPI_STO_INT_LEN (1U)
#define SPI_STO_INT_MSK (((1U<<SPI_STO_INT_LEN)-1)<<SPI_STO_INT_POS)
#define SPI_STO_INT_UMSK (~(((1U<<SPI_STO_INT_LEN)-1)<<SPI_STO_INT_POS))
#define SPI_TXU_INT SPI_TXU_INT
#define SPI_TXU_INT_POS (4U)
#define SPI_TXU_INT_LEN (1U)
#define SPI_TXU_INT_MSK (((1U<<SPI_TXU_INT_LEN)-1)<<SPI_TXU_INT_POS)
#define SPI_TXU_INT_UMSK (~(((1U<<SPI_TXU_INT_LEN)-1)<<SPI_TXU_INT_POS))
#define SPI_FER_INT SPI_FER_INT
#define SPI_FER_INT_POS (5U)
#define SPI_FER_INT_LEN (1U)
#define SPI_FER_INT_MSK (((1U<<SPI_FER_INT_LEN)-1)<<SPI_FER_INT_POS)
#define SPI_FER_INT_UMSK (~(((1U<<SPI_FER_INT_LEN)-1)<<SPI_FER_INT_POS))
#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK
#define SPI_CR_SPI_END_MASK_POS (8U)
#define SPI_CR_SPI_END_MASK_LEN (1U)
#define SPI_CR_SPI_END_MASK_MSK (((1U<<SPI_CR_SPI_END_MASK_LEN)-1)<<SPI_CR_SPI_END_MASK_POS)
#define SPI_CR_SPI_END_MASK_UMSK (~(((1U<<SPI_CR_SPI_END_MASK_LEN)-1)<<SPI_CR_SPI_END_MASK_POS))
#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK
#define SPI_CR_SPI_TXF_MASK_POS (9U)
#define SPI_CR_SPI_TXF_MASK_LEN (1U)
#define SPI_CR_SPI_TXF_MASK_MSK (((1U<<SPI_CR_SPI_TXF_MASK_LEN)-1)<<SPI_CR_SPI_TXF_MASK_POS)
#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U<<SPI_CR_SPI_TXF_MASK_LEN)-1)<<SPI_CR_SPI_TXF_MASK_POS))
#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK
#define SPI_CR_SPI_RXF_MASK_POS (10U)
#define SPI_CR_SPI_RXF_MASK_LEN (1U)
#define SPI_CR_SPI_RXF_MASK_MSK (((1U<<SPI_CR_SPI_RXF_MASK_LEN)-1)<<SPI_CR_SPI_RXF_MASK_POS)
#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U<<SPI_CR_SPI_RXF_MASK_LEN)-1)<<SPI_CR_SPI_RXF_MASK_POS))
#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK
#define SPI_CR_SPI_STO_MASK_POS (11U)
#define SPI_CR_SPI_STO_MASK_LEN (1U)
#define SPI_CR_SPI_STO_MASK_MSK (((1U<<SPI_CR_SPI_STO_MASK_LEN)-1)<<SPI_CR_SPI_STO_MASK_POS)
#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U<<SPI_CR_SPI_STO_MASK_LEN)-1)<<SPI_CR_SPI_STO_MASK_POS))
#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK
#define SPI_CR_SPI_TXU_MASK_POS (12U)
#define SPI_CR_SPI_TXU_MASK_LEN (1U)
#define SPI_CR_SPI_TXU_MASK_MSK (((1U<<SPI_CR_SPI_TXU_MASK_LEN)-1)<<SPI_CR_SPI_TXU_MASK_POS)
#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U<<SPI_CR_SPI_TXU_MASK_LEN)-1)<<SPI_CR_SPI_TXU_MASK_POS))
#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK
#define SPI_CR_SPI_FER_MASK_POS (13U)
#define SPI_CR_SPI_FER_MASK_LEN (1U)
#define SPI_CR_SPI_FER_MASK_MSK (((1U<<SPI_CR_SPI_FER_MASK_LEN)-1)<<SPI_CR_SPI_FER_MASK_POS)
#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U<<SPI_CR_SPI_FER_MASK_LEN)-1)<<SPI_CR_SPI_FER_MASK_POS))
#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR
#define SPI_CR_SPI_END_CLR_POS (16U)
#define SPI_CR_SPI_END_CLR_LEN (1U)
#define SPI_CR_SPI_END_CLR_MSK (((1U<<SPI_CR_SPI_END_CLR_LEN)-1)<<SPI_CR_SPI_END_CLR_POS)
#define SPI_CR_SPI_END_CLR_UMSK (~(((1U<<SPI_CR_SPI_END_CLR_LEN)-1)<<SPI_CR_SPI_END_CLR_POS))
#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR
#define SPI_CR_SPI_STO_CLR_POS (19U)
#define SPI_CR_SPI_STO_CLR_LEN (1U)
#define SPI_CR_SPI_STO_CLR_MSK (((1U<<SPI_CR_SPI_STO_CLR_LEN)-1)<<SPI_CR_SPI_STO_CLR_POS)
#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U<<SPI_CR_SPI_STO_CLR_LEN)-1)<<SPI_CR_SPI_STO_CLR_POS))
#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR
#define SPI_CR_SPI_TXU_CLR_POS (20U)
#define SPI_CR_SPI_TXU_CLR_LEN (1U)
#define SPI_CR_SPI_TXU_CLR_MSK (((1U<<SPI_CR_SPI_TXU_CLR_LEN)-1)<<SPI_CR_SPI_TXU_CLR_POS)
#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U<<SPI_CR_SPI_TXU_CLR_LEN)-1)<<SPI_CR_SPI_TXU_CLR_POS))
#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN
#define SPI_CR_SPI_END_EN_POS (24U)
#define SPI_CR_SPI_END_EN_LEN (1U)
#define SPI_CR_SPI_END_EN_MSK (((1U<<SPI_CR_SPI_END_EN_LEN)-1)<<SPI_CR_SPI_END_EN_POS)
#define SPI_CR_SPI_END_EN_UMSK (~(((1U<<SPI_CR_SPI_END_EN_LEN)-1)<<SPI_CR_SPI_END_EN_POS))
#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN
#define SPI_CR_SPI_TXF_EN_POS (25U)
#define SPI_CR_SPI_TXF_EN_LEN (1U)
#define SPI_CR_SPI_TXF_EN_MSK (((1U<<SPI_CR_SPI_TXF_EN_LEN)-1)<<SPI_CR_SPI_TXF_EN_POS)
#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U<<SPI_CR_SPI_TXF_EN_LEN)-1)<<SPI_CR_SPI_TXF_EN_POS))
#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN
#define SPI_CR_SPI_RXF_EN_POS (26U)
#define SPI_CR_SPI_RXF_EN_LEN (1U)
#define SPI_CR_SPI_RXF_EN_MSK (((1U<<SPI_CR_SPI_RXF_EN_LEN)-1)<<SPI_CR_SPI_RXF_EN_POS)
#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U<<SPI_CR_SPI_RXF_EN_LEN)-1)<<SPI_CR_SPI_RXF_EN_POS))
#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN
#define SPI_CR_SPI_STO_EN_POS (27U)
#define SPI_CR_SPI_STO_EN_LEN (1U)
#define SPI_CR_SPI_STO_EN_MSK (((1U<<SPI_CR_SPI_STO_EN_LEN)-1)<<SPI_CR_SPI_STO_EN_POS)
#define SPI_CR_SPI_STO_EN_UMSK (~(((1U<<SPI_CR_SPI_STO_EN_LEN)-1)<<SPI_CR_SPI_STO_EN_POS))
#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN
#define SPI_CR_SPI_TXU_EN_POS (28U)
#define SPI_CR_SPI_TXU_EN_LEN (1U)
#define SPI_CR_SPI_TXU_EN_MSK (((1U<<SPI_CR_SPI_TXU_EN_LEN)-1)<<SPI_CR_SPI_TXU_EN_POS)
#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U<<SPI_CR_SPI_TXU_EN_LEN)-1)<<SPI_CR_SPI_TXU_EN_POS))
#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN
#define SPI_CR_SPI_FER_EN_POS (29U)
#define SPI_CR_SPI_FER_EN_LEN (1U)
#define SPI_CR_SPI_FER_EN_MSK (((1U<<SPI_CR_SPI_FER_EN_LEN)-1)<<SPI_CR_SPI_FER_EN_POS)
#define SPI_CR_SPI_FER_EN_UMSK (~(((1U<<SPI_CR_SPI_FER_EN_LEN)-1)<<SPI_CR_SPI_FER_EN_POS))
/* 0x8 : spi_bus_busy */
#define SPI_BUS_BUSY_OFFSET (0x8)
#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY
#define SPI_STS_SPI_BUS_BUSY_POS (0U)
#define SPI_STS_SPI_BUS_BUSY_LEN (1U)
#define SPI_STS_SPI_BUS_BUSY_MSK (((1U<<SPI_STS_SPI_BUS_BUSY_LEN)-1)<<SPI_STS_SPI_BUS_BUSY_POS)
#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U<<SPI_STS_SPI_BUS_BUSY_LEN)-1)<<SPI_STS_SPI_BUS_BUSY_POS))
/* 0x10 : spi_prd_0 */
#define SPI_PRD_0_OFFSET (0x10)
#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S
#define SPI_CR_SPI_PRD_S_POS (0U)
#define SPI_CR_SPI_PRD_S_LEN (8U)
#define SPI_CR_SPI_PRD_S_MSK (((1U<<SPI_CR_SPI_PRD_S_LEN)-1)<<SPI_CR_SPI_PRD_S_POS)
#define SPI_CR_SPI_PRD_S_UMSK (~(((1U<<SPI_CR_SPI_PRD_S_LEN)-1)<<SPI_CR_SPI_PRD_S_POS))
#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P
#define SPI_CR_SPI_PRD_P_POS (8U)
#define SPI_CR_SPI_PRD_P_LEN (8U)
#define SPI_CR_SPI_PRD_P_MSK (((1U<<SPI_CR_SPI_PRD_P_LEN)-1)<<SPI_CR_SPI_PRD_P_POS)
#define SPI_CR_SPI_PRD_P_UMSK (~(((1U<<SPI_CR_SPI_PRD_P_LEN)-1)<<SPI_CR_SPI_PRD_P_POS))
#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0
#define SPI_CR_SPI_PRD_D_PH_0_POS (16U)
#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U)
#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U<<SPI_CR_SPI_PRD_D_PH_0_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_0_POS)
#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U<<SPI_CR_SPI_PRD_D_PH_0_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_0_POS))
#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1
#define SPI_CR_SPI_PRD_D_PH_1_POS (24U)
#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U)
#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U<<SPI_CR_SPI_PRD_D_PH_1_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_1_POS)
#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U<<SPI_CR_SPI_PRD_D_PH_1_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_1_POS))
/* 0x14 : spi_prd_1 */
#define SPI_PRD_1_OFFSET (0x14)
#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I
#define SPI_CR_SPI_PRD_I_POS (0U)
#define SPI_CR_SPI_PRD_I_LEN (8U)
#define SPI_CR_SPI_PRD_I_MSK (((1U<<SPI_CR_SPI_PRD_I_LEN)-1)<<SPI_CR_SPI_PRD_I_POS)
#define SPI_CR_SPI_PRD_I_UMSK (~(((1U<<SPI_CR_SPI_PRD_I_LEN)-1)<<SPI_CR_SPI_PRD_I_POS))
/* 0x18 : spi_rxd_ignr */
#define SPI_RXD_IGNR_OFFSET (0x18)
#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P
#define SPI_CR_SPI_RXD_IGNR_P_POS (0U)
#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U)
#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U<<SPI_CR_SPI_RXD_IGNR_P_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_P_POS)
#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U<<SPI_CR_SPI_RXD_IGNR_P_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_P_POS))
#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S
#define SPI_CR_SPI_RXD_IGNR_S_POS (16U)
#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U)
#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U<<SPI_CR_SPI_RXD_IGNR_S_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_S_POS)
#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U<<SPI_CR_SPI_RXD_IGNR_S_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_S_POS))
/* 0x1C : spi_sto_value */
#define SPI_STO_VALUE_OFFSET (0x1C)
#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE
#define SPI_CR_SPI_STO_VALUE_POS (0U)
#define SPI_CR_SPI_STO_VALUE_LEN (12U)
#define SPI_CR_SPI_STO_VALUE_MSK (((1U<<SPI_CR_SPI_STO_VALUE_LEN)-1)<<SPI_CR_SPI_STO_VALUE_POS)
#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U<<SPI_CR_SPI_STO_VALUE_LEN)-1)<<SPI_CR_SPI_STO_VALUE_POS))
/* 0x80 : spi_fifo_config_0 */
#define SPI_FIFO_CONFIG_0_OFFSET (0x80)
#define SPI_DMA_TX_EN SPI_DMA_TX_EN
#define SPI_DMA_TX_EN_POS (0U)
#define SPI_DMA_TX_EN_LEN (1U)
#define SPI_DMA_TX_EN_MSK (((1U<<SPI_DMA_TX_EN_LEN)-1)<<SPI_DMA_TX_EN_POS)
#define SPI_DMA_TX_EN_UMSK (~(((1U<<SPI_DMA_TX_EN_LEN)-1)<<SPI_DMA_TX_EN_POS))
#define SPI_DMA_RX_EN SPI_DMA_RX_EN
#define SPI_DMA_RX_EN_POS (1U)
#define SPI_DMA_RX_EN_LEN (1U)
#define SPI_DMA_RX_EN_MSK (((1U<<SPI_DMA_RX_EN_LEN)-1)<<SPI_DMA_RX_EN_POS)
#define SPI_DMA_RX_EN_UMSK (~(((1U<<SPI_DMA_RX_EN_LEN)-1)<<SPI_DMA_RX_EN_POS))
#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR
#define SPI_TX_FIFO_CLR_POS (2U)
#define SPI_TX_FIFO_CLR_LEN (1U)
#define SPI_TX_FIFO_CLR_MSK (((1U<<SPI_TX_FIFO_CLR_LEN)-1)<<SPI_TX_FIFO_CLR_POS)
#define SPI_TX_FIFO_CLR_UMSK (~(((1U<<SPI_TX_FIFO_CLR_LEN)-1)<<SPI_TX_FIFO_CLR_POS))
#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR
#define SPI_RX_FIFO_CLR_POS (3U)
#define SPI_RX_FIFO_CLR_LEN (1U)
#define SPI_RX_FIFO_CLR_MSK (((1U<<SPI_RX_FIFO_CLR_LEN)-1)<<SPI_RX_FIFO_CLR_POS)
#define SPI_RX_FIFO_CLR_UMSK (~(((1U<<SPI_RX_FIFO_CLR_LEN)-1)<<SPI_RX_FIFO_CLR_POS))
#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW
#define SPI_TX_FIFO_OVERFLOW_POS (4U)
#define SPI_TX_FIFO_OVERFLOW_LEN (1U)
#define SPI_TX_FIFO_OVERFLOW_MSK (((1U<<SPI_TX_FIFO_OVERFLOW_LEN)-1)<<SPI_TX_FIFO_OVERFLOW_POS)
#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U<<SPI_TX_FIFO_OVERFLOW_LEN)-1)<<SPI_TX_FIFO_OVERFLOW_POS))
#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW
#define SPI_TX_FIFO_UNDERFLOW_POS (5U)
#define SPI_TX_FIFO_UNDERFLOW_LEN (1U)
#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U<<SPI_TX_FIFO_UNDERFLOW_LEN)-1)<<SPI_TX_FIFO_UNDERFLOW_POS)
#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U<<SPI_TX_FIFO_UNDERFLOW_LEN)-1)<<SPI_TX_FIFO_UNDERFLOW_POS))
#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW
#define SPI_RX_FIFO_OVERFLOW_POS (6U)
#define SPI_RX_FIFO_OVERFLOW_LEN (1U)
#define SPI_RX_FIFO_OVERFLOW_MSK (((1U<<SPI_RX_FIFO_OVERFLOW_LEN)-1)<<SPI_RX_FIFO_OVERFLOW_POS)
#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U<<SPI_RX_FIFO_OVERFLOW_LEN)-1)<<SPI_RX_FIFO_OVERFLOW_POS))
#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW
#define SPI_RX_FIFO_UNDERFLOW_POS (7U)
#define SPI_RX_FIFO_UNDERFLOW_LEN (1U)
#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U<<SPI_RX_FIFO_UNDERFLOW_LEN)-1)<<SPI_RX_FIFO_UNDERFLOW_POS)
#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U<<SPI_RX_FIFO_UNDERFLOW_LEN)-1)<<SPI_RX_FIFO_UNDERFLOW_POS))
/* 0x84 : spi_fifo_config_1 */
#define SPI_FIFO_CONFIG_1_OFFSET (0x84)
#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT
#define SPI_TX_FIFO_CNT_POS (0U)
#define SPI_TX_FIFO_CNT_LEN (3U)
#define SPI_TX_FIFO_CNT_MSK (((1U<<SPI_TX_FIFO_CNT_LEN)-1)<<SPI_TX_FIFO_CNT_POS)
#define SPI_TX_FIFO_CNT_UMSK (~(((1U<<SPI_TX_FIFO_CNT_LEN)-1)<<SPI_TX_FIFO_CNT_POS))
#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT
#define SPI_RX_FIFO_CNT_POS (8U)
#define SPI_RX_FIFO_CNT_LEN (3U)
#define SPI_RX_FIFO_CNT_MSK (((1U<<SPI_RX_FIFO_CNT_LEN)-1)<<SPI_RX_FIFO_CNT_POS)
#define SPI_RX_FIFO_CNT_UMSK (~(((1U<<SPI_RX_FIFO_CNT_LEN)-1)<<SPI_RX_FIFO_CNT_POS))
#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH
#define SPI_TX_FIFO_TH_POS (16U)
#define SPI_TX_FIFO_TH_LEN (2U)
#define SPI_TX_FIFO_TH_MSK (((1U<<SPI_TX_FIFO_TH_LEN)-1)<<SPI_TX_FIFO_TH_POS)
#define SPI_TX_FIFO_TH_UMSK (~(((1U<<SPI_TX_FIFO_TH_LEN)-1)<<SPI_TX_FIFO_TH_POS))
#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH
#define SPI_RX_FIFO_TH_POS (24U)
#define SPI_RX_FIFO_TH_LEN (2U)
#define SPI_RX_FIFO_TH_MSK (((1U<<SPI_RX_FIFO_TH_LEN)-1)<<SPI_RX_FIFO_TH_POS)
#define SPI_RX_FIFO_TH_UMSK (~(((1U<<SPI_RX_FIFO_TH_LEN)-1)<<SPI_RX_FIFO_TH_POS))
/* 0x88 : spi_fifo_wdata */
#define SPI_FIFO_WDATA_OFFSET (0x88)
#define SPI_FIFO_WDATA SPI_FIFO_WDATA
#define SPI_FIFO_WDATA_POS (0U)
#define SPI_FIFO_WDATA_LEN (32U)
#define SPI_FIFO_WDATA_MSK (((1U<<SPI_FIFO_WDATA_LEN)-1)<<SPI_FIFO_WDATA_POS)
#define SPI_FIFO_WDATA_UMSK (~(((1U<<SPI_FIFO_WDATA_LEN)-1)<<SPI_FIFO_WDATA_POS))
/* 0x8C : spi_fifo_rdata */
#define SPI_FIFO_RDATA_OFFSET (0x8C)
#define SPI_FIFO_RDATA SPI_FIFO_RDATA
#define SPI_FIFO_RDATA_POS (0U)
#define SPI_FIFO_RDATA_LEN (32U)
#define SPI_FIFO_RDATA_MSK (((1U<<SPI_FIFO_RDATA_LEN)-1)<<SPI_FIFO_RDATA_POS)
#define SPI_FIFO_RDATA_UMSK (~(((1U<<SPI_FIFO_RDATA_LEN)-1)<<SPI_FIFO_RDATA_POS))
struct spi_reg {
/* 0x0 : spi_config */
union {
struct {
uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */
uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */
uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */
uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */
uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */
uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_config;
/* 0x4 : spi_int_sts */
union {
struct {
uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */
uint32_t spi_txf_int : 1; /* [ 1], r, 0x0 */
uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */
uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */
uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */
uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */
uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */
uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */
uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */
uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */
uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */
uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */
uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */
uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */
uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */
uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */
uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */
uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */
uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */
uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_int_sts;
/* 0x8 : spi_bus_busy */
union {
struct {
uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_bus_busy;
/* 0xc reserved */
uint8_t RESERVED0xc[4];
/* 0x10 : spi_prd_0 */
union {
struct {
uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */
uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */
uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */
uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */
}BF;
uint32_t WORD;
} spi_prd_0;
/* 0x14 : spi_prd_1 */
union {
struct {
uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_prd_1;
/* 0x18 : spi_rxd_ignr */
union {
struct {
uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */
uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */
uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_rxd_ignr;
/* 0x1C : spi_sto_value */
union {
struct {
uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_sto_value;
/* 0x20 reserved */
uint8_t RESERVED0x20[96];
/* 0x80 : spi_fifo_config_0 */
union {
struct {
uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_fifo_config_0;
/* 0x84 : spi_fifo_config_1 */
union {
struct {
uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */
uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
}BF;
uint32_t WORD;
} spi_fifo_config_1;
/* 0x88 : spi_fifo_wdata */
union {
struct {
uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */
}BF;
uint32_t WORD;
} spi_fifo_wdata;
/* 0x8C : spi_fifo_rdata */
union {
struct {
uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} spi_fifo_rdata;
};
typedef volatile struct spi_reg spi_reg_t;
#endif /* __SPI_REG_H__ */

819
drivers/bl602_driver/regs/timer_reg.h Normal file
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@ -0,0 +1,819 @@
/**
******************************************************************************
* @file timer_reg.h
* @version V1.2
* @date 2019-10-21
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __TIMER_REG_H__
#define __TIMER_REG_H__
#include "bl602.h"
/* 0x0 : TCCR */
#define TIMER_TCCR_OFFSET (0x0)
#define TIMER_CS_1 TIMER_CS_1
#define TIMER_CS_1_POS (2U)
#define TIMER_CS_1_LEN (2U)
#define TIMER_CS_1_MSK (((1U<<TIMER_CS_1_LEN)-1)<<TIMER_CS_1_POS)
#define TIMER_CS_1_UMSK (~(((1U<<TIMER_CS_1_LEN)-1)<<TIMER_CS_1_POS))
#define TIMER_CS_2 TIMER_CS_2
#define TIMER_CS_2_POS (5U)
#define TIMER_CS_2_LEN (2U)
#define TIMER_CS_2_MSK (((1U<<TIMER_CS_2_LEN)-1)<<TIMER_CS_2_POS)
#define TIMER_CS_2_UMSK (~(((1U<<TIMER_CS_2_LEN)-1)<<TIMER_CS_2_POS))
#define TIMER_CS_WDT TIMER_CS_WDT
#define TIMER_CS_WDT_POS (8U)
#define TIMER_CS_WDT_LEN (2U)
#define TIMER_CS_WDT_MSK (((1U<<TIMER_CS_WDT_LEN)-1)<<TIMER_CS_WDT_POS)
#define TIMER_CS_WDT_UMSK (~(((1U<<TIMER_CS_WDT_LEN)-1)<<TIMER_CS_WDT_POS))
/* 0x10 : TMR2_0 */
#define TIMER_TMR2_0_OFFSET (0x10)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS))
/* 0x14 : TMR2_1 */
#define TIMER_TMR2_1_OFFSET (0x14)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS))
/* 0x18 : TMR2_2 */
#define TIMER_TMR2_2_OFFSET (0x18)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS))
/* 0x1C : TMR3_0 */
#define TIMER_TMR3_0_OFFSET (0x1C)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS))
/* 0x20 : TMR3_1 */
#define TIMER_TMR3_1_OFFSET (0x20)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS))
/* 0x24 : TMR3_2 */
#define TIMER_TMR3_2_OFFSET (0x24)
#define TIMER_TMR TIMER_TMR
#define TIMER_TMR_POS (0U)
#define TIMER_TMR_LEN (32U)
#define TIMER_TMR_MSK (((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS)
#define TIMER_TMR_UMSK (~(((1U<<TIMER_TMR_LEN)-1)<<TIMER_TMR_POS))
/* 0x2C : TCR2 */
#define TIMER_TCR2_OFFSET (0x2C)
#define TIMER_TCR TIMER_TCR
#define TIMER_TCR_POS (0U)
#define TIMER_TCR_LEN (32U)
#define TIMER_TCR_MSK (((1U<<TIMER_TCR_LEN)-1)<<TIMER_TCR_POS)
#define TIMER_TCR_UMSK (~(((1U<<TIMER_TCR_LEN)-1)<<TIMER_TCR_POS))
/* 0x30 : TCR3 */
#define TIMER_TCR3_OFFSET (0x30)
#define TIMER_TCR3_COUNTER TIMER_TCR3_COUNTER
#define TIMER_TCR3_COUNTER_POS (0U)
#define TIMER_TCR3_COUNTER_LEN (32U)
#define TIMER_TCR3_COUNTER_MSK (((1U<<TIMER_TCR3_COUNTER_LEN)-1)<<TIMER_TCR3_COUNTER_POS)
#define TIMER_TCR3_COUNTER_UMSK (~(((1U<<TIMER_TCR3_COUNTER_LEN)-1)<<TIMER_TCR3_COUNTER_POS))
/* 0x38 : TMSR2 */
#define TIMER_TMSR2_OFFSET (0x38)
#define TIMER_TMSR_0 TIMER_TMSR_0
#define TIMER_TMSR_0_POS (0U)
#define TIMER_TMSR_0_LEN (1U)
#define TIMER_TMSR_0_MSK (((1U<<TIMER_TMSR_0_LEN)-1)<<TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK (~(((1U<<TIMER_TMSR_0_LEN)-1)<<TIMER_TMSR_0_POS))
#define TIMER_TMSR_1 TIMER_TMSR_1
#define TIMER_TMSR_1_POS (1U)
#define TIMER_TMSR_1_LEN (1U)
#define TIMER_TMSR_1_MSK (((1U<<TIMER_TMSR_1_LEN)-1)<<TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK (~(((1U<<TIMER_TMSR_1_LEN)-1)<<TIMER_TMSR_1_POS))
#define TIMER_TMSR_2 TIMER_TMSR_2
#define TIMER_TMSR_2_POS (2U)
#define TIMER_TMSR_2_LEN (1U)
#define TIMER_TMSR_2_MSK (((1U<<TIMER_TMSR_2_LEN)-1)<<TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK (~(((1U<<TIMER_TMSR_2_LEN)-1)<<TIMER_TMSR_2_POS))
/* 0x3C : TMSR3 */
#define TIMER_TMSR3_OFFSET (0x3C)
#define TIMER_TMSR_0 TIMER_TMSR_0
#define TIMER_TMSR_0_POS (0U)
#define TIMER_TMSR_0_LEN (1U)
#define TIMER_TMSR_0_MSK (((1U<<TIMER_TMSR_0_LEN)-1)<<TIMER_TMSR_0_POS)
#define TIMER_TMSR_0_UMSK (~(((1U<<TIMER_TMSR_0_LEN)-1)<<TIMER_TMSR_0_POS))
#define TIMER_TMSR_1 TIMER_TMSR_1
#define TIMER_TMSR_1_POS (1U)
#define TIMER_TMSR_1_LEN (1U)
#define TIMER_TMSR_1_MSK (((1U<<TIMER_TMSR_1_LEN)-1)<<TIMER_TMSR_1_POS)
#define TIMER_TMSR_1_UMSK (~(((1U<<TIMER_TMSR_1_LEN)-1)<<TIMER_TMSR_1_POS))
#define TIMER_TMSR_2 TIMER_TMSR_2
#define TIMER_TMSR_2_POS (2U)
#define TIMER_TMSR_2_LEN (1U)
#define TIMER_TMSR_2_MSK (((1U<<TIMER_TMSR_2_LEN)-1)<<TIMER_TMSR_2_POS)
#define TIMER_TMSR_2_UMSK (~(((1U<<TIMER_TMSR_2_LEN)-1)<<TIMER_TMSR_2_POS))
/* 0x44 : TIER2 */
#define TIMER_TIER2_OFFSET (0x44)
#define TIMER_TIER_0 TIMER_TIER_0
#define TIMER_TIER_0_POS (0U)
#define TIMER_TIER_0_LEN (1U)
#define TIMER_TIER_0_MSK (((1U<<TIMER_TIER_0_LEN)-1)<<TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK (~(((1U<<TIMER_TIER_0_LEN)-1)<<TIMER_TIER_0_POS))
#define TIMER_TIER_1 TIMER_TIER_1
#define TIMER_TIER_1_POS (1U)
#define TIMER_TIER_1_LEN (1U)
#define TIMER_TIER_1_MSK (((1U<<TIMER_TIER_1_LEN)-1)<<TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK (~(((1U<<TIMER_TIER_1_LEN)-1)<<TIMER_TIER_1_POS))
#define TIMER_TIER_2 TIMER_TIER_2
#define TIMER_TIER_2_POS (2U)
#define TIMER_TIER_2_LEN (1U)
#define TIMER_TIER_2_MSK (((1U<<TIMER_TIER_2_LEN)-1)<<TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK (~(((1U<<TIMER_TIER_2_LEN)-1)<<TIMER_TIER_2_POS))
/* 0x48 : TIER3 */
#define TIMER_TIER3_OFFSET (0x48)
#define TIMER_TIER_0 TIMER_TIER_0
#define TIMER_TIER_0_POS (0U)
#define TIMER_TIER_0_LEN (1U)
#define TIMER_TIER_0_MSK (((1U<<TIMER_TIER_0_LEN)-1)<<TIMER_TIER_0_POS)
#define TIMER_TIER_0_UMSK (~(((1U<<TIMER_TIER_0_LEN)-1)<<TIMER_TIER_0_POS))
#define TIMER_TIER_1 TIMER_TIER_1
#define TIMER_TIER_1_POS (1U)
#define TIMER_TIER_1_LEN (1U)
#define TIMER_TIER_1_MSK (((1U<<TIMER_TIER_1_LEN)-1)<<TIMER_TIER_1_POS)
#define TIMER_TIER_1_UMSK (~(((1U<<TIMER_TIER_1_LEN)-1)<<TIMER_TIER_1_POS))
#define TIMER_TIER_2 TIMER_TIER_2
#define TIMER_TIER_2_POS (2U)
#define TIMER_TIER_2_LEN (1U)
#define TIMER_TIER_2_MSK (((1U<<TIMER_TIER_2_LEN)-1)<<TIMER_TIER_2_POS)
#define TIMER_TIER_2_UMSK (~(((1U<<TIMER_TIER_2_LEN)-1)<<TIMER_TIER_2_POS))
/* 0x50 : TPLVR2 */
#define TIMER_TPLVR2_OFFSET (0x50)
#define TIMER_TPLVR TIMER_TPLVR
#define TIMER_TPLVR_POS (0U)
#define TIMER_TPLVR_LEN (32U)
#define TIMER_TPLVR_MSK (((1U<<TIMER_TPLVR_LEN)-1)<<TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK (~(((1U<<TIMER_TPLVR_LEN)-1)<<TIMER_TPLVR_POS))
/* 0x54 : TPLVR3 */
#define TIMER_TPLVR3_OFFSET (0x54)
#define TIMER_TPLVR TIMER_TPLVR
#define TIMER_TPLVR_POS (0U)
#define TIMER_TPLVR_LEN (32U)
#define TIMER_TPLVR_MSK (((1U<<TIMER_TPLVR_LEN)-1)<<TIMER_TPLVR_POS)
#define TIMER_TPLVR_UMSK (~(((1U<<TIMER_TPLVR_LEN)-1)<<TIMER_TPLVR_POS))
/* 0x5C : TPLCR2 */
#define TIMER_TPLCR2_OFFSET (0x5C)
#define TIMER_TPLCR TIMER_TPLCR
#define TIMER_TPLCR_POS (0U)
#define TIMER_TPLCR_LEN (2U)
#define TIMER_TPLCR_MSK (((1U<<TIMER_TPLCR_LEN)-1)<<TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK (~(((1U<<TIMER_TPLCR_LEN)-1)<<TIMER_TPLCR_POS))
/* 0x60 : TPLCR3 */
#define TIMER_TPLCR3_OFFSET (0x60)
#define TIMER_TPLCR TIMER_TPLCR
#define TIMER_TPLCR_POS (0U)
#define TIMER_TPLCR_LEN (2U)
#define TIMER_TPLCR_MSK (((1U<<TIMER_TPLCR_LEN)-1)<<TIMER_TPLCR_POS)
#define TIMER_TPLCR_UMSK (~(((1U<<TIMER_TPLCR_LEN)-1)<<TIMER_TPLCR_POS))
/* 0x64 : WMER */
#define TIMER_WMER_OFFSET (0x64)
#define TIMER_WE TIMER_WE
#define TIMER_WE_POS (0U)
#define TIMER_WE_LEN (1U)
#define TIMER_WE_MSK (((1U<<TIMER_WE_LEN)-1)<<TIMER_WE_POS)
#define TIMER_WE_UMSK (~(((1U<<TIMER_WE_LEN)-1)<<TIMER_WE_POS))
#define TIMER_WRIE TIMER_WRIE
#define TIMER_WRIE_POS (1U)
#define TIMER_WRIE_LEN (1U)
#define TIMER_WRIE_MSK (((1U<<TIMER_WRIE_LEN)-1)<<TIMER_WRIE_POS)
#define TIMER_WRIE_UMSK (~(((1U<<TIMER_WRIE_LEN)-1)<<TIMER_WRIE_POS))
/* 0x68 : WMR */
#define TIMER_WMR_OFFSET (0x68)
#define TIMER_WMR TIMER_WMR
#define TIMER_WMR_POS (0U)
#define TIMER_WMR_LEN (16U)
#define TIMER_WMR_MSK (((1U<<TIMER_WMR_LEN)-1)<<TIMER_WMR_POS)
#define TIMER_WMR_UMSK (~(((1U<<TIMER_WMR_LEN)-1)<<TIMER_WMR_POS))
/* 0x6C : WVR */
#define TIMER_WVR_OFFSET (0x6C)
#define TIMER_WVR TIMER_WVR
#define TIMER_WVR_POS (0U)
#define TIMER_WVR_LEN (16U)
#define TIMER_WVR_MSK (((1U<<TIMER_WVR_LEN)-1)<<TIMER_WVR_POS)
#define TIMER_WVR_UMSK (~(((1U<<TIMER_WVR_LEN)-1)<<TIMER_WVR_POS))
/* 0x70 : WSR */
#define TIMER_WSR_OFFSET (0x70)
#define TIMER_WTS TIMER_WTS
#define TIMER_WTS_POS (0U)
#define TIMER_WTS_LEN (1U)
#define TIMER_WTS_MSK (((1U<<TIMER_WTS_LEN)-1)<<TIMER_WTS_POS)
#define TIMER_WTS_UMSK (~(((1U<<TIMER_WTS_LEN)-1)<<TIMER_WTS_POS))
/* 0x78 : TICR2 */
#define TIMER_TICR2_OFFSET (0x78)
#define TIMER_TCLR_0 TIMER_TCLR_0
#define TIMER_TCLR_0_POS (0U)
#define TIMER_TCLR_0_LEN (1U)
#define TIMER_TCLR_0_MSK (((1U<<TIMER_TCLR_0_LEN)-1)<<TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK (~(((1U<<TIMER_TCLR_0_LEN)-1)<<TIMER_TCLR_0_POS))
#define TIMER_TCLR_1 TIMER_TCLR_1
#define TIMER_TCLR_1_POS (1U)
#define TIMER_TCLR_1_LEN (1U)
#define TIMER_TCLR_1_MSK (((1U<<TIMER_TCLR_1_LEN)-1)<<TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK (~(((1U<<TIMER_TCLR_1_LEN)-1)<<TIMER_TCLR_1_POS))
#define TIMER_TCLR_2 TIMER_TCLR_2
#define TIMER_TCLR_2_POS (2U)
#define TIMER_TCLR_2_LEN (1U)
#define TIMER_TCLR_2_MSK (((1U<<TIMER_TCLR_2_LEN)-1)<<TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK (~(((1U<<TIMER_TCLR_2_LEN)-1)<<TIMER_TCLR_2_POS))
/* 0x7C : TICR3 */
#define TIMER_TICR3_OFFSET (0x7C)
#define TIMER_TCLR_0 TIMER_TCLR_0
#define TIMER_TCLR_0_POS (0U)
#define TIMER_TCLR_0_LEN (1U)
#define TIMER_TCLR_0_MSK (((1U<<TIMER_TCLR_0_LEN)-1)<<TIMER_TCLR_0_POS)
#define TIMER_TCLR_0_UMSK (~(((1U<<TIMER_TCLR_0_LEN)-1)<<TIMER_TCLR_0_POS))
#define TIMER_TCLR_1 TIMER_TCLR_1
#define TIMER_TCLR_1_POS (1U)
#define TIMER_TCLR_1_LEN (1U)
#define TIMER_TCLR_1_MSK (((1U<<TIMER_TCLR_1_LEN)-1)<<TIMER_TCLR_1_POS)
#define TIMER_TCLR_1_UMSK (~(((1U<<TIMER_TCLR_1_LEN)-1)<<TIMER_TCLR_1_POS))
#define TIMER_TCLR_2 TIMER_TCLR_2
#define TIMER_TCLR_2_POS (2U)
#define TIMER_TCLR_2_LEN (1U)
#define TIMER_TCLR_2_MSK (((1U<<TIMER_TCLR_2_LEN)-1)<<TIMER_TCLR_2_POS)
#define TIMER_TCLR_2_UMSK (~(((1U<<TIMER_TCLR_2_LEN)-1)<<TIMER_TCLR_2_POS))
/* 0x80 : WICR */
#define TIMER_WICR_OFFSET (0x80)
#define TIMER_WICLR TIMER_WICLR
#define TIMER_WICLR_POS (0U)
#define TIMER_WICLR_LEN (1U)
#define TIMER_WICLR_MSK (((1U<<TIMER_WICLR_LEN)-1)<<TIMER_WICLR_POS)
#define TIMER_WICLR_UMSK (~(((1U<<TIMER_WICLR_LEN)-1)<<TIMER_WICLR_POS))
/* 0x84 : TCER */
#define TIMER_TCER_OFFSET (0x84)
#define TIMER2_EN TIMER2_EN
#define TIMER2_EN_POS (1U)
#define TIMER2_EN_LEN (1U)
#define TIMER2_EN_MSK (((1U<<TIMER2_EN_LEN)-1)<<TIMER2_EN_POS)
#define TIMER2_EN_UMSK (~(((1U<<TIMER2_EN_LEN)-1)<<TIMER2_EN_POS))
#define TIMER3_EN TIMER3_EN
#define TIMER3_EN_POS (2U)
#define TIMER3_EN_LEN (1U)
#define TIMER3_EN_MSK (((1U<<TIMER3_EN_LEN)-1)<<TIMER3_EN_POS)
#define TIMER3_EN_UMSK (~(((1U<<TIMER3_EN_LEN)-1)<<TIMER3_EN_POS))
/* 0x88 : TCMR */
#define TIMER_TCMR_OFFSET (0x88)
#define TIMER2_MODE TIMER2_MODE
#define TIMER2_MODE_POS (1U)
#define TIMER2_MODE_LEN (1U)
#define TIMER2_MODE_MSK (((1U<<TIMER2_MODE_LEN)-1)<<TIMER2_MODE_POS)
#define TIMER2_MODE_UMSK (~(((1U<<TIMER2_MODE_LEN)-1)<<TIMER2_MODE_POS))
#define TIMER3_MODE TIMER3_MODE
#define TIMER3_MODE_POS (2U)
#define TIMER3_MODE_LEN (1U)
#define TIMER3_MODE_MSK (((1U<<TIMER3_MODE_LEN)-1)<<TIMER3_MODE_POS)
#define TIMER3_MODE_UMSK (~(((1U<<TIMER3_MODE_LEN)-1)<<TIMER3_MODE_POS))
/* 0x90 : TILR2 */
#define TIMER_TILR2_OFFSET (0x90)
#define TIMER_TILR_0 TIMER_TILR_0
#define TIMER_TILR_0_POS (0U)
#define TIMER_TILR_0_LEN (1U)
#define TIMER_TILR_0_MSK (((1U<<TIMER_TILR_0_LEN)-1)<<TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK (~(((1U<<TIMER_TILR_0_LEN)-1)<<TIMER_TILR_0_POS))
#define TIMER_TILR_1 TIMER_TILR_1
#define TIMER_TILR_1_POS (1U)
#define TIMER_TILR_1_LEN (1U)
#define TIMER_TILR_1_MSK (((1U<<TIMER_TILR_1_LEN)-1)<<TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK (~(((1U<<TIMER_TILR_1_LEN)-1)<<TIMER_TILR_1_POS))
#define TIMER_TILR_2 TIMER_TILR_2
#define TIMER_TILR_2_POS (2U)
#define TIMER_TILR_2_LEN (1U)
#define TIMER_TILR_2_MSK (((1U<<TIMER_TILR_2_LEN)-1)<<TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK (~(((1U<<TIMER_TILR_2_LEN)-1)<<TIMER_TILR_2_POS))
/* 0x94 : TILR3 */
#define TIMER_TILR3_OFFSET (0x94)
#define TIMER_TILR_0 TIMER_TILR_0
#define TIMER_TILR_0_POS (0U)
#define TIMER_TILR_0_LEN (1U)
#define TIMER_TILR_0_MSK (((1U<<TIMER_TILR_0_LEN)-1)<<TIMER_TILR_0_POS)
#define TIMER_TILR_0_UMSK (~(((1U<<TIMER_TILR_0_LEN)-1)<<TIMER_TILR_0_POS))
#define TIMER_TILR_1 TIMER_TILR_1
#define TIMER_TILR_1_POS (1U)
#define TIMER_TILR_1_LEN (1U)
#define TIMER_TILR_1_MSK (((1U<<TIMER_TILR_1_LEN)-1)<<TIMER_TILR_1_POS)
#define TIMER_TILR_1_UMSK (~(((1U<<TIMER_TILR_1_LEN)-1)<<TIMER_TILR_1_POS))
#define TIMER_TILR_2 TIMER_TILR_2
#define TIMER_TILR_2_POS (2U)
#define TIMER_TILR_2_LEN (1U)
#define TIMER_TILR_2_MSK (((1U<<TIMER_TILR_2_LEN)-1)<<TIMER_TILR_2_POS)
#define TIMER_TILR_2_UMSK (~(((1U<<TIMER_TILR_2_LEN)-1)<<TIMER_TILR_2_POS))
/* 0x98 : WCR */
#define TIMER_WCR_OFFSET (0x98)
#define TIMER_WCR TIMER_WCR
#define TIMER_WCR_POS (0U)
#define TIMER_WCR_LEN (1U)
#define TIMER_WCR_MSK (((1U<<TIMER_WCR_LEN)-1)<<TIMER_WCR_POS)
#define TIMER_WCR_UMSK (~(((1U<<TIMER_WCR_LEN)-1)<<TIMER_WCR_POS))
/* 0x9C : WFAR */
#define TIMER_WFAR_OFFSET (0x9C)
#define TIMER_WFAR TIMER_WFAR
#define TIMER_WFAR_POS (0U)
#define TIMER_WFAR_LEN (16U)
#define TIMER_WFAR_MSK (((1U<<TIMER_WFAR_LEN)-1)<<TIMER_WFAR_POS)
#define TIMER_WFAR_UMSK (~(((1U<<TIMER_WFAR_LEN)-1)<<TIMER_WFAR_POS))
/* 0xA0 : WSAR */
#define TIMER_WSAR_OFFSET (0xA0)
#define TIMER_WSAR TIMER_WSAR
#define TIMER_WSAR_POS (0U)
#define TIMER_WSAR_LEN (16U)
#define TIMER_WSAR_MSK (((1U<<TIMER_WSAR_LEN)-1)<<TIMER_WSAR_POS)
#define TIMER_WSAR_UMSK (~(((1U<<TIMER_WSAR_LEN)-1)<<TIMER_WSAR_POS))
/* 0xA8 : TCVWR2 */
#define TIMER_TCVWR2_OFFSET (0xA8)
#define TIMER_TCVWR TIMER_TCVWR
#define TIMER_TCVWR_POS (0U)
#define TIMER_TCVWR_LEN (32U)
#define TIMER_TCVWR_MSK (((1U<<TIMER_TCVWR_LEN)-1)<<TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK (~(((1U<<TIMER_TCVWR_LEN)-1)<<TIMER_TCVWR_POS))
/* 0xAC : TCVWR3 */
#define TIMER_TCVWR3_OFFSET (0xAC)
#define TIMER_TCVWR TIMER_TCVWR
#define TIMER_TCVWR_POS (0U)
#define TIMER_TCVWR_LEN (32U)
#define TIMER_TCVWR_MSK (((1U<<TIMER_TCVWR_LEN)-1)<<TIMER_TCVWR_POS)
#define TIMER_TCVWR_UMSK (~(((1U<<TIMER_TCVWR_LEN)-1)<<TIMER_TCVWR_POS))
/* 0xB4 : TCVSYN2 */
#define TIMER_TCVSYN2_OFFSET (0xB4)
#define TIMER_TCVSYN2 TIMER_TCVSYN2
#define TIMER_TCVSYN2_POS (0U)
#define TIMER_TCVSYN2_LEN (32U)
#define TIMER_TCVSYN2_MSK (((1U<<TIMER_TCVSYN2_LEN)-1)<<TIMER_TCVSYN2_POS)
#define TIMER_TCVSYN2_UMSK (~(((1U<<TIMER_TCVSYN2_LEN)-1)<<TIMER_TCVSYN2_POS))
/* 0xB8 : TCVSYN3 */
#define TIMER_TCVSYN3_OFFSET (0xB8)
#define TIMER_TCVSYN3 TIMER_TCVSYN3
#define TIMER_TCVSYN3_POS (0U)
#define TIMER_TCVSYN3_LEN (32U)
#define TIMER_TCVSYN3_MSK (((1U<<TIMER_TCVSYN3_LEN)-1)<<TIMER_TCVSYN3_POS)
#define TIMER_TCVSYN3_UMSK (~(((1U<<TIMER_TCVSYN3_LEN)-1)<<TIMER_TCVSYN3_POS))
/* 0xBC : TCDR */
#define TIMER_TCDR_OFFSET (0xBC)
#define TIMER_TCDR2 TIMER_TCDR2
#define TIMER_TCDR2_POS (8U)
#define TIMER_TCDR2_LEN (8U)
#define TIMER_TCDR2_MSK (((1U<<TIMER_TCDR2_LEN)-1)<<TIMER_TCDR2_POS)
#define TIMER_TCDR2_UMSK (~(((1U<<TIMER_TCDR2_LEN)-1)<<TIMER_TCDR2_POS))
#define TIMER_TCDR3 TIMER_TCDR3
#define TIMER_TCDR3_POS (16U)
#define TIMER_TCDR3_LEN (8U)
#define TIMER_TCDR3_MSK (((1U<<TIMER_TCDR3_LEN)-1)<<TIMER_TCDR3_POS)
#define TIMER_TCDR3_UMSK (~(((1U<<TIMER_TCDR3_LEN)-1)<<TIMER_TCDR3_POS))
#define TIMER_WCDR TIMER_WCDR
#define TIMER_WCDR_POS (24U)
#define TIMER_WCDR_LEN (8U)
#define TIMER_WCDR_MSK (((1U<<TIMER_WCDR_LEN)-1)<<TIMER_WCDR_POS)
#define TIMER_WCDR_UMSK (~(((1U<<TIMER_WCDR_LEN)-1)<<TIMER_WCDR_POS))
struct timer_reg {
/* 0x0 : TCCR */
union {
struct {
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
uint32_t cs_1 : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t RESERVED_4 : 1; /* [ 4], rsvd, 0x0 */
uint32_t cs_2 : 2; /* [ 6: 5], r/w, 0x0 */
uint32_t RESERVED_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t cs_wdt : 2; /* [ 9: 8], r/w, 0x0 */
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TCCR;
/* 0x4 reserved */
uint8_t RESERVED0x4[12];
/* 0x10 : TMR2_0 */
union {
struct {
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} TMR2_0;
/* 0x14 : TMR2_1 */
union {
struct {
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} TMR2_1;
/* 0x18 : TMR2_2 */
union {
struct {
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} TMR2_2;
/* 0x1C : TMR3_0 */
union {
struct {
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} TMR3_0;
/* 0x20 : TMR3_1 */
union {
struct {
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} TMR3_1;
/* 0x24 : TMR3_2 */
union {
struct {
uint32_t tmr : 32; /* [31: 0], r/w, 0xffffffffL */
}BF;
uint32_t WORD;
} TMR3_2;
/* 0x28 reserved */
uint8_t RESERVED0x28[4];
/* 0x2C : TCR2 */
union {
struct {
uint32_t tcr : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} TCR2;
/* 0x30 : TCR3 */
union {
struct {
uint32_t tcr3_counter : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} TCR3;
/* 0x34 reserved */
uint8_t RESERVED0x34[4];
/* 0x38 : TMSR2 */
union {
struct {
uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */
uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */
uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TMSR2;
/* 0x3C : TMSR3 */
union {
struct {
uint32_t tmsr_0 : 1; /* [ 0], r, 0x0 */
uint32_t tmsr_1 : 1; /* [ 1], r, 0x0 */
uint32_t tmsr_2 : 1; /* [ 2], r, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TMSR3;
/* 0x40 reserved */
uint8_t RESERVED0x40[4];
/* 0x44 : TIER2 */
union {
struct {
uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TIER2;
/* 0x48 : TIER3 */
union {
struct {
uint32_t tier_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tier_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tier_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TIER3;
/* 0x4c reserved */
uint8_t RESERVED0x4c[4];
/* 0x50 : TPLVR2 */
union {
struct {
uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} TPLVR2;
/* 0x54 : TPLVR3 */
union {
struct {
uint32_t tplvr : 32; /* [31: 0], r/w, 0x0 */
}BF;
uint32_t WORD;
} TPLVR3;
/* 0x58 reserved */
uint8_t RESERVED0x58[4];
/* 0x5C : TPLCR2 */
union {
struct {
uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TPLCR2;
/* 0x60 : TPLCR3 */
union {
struct {
uint32_t tplcr : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TPLCR3;
/* 0x64 : WMER */
union {
struct {
uint32_t we : 1; /* [ 0], r/w, 0x0 */
uint32_t wrie : 1; /* [ 1], r/w, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WMER;
/* 0x68 : WMR */
union {
struct {
uint32_t wmr : 16; /* [15: 0], r/w, 0xffff */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WMR;
/* 0x6C : WVR */
union {
struct {
uint32_t wvr : 16; /* [15: 0], r, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WVR;
/* 0x70 : WSR */
union {
struct {
uint32_t wts : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WSR;
/* 0x74 reserved */
uint8_t RESERVED0x74[4];
/* 0x78 : TICR2 */
union {
struct {
uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */
uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */
uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TICR2;
/* 0x7C : TICR3 */
union {
struct {
uint32_t tclr_0 : 1; /* [ 0], w, 0x0 */
uint32_t tclr_1 : 1; /* [ 1], w, 0x0 */
uint32_t tclr_2 : 1; /* [ 2], w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TICR3;
/* 0x80 : WICR */
union {
struct {
uint32_t wiclr : 1; /* [ 0], w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WICR;
/* 0x84 : TCER */
union {
struct {
uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
uint32_t timer2_en : 1; /* [ 1], r/w, 0x0 */
uint32_t timer3_en : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TCER;
/* 0x88 : TCMR */
union {
struct {
uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
uint32_t timer2_mode : 1; /* [ 1], r/w, 0x0 */
uint32_t timer3_mode : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TCMR;
/* 0x8c reserved */
uint8_t RESERVED0x8c[4];
/* 0x90 : TILR2 */
union {
struct {
uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TILR2;
/* 0x94 : TILR3 */
union {
struct {
uint32_t tilr_0 : 1; /* [ 0], r/w, 0x0 */
uint32_t tilr_1 : 1; /* [ 1], r/w, 0x0 */
uint32_t tilr_2 : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
}BF;
uint32_t WORD;
} TILR3;
/* 0x98 : WCR */
union {
struct {
uint32_t wcr : 1; /* [ 0], w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WCR;
/* 0x9C : WFAR */
union {
struct {
uint32_t wfar : 16; /* [15: 0], w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WFAR;
/* 0xA0 : WSAR */
union {
struct {
uint32_t wsar : 16; /* [15: 0], w, 0x0 */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} WSAR;
/* 0xa4 reserved */
uint8_t RESERVED0xa4[4];
/* 0xA8 : TCVWR2 */
union {
struct {
uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} TCVWR2;
/* 0xAC : TCVWR3 */
union {
struct {
uint32_t tcvwr : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} TCVWR3;
/* 0xb0 reserved */
uint8_t RESERVED0xb0[4];
/* 0xB4 : TCVSYN2 */
union {
struct {
uint32_t tcvsyn2 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} TCVSYN2;
/* 0xB8 : TCVSYN3 */
union {
struct {
uint32_t tcvsyn3 : 32; /* [31: 0], r, 0x0 */
}BF;
uint32_t WORD;
} TCVSYN3;
/* 0xBC : TCDR */
union {
struct {
uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */
uint32_t tcdr2 : 8; /* [15: 8], r/w, 0x0 */
uint32_t tcdr3 : 8; /* [23:16], r/w, 0x0 */
uint32_t wcdr : 8; /* [31:24], r/w, 0x0 */
}BF;
uint32_t WORD;
} TCDR;
};
typedef volatile struct timer_reg timer_reg_t;
#endif /* __TIMER_REG_H__ */

254
drivers/bl602_driver/regs/tzc_nsec_reg.h Normal file
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@ -0,0 +1,254 @@
/**
******************************************************************************
* @file tzc_nsec_reg.h
* @version V1.2
* @date 2019-11-20
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __TZC_NSEC_REG_H__
#define __TZC_NSEC_REG_H__
#include "bl602.h"
/* 0x40 : tzc_rom_ctrl */
#define TZC_NSEC_TZC_ROM_CTRL_OFFSET (0x40)
#define TZC_NSEC_TZC_ROM0_R0_ID0_EN TZC_NSEC_TZC_ROM0_R0_ID0_EN
#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS (0U)
#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_MSK (((1U<<TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS)
#define TZC_NSEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R0_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_ID0_EN_POS))
#define TZC_NSEC_TZC_ROM0_R1_ID0_EN TZC_NSEC_TZC_ROM0_R1_ID0_EN
#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_POS (1U)
#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_MSK (((1U<<TZC_NSEC_TZC_ROM0_R1_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_ID0_EN_POS)
#define TZC_NSEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R1_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_ID0_EN_POS))
#define TZC_NSEC_TZC_ROM1_R0_ID0_EN TZC_NSEC_TZC_ROM1_R0_ID0_EN
#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_POS (2U)
#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_MSK (((1U<<TZC_NSEC_TZC_ROM1_R0_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_ID0_EN_POS)
#define TZC_NSEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R0_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_ID0_EN_POS))
#define TZC_NSEC_TZC_ROM1_R1_ID0_EN TZC_NSEC_TZC_ROM1_R1_ID0_EN
#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_POS (3U)
#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_MSK (((1U<<TZC_NSEC_TZC_ROM1_R1_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_ID0_EN_POS)
#define TZC_NSEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R1_ID0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_ID0_EN_POS))
#define TZC_NSEC_TZC_ROM0_R0_ID1_EN TZC_NSEC_TZC_ROM0_R0_ID1_EN
#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_POS (8U)
#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_MSK (((1U<<TZC_NSEC_TZC_ROM0_R0_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_ID1_EN_POS)
#define TZC_NSEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R0_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_ID1_EN_POS))
#define TZC_NSEC_TZC_ROM0_R1_ID1_EN TZC_NSEC_TZC_ROM0_R1_ID1_EN
#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_POS (9U)
#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_MSK (((1U<<TZC_NSEC_TZC_ROM0_R1_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_ID1_EN_POS)
#define TZC_NSEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R1_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_ID1_EN_POS))
#define TZC_NSEC_TZC_ROM1_R0_ID1_EN TZC_NSEC_TZC_ROM1_R0_ID1_EN
#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_POS (10U)
#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_MSK (((1U<<TZC_NSEC_TZC_ROM1_R0_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_ID1_EN_POS)
#define TZC_NSEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R0_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_ID1_EN_POS))
#define TZC_NSEC_TZC_ROM1_R1_ID1_EN TZC_NSEC_TZC_ROM1_R1_ID1_EN
#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_POS (11U)
#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_MSK (((1U<<TZC_NSEC_TZC_ROM1_R1_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_ID1_EN_POS)
#define TZC_NSEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R1_ID1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_ID1_EN_POS))
#define TZC_NSEC_TZC_ROM0_R0_EN TZC_NSEC_TZC_ROM0_R0_EN
#define TZC_NSEC_TZC_ROM0_R0_EN_POS (16U)
#define TZC_NSEC_TZC_ROM0_R0_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R0_EN_MSK (((1U<<TZC_NSEC_TZC_ROM0_R0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_EN_POS)
#define TZC_NSEC_TZC_ROM0_R0_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_EN_POS))
#define TZC_NSEC_TZC_ROM0_R1_EN TZC_NSEC_TZC_ROM0_R1_EN
#define TZC_NSEC_TZC_ROM0_R1_EN_POS (17U)
#define TZC_NSEC_TZC_ROM0_R1_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R1_EN_MSK (((1U<<TZC_NSEC_TZC_ROM0_R1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_EN_POS)
#define TZC_NSEC_TZC_ROM0_R1_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_EN_POS))
#define TZC_NSEC_TZC_ROM1_R0_EN TZC_NSEC_TZC_ROM1_R0_EN
#define TZC_NSEC_TZC_ROM1_R0_EN_POS (18U)
#define TZC_NSEC_TZC_ROM1_R0_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R0_EN_MSK (((1U<<TZC_NSEC_TZC_ROM1_R0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_EN_POS)
#define TZC_NSEC_TZC_ROM1_R0_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R0_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_EN_POS))
#define TZC_NSEC_TZC_ROM1_R1_EN TZC_NSEC_TZC_ROM1_R1_EN
#define TZC_NSEC_TZC_ROM1_R1_EN_POS (19U)
#define TZC_NSEC_TZC_ROM1_R1_EN_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R1_EN_MSK (((1U<<TZC_NSEC_TZC_ROM1_R1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_EN_POS)
#define TZC_NSEC_TZC_ROM1_R1_EN_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R1_EN_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_EN_POS))
#define TZC_NSEC_TZC_ROM0_R0_LOCK TZC_NSEC_TZC_ROM0_R0_LOCK
#define TZC_NSEC_TZC_ROM0_R0_LOCK_POS (24U)
#define TZC_NSEC_TZC_ROM0_R0_LOCK_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R0_LOCK_MSK (((1U<<TZC_NSEC_TZC_ROM0_R0_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_LOCK_POS)
#define TZC_NSEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R0_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_LOCK_POS))
#define TZC_NSEC_TZC_ROM0_R1_LOCK TZC_NSEC_TZC_ROM0_R1_LOCK
#define TZC_NSEC_TZC_ROM0_R1_LOCK_POS (25U)
#define TZC_NSEC_TZC_ROM0_R1_LOCK_LEN (1U)
#define TZC_NSEC_TZC_ROM0_R1_LOCK_MSK (((1U<<TZC_NSEC_TZC_ROM0_R1_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_LOCK_POS)
#define TZC_NSEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R1_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_LOCK_POS))
#define TZC_NSEC_TZC_ROM1_R0_LOCK TZC_NSEC_TZC_ROM1_R0_LOCK
#define TZC_NSEC_TZC_ROM1_R0_LOCK_POS (26U)
#define TZC_NSEC_TZC_ROM1_R0_LOCK_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R0_LOCK_MSK (((1U<<TZC_NSEC_TZC_ROM1_R0_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_LOCK_POS)
#define TZC_NSEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R0_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_LOCK_POS))
#define TZC_NSEC_TZC_ROM1_R1_LOCK TZC_NSEC_TZC_ROM1_R1_LOCK
#define TZC_NSEC_TZC_ROM1_R1_LOCK_POS (27U)
#define TZC_NSEC_TZC_ROM1_R1_LOCK_LEN (1U)
#define TZC_NSEC_TZC_ROM1_R1_LOCK_MSK (((1U<<TZC_NSEC_TZC_ROM1_R1_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_LOCK_POS)
#define TZC_NSEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R1_LOCK_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_LOCK_POS))
#define TZC_NSEC_TZC_SBOOT_DONE TZC_NSEC_TZC_SBOOT_DONE
#define TZC_NSEC_TZC_SBOOT_DONE_POS (28U)
#define TZC_NSEC_TZC_SBOOT_DONE_LEN (4U)
#define TZC_NSEC_TZC_SBOOT_DONE_MSK (((1U<<TZC_NSEC_TZC_SBOOT_DONE_LEN)-1)<<TZC_NSEC_TZC_SBOOT_DONE_POS)
#define TZC_NSEC_TZC_SBOOT_DONE_UMSK (~(((1U<<TZC_NSEC_TZC_SBOOT_DONE_LEN)-1)<<TZC_NSEC_TZC_SBOOT_DONE_POS))
/* 0x44 : tzc_rom0_r0 */
#define TZC_NSEC_TZC_ROM0_R0_OFFSET (0x44)
#define TZC_NSEC_TZC_ROM0_R0_END TZC_NSEC_TZC_ROM0_R0_END
#define TZC_NSEC_TZC_ROM0_R0_END_POS (0U)
#define TZC_NSEC_TZC_ROM0_R0_END_LEN (16U)
#define TZC_NSEC_TZC_ROM0_R0_END_MSK (((1U<<TZC_NSEC_TZC_ROM0_R0_END_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_END_POS)
#define TZC_NSEC_TZC_ROM0_R0_END_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R0_END_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_END_POS))
#define TZC_NSEC_TZC_ROM0_R0_START TZC_NSEC_TZC_ROM0_R0_START
#define TZC_NSEC_TZC_ROM0_R0_START_POS (16U)
#define TZC_NSEC_TZC_ROM0_R0_START_LEN (16U)
#define TZC_NSEC_TZC_ROM0_R0_START_MSK (((1U<<TZC_NSEC_TZC_ROM0_R0_START_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_START_POS)
#define TZC_NSEC_TZC_ROM0_R0_START_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R0_START_LEN)-1)<<TZC_NSEC_TZC_ROM0_R0_START_POS))
/* 0x48 : tzc_rom0_r1 */
#define TZC_NSEC_TZC_ROM0_R1_OFFSET (0x48)
#define TZC_NSEC_TZC_ROM0_R1_END TZC_NSEC_TZC_ROM0_R1_END
#define TZC_NSEC_TZC_ROM0_R1_END_POS (0U)
#define TZC_NSEC_TZC_ROM0_R1_END_LEN (16U)
#define TZC_NSEC_TZC_ROM0_R1_END_MSK (((1U<<TZC_NSEC_TZC_ROM0_R1_END_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_END_POS)
#define TZC_NSEC_TZC_ROM0_R1_END_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R1_END_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_END_POS))
#define TZC_NSEC_TZC_ROM0_R1_START TZC_NSEC_TZC_ROM0_R1_START
#define TZC_NSEC_TZC_ROM0_R1_START_POS (16U)
#define TZC_NSEC_TZC_ROM0_R1_START_LEN (16U)
#define TZC_NSEC_TZC_ROM0_R1_START_MSK (((1U<<TZC_NSEC_TZC_ROM0_R1_START_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_START_POS)
#define TZC_NSEC_TZC_ROM0_R1_START_UMSK (~(((1U<<TZC_NSEC_TZC_ROM0_R1_START_LEN)-1)<<TZC_NSEC_TZC_ROM0_R1_START_POS))
/* 0x4C : tzc_rom1_r0 */
#define TZC_NSEC_TZC_ROM1_R0_OFFSET (0x4C)
#define TZC_NSEC_TZC_ROM1_R0_END TZC_NSEC_TZC_ROM1_R0_END
#define TZC_NSEC_TZC_ROM1_R0_END_POS (0U)
#define TZC_NSEC_TZC_ROM1_R0_END_LEN (16U)
#define TZC_NSEC_TZC_ROM1_R0_END_MSK (((1U<<TZC_NSEC_TZC_ROM1_R0_END_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_END_POS)
#define TZC_NSEC_TZC_ROM1_R0_END_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R0_END_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_END_POS))
#define TZC_NSEC_TZC_ROM1_R0_START TZC_NSEC_TZC_ROM1_R0_START
#define TZC_NSEC_TZC_ROM1_R0_START_POS (16U)
#define TZC_NSEC_TZC_ROM1_R0_START_LEN (16U)
#define TZC_NSEC_TZC_ROM1_R0_START_MSK (((1U<<TZC_NSEC_TZC_ROM1_R0_START_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_START_POS)
#define TZC_NSEC_TZC_ROM1_R0_START_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R0_START_LEN)-1)<<TZC_NSEC_TZC_ROM1_R0_START_POS))
/* 0x50 : tzc_rom1_r1 */
#define TZC_NSEC_TZC_ROM1_R1_OFFSET (0x50)
#define TZC_NSEC_TZC_ROM1_R1_END TZC_NSEC_TZC_ROM1_R1_END
#define TZC_NSEC_TZC_ROM1_R1_END_POS (0U)
#define TZC_NSEC_TZC_ROM1_R1_END_LEN (16U)
#define TZC_NSEC_TZC_ROM1_R1_END_MSK (((1U<<TZC_NSEC_TZC_ROM1_R1_END_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_END_POS)
#define TZC_NSEC_TZC_ROM1_R1_END_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R1_END_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_END_POS))
#define TZC_NSEC_TZC_ROM1_R1_START TZC_NSEC_TZC_ROM1_R1_START
#define TZC_NSEC_TZC_ROM1_R1_START_POS (16U)
#define TZC_NSEC_TZC_ROM1_R1_START_LEN (16U)
#define TZC_NSEC_TZC_ROM1_R1_START_MSK (((1U<<TZC_NSEC_TZC_ROM1_R1_START_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_START_POS)
#define TZC_NSEC_TZC_ROM1_R1_START_UMSK (~(((1U<<TZC_NSEC_TZC_ROM1_R1_START_LEN)-1)<<TZC_NSEC_TZC_ROM1_R1_START_POS))
struct tzc_nsec_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[64];
/* 0x40 : tzc_rom_ctrl */
union {
struct {
uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r, 0x1 */
uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r, 0x1 */
uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r, 0x1 */
uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r, 0x1 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r, 0x1 */
uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r, 0x1 */
uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r, 0x1 */
uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r, 0x1 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t tzc_rom0_r0_en : 1; /* [ 16], r, 0x0 */
uint32_t tzc_rom0_r1_en : 1; /* [ 17], r, 0x0 */
uint32_t tzc_rom1_r0_en : 1; /* [ 18], r, 0x0 */
uint32_t tzc_rom1_r1_en : 1; /* [ 19], r, 0x0 */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r, 0x0 */
uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r, 0x0 */
uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r, 0x0 */
uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r, 0x0 */
uint32_t tzc_sboot_done : 4; /* [31:28], r, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom_ctrl;
/* 0x44 : tzc_rom0_r0 */
union {
struct {
uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r, 0xffff */
uint32_t tzc_rom0_r0_start : 16; /* [31:16], r, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom0_r0;
/* 0x48 : tzc_rom0_r1 */
union {
struct {
uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r, 0xffff */
uint32_t tzc_rom0_r1_start : 16; /* [31:16], r, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom0_r1;
/* 0x4C : tzc_rom1_r0 */
union {
struct {
uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r, 0xffff */
uint32_t tzc_rom1_r0_start : 16; /* [31:16], r, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom1_r0;
/* 0x50 : tzc_rom1_r1 */
union {
struct {
uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r, 0xffff */
uint32_t tzc_rom1_r1_start : 16; /* [31:16], r, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom1_r1;
};
typedef volatile struct tzc_nsec_reg tzc_nsec_reg_t;
#endif /* __TZC_NSEC_REG_H__ */

254
drivers/bl602_driver/regs/tzc_sec_reg.h Normal file
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@ -0,0 +1,254 @@
/**
******************************************************************************
* @file tzc_sec_reg.h
* @version V1.2
* @date 2020-04-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __TZC_SEC_REG_H__
#define __TZC_SEC_REG_H__
#include "bl602.h"
/* 0x40 : tzc_rom_ctrl */
#define TZC_SEC_TZC_ROM_CTRL_OFFSET (0x40)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN TZC_SEC_TZC_ROM0_R0_ID0_EN
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS (0U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK (((1U<<TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID0_EN TZC_SEC_TZC_ROM0_R1_ID0_EN
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK (((1U<<TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID0_EN TZC_SEC_TZC_ROM1_R0_ID0_EN
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS (2U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK (((1U<<TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID0_EN TZC_SEC_TZC_ROM1_R1_ID0_EN
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS (3U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK (((1U<<TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_ID1_EN TZC_SEC_TZC_ROM0_R0_ID1_EN
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS (8U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK (((1U<<TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_ID1_EN TZC_SEC_TZC_ROM0_R1_ID1_EN
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS (9U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK (((1U<<TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_ID1_EN TZC_SEC_TZC_ROM1_R0_ID1_EN
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS (10U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK (((1U<<TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_ID1_EN TZC_SEC_TZC_ROM1_R1_ID1_EN
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS (11U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK (((1U<<TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_EN TZC_SEC_TZC_ROM0_R0_EN
#define TZC_SEC_TZC_ROM0_R0_EN_POS (16U)
#define TZC_SEC_TZC_ROM0_R0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_EN_MSK (((1U<<TZC_SEC_TZC_ROM0_R0_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_EN_POS)
#define TZC_SEC_TZC_ROM0_R0_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R0_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_EN_POS))
#define TZC_SEC_TZC_ROM0_R1_EN TZC_SEC_TZC_ROM0_R1_EN
#define TZC_SEC_TZC_ROM0_R1_EN_POS (17U)
#define TZC_SEC_TZC_ROM0_R1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_EN_MSK (((1U<<TZC_SEC_TZC_ROM0_R1_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_EN_POS)
#define TZC_SEC_TZC_ROM0_R1_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R1_EN_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_EN_POS))
#define TZC_SEC_TZC_ROM1_R0_EN TZC_SEC_TZC_ROM1_R0_EN
#define TZC_SEC_TZC_ROM1_R0_EN_POS (18U)
#define TZC_SEC_TZC_ROM1_R0_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_EN_MSK (((1U<<TZC_SEC_TZC_ROM1_R0_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_EN_POS)
#define TZC_SEC_TZC_ROM1_R0_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R0_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_EN_POS))
#define TZC_SEC_TZC_ROM1_R1_EN TZC_SEC_TZC_ROM1_R1_EN
#define TZC_SEC_TZC_ROM1_R1_EN_POS (19U)
#define TZC_SEC_TZC_ROM1_R1_EN_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_EN_MSK (((1U<<TZC_SEC_TZC_ROM1_R1_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_EN_POS)
#define TZC_SEC_TZC_ROM1_R1_EN_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R1_EN_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_EN_POS))
#define TZC_SEC_TZC_ROM0_R0_LOCK TZC_SEC_TZC_ROM0_R0_LOCK
#define TZC_SEC_TZC_ROM0_R0_LOCK_POS (24U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK (((1U<<TZC_SEC_TZC_ROM0_R0_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R0_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM0_R1_LOCK TZC_SEC_TZC_ROM0_R1_LOCK
#define TZC_SEC_TZC_ROM0_R1_LOCK_POS (25U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK (((1U<<TZC_SEC_TZC_ROM0_R1_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R1_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R0_LOCK TZC_SEC_TZC_ROM1_R0_LOCK
#define TZC_SEC_TZC_ROM1_R0_LOCK_POS (26U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK (((1U<<TZC_SEC_TZC_ROM1_R0_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R0_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_LOCK_POS))
#define TZC_SEC_TZC_ROM1_R1_LOCK TZC_SEC_TZC_ROM1_R1_LOCK
#define TZC_SEC_TZC_ROM1_R1_LOCK_POS (27U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN (1U)
#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK (((1U<<TZC_SEC_TZC_ROM1_R1_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_LOCK_POS)
#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R1_LOCK_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_LOCK_POS))
#define TZC_SEC_TZC_SBOOT_DONE TZC_SEC_TZC_SBOOT_DONE
#define TZC_SEC_TZC_SBOOT_DONE_POS (28U)
#define TZC_SEC_TZC_SBOOT_DONE_LEN (4U)
#define TZC_SEC_TZC_SBOOT_DONE_MSK (((1U<<TZC_SEC_TZC_SBOOT_DONE_LEN)-1)<<TZC_SEC_TZC_SBOOT_DONE_POS)
#define TZC_SEC_TZC_SBOOT_DONE_UMSK (~(((1U<<TZC_SEC_TZC_SBOOT_DONE_LEN)-1)<<TZC_SEC_TZC_SBOOT_DONE_POS))
/* 0x44 : tzc_rom0_r0 */
#define TZC_SEC_TZC_ROM0_R0_OFFSET (0x44)
#define TZC_SEC_TZC_ROM0_R0_END TZC_SEC_TZC_ROM0_R0_END
#define TZC_SEC_TZC_ROM0_R0_END_POS (0U)
#define TZC_SEC_TZC_ROM0_R0_END_LEN (16U)
#define TZC_SEC_TZC_ROM0_R0_END_MSK (((1U<<TZC_SEC_TZC_ROM0_R0_END_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_END_POS)
#define TZC_SEC_TZC_ROM0_R0_END_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R0_END_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_END_POS))
#define TZC_SEC_TZC_ROM0_R0_START TZC_SEC_TZC_ROM0_R0_START
#define TZC_SEC_TZC_ROM0_R0_START_POS (16U)
#define TZC_SEC_TZC_ROM0_R0_START_LEN (16U)
#define TZC_SEC_TZC_ROM0_R0_START_MSK (((1U<<TZC_SEC_TZC_ROM0_R0_START_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_START_POS)
#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R0_START_LEN)-1)<<TZC_SEC_TZC_ROM0_R0_START_POS))
/* 0x48 : tzc_rom0_r1 */
#define TZC_SEC_TZC_ROM0_R1_OFFSET (0x48)
#define TZC_SEC_TZC_ROM0_R1_END TZC_SEC_TZC_ROM0_R1_END
#define TZC_SEC_TZC_ROM0_R1_END_POS (0U)
#define TZC_SEC_TZC_ROM0_R1_END_LEN (16U)
#define TZC_SEC_TZC_ROM0_R1_END_MSK (((1U<<TZC_SEC_TZC_ROM0_R1_END_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_END_POS)
#define TZC_SEC_TZC_ROM0_R1_END_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R1_END_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_END_POS))
#define TZC_SEC_TZC_ROM0_R1_START TZC_SEC_TZC_ROM0_R1_START
#define TZC_SEC_TZC_ROM0_R1_START_POS (16U)
#define TZC_SEC_TZC_ROM0_R1_START_LEN (16U)
#define TZC_SEC_TZC_ROM0_R1_START_MSK (((1U<<TZC_SEC_TZC_ROM0_R1_START_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_START_POS)
#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U<<TZC_SEC_TZC_ROM0_R1_START_LEN)-1)<<TZC_SEC_TZC_ROM0_R1_START_POS))
/* 0x4C : tzc_rom1_r0 */
#define TZC_SEC_TZC_ROM1_R0_OFFSET (0x4C)
#define TZC_SEC_TZC_ROM1_R0_END TZC_SEC_TZC_ROM1_R0_END
#define TZC_SEC_TZC_ROM1_R0_END_POS (0U)
#define TZC_SEC_TZC_ROM1_R0_END_LEN (16U)
#define TZC_SEC_TZC_ROM1_R0_END_MSK (((1U<<TZC_SEC_TZC_ROM1_R0_END_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_END_POS)
#define TZC_SEC_TZC_ROM1_R0_END_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R0_END_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_END_POS))
#define TZC_SEC_TZC_ROM1_R0_START TZC_SEC_TZC_ROM1_R0_START
#define TZC_SEC_TZC_ROM1_R0_START_POS (16U)
#define TZC_SEC_TZC_ROM1_R0_START_LEN (16U)
#define TZC_SEC_TZC_ROM1_R0_START_MSK (((1U<<TZC_SEC_TZC_ROM1_R0_START_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_START_POS)
#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R0_START_LEN)-1)<<TZC_SEC_TZC_ROM1_R0_START_POS))
/* 0x50 : tzc_rom1_r1 */
#define TZC_SEC_TZC_ROM1_R1_OFFSET (0x50)
#define TZC_SEC_TZC_ROM1_R1_END TZC_SEC_TZC_ROM1_R1_END
#define TZC_SEC_TZC_ROM1_R1_END_POS (0U)
#define TZC_SEC_TZC_ROM1_R1_END_LEN (16U)
#define TZC_SEC_TZC_ROM1_R1_END_MSK (((1U<<TZC_SEC_TZC_ROM1_R1_END_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_END_POS)
#define TZC_SEC_TZC_ROM1_R1_END_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R1_END_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_END_POS))
#define TZC_SEC_TZC_ROM1_R1_START TZC_SEC_TZC_ROM1_R1_START
#define TZC_SEC_TZC_ROM1_R1_START_POS (16U)
#define TZC_SEC_TZC_ROM1_R1_START_LEN (16U)
#define TZC_SEC_TZC_ROM1_R1_START_MSK (((1U<<TZC_SEC_TZC_ROM1_R1_START_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_START_POS)
#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U<<TZC_SEC_TZC_ROM1_R1_START_LEN)-1)<<TZC_SEC_TZC_ROM1_R1_START_POS))
struct tzc_sec_reg {
/* 0x0 reserved */
uint8_t RESERVED0x0[64];
/* 0x40 : tzc_rom_ctrl */
union {
struct {
uint32_t tzc_rom0_r0_id0_en : 1; /* [ 0], r/w, 0x1 */
uint32_t tzc_rom0_r1_id0_en : 1; /* [ 1], r/w, 0x1 */
uint32_t tzc_rom1_r0_id0_en : 1; /* [ 2], r/w, 0x1 */
uint32_t tzc_rom1_r1_id0_en : 1; /* [ 3], r/w, 0x1 */
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
uint32_t tzc_rom0_r0_id1_en : 1; /* [ 8], r/w, 0x1 */
uint32_t tzc_rom0_r1_id1_en : 1; /* [ 9], r/w, 0x1 */
uint32_t tzc_rom1_r0_id1_en : 1; /* [ 10], r/w, 0x1 */
uint32_t tzc_rom1_r1_id1_en : 1; /* [ 11], r/w, 0x1 */
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
uint32_t tzc_rom0_r0_en : 1; /* [ 16], r/w, 0x0 */
uint32_t tzc_rom0_r1_en : 1; /* [ 17], r/w, 0x0 */
uint32_t tzc_rom1_r0_en : 1; /* [ 18], r/w, 0x0 */
uint32_t tzc_rom1_r1_en : 1; /* [ 19], r/w, 0x0 */
uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
uint32_t tzc_rom0_r0_lock : 1; /* [ 24], r/w, 0x0 */
uint32_t tzc_rom0_r1_lock : 1; /* [ 25], r/w, 0x0 */
uint32_t tzc_rom1_r0_lock : 1; /* [ 26], r/w, 0x0 */
uint32_t tzc_rom1_r1_lock : 1; /* [ 27], r/w, 0x0 */
uint32_t tzc_sboot_done : 4; /* [31:28], r/w, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom_ctrl;
/* 0x44 : tzc_rom0_r0 */
union {
struct {
uint32_t tzc_rom0_r0_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom0_r0_start : 16; /* [31:16], r/w, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom0_r0;
/* 0x48 : tzc_rom0_r1 */
union {
struct {
uint32_t tzc_rom0_r1_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom0_r1_start : 16; /* [31:16], r/w, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom0_r1;
/* 0x4C : tzc_rom1_r0 */
union {
struct {
uint32_t tzc_rom1_r0_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom1_r0_start : 16; /* [31:16], r/w, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom1_r0;
/* 0x50 : tzc_rom1_r1 */
union {
struct {
uint32_t tzc_rom1_r1_end : 16; /* [15: 0], r/w, 0xffff */
uint32_t tzc_rom1_r1_start : 16; /* [31:16], r/w, 0x0 */
}BF;
uint32_t WORD;
} tzc_rom1_r1;
};
typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
#endif /* __TZC_SEC_REG_H__ */

696
drivers/bl602_driver/regs/uart_reg.h Normal file
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@ -0,0 +1,696 @@
/**
******************************************************************************
* @file uart_reg.h
* @version V1.2
* @date 2019-10-21
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __UART_REG_H__
#define __UART_REG_H__
#include "bl602.h"
/* 0x0 : utx_config */
#define UART_UTX_CONFIG_OFFSET (0x0)
#define UART_CR_UTX_EN UART_CR_UTX_EN
#define UART_CR_UTX_EN_POS (0U)
#define UART_CR_UTX_EN_LEN (1U)
#define UART_CR_UTX_EN_MSK (((1U<<UART_CR_UTX_EN_LEN)-1)<<UART_CR_UTX_EN_POS)
#define UART_CR_UTX_EN_UMSK (~(((1U<<UART_CR_UTX_EN_LEN)-1)<<UART_CR_UTX_EN_POS))
#define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN
#define UART_CR_UTX_CTS_EN_POS (1U)
#define UART_CR_UTX_CTS_EN_LEN (1U)
#define UART_CR_UTX_CTS_EN_MSK (((1U<<UART_CR_UTX_CTS_EN_LEN)-1)<<UART_CR_UTX_CTS_EN_POS)
#define UART_CR_UTX_CTS_EN_UMSK (~(((1U<<UART_CR_UTX_CTS_EN_LEN)-1)<<UART_CR_UTX_CTS_EN_POS))
#define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN
#define UART_CR_UTX_FRM_EN_POS (2U)
#define UART_CR_UTX_FRM_EN_LEN (1U)
#define UART_CR_UTX_FRM_EN_MSK (((1U<<UART_CR_UTX_FRM_EN_LEN)-1)<<UART_CR_UTX_FRM_EN_POS)
#define UART_CR_UTX_FRM_EN_UMSK (~(((1U<<UART_CR_UTX_FRM_EN_LEN)-1)<<UART_CR_UTX_FRM_EN_POS))
#define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN
#define UART_CR_UTX_PRT_EN_POS (4U)
#define UART_CR_UTX_PRT_EN_LEN (1U)
#define UART_CR_UTX_PRT_EN_MSK (((1U<<UART_CR_UTX_PRT_EN_LEN)-1)<<UART_CR_UTX_PRT_EN_POS)
#define UART_CR_UTX_PRT_EN_UMSK (~(((1U<<UART_CR_UTX_PRT_EN_LEN)-1)<<UART_CR_UTX_PRT_EN_POS))
#define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL
#define UART_CR_UTX_PRT_SEL_POS (5U)
#define UART_CR_UTX_PRT_SEL_LEN (1U)
#define UART_CR_UTX_PRT_SEL_MSK (((1U<<UART_CR_UTX_PRT_SEL_LEN)-1)<<UART_CR_UTX_PRT_SEL_POS)
#define UART_CR_UTX_PRT_SEL_UMSK (~(((1U<<UART_CR_UTX_PRT_SEL_LEN)-1)<<UART_CR_UTX_PRT_SEL_POS))
#define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN
#define UART_CR_UTX_IR_EN_POS (6U)
#define UART_CR_UTX_IR_EN_LEN (1U)
#define UART_CR_UTX_IR_EN_MSK (((1U<<UART_CR_UTX_IR_EN_LEN)-1)<<UART_CR_UTX_IR_EN_POS)
#define UART_CR_UTX_IR_EN_UMSK (~(((1U<<UART_CR_UTX_IR_EN_LEN)-1)<<UART_CR_UTX_IR_EN_POS))
#define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV
#define UART_CR_UTX_IR_INV_POS (7U)
#define UART_CR_UTX_IR_INV_LEN (1U)
#define UART_CR_UTX_IR_INV_MSK (((1U<<UART_CR_UTX_IR_INV_LEN)-1)<<UART_CR_UTX_IR_INV_POS)
#define UART_CR_UTX_IR_INV_UMSK (~(((1U<<UART_CR_UTX_IR_INV_LEN)-1)<<UART_CR_UTX_IR_INV_POS))
#define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D
#define UART_CR_UTX_BIT_CNT_D_POS (8U)
#define UART_CR_UTX_BIT_CNT_D_LEN (3U)
#define UART_CR_UTX_BIT_CNT_D_MSK (((1U<<UART_CR_UTX_BIT_CNT_D_LEN)-1)<<UART_CR_UTX_BIT_CNT_D_POS)
#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U<<UART_CR_UTX_BIT_CNT_D_LEN)-1)<<UART_CR_UTX_BIT_CNT_D_POS))
#define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P
#define UART_CR_UTX_BIT_CNT_P_POS (12U)
#define UART_CR_UTX_BIT_CNT_P_LEN (2U)
#define UART_CR_UTX_BIT_CNT_P_MSK (((1U<<UART_CR_UTX_BIT_CNT_P_LEN)-1)<<UART_CR_UTX_BIT_CNT_P_POS)
#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U<<UART_CR_UTX_BIT_CNT_P_LEN)-1)<<UART_CR_UTX_BIT_CNT_P_POS))
#define UART_CR_UTX_LEN UART_CR_UTX_LEN
#define UART_CR_UTX_LEN_POS (16U)
#define UART_CR_UTX_LEN_LEN (16U)
#define UART_CR_UTX_LEN_MSK (((1U<<UART_CR_UTX_LEN_LEN)-1)<<UART_CR_UTX_LEN_POS)
#define UART_CR_UTX_LEN_UMSK (~(((1U<<UART_CR_UTX_LEN_LEN)-1)<<UART_CR_UTX_LEN_POS))
/* 0x4 : urx_config */
#define UART_URX_CONFIG_OFFSET (0x4)
#define UART_CR_URX_EN UART_CR_URX_EN
#define UART_CR_URX_EN_POS (0U)
#define UART_CR_URX_EN_LEN (1U)
#define UART_CR_URX_EN_MSK (((1U<<UART_CR_URX_EN_LEN)-1)<<UART_CR_URX_EN_POS)
#define UART_CR_URX_EN_UMSK (~(((1U<<UART_CR_URX_EN_LEN)-1)<<UART_CR_URX_EN_POS))
#define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE
#define UART_CR_URX_RTS_SW_MODE_POS (1U)
#define UART_CR_URX_RTS_SW_MODE_LEN (1U)
#define UART_CR_URX_RTS_SW_MODE_MSK (((1U<<UART_CR_URX_RTS_SW_MODE_LEN)-1)<<UART_CR_URX_RTS_SW_MODE_POS)
#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U<<UART_CR_URX_RTS_SW_MODE_LEN)-1)<<UART_CR_URX_RTS_SW_MODE_POS))
#define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL
#define UART_CR_URX_RTS_SW_VAL_POS (2U)
#define UART_CR_URX_RTS_SW_VAL_LEN (1U)
#define UART_CR_URX_RTS_SW_VAL_MSK (((1U<<UART_CR_URX_RTS_SW_VAL_LEN)-1)<<UART_CR_URX_RTS_SW_VAL_POS)
#define UART_CR_URX_RTS_SW_VAL_UMSK (~(((1U<<UART_CR_URX_RTS_SW_VAL_LEN)-1)<<UART_CR_URX_RTS_SW_VAL_POS))
#define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN
#define UART_CR_URX_ABR_EN_POS (3U)
#define UART_CR_URX_ABR_EN_LEN (1U)
#define UART_CR_URX_ABR_EN_MSK (((1U<<UART_CR_URX_ABR_EN_LEN)-1)<<UART_CR_URX_ABR_EN_POS)
#define UART_CR_URX_ABR_EN_UMSK (~(((1U<<UART_CR_URX_ABR_EN_LEN)-1)<<UART_CR_URX_ABR_EN_POS))
#define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN
#define UART_CR_URX_PRT_EN_POS (4U)
#define UART_CR_URX_PRT_EN_LEN (1U)
#define UART_CR_URX_PRT_EN_MSK (((1U<<UART_CR_URX_PRT_EN_LEN)-1)<<UART_CR_URX_PRT_EN_POS)
#define UART_CR_URX_PRT_EN_UMSK (~(((1U<<UART_CR_URX_PRT_EN_LEN)-1)<<UART_CR_URX_PRT_EN_POS))
#define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL
#define UART_CR_URX_PRT_SEL_POS (5U)
#define UART_CR_URX_PRT_SEL_LEN (1U)
#define UART_CR_URX_PRT_SEL_MSK (((1U<<UART_CR_URX_PRT_SEL_LEN)-1)<<UART_CR_URX_PRT_SEL_POS)
#define UART_CR_URX_PRT_SEL_UMSK (~(((1U<<UART_CR_URX_PRT_SEL_LEN)-1)<<UART_CR_URX_PRT_SEL_POS))
#define UART_CR_URX_IR_EN UART_CR_URX_IR_EN
#define UART_CR_URX_IR_EN_POS (6U)
#define UART_CR_URX_IR_EN_LEN (1U)
#define UART_CR_URX_IR_EN_MSK (((1U<<UART_CR_URX_IR_EN_LEN)-1)<<UART_CR_URX_IR_EN_POS)
#define UART_CR_URX_IR_EN_UMSK (~(((1U<<UART_CR_URX_IR_EN_LEN)-1)<<UART_CR_URX_IR_EN_POS))
#define UART_CR_URX_IR_INV UART_CR_URX_IR_INV
#define UART_CR_URX_IR_INV_POS (7U)
#define UART_CR_URX_IR_INV_LEN (1U)
#define UART_CR_URX_IR_INV_MSK (((1U<<UART_CR_URX_IR_INV_LEN)-1)<<UART_CR_URX_IR_INV_POS)
#define UART_CR_URX_IR_INV_UMSK (~(((1U<<UART_CR_URX_IR_INV_LEN)-1)<<UART_CR_URX_IR_INV_POS))
#define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D
#define UART_CR_URX_BIT_CNT_D_POS (8U)
#define UART_CR_URX_BIT_CNT_D_LEN (3U)
#define UART_CR_URX_BIT_CNT_D_MSK (((1U<<UART_CR_URX_BIT_CNT_D_LEN)-1)<<UART_CR_URX_BIT_CNT_D_POS)
#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U<<UART_CR_URX_BIT_CNT_D_LEN)-1)<<UART_CR_URX_BIT_CNT_D_POS))
#define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN
#define UART_CR_URX_DEG_EN_POS (11U)
#define UART_CR_URX_DEG_EN_LEN (1U)
#define UART_CR_URX_DEG_EN_MSK (((1U<<UART_CR_URX_DEG_EN_LEN)-1)<<UART_CR_URX_DEG_EN_POS)
#define UART_CR_URX_DEG_EN_UMSK (~(((1U<<UART_CR_URX_DEG_EN_LEN)-1)<<UART_CR_URX_DEG_EN_POS))
#define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT
#define UART_CR_URX_DEG_CNT_POS (12U)
#define UART_CR_URX_DEG_CNT_LEN (4U)
#define UART_CR_URX_DEG_CNT_MSK (((1U<<UART_CR_URX_DEG_CNT_LEN)-1)<<UART_CR_URX_DEG_CNT_POS)
#define UART_CR_URX_DEG_CNT_UMSK (~(((1U<<UART_CR_URX_DEG_CNT_LEN)-1)<<UART_CR_URX_DEG_CNT_POS))
#define UART_CR_URX_LEN UART_CR_URX_LEN
#define UART_CR_URX_LEN_POS (16U)
#define UART_CR_URX_LEN_LEN (16U)
#define UART_CR_URX_LEN_MSK (((1U<<UART_CR_URX_LEN_LEN)-1)<<UART_CR_URX_LEN_POS)
#define UART_CR_URX_LEN_UMSK (~(((1U<<UART_CR_URX_LEN_LEN)-1)<<UART_CR_URX_LEN_POS))
/* 0x8 : uart_bit_prd */
#define UART_BIT_PRD_OFFSET (0x8)
#define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD
#define UART_CR_UTX_BIT_PRD_POS (0U)
#define UART_CR_UTX_BIT_PRD_LEN (16U)
#define UART_CR_UTX_BIT_PRD_MSK (((1U<<UART_CR_UTX_BIT_PRD_LEN)-1)<<UART_CR_UTX_BIT_PRD_POS)
#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U<<UART_CR_UTX_BIT_PRD_LEN)-1)<<UART_CR_UTX_BIT_PRD_POS))
#define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD
#define UART_CR_URX_BIT_PRD_POS (16U)
#define UART_CR_URX_BIT_PRD_LEN (16U)
#define UART_CR_URX_BIT_PRD_MSK (((1U<<UART_CR_URX_BIT_PRD_LEN)-1)<<UART_CR_URX_BIT_PRD_POS)
#define UART_CR_URX_BIT_PRD_UMSK (~(((1U<<UART_CR_URX_BIT_PRD_LEN)-1)<<UART_CR_URX_BIT_PRD_POS))
/* 0xC : data_config */
#define UART_DATA_CONFIG_OFFSET (0xC)
#define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV
#define UART_CR_UART_BIT_INV_POS (0U)
#define UART_CR_UART_BIT_INV_LEN (1U)
#define UART_CR_UART_BIT_INV_MSK (((1U<<UART_CR_UART_BIT_INV_LEN)-1)<<UART_CR_UART_BIT_INV_POS)
#define UART_CR_UART_BIT_INV_UMSK (~(((1U<<UART_CR_UART_BIT_INV_LEN)-1)<<UART_CR_UART_BIT_INV_POS))
/* 0x10 : utx_ir_position */
#define UART_UTX_IR_POSITION_OFFSET (0x10)
#define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S
#define UART_CR_UTX_IR_POS_S_POS (0U)
#define UART_CR_UTX_IR_POS_S_LEN (16U)
#define UART_CR_UTX_IR_POS_S_MSK (((1U<<UART_CR_UTX_IR_POS_S_LEN)-1)<<UART_CR_UTX_IR_POS_S_POS)
#define UART_CR_UTX_IR_POS_S_UMSK (~(((1U<<UART_CR_UTX_IR_POS_S_LEN)-1)<<UART_CR_UTX_IR_POS_S_POS))
#define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P
#define UART_CR_UTX_IR_POS_P_POS (16U)
#define UART_CR_UTX_IR_POS_P_LEN (16U)
#define UART_CR_UTX_IR_POS_P_MSK (((1U<<UART_CR_UTX_IR_POS_P_LEN)-1)<<UART_CR_UTX_IR_POS_P_POS)
#define UART_CR_UTX_IR_POS_P_UMSK (~(((1U<<UART_CR_UTX_IR_POS_P_LEN)-1)<<UART_CR_UTX_IR_POS_P_POS))
/* 0x14 : urx_ir_position */
#define UART_URX_IR_POSITION_OFFSET (0x14)
#define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S
#define UART_CR_URX_IR_POS_S_POS (0U)
#define UART_CR_URX_IR_POS_S_LEN (16U)
#define UART_CR_URX_IR_POS_S_MSK (((1U<<UART_CR_URX_IR_POS_S_LEN)-1)<<UART_CR_URX_IR_POS_S_POS)
#define UART_CR_URX_IR_POS_S_UMSK (~(((1U<<UART_CR_URX_IR_POS_S_LEN)-1)<<UART_CR_URX_IR_POS_S_POS))
/* 0x18 : urx_rto_timer */
#define UART_URX_RTO_TIMER_OFFSET (0x18)
#define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE
#define UART_CR_URX_RTO_VALUE_POS (0U)
#define UART_CR_URX_RTO_VALUE_LEN (8U)
#define UART_CR_URX_RTO_VALUE_MSK (((1U<<UART_CR_URX_RTO_VALUE_LEN)-1)<<UART_CR_URX_RTO_VALUE_POS)
#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U<<UART_CR_URX_RTO_VALUE_LEN)-1)<<UART_CR_URX_RTO_VALUE_POS))
/* 0x20 : UART interrupt status */
#define UART_INT_STS_OFFSET (0x20)
#define UART_UTX_END_INT UART_UTX_END_INT
#define UART_UTX_END_INT_POS (0U)
#define UART_UTX_END_INT_LEN (1U)
#define UART_UTX_END_INT_MSK (((1U<<UART_UTX_END_INT_LEN)-1)<<UART_UTX_END_INT_POS)
#define UART_UTX_END_INT_UMSK (~(((1U<<UART_UTX_END_INT_LEN)-1)<<UART_UTX_END_INT_POS))
#define UART_URX_END_INT UART_URX_END_INT
#define UART_URX_END_INT_POS (1U)
#define UART_URX_END_INT_LEN (1U)
#define UART_URX_END_INT_MSK (((1U<<UART_URX_END_INT_LEN)-1)<<UART_URX_END_INT_POS)
#define UART_URX_END_INT_UMSK (~(((1U<<UART_URX_END_INT_LEN)-1)<<UART_URX_END_INT_POS))
#define UART_UTX_FIFO_INT UART_UTX_FIFO_INT
#define UART_UTX_FIFO_INT_POS (2U)
#define UART_UTX_FIFO_INT_LEN (1U)
#define UART_UTX_FIFO_INT_MSK (((1U<<UART_UTX_FIFO_INT_LEN)-1)<<UART_UTX_FIFO_INT_POS)
#define UART_UTX_FIFO_INT_UMSK (~(((1U<<UART_UTX_FIFO_INT_LEN)-1)<<UART_UTX_FIFO_INT_POS))
#define UART_URX_FIFO_INT UART_URX_FIFO_INT
#define UART_URX_FIFO_INT_POS (3U)
#define UART_URX_FIFO_INT_LEN (1U)
#define UART_URX_FIFO_INT_MSK (((1U<<UART_URX_FIFO_INT_LEN)-1)<<UART_URX_FIFO_INT_POS)
#define UART_URX_FIFO_INT_UMSK (~(((1U<<UART_URX_FIFO_INT_LEN)-1)<<UART_URX_FIFO_INT_POS))
#define UART_URX_RTO_INT UART_URX_RTO_INT
#define UART_URX_RTO_INT_POS (4U)
#define UART_URX_RTO_INT_LEN (1U)
#define UART_URX_RTO_INT_MSK (((1U<<UART_URX_RTO_INT_LEN)-1)<<UART_URX_RTO_INT_POS)
#define UART_URX_RTO_INT_UMSK (~(((1U<<UART_URX_RTO_INT_LEN)-1)<<UART_URX_RTO_INT_POS))
#define UART_URX_PCE_INT UART_URX_PCE_INT
#define UART_URX_PCE_INT_POS (5U)
#define UART_URX_PCE_INT_LEN (1U)
#define UART_URX_PCE_INT_MSK (((1U<<UART_URX_PCE_INT_LEN)-1)<<UART_URX_PCE_INT_POS)
#define UART_URX_PCE_INT_UMSK (~(((1U<<UART_URX_PCE_INT_LEN)-1)<<UART_URX_PCE_INT_POS))
#define UART_UTX_FER_INT UART_UTX_FER_INT
#define UART_UTX_FER_INT_POS (6U)
#define UART_UTX_FER_INT_LEN (1U)
#define UART_UTX_FER_INT_MSK (((1U<<UART_UTX_FER_INT_LEN)-1)<<UART_UTX_FER_INT_POS)
#define UART_UTX_FER_INT_UMSK (~(((1U<<UART_UTX_FER_INT_LEN)-1)<<UART_UTX_FER_INT_POS))
#define UART_URX_FER_INT UART_URX_FER_INT
#define UART_URX_FER_INT_POS (7U)
#define UART_URX_FER_INT_LEN (1U)
#define UART_URX_FER_INT_MSK (((1U<<UART_URX_FER_INT_LEN)-1)<<UART_URX_FER_INT_POS)
#define UART_URX_FER_INT_UMSK (~(((1U<<UART_URX_FER_INT_LEN)-1)<<UART_URX_FER_INT_POS))
/* 0x24 : UART interrupt mask */
#define UART_INT_MASK_OFFSET (0x24)
#define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK
#define UART_CR_UTX_END_MASK_POS (0U)
#define UART_CR_UTX_END_MASK_LEN (1U)
#define UART_CR_UTX_END_MASK_MSK (((1U<<UART_CR_UTX_END_MASK_LEN)-1)<<UART_CR_UTX_END_MASK_POS)
#define UART_CR_UTX_END_MASK_UMSK (~(((1U<<UART_CR_UTX_END_MASK_LEN)-1)<<UART_CR_UTX_END_MASK_POS))
#define UART_CR_URX_END_MASK UART_CR_URX_END_MASK
#define UART_CR_URX_END_MASK_POS (1U)
#define UART_CR_URX_END_MASK_LEN (1U)
#define UART_CR_URX_END_MASK_MSK (((1U<<UART_CR_URX_END_MASK_LEN)-1)<<UART_CR_URX_END_MASK_POS)
#define UART_CR_URX_END_MASK_UMSK (~(((1U<<UART_CR_URX_END_MASK_LEN)-1)<<UART_CR_URX_END_MASK_POS))
#define UART_CR_UTX_FIFO_MASK UART_CR_UTX_FIFO_MASK
#define UART_CR_UTX_FIFO_MASK_POS (2U)
#define UART_CR_UTX_FIFO_MASK_LEN (1U)
#define UART_CR_UTX_FIFO_MASK_MSK (((1U<<UART_CR_UTX_FIFO_MASK_LEN)-1)<<UART_CR_UTX_FIFO_MASK_POS)
#define UART_CR_UTX_FIFO_MASK_UMSK (~(((1U<<UART_CR_UTX_FIFO_MASK_LEN)-1)<<UART_CR_UTX_FIFO_MASK_POS))
#define UART_CR_URX_FIFO_MASK UART_CR_URX_FIFO_MASK
#define UART_CR_URX_FIFO_MASK_POS (3U)
#define UART_CR_URX_FIFO_MASK_LEN (1U)
#define UART_CR_URX_FIFO_MASK_MSK (((1U<<UART_CR_URX_FIFO_MASK_LEN)-1)<<UART_CR_URX_FIFO_MASK_POS)
#define UART_CR_URX_FIFO_MASK_UMSK (~(((1U<<UART_CR_URX_FIFO_MASK_LEN)-1)<<UART_CR_URX_FIFO_MASK_POS))
#define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK
#define UART_CR_URX_RTO_MASK_POS (4U)
#define UART_CR_URX_RTO_MASK_LEN (1U)
#define UART_CR_URX_RTO_MASK_MSK (((1U<<UART_CR_URX_RTO_MASK_LEN)-1)<<UART_CR_URX_RTO_MASK_POS)
#define UART_CR_URX_RTO_MASK_UMSK (~(((1U<<UART_CR_URX_RTO_MASK_LEN)-1)<<UART_CR_URX_RTO_MASK_POS))
#define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK
#define UART_CR_URX_PCE_MASK_POS (5U)
#define UART_CR_URX_PCE_MASK_LEN (1U)
#define UART_CR_URX_PCE_MASK_MSK (((1U<<UART_CR_URX_PCE_MASK_LEN)-1)<<UART_CR_URX_PCE_MASK_POS)
#define UART_CR_URX_PCE_MASK_UMSK (~(((1U<<UART_CR_URX_PCE_MASK_LEN)-1)<<UART_CR_URX_PCE_MASK_POS))
#define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK
#define UART_CR_UTX_FER_MASK_POS (6U)
#define UART_CR_UTX_FER_MASK_LEN (1U)
#define UART_CR_UTX_FER_MASK_MSK (((1U<<UART_CR_UTX_FER_MASK_LEN)-1)<<UART_CR_UTX_FER_MASK_POS)
#define UART_CR_UTX_FER_MASK_UMSK (~(((1U<<UART_CR_UTX_FER_MASK_LEN)-1)<<UART_CR_UTX_FER_MASK_POS))
#define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK
#define UART_CR_URX_FER_MASK_POS (7U)
#define UART_CR_URX_FER_MASK_LEN (1U)
#define UART_CR_URX_FER_MASK_MSK (((1U<<UART_CR_URX_FER_MASK_LEN)-1)<<UART_CR_URX_FER_MASK_POS)
#define UART_CR_URX_FER_MASK_UMSK (~(((1U<<UART_CR_URX_FER_MASK_LEN)-1)<<UART_CR_URX_FER_MASK_POS))
/* 0x28 : UART interrupt clear */
#define UART_INT_CLEAR_OFFSET (0x28)
#define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR
#define UART_CR_UTX_END_CLR_POS (0U)
#define UART_CR_UTX_END_CLR_LEN (1U)
#define UART_CR_UTX_END_CLR_MSK (((1U<<UART_CR_UTX_END_CLR_LEN)-1)<<UART_CR_UTX_END_CLR_POS)
#define UART_CR_UTX_END_CLR_UMSK (~(((1U<<UART_CR_UTX_END_CLR_LEN)-1)<<UART_CR_UTX_END_CLR_POS))
#define UART_CR_URX_END_CLR UART_CR_URX_END_CLR
#define UART_CR_URX_END_CLR_POS (1U)
#define UART_CR_URX_END_CLR_LEN (1U)
#define UART_CR_URX_END_CLR_MSK (((1U<<UART_CR_URX_END_CLR_LEN)-1)<<UART_CR_URX_END_CLR_POS)
#define UART_CR_URX_END_CLR_UMSK (~(((1U<<UART_CR_URX_END_CLR_LEN)-1)<<UART_CR_URX_END_CLR_POS))
#define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR
#define UART_CR_URX_RTO_CLR_POS (4U)
#define UART_CR_URX_RTO_CLR_LEN (1U)
#define UART_CR_URX_RTO_CLR_MSK (((1U<<UART_CR_URX_RTO_CLR_LEN)-1)<<UART_CR_URX_RTO_CLR_POS)
#define UART_CR_URX_RTO_CLR_UMSK (~(((1U<<UART_CR_URX_RTO_CLR_LEN)-1)<<UART_CR_URX_RTO_CLR_POS))
#define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR
#define UART_CR_URX_PCE_CLR_POS (5U)
#define UART_CR_URX_PCE_CLR_LEN (1U)
#define UART_CR_URX_PCE_CLR_MSK (((1U<<UART_CR_URX_PCE_CLR_LEN)-1)<<UART_CR_URX_PCE_CLR_POS)
#define UART_CR_URX_PCE_CLR_UMSK (~(((1U<<UART_CR_URX_PCE_CLR_LEN)-1)<<UART_CR_URX_PCE_CLR_POS))
/* 0x2C : UART interrupt enable */
#define UART_INT_EN_OFFSET (0x2C)
#define UART_CR_UTX_END_EN UART_CR_UTX_END_EN
#define UART_CR_UTX_END_EN_POS (0U)
#define UART_CR_UTX_END_EN_LEN (1U)
#define UART_CR_UTX_END_EN_MSK (((1U<<UART_CR_UTX_END_EN_LEN)-1)<<UART_CR_UTX_END_EN_POS)
#define UART_CR_UTX_END_EN_UMSK (~(((1U<<UART_CR_UTX_END_EN_LEN)-1)<<UART_CR_UTX_END_EN_POS))
#define UART_CR_URX_END_EN UART_CR_URX_END_EN
#define UART_CR_URX_END_EN_POS (1U)
#define UART_CR_URX_END_EN_LEN (1U)
#define UART_CR_URX_END_EN_MSK (((1U<<UART_CR_URX_END_EN_LEN)-1)<<UART_CR_URX_END_EN_POS)
#define UART_CR_URX_END_EN_UMSK (~(((1U<<UART_CR_URX_END_EN_LEN)-1)<<UART_CR_URX_END_EN_POS))
#define UART_CR_UTX_FIFO_EN UART_CR_UTX_FIFO_EN
#define UART_CR_UTX_FIFO_EN_POS (2U)
#define UART_CR_UTX_FIFO_EN_LEN (1U)
#define UART_CR_UTX_FIFO_EN_MSK (((1U<<UART_CR_UTX_FIFO_EN_LEN)-1)<<UART_CR_UTX_FIFO_EN_POS)
#define UART_CR_UTX_FIFO_EN_UMSK (~(((1U<<UART_CR_UTX_FIFO_EN_LEN)-1)<<UART_CR_UTX_FIFO_EN_POS))
#define UART_CR_URX_FIFO_EN UART_CR_URX_FIFO_EN
#define UART_CR_URX_FIFO_EN_POS (3U)
#define UART_CR_URX_FIFO_EN_LEN (1U)
#define UART_CR_URX_FIFO_EN_MSK (((1U<<UART_CR_URX_FIFO_EN_LEN)-1)<<UART_CR_URX_FIFO_EN_POS)
#define UART_CR_URX_FIFO_EN_UMSK (~(((1U<<UART_CR_URX_FIFO_EN_LEN)-1)<<UART_CR_URX_FIFO_EN_POS))
#define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN
#define UART_CR_URX_RTO_EN_POS (4U)
#define UART_CR_URX_RTO_EN_LEN (1U)
#define UART_CR_URX_RTO_EN_MSK (((1U<<UART_CR_URX_RTO_EN_LEN)-1)<<UART_CR_URX_RTO_EN_POS)
#define UART_CR_URX_RTO_EN_UMSK (~(((1U<<UART_CR_URX_RTO_EN_LEN)-1)<<UART_CR_URX_RTO_EN_POS))
#define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN
#define UART_CR_URX_PCE_EN_POS (5U)
#define UART_CR_URX_PCE_EN_LEN (1U)
#define UART_CR_URX_PCE_EN_MSK (((1U<<UART_CR_URX_PCE_EN_LEN)-1)<<UART_CR_URX_PCE_EN_POS)
#define UART_CR_URX_PCE_EN_UMSK (~(((1U<<UART_CR_URX_PCE_EN_LEN)-1)<<UART_CR_URX_PCE_EN_POS))
#define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN
#define UART_CR_UTX_FER_EN_POS (6U)
#define UART_CR_UTX_FER_EN_LEN (1U)
#define UART_CR_UTX_FER_EN_MSK (((1U<<UART_CR_UTX_FER_EN_LEN)-1)<<UART_CR_UTX_FER_EN_POS)
#define UART_CR_UTX_FER_EN_UMSK (~(((1U<<UART_CR_UTX_FER_EN_LEN)-1)<<UART_CR_UTX_FER_EN_POS))
#define UART_CR_URX_FER_EN UART_CR_URX_FER_EN
#define UART_CR_URX_FER_EN_POS (7U)
#define UART_CR_URX_FER_EN_LEN (1U)
#define UART_CR_URX_FER_EN_MSK (((1U<<UART_CR_URX_FER_EN_LEN)-1)<<UART_CR_URX_FER_EN_POS)
#define UART_CR_URX_FER_EN_UMSK (~(((1U<<UART_CR_URX_FER_EN_LEN)-1)<<UART_CR_URX_FER_EN_POS))
/* 0x30 : uart_status */
#define UART_STATUS_OFFSET (0x30)
#define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY
#define UART_STS_UTX_BUS_BUSY_POS (0U)
#define UART_STS_UTX_BUS_BUSY_LEN (1U)
#define UART_STS_UTX_BUS_BUSY_MSK (((1U<<UART_STS_UTX_BUS_BUSY_LEN)-1)<<UART_STS_UTX_BUS_BUSY_POS)
#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U<<UART_STS_UTX_BUS_BUSY_LEN)-1)<<UART_STS_UTX_BUS_BUSY_POS))
#define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY
#define UART_STS_URX_BUS_BUSY_POS (1U)
#define UART_STS_URX_BUS_BUSY_LEN (1U)
#define UART_STS_URX_BUS_BUSY_MSK (((1U<<UART_STS_URX_BUS_BUSY_LEN)-1)<<UART_STS_URX_BUS_BUSY_POS)
#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U<<UART_STS_URX_BUS_BUSY_LEN)-1)<<UART_STS_URX_BUS_BUSY_POS))
/* 0x34 : sts_urx_abr_prd */
#define UART_STS_URX_ABR_PRD_OFFSET (0x34)
#define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START
#define UART_STS_URX_ABR_PRD_START_POS (0U)
#define UART_STS_URX_ABR_PRD_START_LEN (16U)
#define UART_STS_URX_ABR_PRD_START_MSK (((1U<<UART_STS_URX_ABR_PRD_START_LEN)-1)<<UART_STS_URX_ABR_PRD_START_POS)
#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U<<UART_STS_URX_ABR_PRD_START_LEN)-1)<<UART_STS_URX_ABR_PRD_START_POS))
#define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55
#define UART_STS_URX_ABR_PRD_0X55_POS (16U)
#define UART_STS_URX_ABR_PRD_0X55_LEN (16U)
#define UART_STS_URX_ABR_PRD_0X55_MSK (((1U<<UART_STS_URX_ABR_PRD_0X55_LEN)-1)<<UART_STS_URX_ABR_PRD_0X55_POS)
#define UART_STS_URX_ABR_PRD_0X55_UMSK (~(((1U<<UART_STS_URX_ABR_PRD_0X55_LEN)-1)<<UART_STS_URX_ABR_PRD_0X55_POS))
/* 0x80 : uart_fifo_config_0 */
#define UART_FIFO_CONFIG_0_OFFSET (0x80)
#define UART_DMA_TX_EN UART_DMA_TX_EN
#define UART_DMA_TX_EN_POS (0U)
#define UART_DMA_TX_EN_LEN (1U)
#define UART_DMA_TX_EN_MSK (((1U<<UART_DMA_TX_EN_LEN)-1)<<UART_DMA_TX_EN_POS)
#define UART_DMA_TX_EN_UMSK (~(((1U<<UART_DMA_TX_EN_LEN)-1)<<UART_DMA_TX_EN_POS))
#define UART_DMA_RX_EN UART_DMA_RX_EN
#define UART_DMA_RX_EN_POS (1U)
#define UART_DMA_RX_EN_LEN (1U)
#define UART_DMA_RX_EN_MSK (((1U<<UART_DMA_RX_EN_LEN)-1)<<UART_DMA_RX_EN_POS)
#define UART_DMA_RX_EN_UMSK (~(((1U<<UART_DMA_RX_EN_LEN)-1)<<UART_DMA_RX_EN_POS))
#define UART_TX_FIFO_CLR UART_TX_FIFO_CLR
#define UART_TX_FIFO_CLR_POS (2U)
#define UART_TX_FIFO_CLR_LEN (1U)
#define UART_TX_FIFO_CLR_MSK (((1U<<UART_TX_FIFO_CLR_LEN)-1)<<UART_TX_FIFO_CLR_POS)
#define UART_TX_FIFO_CLR_UMSK (~(((1U<<UART_TX_FIFO_CLR_LEN)-1)<<UART_TX_FIFO_CLR_POS))
#define UART_RX_FIFO_CLR UART_RX_FIFO_CLR
#define UART_RX_FIFO_CLR_POS (3U)
#define UART_RX_FIFO_CLR_LEN (1U)
#define UART_RX_FIFO_CLR_MSK (((1U<<UART_RX_FIFO_CLR_LEN)-1)<<UART_RX_FIFO_CLR_POS)
#define UART_RX_FIFO_CLR_UMSK (~(((1U<<UART_RX_FIFO_CLR_LEN)-1)<<UART_RX_FIFO_CLR_POS))
#define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW
#define UART_TX_FIFO_OVERFLOW_POS (4U)
#define UART_TX_FIFO_OVERFLOW_LEN (1U)
#define UART_TX_FIFO_OVERFLOW_MSK (((1U<<UART_TX_FIFO_OVERFLOW_LEN)-1)<<UART_TX_FIFO_OVERFLOW_POS)
#define UART_TX_FIFO_OVERFLOW_UMSK (~(((1U<<UART_TX_FIFO_OVERFLOW_LEN)-1)<<UART_TX_FIFO_OVERFLOW_POS))
#define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW
#define UART_TX_FIFO_UNDERFLOW_POS (5U)
#define UART_TX_FIFO_UNDERFLOW_LEN (1U)
#define UART_TX_FIFO_UNDERFLOW_MSK (((1U<<UART_TX_FIFO_UNDERFLOW_LEN)-1)<<UART_TX_FIFO_UNDERFLOW_POS)
#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U<<UART_TX_FIFO_UNDERFLOW_LEN)-1)<<UART_TX_FIFO_UNDERFLOW_POS))
#define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW
#define UART_RX_FIFO_OVERFLOW_POS (6U)
#define UART_RX_FIFO_OVERFLOW_LEN (1U)
#define UART_RX_FIFO_OVERFLOW_MSK (((1U<<UART_RX_FIFO_OVERFLOW_LEN)-1)<<UART_RX_FIFO_OVERFLOW_POS)
#define UART_RX_FIFO_OVERFLOW_UMSK (~(((1U<<UART_RX_FIFO_OVERFLOW_LEN)-1)<<UART_RX_FIFO_OVERFLOW_POS))
#define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW
#define UART_RX_FIFO_UNDERFLOW_POS (7U)
#define UART_RX_FIFO_UNDERFLOW_LEN (1U)
#define UART_RX_FIFO_UNDERFLOW_MSK (((1U<<UART_RX_FIFO_UNDERFLOW_LEN)-1)<<UART_RX_FIFO_UNDERFLOW_POS)
#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U<<UART_RX_FIFO_UNDERFLOW_LEN)-1)<<UART_RX_FIFO_UNDERFLOW_POS))
/* 0x84 : uart_fifo_config_1 */
#define UART_FIFO_CONFIG_1_OFFSET (0x84)
#define UART_TX_FIFO_CNT UART_TX_FIFO_CNT
#define UART_TX_FIFO_CNT_POS (0U)
#define UART_TX_FIFO_CNT_LEN (6U)
#define UART_TX_FIFO_CNT_MSK (((1U<<UART_TX_FIFO_CNT_LEN)-1)<<UART_TX_FIFO_CNT_POS)
#define UART_TX_FIFO_CNT_UMSK (~(((1U<<UART_TX_FIFO_CNT_LEN)-1)<<UART_TX_FIFO_CNT_POS))
#define UART_RX_FIFO_CNT UART_RX_FIFO_CNT
#define UART_RX_FIFO_CNT_POS (8U)
#define UART_RX_FIFO_CNT_LEN (6U)
#define UART_RX_FIFO_CNT_MSK (((1U<<UART_RX_FIFO_CNT_LEN)-1)<<UART_RX_FIFO_CNT_POS)
#define UART_RX_FIFO_CNT_UMSK (~(((1U<<UART_RX_FIFO_CNT_LEN)-1)<<UART_RX_FIFO_CNT_POS))
#define UART_TX_FIFO_TH UART_TX_FIFO_TH
#define UART_TX_FIFO_TH_POS (16U)
#define UART_TX_FIFO_TH_LEN (5U)
#define UART_TX_FIFO_TH_MSK (((1U<<UART_TX_FIFO_TH_LEN)-1)<<UART_TX_FIFO_TH_POS)
#define UART_TX_FIFO_TH_UMSK (~(((1U<<UART_TX_FIFO_TH_LEN)-1)<<UART_TX_FIFO_TH_POS))
#define UART_RX_FIFO_TH UART_RX_FIFO_TH
#define UART_RX_FIFO_TH_POS (24U)
#define UART_RX_FIFO_TH_LEN (5U)
#define UART_RX_FIFO_TH_MSK (((1U<<UART_RX_FIFO_TH_LEN)-1)<<UART_RX_FIFO_TH_POS)
#define UART_RX_FIFO_TH_UMSK (~(((1U<<UART_RX_FIFO_TH_LEN)-1)<<UART_RX_FIFO_TH_POS))
/* 0x88 : uart_fifo_wdata */
#define UART_FIFO_WDATA_OFFSET (0x88)
#define UART_FIFO_WDATA UART_FIFO_WDATA
#define UART_FIFO_WDATA_POS (0U)
#define UART_FIFO_WDATA_LEN (8U)
#define UART_FIFO_WDATA_MSK (((1U<<UART_FIFO_WDATA_LEN)-1)<<UART_FIFO_WDATA_POS)
#define UART_FIFO_WDATA_UMSK (~(((1U<<UART_FIFO_WDATA_LEN)-1)<<UART_FIFO_WDATA_POS))
/* 0x8C : uart_fifo_rdata */
#define UART_FIFO_RDATA_OFFSET (0x8C)
#define UART_FIFO_RDATA UART_FIFO_RDATA
#define UART_FIFO_RDATA_POS (0U)
#define UART_FIFO_RDATA_LEN (8U)
#define UART_FIFO_RDATA_MSK (((1U<<UART_FIFO_RDATA_LEN)-1)<<UART_FIFO_RDATA_POS)
#define UART_FIFO_RDATA_UMSK (~(((1U<<UART_FIFO_RDATA_LEN)-1)<<UART_FIFO_RDATA_POS))
struct uart_reg {
/* 0x0 : utx_config */
union {
struct {
uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */
uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */
uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */
uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
uint32_t cr_utx_bit_cnt_p : 2; /* [13:12], r/w, 0x1 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */
}BF;
uint32_t WORD;
} utx_config;
/* 0x4 : urx_config */
union {
struct {
uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t cr_urx_rts_sw_mode : 1; /* [ 1], r/w, 0x0 */
uint32_t cr_urx_rts_sw_val : 1; /* [ 2], r/w, 0x0 */
uint32_t cr_urx_abr_en : 1; /* [ 3], r/w, 0x0 */
uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */
uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */
uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */
uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */
uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */
uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */
uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */
uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */
}BF;
uint32_t WORD;
} urx_config;
/* 0x8 : uart_bit_prd */
union {
struct {
uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */
uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */
}BF;
uint32_t WORD;
} uart_bit_prd;
/* 0xC : data_config */
union {
struct {
uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
}BF;
uint32_t WORD;
} data_config;
/* 0x10 : utx_ir_position */
union {
struct {
uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */
uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */
}BF;
uint32_t WORD;
} utx_ir_position;
/* 0x14 : urx_ir_position */
union {
struct {
uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
}BF;
uint32_t WORD;
} urx_ir_position;
/* 0x18 : urx_rto_timer */
union {
struct {
uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} urx_rto_timer;
/* 0x1c reserved */
uint8_t RESERVED0x1c[4];
/* 0x20 : UART interrupt status */
union {
struct {
uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */
uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */
uint32_t utx_fifo_int : 1; /* [ 2], r, 0x0 */
uint32_t urx_fifo_int : 1; /* [ 3], r, 0x0 */
uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */
uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */
uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */
uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_int_sts;
/* 0x24 : UART interrupt mask */
union {
struct {
uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */
uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */
uint32_t cr_utx_fifo_mask : 1; /* [ 2], r/w, 0x1 */
uint32_t cr_urx_fifo_mask : 1; /* [ 3], r/w, 0x1 */
uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */
uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */
uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */
uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_int_mask;
/* 0x28 : UART interrupt clear */
union {
struct {
uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */
uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */
uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */
uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */
uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */
uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */
uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_int_clear;
/* 0x2C : UART interrupt enable */
union {
struct {
uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */
uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */
uint32_t cr_utx_fifo_en : 1; /* [ 2], r/w, 0x1 */
uint32_t cr_urx_fifo_en : 1; /* [ 3], r/w, 0x1 */
uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */
uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */
uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */
uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_int_en;
/* 0x30 : uart_status */
union {
struct {
uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */
uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */
uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_status;
/* 0x34 : sts_urx_abr_prd */
union {
struct {
uint32_t sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */
uint32_t sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */
}BF;
uint32_t WORD;
} sts_urx_abr_prd;
/* 0x38 reserved */
uint8_t RESERVED0x38[72];
/* 0x80 : uart_fifo_config_0 */
union {
struct {
uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_fifo_config_0;
/* 0x84 : uart_fifo_config_1 */
union {
struct {
uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */
uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */
uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_fifo_config_1;
/* 0x88 : uart_fifo_wdata */
union {
struct {
uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_fifo_wdata;
/* 0x8C : uart_fifo_rdata */
union {
struct {
uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
}BF;
uint32_t WORD;
} uart_fifo_rdata;
};
typedef volatile struct uart_reg uart_reg_t;
#endif /* __UART_REG_H__ */

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drivers/bl602_driver/risc-v/Core/Include/clic.h Normal file
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// See LICENSE for license details.
#ifndef _SIFIVE_CLIC_H
#define _SIFIVE_CLIC_H
#define CLIC_CTRL_ADDR 0x02000000UL
#define CLIC_HART0_ADDR 0x02800000UL
#define CLIC_MSIP 0x0000
#define CLIC_MSIP_size 0x4
#define CLIC_MTIMECMP 0x4000
#define CLIC_MTIMECMP_size 0x8
#define CLIC_MTIME 0xBFF8
#define CLIC_MTIME_size 0x8
#define CLIC_INTIP 0x000
#define CLIC_INTIE 0x400
#define CLIC_INTCFG 0x800
#define CLIC_CFG 0xc00
#endif /* _SIFIVE_CLIC_H */

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drivers/bl602_driver/risc-v/Core/Include/cmsis_compatible_gcc.h Normal file
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#ifndef __CMSIS_COMPATIBLE_GCC_H
#define __CMSIS_COMPATIBLE_GCC_H
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __ALWAYS_INLINE
#define __ALWAYS_INLINE inline __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __IRQ
#define __IRQ __attribute__((interrupt))
#endif
#ifndef __IRQ_ALIGN64
#define __IRQ_ALIGN64 __attribute__((interrupt,aligned(64)))
#endif
#ifndef ALIGN4
#define ALIGN4 __attribute((aligned (4)))
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
//{
// __ASM volatile ("nop");
//}
#define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
//{
// __ASM volatile ("wfi");
//}
#define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
//{
// __ASM volatile ("wfe");
//}
#define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
//{
// __ASM volatile ("sev");
//}
#define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("csrsi mstatus, 8");
}
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("csrci mstatus, 8");
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
//return __builtin_bswap32(value);
uint32_t res = 0;
res = (value << 24) | (value >> 24);
res &= 0xFF0000FF; /* only for sure */
res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
return res;
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
return __builtin_bswap16(value);
}
extern void clic_enable_interrupt (uint32_t source);
extern void clic_disable_interrupt ( uint32_t source);
extern void clic_set_pending(uint32_t source);
extern void clic_clear_pending(uint32_t source);
#define NVIC_EnableIRQ clic_enable_interrupt
#define NVIC_DisableIRQ clic_disable_interrupt
#define NVIC_ClearPendingIRQ clic_clear_pending
//#define __set_MSP(val) __ASM volatile ("lw sp,0(%0)":: "r"(val))
#define __set_MSP(msp) __ASM volatile ("add sp, x0, %0":: "r"(msp))
#endif /* __CMSIS_COMPATIBLE_GCC_H */

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// See LICENSE for license details.
#ifndef _RISCV_BITS_H
#define _RISCV_BITS_H
#define likely(x) __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#if __riscv_xlen == 64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#endif

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// See LICENSE for license details.
/* Derived from <linux/const.h> */
#ifndef _RISCV_CONST_H
#define _RISCV_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif /* _NUCLEI_CONST_H */

1370
drivers/bl602_driver/risc-v/Core/Include/riscv_encoding.h Normal file
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/* Copyright 2018 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include "riscv_encoding.h"
/* This code executes before _start, which is contained inside the C library.
* In embedded systems we want to ensure that _enter, which contains the first
* code to be executed, can be loaded at a specific address. To enable this
* feature we provide the '.text.metal.init.enter' section, which is
* defined to have the first address being where execution should start. */
.section .text.metal.init.enter
.global _enter
_enter:
.cfi_startproc
/* Inform the debugger that there is nowhere to backtrace past _enter. */
.cfi_undefined ra
/* The absolute first thing that must happen is configuring the global
* pointer register, which must be done with relaxation disabled because
* it's not valid to obtain the address of any symbol without GP
* configured. The C environment might go ahead and do this again, but
* that's safe as it's a fixed register. */
.option push
.option norelax
la gp, __global_pointer$
.option pop
/* Disable global interrupt */
/*clear_csr(mstatus, MSTATUS_MIE);*/
csrci mstatus,8
/* Set up a simple trap vector to catch anything that goes wrong early in
* the boot process. */
la t0, Trap_Handler_Stub
/* enable CLIC Vectored mode */
ori t0,t0,3
csrw mtvec, t0
/* enable chicken bit if core is bullet series*/
la t0, __metal_chicken_bit
beqz t0, 1f
csrwi 0x7C1, 0
1:
/* There may be pre-initialization routines inside the MBI code that run in
* C, so here we set up a C environment. First we set up a stack pointer,
* which is left as a weak reference in order to allow initialization
* routines that do not need a stack to be set up to transparently be
* called. */
.weak __StackTop
la sp, __StackTop
/* Intial the mtvt, MUST BE 64 bytes aligned*/
.weak __Vectors
la t0, __Vectors
csrw mtvt, t0
#if __riscv_float_abi_single
/* deal with FP */
/* Is F extension present? */
csrr t0, misa
andi t0, t0, (1 << ('F' - 'A'))
beqz t0, 1f
/* If so, enable it */
li t0, MSTATUS_FS
csrs mstatus, t0
fssr x0
1:
#endif
/* Check for an initialization routine and call it if one exists, otherwise
* just skip over the call entirely. Note that __metal_initialize isn't
* actually a full C function, as it doesn't end up with the .bss or .data
* segments having been initialized. This is done to avoid putting a
* burden on systems that can be initialized without having a C environment
* set up. */
call SystemInit
/* start load code to itcm like. */
call start_load
/* At this point we can enter the C runtime's startup file. The arguments
* to this function are designed to match those provided to the SEE, just
* so we don't have to write another ABI. */
csrr a0, mhartid
li a1, 0
li a2, 0
call main
/* If we've made it back here then there's probably something wrong. We
* allow the METAL to register a handler here. */
.weak __metal_after_main
la ra, __metal_after_main
beqz ra, 1f
jalr ra
1:
/* If that handler returns then there's not a whole lot we can do. Just
* try to make some noise. */
la t0, 1f
csrw mtvec, t0
1:
lw t1, 0(x0)
j 1b
.cfi_endproc
/* For sanity's sake we set up an early trap vector that just does nothing. If
* you end up here then there's a bug in the early boot code somewhere. */
.weak Trap_Handler_Stub
.section .text.metal.init.trapvec
.align 2
Trap_Handler_Stub:
.cfi_startproc
csrr t0, mcause
csrr t1, mepc
csrr t2, mtval
j Trap_Handler_Stub
.cfi_endproc
/* The GCC port might not emit a __register_frame_info symbol, which eventually
* results in a weak undefined reference that eventually causes crash when it
* is dereference early in boot. We really shouldn't need to put this here,
* but to deal with what I think is probably a bug in the linker script I'm
* going to leave this in for now. At least it's fairly cheap :) */
.weak __register_frame_info
.global __register_frame_info
.section .text.metal.init.__register_frame_info
__register_frame_info:
.cfi_startproc
ret
.cfi_endproc

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drivers/bl602_driver/startup/GCC/start_load.c Normal file
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#include <stdint.h>
#include "bl602.h"
#define __STARTUP_CLEAR_BSS 1
/*----------------------------------------------------------------------------
Linker generated Symbols
*----------------------------------------------------------------------------*/
extern uint32_t __itcm_load_addr;
extern uint32_t __dtcm_load_addr;
extern uint32_t __system_ram_load_addr;
extern uint32_t __ram_load_addr;
extern uint32_t __text_code_start__;
extern uint32_t __text_code_end__;
extern uint32_t __tcm_code_start__;
extern uint32_t __tcm_code_end__;
extern uint32_t __tcm_data_start__;
extern uint32_t __tcm_data_end__;
extern uint32_t __system_ram_data_start__;
extern uint32_t __system_ram_data_end__;
extern uint32_t __ram_data_start__;
extern uint32_t __ram_data_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __noinit_data_start__;
extern uint32_t __noinit_data_end__;
extern uint32_t __StackTop;
extern uint32_t __StackLimit;
//extern uint32_t __copy_table_start__;
//extern uint32_t __copy_table_end__;
//extern uint32_t __zero_table_start__;
//extern uint32_t __zero_table_end__;
void start_load(void) {
uint32_t *pSrc, *pDest;
uint32_t *pTable __attribute__((unused));
/* Copy ITCM code */
pSrc = &__itcm_load_addr;
pDest = &__tcm_code_start__;
for ( ; pDest < &__tcm_code_end__ ; ) {
*pDest++ = *pSrc++;
}
/* Copy DTCM code */
pSrc = &__dtcm_load_addr;
pDest = &__tcm_data_start__;
for( ; pDest < &__tcm_data_end__; ){
*pDest++ = *pSrc++;
}
/* BF Add system RAM data copy */
pSrc = &__system_ram_load_addr;
pDest = &__system_ram_data_start__;
for ( ; pDest < &__system_ram_data_end__ ; ) {
*pDest++ = *pSrc++;
}
/* BF Add OCARAM data copy */
pSrc = &__ram_load_addr;
pDest = &__ram_data_start__;
for ( ; pDest < &__ram_data_end__ ; ) {
*pDest++ = *pSrc++;
}
#ifdef __STARTUP_CLEAR_BSS
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
pDest = &__bss_start__;
for ( ; pDest < &__bss_end__ ; ) {
*pDest++ = 0ul;
}
#endif
}

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#include <stdint.h>
#include "../risc-v/Core/Include/clic.h"
#include "../risc-v/Core/Include/cmsis_compatible_gcc.h"
typedef void( *pFunc )( void );
extern void Trap_Handler(void);
extern void Interrupt_Handler(void);
void Interrupt_Handler_Stub(void);
void clic_msip_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void clic_mtimer_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void clic_mext_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void clic_csoft_handler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void BMX_TO_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void L1C_BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void L1C_BMX_TO_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void RF_TOP_INT0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void RF_TOP_INT1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SDIO_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void DMA_BMX_ERR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_GMAC_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_CDET_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_PKA_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_TRNG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_AES_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SEC_SHA_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void DMA_ALL_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void IRTX_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void IRRX_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SF_CTRL_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void GPADC_DMA_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void EFUSE_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void SPI_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void UART0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void UART1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void I2C_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void PWM_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void TIMER_CH0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void TIMER_CH1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void TIMER_WDT_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void GPIO_INT0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void PDS_WAKEUP_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void HBN_OUT0_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void HBN_OUT1_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void BOR_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void WIFI_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void BZ_PHY_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void BLE_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void MAC_TXRX_TIMER_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void MAC_TXRX_MISC_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void MAC_RX_TRG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void MAC_TX_TRG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void MAC_GEN_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void MAC_PORT_TRG_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
void WIFI_IPC_PUBLIC_IRQHandler_Wrapper (void) __attribute__ ((weak, alias("Interrupt_Handler_Stub")));
const pFunc __Vectors[] __attribute__ ((section(".init"),aligned(64))) = {
0, /* */
0, /* */
0, /* */
clic_msip_handler_Wrapper, /* */
0, /* */
0, /* */
0, /* */
clic_mtimer_handler_Wrapper, /* */
(pFunc)0x00000004, /* */
(pFunc)0x00001007, /* */
(pFunc)0x00010002, /* */
clic_mext_handler_Wrapper, /* */
clic_csoft_handler_Wrapper, /* */
(pFunc)2000000, /* */
0, /* */
0, /* */
BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */
BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */
L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */
L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */
SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */
RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */
RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */
SDIO_IRQHandler_Wrapper, /* 16 + 7 */
DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */
SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */
SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */
SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */
SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */
SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */
SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */
DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */
0, /* 16 + 16 */
0, /* 16 + 17 */
0, /* 16 + 18 */
IRTX_IRQHandler_Wrapper, /* 16 + 19 */
IRRX_IRQHandler_Wrapper, /* 16 + 20 */
0, /* 16 + 21 */
0, /* 16 + 22 */
SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */
0, /* 16 + 24 */
GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */
EFUSE_IRQHandler_Wrapper, /* 16 + 26 */
SPI_IRQHandler_Wrapper, /* 16 + 27 */
0, /* 16 + 28 */
UART0_IRQHandler_Wrapper, /* 16 + 29 */
UART1_IRQHandler_Wrapper, /* 16 + 30 */
0, /* 16 + 31 */
I2C_IRQHandler_Wrapper, /* 16 + 32 */
0, /* 16 + 33 */
PWM_IRQHandler_Wrapper, /* 16 + 34 */
0, /* 16 + 35 */
TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */
TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */
TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */
0, /* 16 + 39 */
0, /* 16 + 40 */
0, /* 16 + 41 */
0, /* 16 + 42 */
0, /* 16 + 43 */
GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */
0, /* 16 + 45 */
0, /* 16 + 46 */
0, /* 16 + 47 */
0, /* 16 + 48 */
0, /* 16 + 49 */
PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */
HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */
HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */
BOR_IRQHandler_Wrapper, /* 16 + 53 */
WIFI_IRQHandler_Wrapper, /* 16 + 54 */
BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */
BLE_IRQHandler_Wrapper, /* 16 + 56 */
MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */
MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */
MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */
MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */
MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */
MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */
WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
};
void __IRQ_ALIGN64 Trap_Handler_Stub(void){
Trap_Handler();
}
void __IRQ Interrupt_Handler_Stub(void){
Interrupt_Handler();
}
void clic_enable_interrupt (uint32_t source) {
*(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIE+source) = 1;
}
void clic_disable_interrupt ( uint32_t source){
*(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIE+source) = 0;
}
void clic_set_pending(uint32_t source){
*(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIP+source) = 1;
}
void clic_clear_pending(uint32_t source){
*(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTIP+source) = 0;
}
void clic_set_intcfg (uint32_t source, uint32_t intcfg){
*(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTCFG+source) = intcfg;
}
uint8_t clic_get_intcfg ( uint32_t source){
return *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_INTCFG+source);
}
void clic_set_cliccfg ( uint32_t cfg){
*(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_CFG) = cfg;
}
uint8_t clic_get_cliccfg (void){
return *(volatile uint8_t*)(CLIC_HART0_ADDR+CLIC_CFG);
}

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#include "bl602.h"
#include "bl602_glb.h"
#include "bl602_hbn.h"
#include "system_bl602.h"
#ifdef BOOTROM
#include "bflb_bootrom.h"
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define SYSTEM_CLOCK ( 32000000UL )
/*----------------------------------------------------------------------------
Vector Table
*----------------------------------------------------------------------------*/
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void system_bor_init(void)
{
HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */};
HBN_Set_BOR_Cfg(&borCfg);
}
void SystemInit (void)
{
uint32_t *p;
uint32_t i=0;
uint32_t tmpVal=0;
#ifdef BOOTROM
extern void GLB_Power_On_LDO18_IO(void);
extern void WDT_Disable(void);
extern void HBN_Clear_RTC_INT(void);
BMX_Cfg_Type bmxCfg={
.timeoutEn=0,
.errEn=DISABLE,
.arbMod=BMX_ARB_FIX
};
L1C_BMX_Cfg_Type l1cBmxCfg={
.timeoutEn=0,
.errEn=DISABLE,
.arbMod=L1C_BMX_ARB_FIX,
};
/* NP boot log Flag */
p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR);
*p=0x5A5AA5A5;
/*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,
if not disable this bit, CPU will also get hardfault at the same time*/
//GLB->bmx_cfg1.BF.bmx_err_en=0;
//GLB->bmx_cfg1.BF.bmx_timeout_en=0;
//GLB->bmx_cfg2.BF.bmx_err_addr_dis=1;
GLB_BMX_Init(&bmxCfg);
GLB_BMX_Addr_Monitor_Disable();
//L1C->l1c_config.BF.l1c_bmx_err_en=0;
//L1C->l1c_config.BF.l1c_bmx_timeout_en=0;
//L1C->l1c_bmx_err_addr_en.BF.l1c_bmx_err_addr_dis=1;
L1C_BMX_Init(&l1cBmxCfg);
L1C_BMX_Addr_Monitor_Disable();
//L1C->l1c_config.BF.l1c_way_dis=0xf;
L1C_Set_Way_Disable(0x0f);
/* Disable Watchdog */
WDT_Disable();
/* Clear RTC */
HBN_Clear_RTC_INT();
/* Make OCRAM Idle from retention or sleep */
GLB_Set_OCRAM_Idle();
/* Disable embedded flash power up*/
HBN_Set_Embedded_Flash_Pullup(DISABLE);
#endif
/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE);
tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD);
BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal);
/* GLB_Set_EM_Sel(GLB_EM_0KB); */
tmpVal=BL_RD_REG(GLB_BASE,GLB_SEAM_MISC);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_EM_SEL,GLB_EM_0KB);
BL_WR_REG(GLB_BASE,GLB_SEAM_MISC,tmpVal);
/* Fix 26M xtal clkpll_sdmin */
tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_SDM);
if(0x49D39D==BL_GET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN)){
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN,0x49D89E);
BL_WR_REG(PDS_BASE,PDS_CLKPLL_SDM,tmpVal);
}
/* Restore default setting*/
/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
tmpVal=BL_RD_REG(GLB_BASE,GLB_PARM);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_UART_SWAP_SET,UART_SIG_SWAP_NONE);
BL_WR_REG(GLB_BASE,GLB_PARM,tmpVal);
/* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */
tmpVal=BL_RD_REG(GLB_BASE,GLB_PARM);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_JTAG_SWAP_SET,JTAG_SIG_SWAP_NONE);
BL_WR_REG(GLB_BASE,GLB_PARM,tmpVal);
/* CLear all interrupt */
p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIE);
for(i=0;i<(IRQn_LAST+3)/4;i++){
p[i]=0;
}
p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIP);
for(i=0;i<(IRQn_LAST+3)/4;i++){
p[i]=0;
}
/* global IRQ enable */
__enable_irq();
/* init bor for all platform */
system_bor_init();
#ifdef BOOTROM
/*Power up soc 11 power domain,TODO: This should be optional */
//AON_Power_On_SOC_11();
/* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/
//BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);
/* Power up flash power*/
//GLB_Power_On_LDO18_IO();
#endif
}
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
}

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drivers/bl602_driver/startup/system_bl602.h Normal file
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#ifndef __SYSTEM_BL602_H__
#define __SYSTEM_BL602_H__
/**
* @brief PLL Clock type definition
*/
extern uint32_t SystemCoreClock;
extern void SystemCoreClockUpdate (void);
extern void SystemInit (void);
extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
extern void Systick_Stop(void);
extern void Systick_Start(void);
#endif

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drivers/bl602_driver/std_drv/inc/bl602_acomp.h Normal file
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/**
******************************************************************************
* @file bl602_acomp.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_ACOMP_H__
#define __BL602_ACOMP_H__
#include "aon_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup ACOMP
* @{
*/
/** @defgroup ACOMP_Public_Types
* @{
*/
/**
* @brief Analog compare id type definition
*/
typedef enum {
AON_ACOMP0_ID, /*!< Analog compare 0 */
AON_ACOMP1_ID, /*!< Analog compare 1 */
}AON_ACOMP_ID_Type;
/**
* @brief Analog compare level type definition
*/
typedef enum {
AON_ACOMP_LEVEL_FACTOR_0P25, /*!< Analog compare level scaling factor 0.25 */
AON_ACOMP_LEVEL_FACTOR_0P5, /*!< Analog compare level scaling factor 0.5 */
AON_ACOMP_LEVEL_FACTOR_0P75, /*!< Analog compare level scaling factor 0.75 */
AON_ACOMP_LEVEL_FACTOR_1, /*!< Analog compare level scaling factor 1 */
}AON_ACOMP_Level_Factor_Type;
/**
* @brief Analog compare channel type definition
*/
typedef enum {
AON_ACOMP_CHAN_ADC0, /*!< Analog compare channel,ADC input channel 0 */
AON_ACOMP_CHAN_ADC1, /*!< Analog compare channel,ADC input channel 1 */
AON_ACOMP_CHAN_ADC2, /*!< Analog compare channel,ADC input channel 2 */
AON_ACOMP_CHAN_ADC3, /*!< Analog compare channel,ADC input channel 3 */
AON_ACOMP_CHAN_ADC4, /*!< Analog compare channel,ADC input channel 4 */
AON_ACOMP_CHAN_ADC5, /*!< Analog compare channel,ADC input channel 5 */
AON_ACOMP_CHAN_ADC6, /*!< Analog compare channel,ADC input channel 6 */
AON_ACOMP_CHAN_ADC7, /*!< Analog compare channel,ADC input channel 7 */
AON_ACOMP_CHAN_DACA, /*!< Analog compare channel,DAC output channel A */
AON_ACOMP_CHAN_DACB, /*!< Analog compare channel,DAC output channel B */
AON_ACOMP_CHAN_VREF_1P2V, /*!< Analog compare channel,1.2V ref voltage */
AON_ACOMP_CHAN_0P375VBAT_NOT_IMP, /*!< Analog compare channel,6/16Vbat */
AON_ACOMP_CHAN_0P25VBAT, /*!< Analog compare channel,4/16Vbat */
AON_ACOMP_CHAN_0P1875VBAT, /*!< Analog compare channel,3/16Vbat */
AON_ACOMP_CHAN_0P3125VBAT, /*!< Analog compare channel,5/16Vbat */
AON_ACOMP_CHAN_VSS, /*!< Analog compare channel,vss */
}AON_ACOMP_Chan_Type;
/**
* @brief Analog compare bias current control type definition
*/
typedef enum {
AON_ACOMP_BIAS_POWER_MODE1, /*!< Analog compare power mode 1,slow response mode */
AON_ACOMP_BIAS_POWER_MODE2, /*!< Analog compare power mode 2,medium response mode */
AON_ACOMP_BIAS_POWER_MODE3, /*!< Analog compare power mode 3,fast response mode */
AON_ACOMP_BIAS_POWER_NONE, /*!< Analog compare power mode none */
}AON_ACOMP_Bias_Prog_Type;
/**
* @brief Analog compare hysteresis voltage type definition
*/
typedef enum {
AON_ACOMP_HYSTERESIS_VOLT_NONE, /*!< Analog compare hysteresis voltage none */
AON_ACOMP_HYSTERESIS_VOLT_10MV, /*!< Analog compare hysteresis voltage 10mv */
AON_ACOMP_HYSTERESIS_VOLT_20MV, /*!< Analog compare hysteresis voltage 20mv */
AON_ACOMP_HYSTERESIS_VOLT_30MV, /*!< Analog compare hysteresis voltage 30mv */
AON_ACOMP_HYSTERESIS_VOLT_40MV, /*!< Analog compare hysteresis voltage 40mv */
AON_ACOMP_HYSTERESIS_VOLT_50MV, /*!< Analog compare hysteresis voltage 50mv */
AON_ACOMP_HYSTERESIS_VOLT_60MV, /*!< Analog compare hysteresis voltage 60mv */
AON_ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */
}AON_ACOMP_Hysteresis_Volt_Type;
/**
* @brief AON ACOMP configuration type definition
*/
typedef struct {
BL_Fun_Type muxEn; /*!< ACOMP mux enable */
uint8_t posChanSel; /*!< ACOMP positive channel select */
uint8_t negChanSel; /*!< ACOMP negtive channel select */
AON_ACOMP_Level_Factor_Type levelFactor; /*!< ACOMP level select factor */
AON_ACOMP_Bias_Prog_Type biasProg; /*!< ACOMP bias current control */
AON_ACOMP_Hysteresis_Volt_Type hysteresisPosVolt; /*!< ACOMP hysteresis voltage for positive */
AON_ACOMP_Hysteresis_Volt_Type hysteresisNegVolt; /*!< ACOMP hysteresis voltage for negtive */
}AON_ACOMP_CFG_Type;
/*@} end of group ACOMP_Public_Types */
/** @defgroup ACOMP_Public_Constants
* @{
*/
/** @defgroup AON_ACOMP_ID_TYPE
* @{
*/
#define IS_AON_ACOMP_ID_TYPE(type) (((type) == AON_ACOMP0_ID) || \
((type) == AON_ACOMP1_ID))
/** @defgroup AON_ACOMP_LEVEL_FACTOR_TYPE
* @{
*/
#define IS_AON_ACOMP_LEVEL_FACTOR_TYPE(type) (((type) == AON_ACOMP_LEVEL_FACTOR_0P25) || \
((type) == AON_ACOMP_LEVEL_FACTOR_0P5) || \
((type) == AON_ACOMP_LEVEL_FACTOR_0P75) || \
((type) == AON_ACOMP_LEVEL_FACTOR_1))
/** @defgroup AON_ACOMP_CHAN_TYPE
* @{
*/
#define IS_AON_ACOMP_CHAN_TYPE(type) (((type) == AON_ACOMP_CHAN_ADC0) || \
((type) == AON_ACOMP_CHAN_ADC1) || \
((type) == AON_ACOMP_CHAN_ADC2) || \
((type) == AON_ACOMP_CHAN_ADC3) || \
((type) == AON_ACOMP_CHAN_ADC4) || \
((type) == AON_ACOMP_CHAN_ADC5) || \
((type) == AON_ACOMP_CHAN_ADC6) || \
((type) == AON_ACOMP_CHAN_ADC7) || \
((type) == AON_ACOMP_CHAN_DACA) || \
((type) == AON_ACOMP_CHAN_DACB) || \
((type) == AON_ACOMP_CHAN_VREF_1P2V) || \
((type) == AON_ACOMP_CHAN_0P375VBAT_NOT_IMP) || \
((type) == AON_ACOMP_CHAN_0P25VBAT) || \
((type) == AON_ACOMP_CHAN_0P1875VBAT) || \
((type) == AON_ACOMP_CHAN_0P3125VBAT) || \
((type) == AON_ACOMP_CHAN_VSS))
/** @defgroup AON_ACOMP_BIAS_PROG_TYPE
* @{
*/
#define IS_AON_ACOMP_BIAS_PROG_TYPE(type) (((type) == AON_ACOMP_BIAS_POWER_MODE1) || \
((type) == AON_ACOMP_BIAS_POWER_MODE2) || \
((type) == AON_ACOMP_BIAS_POWER_MODE3) || \
((type) == AON_ACOMP_BIAS_POWER_NONE))
/** @defgroup AON_ACOMP_HYSTERESIS_VOLT_TYPE
* @{
*/
#define IS_AON_ACOMP_HYSTERESIS_VOLT_TYPE(type) (((type) == AON_ACOMP_HYSTERESIS_VOLT_NONE) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_10MV) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_20MV) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_30MV) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_40MV) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_50MV) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_60MV) || \
((type) == AON_ACOMP_HYSTERESIS_VOLT_70MV))
/*@} end of group ACOMP_Public_Constants */
/** @defgroup ACOMP_Public_Macros
* @{
*/
/*@} end of group ACOMP_Public_Macros */
/** @defgroup ACOMP_Public_Functions
* @{
*/
void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg);
void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo);
BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo);
/*@} end of group ACOMP_Public_Functions */
/*@} end of group ACOMP */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_ACOMP_H__ */

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/**
******************************************************************************
* @file bl602_adc.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_ADC_H__
#define __BL602_ADC_H__
#include "aon_reg.h"
#include "gpip_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_Public_Types
* @{
*/
/**
* @brief ADC channel type definition
*/
typedef enum {
ADC_CHAN0, /*!< GPIO 0, ADC channel 0 */
ADC_CHAN1, /*!< GPIO 1, ADC channel 1 */
ADC_CHAN2, /*!< GPIO 2, ADC channel 2 */
ADC_CHAN3, /*!< GPIO 3, ADC channel 3 */
ADC_CHAN4, /*!< GPIO 4, ADC channel 4 */
ADC_CHAN5, /*!< GPIO 5, ADC channel 5 */
ADC_CHAN6, /*!< GPIO 6, ADC channel 6 */
ADC_CHAN7, /*!< GPIO 7, ADC channel 7 */
ADC_CHAN8, /*!< GPIO 8, ADC channel 8 */
ADC_CHAN9, /*!< GPIO 9, ADC channel 9 */
ADC_CHAN10, /*!< GPIO 10, ADC channel 10 */
ADC_CHAN11, /*!< GPIO 11, ADC channel 11 */
ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */
ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */
ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */
ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */
ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */
ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */
ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */
ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */
ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */
ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */
ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */
ADC_CHAN_GND, /*!< GND, ADC channel 23 */
}ADC_Chan_Type;
/**
* @brief ADC V18 selection type definition
*/
typedef enum {
ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */
ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */
ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */
ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */
}ADC_V18_SEL_Type;
/**
* @brief ADC V11 selection type definition
*/
typedef enum {
ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */
ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */
ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */
ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */
}ADC_V11_SEL_Type;
/**
* @brief ADC clock type definition
*/
typedef enum {
ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */
ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */
ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */
ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
}ADC_CLK_Type;
/**
* @brief ADC conversion speed type definition
*/
typedef enum {
ADC_DELAY_SEL_0, /*!< Select delay 0 */
ADC_DELAY_SEL_1, /*!< Select delay 1 */
ADC_DELAY_SEL_2, /*!< Select delay 2 */
ADC_DELAY_SEL_3, /*!< Select delay 3 */
ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */
ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */
ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */
ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */
}ADC_DELAY_SEL_Type;
/**
* @brief ADC PGA gain type definition
*/
typedef enum {
ADC_PGA_GAIN_NONE, /*!< No PGA gain */
ADC_PGA_GAIN_1, /*!< PGA gain 1 */
ADC_PGA_GAIN_2, /*!< PGA gain 2 */
ADC_PGA_GAIN_4, /*!< PGA gain 4 */
ADC_PGA_GAIN_8, /*!< PGA gain 8 */
ADC_PGA_GAIN_16, /*!< PGA gain 16 */
ADC_PGA_GAIN_32, /*!< PGA gain 32 */
}ADC_PGA_GAIN_Type;
/**
* @brief ADC analog portion low power mode selection type definition
*/
typedef enum {
ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */
ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */
}ADC_BIAS_SEL_Type;
/**
* @brief ADC chop mode type definition
*/
typedef enum {
ADC_CHOP_MOD_ALL_OFF, /*!< all off */
ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */
ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */
ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */
}ADC_CHOP_MOD_Type;
/**
* @brief ADC audio PGA output common mode control type definition
*/
typedef enum {
ADC_PGA_VCM_1V, /*!< ADC VCM=1V */
ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */
ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */
ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */
}ADC_PGA_VCM_Type;
/**
* @brief ADC tsen diode mode type definition
*/
typedef enum {
ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */
ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */
}ADC_TSEN_MOD_Type;
/**
* @brief ADC voltage reference type definition
*/
typedef enum {
ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */
ADC_VREF_2V, /*!< ADC select 2V as reference voltage */
}ADC_VREF_Type;
/**
* @brief ADC signal input type definition
*/
typedef enum {
ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */
ADC_INPUT_DIFF, /*!< ADC signal is differential */
}ADC_SIG_INPUT_Type;
/**
* @brief ADC data width type definition
*/
typedef enum {
ADC_DATA_WIDTH_12, /*!< ADC 12 bits */
ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */
ADC_DATA_WIDTH_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
}ADC_Data_Width_Type;
/**
* @brief ADC micboost 32db type definition
*/
typedef enum {
ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */
ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */
}ADC_MICBOOST_DB_Type;
/**
* @brief ADC pga2 gain type definition
*/
typedef enum {
ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */
ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */
ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */
ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */
}ADC_PGA2_GAIN_Type;
/**
* @brief ADC mic mode type definition
*/
typedef enum {
ADC_MIC_MODE_SINGLE, /*!< MIC single mode */
ADC_MIC_MODE_DIFF, /*!< MIC diff mode */
}ADC_MIC_MODE_Type;
/**
* @brief ADC mic type definition
*/
typedef struct {
ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */
ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */
ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */
ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */
BL_Fun_Type dwaEn; /*!< Improve dynamic performance */
BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */
BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */
BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */
}ADC_MIC_Type;
/**
* @brief ADC configuration type definition
*/
typedef struct {
ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */
ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */
ADC_CLK_Type clkDiv; /*!< Clock divider */
ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */
ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */
ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */
ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */
ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */
ADC_VREF_Type vref; /*!< ADC voltage reference */
ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */
ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */
BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */
int16_t offsetCalibVal; /*!< Offset calibration value */
}ADC_CFG_Type;
/**
* @brief ADC configuration type definition
*/
typedef struct {
int8_t posChan; /*!< Positive channel */
int8_t negChan; /*!< Negative channel */
uint16_t value; /*!< ADC value */
float volt; /*!< ADC voltage result */
}ADC_Result_Type;
/**
* @brief ADC FIFO threshold type definition
*/
typedef enum {
ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */
ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */
ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */
ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */
}ADC_FIFO_Threshold_Type;
/**
* @brief ADC interrupt type definition
*/
typedef enum {
ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */
ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */
ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */
ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */
ADC_INT_ADC_READY, /*!< ADC data ready interrupt */
ADC_INT_ALL, /*!< ADC all the interrupt */
}ADC_INT_Type;
/**
* @brief ADC FIFO configuration structure type definition
*/
typedef struct {
ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */
BL_Fun_Type dmaEn; /*!< ADC DMA enable */
}ADC_FIFO_Cfg_Type;
/**
* @brief ADC REG GAIN CAL
*/
typedef struct {
BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */
uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */
float coe; /*!< ADC_Gain_Coeff result */
}ADC_Gain_Coeff_Type;
/*@} end of group ADC_Public_Types */
/** @defgroup ADC_Public_Constants
* @{
*/
/** @defgroup ADC_CHAN_TYPE
* @{
*/
#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \
((type) == ADC_CHAN1) || \
((type) == ADC_CHAN2) || \
((type) == ADC_CHAN3) || \
((type) == ADC_CHAN4) || \
((type) == ADC_CHAN5) || \
((type) == ADC_CHAN6) || \
((type) == ADC_CHAN7) || \
((type) == ADC_CHAN8) || \
((type) == ADC_CHAN9) || \
((type) == ADC_CHAN10) || \
((type) == ADC_CHAN11) || \
((type) == ADC_CHAN_DAC_OUTA) || \
((type) == ADC_CHAN_DAC_OUTB) || \
((type) == ADC_CHAN_TSEN_P) || \
((type) == ADC_CHAN_TSEN_N) || \
((type) == ADC_CHAN_VREF) || \
((type) == ADC_CHAN_DCTEST) || \
((type) == ADC_CHAN_VABT_HALF) || \
((type) == ADC_CHAN_SENP3) || \
((type) == ADC_CHAN_SENP2) || \
((type) == ADC_CHAN_SENP1) || \
((type) == ADC_CHAN_SENP0) || \
((type) == ADC_CHAN_GND))
/** @defgroup ADC_V18_SEL_TYPE
* @{
*/
#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \
((type) == ADC_V18_SEL_1P72V) || \
((type) == ADC_V18_SEL_1P82V) || \
((type) == ADC_V18_SEL_1P92V))
/** @defgroup ADC_V11_SEL_TYPE
* @{
*/
#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \
((type) == ADC_V11_SEL_1P1V) || \
((type) == ADC_V11_SEL_1P18V) || \
((type) == ADC_V11_SEL_1P26V))
/** @defgroup ADC_CLK_TYPE
* @{
*/
#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \
((type) == ADC_CLK_DIV_4) || \
((type) == ADC_CLK_DIV_8) || \
((type) == ADC_CLK_DIV_12) || \
((type) == ADC_CLK_DIV_16) || \
((type) == ADC_CLK_DIV_20) || \
((type) == ADC_CLK_DIV_24) || \
((type) == ADC_CLK_DIV_32))
/** @defgroup ADC_DELAY_SEL_TYPE
* @{
*/
#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \
((type) == ADC_DELAY_SEL_1) || \
((type) == ADC_DELAY_SEL_2) || \
((type) == ADC_DELAY_SEL_3) || \
((type) == ADC_DELAY_SEL_4) || \
((type) == ADC_DELAY_SEL_5) || \
((type) == ADC_DELAY_SEL_6) || \
((type) == ADC_DELAY_SEL_7))
/** @defgroup ADC_PGA_GAIN_TYPE
* @{
*/
#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \
((type) == ADC_PGA_GAIN_1) || \
((type) == ADC_PGA_GAIN_2) || \
((type) == ADC_PGA_GAIN_4) || \
((type) == ADC_PGA_GAIN_8) || \
((type) == ADC_PGA_GAIN_16) || \
((type) == ADC_PGA_GAIN_32))
/** @defgroup ADC_BIAS_SEL_TYPE
* @{
*/
#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \
((type) == ADC_BIAS_SEL_AON_BANDGAP))
/** @defgroup ADC_CHOP_MOD_TYPE
* @{
*/
#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \
((type) == ADC_CHOP_MOD_AZ_ON) || \
((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \
((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON))
/** @defgroup ADC_PGA_VCM_TYPE
* @{
*/
#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \
((type) == ADC_PGA_VCM_1P2V) || \
((type) == ADC_PGA_VCM_1P4V) || \
((type) == ADC_PGA_VCM_1P6V))
/** @defgroup ADC_TSEN_MOD_TYPE
* @{
*/
#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \
((type) == ADC_TSEN_MOD_EXTERNAL_DIODE))
/** @defgroup ADC_VREF_TYPE
* @{
*/
#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P2V) || \
((type) == ADC_VREF_2V))
/** @defgroup ADC_SIG_INPUT_TYPE
* @{
*/
#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \
((type) == ADC_INPUT_DIFF))
/** @defgroup ADC_DATA_WIDTH_TYPE
* @{
*/
#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \
((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \
((type) == ADC_DATA_WIDTH_16_WITH_64_AVERAGE) || \
((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \
((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE))
/** @defgroup ADC_MICBOOST_DB_TYPE
* @{
*/
#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \
((type) == ADC_MICBOOST_DB_32DB))
/** @defgroup ADC_PGA2_GAIN_TYPE
* @{
*/
#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \
((type) == ADC_PGA2_GAIN_6DB) || \
((type) == ADC_PGA2_GAIN_N6DB) || \
((type) == ADC_PGA2_GAIN_12DB))
/** @defgroup ADC_MIC_MODE_TYPE
* @{
*/
#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \
((type) == ADC_MIC_MODE_DIFF))
/** @defgroup ADC_FIFO_THRESHOLD_TYPE
* @{
*/
#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \
((type) == ADC_FIFO_THRESHOLD_4) || \
((type) == ADC_FIFO_THRESHOLD_8) || \
((type) == ADC_FIFO_THRESHOLD_16))
/** @defgroup ADC_INT_TYPE
* @{
*/
#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \
((type) == ADC_INT_NEG_SATURATION) || \
((type) == ADC_INT_FIFO_UNDERRUN) || \
((type) == ADC_INT_FIFO_OVERRUN) || \
((type) == ADC_INT_ADC_READY) || \
((type) == ADC_INT_ALL))
/*@} end of group ADC_Public_Constants */
/** @defgroup ADC_Public_Macros
* @{
*/
/*@} end of group ADC_Public_Macros */
/** @defgroup ADC_Public_Functions
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
void GPADC_DMA_IRQHandler(void);
#endif
void ADC_Vbat_Enable(void);
void ADC_Vbat_Disable(void);
void ADC_Reset(void);
void ADC_Enable(void);
void ADC_Disable(void);
void ADC_Init(ADC_CFG_Type* cfg);
void ADC_Channel_Config(ADC_Chan_Type posCh,ADC_Chan_Type negCh,BL_Fun_Type contEn);
void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[],ADC_Chan_Type negChList[],uint8_t scanLength,BL_Fun_Type contEn);
void ADC_Start(void);
void ADC_Stop(void);
void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg);
uint8_t ADC_Get_FIFO_Count(void);
BL_Sts_Type ADC_FIFO_Is_Empty(void);
BL_Sts_Type ADC_FIFO_Is_Full(void);
uint32_t ADC_Read_FIFO(void);
void ADC_Parse_Result(uint32_t *orgVal,uint32_t len,ADC_Result_Type *result);
void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask);
void ADC_IntClr(ADC_INT_Type intType);
BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType);
void ADC_Int_Callback_Install(ADC_INT_Type intType,intCallback_Type* cbFun);
void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask);
void ADC_SET_TSVBE_LOW(void);
void ADC_SET_TSVBE_HIGH(void);
void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod);
BL_Err_Type ADC_Mic_Init(ADC_MIC_Type * adc_mic_config);
void ADC_MIC_Bias_Disable(void);
void ADC_MIC_Bias_Enable(void);
BL_Err_Type ADC_Trim_TSEN(uint16_t * tsen_offset);
BL_Err_Type ADC_Gain_Trim(void);
uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg);
float TSEN_Get_Temp(uint32_t tsen_offset);
/*@} end of group ADC_Public_Functions */
/*@} end of group ADC */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_ADC_H__ */

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/**
******************************************************************************
* @file bl602_aon.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_AON_H__
#define __BL602_AON_H__
#include "aon_reg.h"
#include "glb_reg.h"
#include "hbn_reg.h"
#include "pds_reg.h"
#include "bl602_ef_ctrl.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup AON
* @{
*/
/** @defgroup AON_Public_Types
* @{
*/
/*@} end of group AON_Public_Types */
/** @defgroup AON_Public_Constants
* @{
*/
/*@} end of group AON_Public_Constants */
/** @defgroup AON_Public_Macros
* @{
*/
/*@} end of group AON_Public_Macros */
/** @defgroup AON_Public_Functions
* @{
*/
/*----------*/
BL_Err_Type AON_Power_On_MBG(void);
BL_Err_Type AON_Power_Off_MBG(void);
/*----------*/
BL_Err_Type AON_Power_On_XTAL(void);
BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut);
uint8_t AON_Get_Xtal_CapCode(void);
BL_Err_Type AON_Power_Off_XTAL(void);
/*----------*/
BL_Err_Type AON_Power_On_BG(void);
BL_Err_Type AON_Power_Off_BG(void);
/*----------*/
BL_Err_Type AON_Power_On_LDO11_SOC(void);
BL_Err_Type AON_Power_Off_LDO11_SOC(void);
/*----------*/
BL_Err_Type AON_Power_On_LDO15_RF(void);
BL_Err_Type AON_Power_Off_LDO15_RF(void);
/*----------*/
BL_Err_Type AON_Power_On_SFReg(void);
BL_Err_Type AON_Power_Off_SFReg(void);
/*----------*/
BL_Err_Type AON_LowPower_Enter_PDS0(void);
BL_Err_Type AON_LowPower_Exit_PDS0(void);
/*----------*/
BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay);
/*----------*/;
/*@} end of group AON_Public_Functions */
/*@} end of group AON */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_AON_H__ */

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#ifndef __BL602_COMMON_H__
#define __BL602_COMMON_H__
#include "bl602.h"
#include "bflb_platform.h"
/** @addtogroup BL606_Peripheral_Driver
* @{
*/
/** @addtogroup COMMON
* @{
*/
/** @defgroup COMMON_Public_Types
* @{
*/
/*@} end of group COMMON_Public_Types */
/** @defgroup COMMON_Public_Constants
* @{
*/
/** @defgroup DRIVER_INT_PERIPH
* @{
*/
#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
/*@} end of group DRIVER_INT_PERIPH */
/** @defgroup DRIVER_INT_MASK
* @{
*/
#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
/*@} end of group COMMON_Public_Constants */
/** @defgroup COMMON_Public_Macros
* @{
*/
/*@} end of group DRIVER_Public_Macro */
/** @defgroup DRIVER_Public_FunctionDeclaration
* @brief DRIVER functions declaration
* @{
*/
#define ARCH_Delay_US BL602_Delay_US
#define ARCH_Delay_MS BL602_Delay_MS
void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun);
void ASM_Delay_Us(uint32_t core,uint32_t cnt);
void BL602_Delay_US(uint32_t cnt);
void BL602_Delay_MS(uint32_t cnt);
#endif /* __BL602_COMMON_H__ */

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/**
******************************************************************************
* @file bl602_dac.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_DAC_H__
#define __BL602_DAC_H__
#include "aon_reg.h"
#include "glb_reg.h"
#include "gpip_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Public_Types
* @{
*/
/**
* @brief DAC reference voltage definition
*/
typedef enum {
GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */
GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */
}GLB_DAC_Ref_Sel_Type;
/**
* @brief DAC reference voltage definition
*/
typedef enum {
GLB_DAC_Output_Volt_0P2_1, /*!< DAC output voltage is 0.2-1V */
GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */
GLB_DAC_Output_Volt_RESEVED, /*!< DAC output voltage is 0.225-1.425V */
GLB_DAC_Output_Volt_0P2_1P8, /*!< DAC output voltage is 0.2-1.8V */
}GLB_DAC_Output_Volt_Range_Type;
/**
* @brief DAC channel type definition
*/
typedef enum {
GLB_DAC_CHAN0, /*!< DAC channel 0 */
GLB_DAC_CHAN1, /*!< DAC channel 1 */
GLB_DAC_CHAN2, /*!< DAC channel 2 */
GLB_DAC_CHAN3, /*!< DAC channel 3 */
GLB_DAC_CHAN4, /*!< DAC channel 4 */
GLB_DAC_CHAN5, /*!< DAC channel 5 */
GLB_DAC_CHAN6, /*!< DAC channel 6 */
GLB_DAC_CHAN7, /*!< DAC channel 7 */
GLB_DAC_CHAN_ALL, /*!< DAC channel all */
}GLB_DAC_Chan_Type;
/**
* @brief DAC channel configuration structure type definition
*/
typedef struct {
BL_Fun_Type chanEn; /*!< Enable this channel or not */
BL_Fun_Type outputEn; /*!< Output this channel result to PAD */
GLB_DAC_Chan_Type outMux; /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */
GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */
}GLB_DAC_Chan_Cfg_Type;
/**
* @brief DAC configuration structure type definition
*/
typedef struct {
GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */
BL_Fun_Type resetChanA; /*!< Reset DAC channel A */
BL_Fun_Type resetChanB; /*!< Reset DAC channel B */
}GLB_DAC_Cfg_Type;
/**
* @brief DAC channel B source selection type definition
*/
typedef enum {
GPIP_DAC_ChanB_SRC_REG, /*!< select Reg as source of DAC channel B */
GPIP_DAC_ChanB_SRC_DMA, /*!< select DMA as source of DAC channel B */
GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */
GPIP_DAC_ChanB_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel B */
GPIP_DAC_ChanB_SRC_A, /*!< select channel A as source of DAC channel B */
GPIP_DAC_ChanB_SRC_INVERSE_A, /*!< select inverse of channel A as source of DAC channel B */
}GPIP_DAC_ChanB_SRC_Type;
/**
* @brief DAC channel A source selection type definition
*/
typedef enum {
GPIP_DAC_ChanA_SRC_REG, /*!< select Reg as source of DAC channel A */
GPIP_DAC_ChanA_SRC_DMA, /*!< select DMA as source of DAC channel A */
GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */
GPIP_DAC_ChanA_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel A */
}GPIP_DAC_ChanA_SRC_Type;
/**
* @brief DAC mode selection type definition
*/
typedef enum {
GPIP_DAC_MOD_32K, /*!< select 32K as DAC mode */
GPIP_DAC_MOD_16K, /*!< select 16K as DAC mode */
GPIP_DAC_MOD_RESERVE, /*!< reserved */
GPIP_DAC_MOD_8K, /*!< select 8K as DAC mode */
GPIP_DAC_MOD_512K, /*!< select 512 as DAC mode Only For DMA Mode */
}GPIP_DAC_MOD_Type;
/**
* @brief DAC DMA TX format selection type definition
*/
typedef enum {
GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */
GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */
GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */
}GPIP_DAC_DMA_TX_FORMAT_Type;
/**
* @brief AON and GPIP DAC configuration structure type definition
*/
typedef struct {
GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */
BL_Fun_Type resetChanA; /*!< Reset DAC channel A */
BL_Fun_Type resetChanB; /*!< Reset DAC channel B */
GPIP_DAC_MOD_Type mod; /*!< DAC mode selection */
BL_Fun_Type dmaEn; /*!< DAC DMA transfer enable */
GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */
}GLB_GPIP_DAC_Cfg_Type;
/**
* @brief AON and GPIP DAC channel A configuration structure type definition
*/
typedef struct {
BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */
BL_Fun_Type outputEn; /*!< Output this channel result to PAD */
BL_Fun_Type chanEn; /*!< Enable this channel or not */
GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */
}GLB_GPIP_DAC_ChanA_Cfg_Type;
/**
* @brief AON and GPIP DAC channel B configuration structure type definition
*/
typedef struct {
BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */
BL_Fun_Type outputEn; /*!< Output this channel result to PAD */
BL_Fun_Type chanEn; /*!< Enable this channel or not */
GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */
}GLB_GPIP_DAC_ChanB_Cfg_Type;
/*@} end of group DAC_Public_Types */
/** @defgroup DAC_Public_Constants
* @{
*/
/** @defgroup GLB_DAC_REF_SEL_TYPE
* @{
*/
#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \
((type) == GLB_DAC_REF_SEL_EXTERNAL))
/** @defgroup GLB_DAC_OUTPUT_VOLT_RANGE_TYPE
* @{
*/
#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) || \
((type) == GLB_DAC_Output_Volt_0P225_1P425) || \
((type) == GLB_DAC_Output_Volt_RESEVED) || \
((type) == GLB_DAC_Output_Volt_0P2_1P8))
/** @defgroup GLB_DAC_CHAN_TYPE
* @{
*/
#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \
((type) == GLB_DAC_CHAN1) || \
((type) == GLB_DAC_CHAN2) || \
((type) == GLB_DAC_CHAN3) || \
((type) == GLB_DAC_CHAN4) || \
((type) == GLB_DAC_CHAN5) || \
((type) == GLB_DAC_CHAN6) || \
((type) == GLB_DAC_CHAN7) || \
((type) == GLB_DAC_CHAN_ALL))
/** @defgroup GPIP_DAC_CHANB_SRC_TYPE
* @{
*/
#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) || \
((type) == GPIP_DAC_ChanB_SRC_DMA) || \
((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \
((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) || \
((type) == GPIP_DAC_ChanB_SRC_A) || \
((type) == GPIP_DAC_ChanB_SRC_INVERSE_A))
/** @defgroup GPIP_DAC_CHANA_SRC_TYPE
* @{
*/
#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) || \
((type) == GPIP_DAC_ChanA_SRC_DMA) || \
((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \
((type) == GPIP_DAC_ChanA_SRC_SIN_GEN))
/** @defgroup GPIP_DAC_MOD_TYPE
* @{
*/
#define IS_GPIP_DAC_MOD_TYPE(type) (((type) == GPIP_DAC_MOD_32K) || \
((type) == GPIP_DAC_MOD_16K) || \
((type) == GPIP_DAC_MOD_RESERVE) || \
((type) == GPIP_DAC_MOD_8K) || \
((type) == GPIP_DAC_MOD_512K))
/** @defgroup GPIP_DAC_DMA_TX_FORMAT_TYPE
* @{
*/
#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \
((type) == GPIP_DAC_DMA_FORMAT_1) || \
((type) == GPIP_DAC_DMA_FORMAT_2))
/*@} end of group DAC_Public_Constants */
/** @defgroup DAC_Public_Macros
* @{
*/
/*@} end of group DAC_Public_Macros */
/** @defgroup DAC_Public_Functions
* @{
*/
void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg);
void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg);
void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg);
void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src);
void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src);
void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod);
void GPIP_DAC_ChanB_Enable(void);
void GPIP_DAC_ChanB_Disable(void);
void GPIP_DAC_ChanA_Enable(void);
void GPIP_DAC_ChanA_Disable(void);
void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt);
void GPIP_Set_DAC_DMA_TX_Enable(void);
void GPIP_Set_DAC_DMA_TX_Disable(void);
void GPIP_DAC_DMA_WriteData(uint32_t data);
BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg);
void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg);
void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg);
void GLB_DAC_Set_ChanA_Value(uint16_t val);
void GLB_DAC_Set_ChanB_Value(uint16_t val);
/*@} end of group DAC_Public_Functions */
/*@} end of group DAC */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_DAC_H__ */

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/**
******************************************************************************
* @file bl602_dma.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_DMA_H__
#define __BL602_DMA_H__
#include "dma_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_Public_Types
* @{
*/
/**
* @brief DMA endian type definition
*/
typedef enum {
DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */
DMA_BIG_ENDIAN, /*!< DMA use big endian */
}DMA_Endian_Type;
/**
* @brief DMA synchronization logic type definition
*/
typedef enum {
DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */
DMA_SYNC_LOGIC_DISABLE, /*!< DMA synchronization logic disable */
}DMA_Sync_Logic_Type;
/**
* @brief DMA transfer width type definition
*/
typedef enum {
DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */
DMA_TRNS_WIDTH_16BITS, /*!< DMA transfer width:16 bits */
DMA_TRNS_WIDTH_32BITS, /*!< DMA transfer width:32 bits */
}DMA_Trans_Width_Type;
/**
* @brief DMA transfer direction type definition
*/
typedef enum {
DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */
DMA_TRNS_M2P, /*!< DMA transfer tyep:memory to peripheral */
DMA_TRNS_P2M, /*!< DMA transfer tyep:peripheral to memory */
DMA_TRNS_P2P, /*!< DMA transfer tyep:peripheral to peripheral */
}DMA_Trans_Dir_Type;
/**
* @brief DMA burst size type definition
*/
typedef enum {
DMA_BURST_SIZE_1 = 0, /*!< DMA transfer width:8 bits */
DMA_BURST_SIZE_4, /*!< DMA transfer width:16 bits */
DMA_BURST_SIZE_8, /*!< DMA transfer width:32 bits */
DMA_BURST_SIZE_16, /*!< DMA transfer width:64 bits */
}DMA_Burst_Size_Type;
/**
* @brief DMA destination peripheral type definition
*/
typedef enum {
DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX */
DMA_REQ_UART0_TX, /*!< DMA request peripheral:UART0 TX */
DMA_REQ_UART1_RX, /*!< DMA request peripheral:UART1 RX */
DMA_REQ_UART1_TX, /*!< DMA request peripheral:UART1 TX */
DMA_REQ_I2C_RX = 6, /*!< DMA request peripheral:I2C RX */
DMA_REQ_I2C_TX, /*!< DMA request peripheral:I2C TX */
DMA_REQ_SPI_RX = 10, /*!< DMA request peripheral:SPI RX */
DMA_REQ_SPI_TX, /*!< DMA request peripheral:SPI TX */
DMA_REQ_GPADC0 = 22, /*!< DMA request peripheral:GPADC0 */
DMA_REQ_GPADC1, /*!< DMA request peripheral:GPADC1 */
DMA_REQ_NONE = 0, /*!< DMA request peripheral:None */
}DMA_Periph_Req_Type;
/**
* @brief DMA channel type definition
*/
typedef enum {
DMA_CH0 = 0, /*!< DMA channel 0 */
DMA_CH1, /*!< DMA channel 1 */
DMA_CH2, /*!< DMA channel 2 */
DMA_CH3, /*!< DMA channel 3 */
DMA_CH_MAX, /*!< */
}DMA_Chan_Type;
/**
* @brief DMA interrupt type definition
*/
typedef enum {
DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */
DMA_INT_ERR, /*!< DMA error interrupt */
DMA_INT_ALL, /*!< All the interrupt */
}DMA_INT_Type;
/**
* @brief DMA LLI Structure PING-PONG
*/
typedef enum {
PING_INDEX = 0, /*!< PING INDEX */
PONG_INDEX, /*!< PONG INDEX */
}DMA_LLI_PP_Index_Type;
/**
* @brief DMA Configuration Structure type definition
*/
typedef struct {
DMA_Endian_Type endian; /*!< DMA endian type */
DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */
}DMA_Cfg_Type;
/**
* @brief DMA channel Configuration Structure type definition
*/
typedef struct {
uint32_t srcDmaAddr; /*!< Source address of DMA transfer */
uint32_t destDmaAddr; /*!< Destination address of DMA transfer */
uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */
DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */
DMA_Chan_Type ch; /*!< Channel select 0-4 */
DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */
DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits */
DMA_Burst_Size_Type srcBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
DMA_Burst_Size_Type dstBurstSzie; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width.
0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */
uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */
uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */
DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */
DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */
}DMA_Channel_Cfg_Type;
/**
* @brief DMA LLI control structure type definition
*/
typedef struct {
uint32_t srcDmaAddr; /*!< Source address of DMA transfer */
uint32_t destDmaAddr; /*!< Destination address of DMA transfer */
uint32_t nextLLI; /*!< Next LLI address */
struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */
}DMA_LLI_Ctrl_Type;
/**
* @brief DMA LLI configuration structure type definition
*/
typedef struct {
DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */
DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */
DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */
}DMA_LLI_Cfg_Type;
/**
* @brief DMA LLI Ping-Pong Buf definition
*/
typedef struct {
uint8_t idleIndex; /*!< Index Idle lliListHeader */
uint8_t dmaChan; /*!< DMA LLI Channel used */
DMA_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */
void (* onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */
}DMA_LLI_PP_Buf;
/**
* @brief DMA LLI Ping-Pong Structure definition
*/
typedef struct {
uint8_t trans_index; /*!< Ping or Pong Trigger TC */
uint8_t dmaChan; /*!< DMA LLI Channel used */
struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */
DMA_LLI_Cfg_Type *DMA_LLI_Cfg; /*!< LLI Config parameter */
uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */
uint32_t chache_buf_addr[2]; /*!< Ping-Pong structure chache */
BL_Fun_Type is_single_mode; /*!< is Ping-pong running forever or single mode ,if is single mode ping-pong will run only once
after one start */
}DMA_LLI_PP_Struct;
/*@} end of group DMA_Public_Types */
/** @defgroup DMA_Public_Constants
* @{
*/
/** @defgroup DMA_ENDIAN_TYPE
* @{
*/
#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN ) || \
((type) == DMA_BIG_ENDIAN))
/** @defgroup DMA_SYNC_LOGIC_TYPE
* @{
*/
#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE ) || \
((type) == DMA_SYNC_LOGIC_DISABLE))
/** @defgroup DMA_TRANS_WIDTH_TYPE
* @{
*/
#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS ) || \
((type) == DMA_TRNS_WIDTH_16BITS) || \
((type) == DMA_TRNS_WIDTH_32BITS))
/** @defgroup DMA_TRANS_DIR_TYPE
* @{
*/
#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M ) || \
((type) == DMA_TRNS_M2P) || \
((type) == DMA_TRNS_P2M) || \
((type) == DMA_TRNS_P2P))
/** @defgroup DMA_BURST_SIZE_TYPE
* @{
*/
#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1 ) || \
((type) == DMA_BURST_SIZE_4) || \
((type) == DMA_BURST_SIZE_8) || \
((type) == DMA_BURST_SIZE_16))
/** @defgroup DMA_PERIPH_REQ_TYPE
* @{
*/
#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX ) || \
((type) == DMA_REQ_UART0_TX) || \
((type) == DMA_REQ_UART1_RX) || \
((type) == DMA_REQ_UART1_TX) || \
((type) == DMA_REQ_I2C_RX ) || \
((type) == DMA_REQ_I2C_TX) || \
((type) == DMA_REQ_SPI_RX ) || \
((type) == DMA_REQ_SPI_TX) || \
((type) == DMA_REQ_GPADC0 ) || \
((type) == DMA_REQ_GPADC1) || \
((type) == DMA_REQ_NONE ))
/** @defgroup DMA_CHAN_TYPE
* @{
*/
#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0 ) || \
((type) == DMA_CH1) || \
((type) == DMA_CH2) || \
((type) == DMA_CH3) || \
((type) == DMA_CH_MAX))
/** @defgroup DMA_INT_TYPE
* @{
*/
#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED ) || \
((type) == DMA_INT_ERR) || \
((type) == DMA_INT_ALL))
/** @defgroup DMA_LLI_PP_INDEX_TYPE
* @{
*/
#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX ) || \
((type) == PONG_INDEX))
/*@} end of group DMA_Public_Constants */
/** @defgroup DMA_Public_Macros
* @{
*/
#define DMA_PINC_ENABLE 1
#define DMA_PINC_DISABLE 0
#define DMA_MINC_ENABLE 1
#define DMA_MINC_DISABLE 0
/*@} end of group DMA_Public_Macros */
/** @defgroup DMA_Public_Functions
* @{
*/
/**
* @brief DMA Functions
*/
void DMA_Enable(void);
void DMA_Disable(void);
void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg);
void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len);
void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len);
uint32_t DMA_Channel_TranferSize(uint8_t ch);
BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch);
void DMA_Channel_Enable(uint8_t ch);
void DMA_Channel_Disable(uint8_t ch);
void DMA_LLI_Init(uint8_t ch,DMA_LLI_Cfg_Type *lliCfg);
void DMA_LLI_Update(uint8_t ch, uint32_t LLI);
void DMA_IntMask(uint8_t ch,DMA_INT_Type intType, BL_Mask_Type intMask);
BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct);
DMA_LLI_Ctrl_Type * DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf);
void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList);
void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf);
void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan,DMA_INT_Type intType,intCallback_Type * cbFun);
void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf);
void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct);
void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct);
BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct,
uint16_t Ping_Transfer_len,uint16_t Pong_Transfer_len);
/*@} end of group DMA_Public_Functions */
/*@} end of group DMA */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_DMA_H__ */

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/**
******************************************************************************
* @file bl602_ef_ctrl.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_EF_CTRL_H__
#define __BL602_EF_CTRL_H__
#include "ef_ctrl_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup EF_CTRL
* @{
*/
/** @defgroup EF_CTRL_Public_Types
* @{
*/
/**
* @brief Efuse Ctrl key slot type definition
*/
typedef enum {
EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
EF_CTRL_KEY_MAX, /*!< */
}EF_Ctrl_Key_Type;
/**
* @brief Efuse Ctrl sign type definition
*/
typedef enum {
EF_CTRL_SIGN_NONE, /*!< no sign */
EF_CTRL_SIGN_RSA, /*!< use RSA to sign */
EF_CTRL_SIGN_ECC, /*!< use ECC to sign */
}EF_Ctrl_Sign_Type;
/**
* @brief Efuse Ctrl flash AES type definition
*/
typedef enum {
EF_CTRL_SF_AES_NONE, /*!< No AES */
EF_CTRL_SF_AES_128, /*!< AES 128 */
EF_CTRL_SF_AES_192, /*!< AES 192 */
EF_CTRL_SF_AES_256, /*!< AES 256 */
}EF_Ctrl_SF_AES_Type;
/**
* @brief Efuse Ctrl Dbg type definition
*/
typedef enum {
EF_CTRL_DBG_OPEN = 0, /*!< Open debug */
EF_CTRL_DBG_PASSWORD, /*!< Open debug with password */
EF_CTRL_DBG_CLOSE=4, /*!< Close debug */
}EF_Ctrl_Dbg_Mode_Type;
/**
* @brief Efuse Ctrl clock type definition
*/
typedef enum {
EF_CTRL_EF_CLK, /*!< Select efuse clock */
EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
}EF_Ctrl_CLK_Type;
/**
* @brief Efuse Ctrl clock type definition
*/
typedef enum {
EF_CTRL_PARA_DFT , /*!< Select default cyc parameter */
EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
}EF_Ctrl_CYC_PARA_Type;
/**
* @brief Efuse Ctrl clock type definition
*/
typedef enum {
EF_CTRL_OP_MODE_AUTO , /*!< Select efuse program auto mode */
EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
}EF_Ctrl_OP_MODE_Type;
/**
* @brief Efuse Ctrl secure configuration structure type definition
*/
typedef struct {
EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */
uint8_t ef_dbg_jtag_0_dis; /*!< Jtag debug disable config value */
uint8_t ef_sboot_en; /*!< Secure boot enable config value */
uint8_t ef_no_hd_boot_en; /*!< No header boot enable */
}EF_Ctrl_Sec_Param_Type;
/**
* @brief Efuse analog RC32M trim type definition
*/
typedef struct {
uint32_t trimRc32mCodeFrExt : 8; /*!< Efuse analog trim:trim_rc32m_code_fr_ext */
uint32_t trimRc32mCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */
uint32_t trimRc32mExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32m_ext_code_en */
uint32_t reserved : 22; /*!< Efuse analog trim:reserved */
}Efuse_Ana_RC32M_Trim_Type;
/**
* @brief Efuse analog RC32K trim type definition
*/
typedef struct {
uint32_t trimRc32kCodeFrExt : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */
uint32_t trimRc32kCodeFrExtParity : 1; /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */
uint32_t trimRc32kExtCodeEn : 1; /*!< Efuse analog trim:trim_rc32k_ext_code_en */
uint32_t reserved : 20; /*!< Efuse analog trim:reserved */
}Efuse_Ana_RC32K_Trim_Type;
/**
* @brief Efuse analog TSEN trim type definition
*/
typedef struct {
uint32_t tsenRefcodeCorner : 12; /*!< TSEN refcode */
uint32_t tsenRefcodeCornerParity : 1; /*!< TSEN refcode parity */
uint32_t tsenRefcodeCornerEn : 1; /*!< TSEN refcode enable */
uint32_t tsenRefcodeCornerVersion : 1; /*!< TSEN refcode version */
uint32_t reserved : 17; /*!< TSEN analog trim:reserved */
}Efuse_TSEN_Refcode_Corner_Type;
/**
* @brief Efuse analog ADC Gain trim type definition
*/
typedef struct {
uint32_t adcGainCoeff : 12; /*!< ADC gain coeff */
uint32_t adcGainCoeffParity : 1; /*!< ADC gain coeff parity */
uint32_t adcGainCoeffEn : 1; /*!< ADC gain coeff enable */
uint32_t reserved : 18; /*!< ADC gain coeff:reserved */
}Efuse_ADC_Gain_Coeff_Type;
/**
* @brief Efuse analog device info type definition
*/
typedef struct {
uint32_t rsvd : 22; /*!< Reserved */
uint32_t customerID : 2; /*!< Efuse customer ID information */
uint32_t rsvd_info : 3; /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E */
uint32_t memoryInfo : 2; /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash */
uint32_t coreInfo : 1; /*!< Efuse reserved */
uint32_t mcuInfo : 1; /*!< Efuse mcu info 0:wifi, 1:mcu */
uint32_t pinInfo : 1; /*!< Efuse pin info 0:QFN32, 1:QFN40 */
}Efuse_Device_Info_Type;
/**
* @brief Efuse Capcode type definition
*/
typedef struct {
uint32_t capCode : 6; /*!< Cap code value */
uint32_t parity : 1; /*!< Parity of capcode */
uint32_t en : 1; /*!< Enable status */
uint32_t rsvd : 24; /*!< Reserved */
}Efuse_Capcode_Info_Type;
/*@} end of group EF_CTRL_Public_Types */
/** @defgroup EF_CTRL_Public_Constants
* @{
*/
/** @defgroup EF_CTRL_KEY_TYPE
* @{
*/
#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \
((type) == EF_CTRL_KEY_SLOT1) || \
((type) == EF_CTRL_KEY_SLOT2) || \
((type) == EF_CTRL_KEY_SLOT3) || \
((type) == EF_CTRL_KEY_SLOT4) || \
((type) == EF_CTRL_KEY_SLOT5) || \
((type) == EF_CTRL_KEY_MAX))
/** @defgroup EF_CTRL_SIGN_TYPE
* @{
*/
#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \
((type) == EF_CTRL_SIGN_RSA) || \
((type) == EF_CTRL_SIGN_ECC))
/** @defgroup EF_CTRL_SF_AES_TYPE
* @{
*/
#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \
((type) == EF_CTRL_SF_AES_128) || \
((type) == EF_CTRL_SF_AES_192) || \
((type) == EF_CTRL_SF_AES_256))
/** @defgroup EF_CTRL_DBG_MODE_TYPE
* @{
*/
#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN ) || \
((type) == EF_CTRL_DBG_PASSWORD) || \
((type) == EF_CTRL_DBG_CLOSE))
/** @defgroup EF_CTRL_CLK_TYPE
* @{
*/
#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \
((type) == EF_CTRL_SAHB_CLK))
/** @defgroup EF_CTRL_CYC_PARA_TYPE
* @{
*/
#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT ) || \
((type) == EF_CTRL_PARA_MANUAL))
/** @defgroup EF_CTRL_OP_MODE_TYPE
* @{
*/
#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO ) || \
((type) == EF_CTRL_OP_MODE_MANUAL))
/*@} end of group EF_CTRL_Public_Constants */
/** @defgroup EF_CTRL_Public_Macros
* @{
*/
#define EF_CTRL_EFUSE_R0_SIZE 128
/*@} end of group EF_CTRL_Public_Macros */
/** @defgroup EF_CTRL_Public_Functions
* @{
*/
void EF_Ctrl_Load_Efuse_R0(void);
void EF_Ctrl_Program_Efuse_0(void);
BL_Sts_Type EF_Ctrl_Busy(void);
BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh,uint8_t program);
void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh);
void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg,uint8_t program);
void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1],uint8_t program);
void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]);
void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled,uint8_t *npDisabled,uint8_t *npCpuType);
uint8_t EF_Ctrl_Get_Trim_Enable(void);
uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val,uint8_t len);
void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim,uint8_t program);
void EF_Ctrl_Read_Ana_Trim( uint32_t index, uint32_t *trim);
void EF_Ctrl_Read_RC32M_Trim( Efuse_Ana_RC32M_Trim_Type *trim);
void EF_Ctrl_Read_RC32K_Trim( Efuse_Ana_RC32K_Trim_Type *trim);
void EF_Ctrl_Read_TSEN_Trim( Efuse_TSEN_Refcode_Corner_Type *trim);
void EF_Ctrl_Read_ADC_Gain_Trim( Efuse_ADC_Gain_Coeff_Type *trim);
void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage,uint8_t program);
void EF_Ctrl_Read_Sw_Usage( uint32_t index, uint32_t *usage);
void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
void EF_Ctrl_Write_MAC_Address(uint8_t mac[6],uint8_t program);
BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
void EF_Ctrl_Writelock_MAC_Address(uint8_t program);
BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo);
void EF_Ctrl_Write_AES_Key(uint8_t index,uint32_t *keyData,uint32_t len,uint8_t program);
void EF_Ctrl_Read_AES_Key(uint8_t index,uint32_t *keyData,uint32_t len);
void EF_Ctrl_Writelock_AES_Key(uint8_t index,uint8_t program);
void EF_Ctrl_Readlock_AES_Key(uint8_t index,uint8_t program);
void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len);
void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len);
void EF_Ctrl_Clear(uint32_t index, uint32_t len);
void EF_Ctrl_Crc_Enable(void);
BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
BL_Err_Type EF_Ctrl_Crc_Result(void);
void EF_Ctrl_Sw_AHB_Clk_0(void);
uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot,uint8_t reload);
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot,uint8_t mac[6],uint8_t program);
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot,uint8_t mac[6],uint8_t reload);
uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot,uint8_t reload);
BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot,uint8_t code,uint8_t program);
BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot,uint8_t *code,uint8_t reload);
uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot,uint8_t reload);
BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot,int8_t pwrOffset[3],uint8_t program);
BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot,int8_t pwrOffset[3],uint8_t reload);
void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len);
void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len);
/*@} end of group EF_CTRL_Public_Functions */
/*@} end of group EF_CTRL */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_EF_CTRL_H__ */

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drivers/bl602_driver/std_drv/inc/bl602_glb.h Normal file
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/**
******************************************************************************
* @file bl602_glb.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_GLB_H__
#define __BL602_GLB_H__
#include "glb_reg.h"
#include "pds_reg.h"
#include "bl602_gpio.h"
#include "bl602_l1c.h"
#include "bl602_hbn.h"
#include "bl602_sf_ctrl.h"
#include "bl602_sf_cfg.h"
#include "bl602_aon.h"
#include "bl602_ef_ctrl.h"
#include "bl602_pds.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup GLB
* @{
*/
/** @defgroup GLB_Public_Types
* @{
*/
/**
* @brief GLB root clock type definition
*/
typedef enum {
GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */
GLB_ROOT_CLK_XTAL, /*!< root clock select XTAL */
GLB_ROOT_CLK_PLL, /*!< root clock select PLL others */
}GLB_ROOT_CLK_Type;
/**
* @brief GLB system clock type definition
*/
typedef enum {
GLB_SYS_CLK_RC32M, /*!< use RC32M as system clock frequency */
GLB_SYS_CLK_XTAL, /*!< use XTAL as system clock */
GLB_SYS_CLK_PLL48M, /*!< use PLL output 48M as system clock */
GLB_SYS_CLK_PLL120M, /*!< use PLL output 120M as system clock */
GLB_SYS_CLK_PLL160M, /*!< use PLL output 160M as system clock */
GLB_SYS_CLK_PLL192M, /*!< use PLL output 192M as system clock */
}GLB_SYS_CLK_Type;
/**
* @brief GLB DMA clock ID type definition
*/
typedef enum {
GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */
GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */
GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */
GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */
}GLB_DMA_CLK_ID_Type;
/**
* @brief GLB clock source type definition
*/
typedef enum {
GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
}GLB_IR_CLK_SRC_Type;
/**
* @brief GLB flash clock type definition
*/
typedef enum {
GLB_SFLASH_CLK_120M, /*!< Select 120M as flash clock */
GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */
GLB_SFLASH_CLK_48M, /*!< Select 48M as flash clock */
GLB_SFLASH_CLK_80M, /*!< Select 80M as flash clock */
GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */
GLB_SFLASH_CLK_96M, /*!< Select 96M as flash clock */
}GLB_SFLASH_CLK_Type;
/**
* @brief GLB SPI pad action type definition
*/
typedef enum {
GLB_SPI_PAD_ACT_AS_SLAVE, /*!< SPI pad act as slave */
GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
}GLB_SPI_PAD_ACT_AS_Type;
/**
* @brief GLB PKA clock type definition
*/
typedef enum {
GLB_PKA_CLK_HCLK, /*!< Select HCLK as PKA clock */
GLB_PKA_CLK_PLL120M, /*!< Select PLL 120M as PKA clock */
}GLB_PKA_CLK_Type;
/**
* @brief BMX arb mode type definition
*/
typedef enum {
BMX_ARB_FIX, /*!< 0->fix */
BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
BMX_ARB_RANDOM, /*!< 3->random */
}BMX_ARB_Type;
/**
* @brief BMX configuration structure type definition
*/
typedef struct {
uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
BL_Fun_Type errEn; /*!< Bus error response enable */
BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
}BMX_Cfg_Type;
/**
* @brief BMX bus err type definition
*/
typedef enum {
BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */
}BMX_BUS_ERR_Type;
/**
* @brief BMX bus err interrupt type definition
*/
typedef enum {
BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
}BMX_ERR_INT_Type;
/**
* @brief BMX time out interrupt type definition
*/
typedef enum {
BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
BMX_TO_INT_ALL, /*!< BMX timeout interrupt max num */
}BMX_TO_INT_Type;
/**
* @brief GLB EM type definition
*/
typedef enum {
GLB_EM_0KB=0x0, /*!< 0x0 --> 0KB */
GLB_EM_8KB=0x3, /*!< 0x3 --> 8KB */
GLB_EM_16KB=0xF, /*!< 0xF --> 16KB */
}GLB_EM_Type;
/**
* @brief GLB RTC clock type definition
*/
typedef enum {
GLB_MTIMER_CLK_BCLK, /*!< BUS clock */
GLB_MTIMER_CLK_32K, /*!< 32KHz */
}GLB_MTIMER_CLK_Type;
/**
* @brief GLB ADC clock type definition
*/
typedef enum {
GLB_ADC_CLK_96M, /*!< use 96M as ADC clock */
GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */
}GLB_ADC_CLK_Type;
/**
* @brief GLB DAC clock type definition
*/
typedef enum {
GLB_DAC_CLK_32M, /*!< use 32M as DAC clock */
GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */
}GLB_DAC_CLK_Type;
/**
* @brief GLB DIG clock source select type definition
*/
typedef enum {
GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */
GLB_DIG_CLK_XCLK, /*!< select XCLK as DIG clock source */
}GLB_DIG_CLK_Type;
/**
* @brief GLB 512K clock out select type definition
*/
typedef enum {
GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */
GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */
GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */
}GLB_512K_CLK_OUT_Type;
/**
* @brief GLB BT bandwidth type definition
*/
typedef enum {
GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
}GLB_BT_BANDWIDTH_Type;
/**
* @brief GLB UART signal type definition
*/
typedef enum {
GLB_UART_SIG_0, /*!< UART signal 0 */
GLB_UART_SIG_1, /*!< UART signal 1 */
GLB_UART_SIG_2, /*!< UART signal 2 */
GLB_UART_SIG_3, /*!< UART signal 3 */
GLB_UART_SIG_4, /*!< UART signal 4 */
GLB_UART_SIG_5, /*!< UART signal 5 */
GLB_UART_SIG_6, /*!< UART signal 6 */
GLB_UART_SIG_7, /*!< UART signal 7 */
}GLB_UART_SIG_Type;
/**
* @brief GLB UART signal function type definition
*/
typedef enum {
GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
}GLB_UART_SIG_FUN_Type;
/**
* @brief GLB GPIO real mode type definition
*/
typedef enum {
GLB_GPIO_REAL_MODE_REG, /*!< GPIO real function is reg_gpio_x_func_sel */
GLB_GPIO_REAL_MODE_SDIO=0x1, /*!< GPIO real function is SDIO */
GLB_GPIO_REAL_MODE_RF=0xC, /*!< GPIO real function is RF */
GLB_GPIO_REAL_MODE_JTAG=0xE, /*!< GPIO real function is JTAG */
GLB_GPIO_REAL_MODE_CCI=0xF, /*!< GPIO real function is CCI */
}GLB_GPIO_REAL_MODE_Type;
/**
* @brief GLB GPIO interrupt trigger mode type definition
*/
typedef enum {
GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */
GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */
GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */
GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */
}GLB_GPIO_INT_TRIG_Type;
/**
* @brief GLB GPIO interrupt control mode type definition
*/
typedef enum {
GLB_GPIO_INT_CONTROL_SYNC, /*!< GPIO interrupt sync mode */
GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */
}GLB_GPIO_INT_CONTROL_Type;
/**
* @brief PLL XTAL type definition
*/
typedef enum {
GLB_PLL_XTAL_NONE, /*!< XTAL is none */
GLB_PLL_XTAL_24M, /*!< XTAL is 24M */
GLB_PLL_XTAL_32M, /*!< XTAL is 32M */
GLB_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */
GLB_PLL_XTAL_40M, /*!< XTAL is 40M */
GLB_PLL_XTAL_26M, /*!< XTAL is 26M */
GLB_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
}GLB_PLL_XTAL_Type;
/**
* @brief PLL output clock type definition
*/
typedef enum {
GLB_PLL_CLK_480M, /*!< PLL output clock:480M */
GLB_PLL_CLK_240M, /*!< PLL output clock:240M */
GLB_PLL_CLK_192M, /*!< PLL output clock:192M */
GLB_PLL_CLK_160M, /*!< PLL output clock:160M */
GLB_PLL_CLK_120M, /*!< PLL output clock:120M */
GLB_PLL_CLK_96M, /*!< PLL output clock:96M */
GLB_PLL_CLK_80M, /*!< PLL output clock:80M */
GLB_PLL_CLK_48M, /*!< PLL output clock:48M */
GLB_PLL_CLK_32M, /*!< PLL output clock:32M */
}GLB_PLL_CLK_Type;
/**
* @brief PLL configuration structure type definition
*/
typedef struct {
uint8_t clkpllIcp1u; /*!< int mode:0, frac mode:1 */
uint8_t clkpllIcp5u; /*!< int mode:2, frac mode:0 */
uint8_t clkpllIntFracSw; /*!< 0:int mode, 1:frac mode */
uint8_t clkpllC3; /*!< int:3, frac:2 */
uint8_t clkpllCz; /*!< int:1, frac:2 */
uint8_t clkpllRz; /*!< int:1, frac:5 */
uint8_t clkpllR4; /*!< int:2, frac:2 */
uint8_t clkpllR4Short; /*!< int:1, frac:0 */
uint8_t clkpllRefdivRatio; /*!< ref divider ratio */
uint8_t clkpllPostdiv; /*!< >=8 and should be even number */
uint32_t clkpllSdmin; /*!< sdmin */
uint8_t clkpllSelFbClk; /*!< 0:mod1, 1:mod2, 2:mod3 */
uint8_t clkpllSelSampleClk; /*!< 0:[16,63)mod3, 1:[32:127)mod4, 2:[64,255)mod5 */
}GLB_PLL_Cfg_Type;
/*@} end of group GLB_Public_Types */
/** @defgroup GLB_Public_Constants
* @{
*/
/** @defgroup GLB_ROOT_CLK_TYPE
* @{
*/
#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \
((type) == GLB_ROOT_CLK_XTAL) || \
((type) == GLB_ROOT_CLK_PLL))
/** @defgroup GLB_SYS_CLK_TYPE
* @{
*/
#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) || \
((type) == GLB_SYS_CLK_XTAL) || \
((type) == GLB_SYS_CLK_PLL48M) || \
((type) == GLB_SYS_CLK_PLL120M) || \
((type) == GLB_SYS_CLK_PLL160M) || \
((type) == GLB_SYS_CLK_PLL192M))
/** @defgroup GLB_DMA_CLK_ID_TYPE
* @{
*/
#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \
((type) == GLB_DMA_CLK_DMA0_CH1) || \
((type) == GLB_DMA_CLK_DMA0_CH2) || \
((type) == GLB_DMA_CLK_DMA0_CH3))
/** @defgroup GLB_IR_CLK_SRC_TYPE
* @{
*/
#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))
/** @defgroup GLB_SFLASH_CLK_TYPE
* @{
*/
#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M) || \
((type) == GLB_SFLASH_CLK_XTAL) || \
((type) == GLB_SFLASH_CLK_48M) || \
((type) == GLB_SFLASH_CLK_80M) || \
((type) == GLB_SFLASH_CLK_BCLK) || \
((type) == GLB_SFLASH_CLK_96M))
/** @defgroup GLB_SPI_PAD_ACT_AS_TYPE
* @{
*/
#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
((type) == GLB_SPI_PAD_ACT_AS_MASTER))
/** @defgroup GLB_PKA_CLK_TYPE
* @{
*/
#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \
((type) == GLB_PKA_CLK_PLL120M))
/** @defgroup BMX_ARB_TYPE
* @{
*/
#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) || \
((type) == BMX_ARB_ROUND_ROBIN) || \
((type) == BMX_ARB_RANDOM))
/** @defgroup BMX_BUS_ERR_TYPE
* @{
*/
#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
((type) == BMX_BUS_ERR_ADDR_DECODE))
/** @defgroup BMX_ERR_INT_TYPE
* @{
*/
#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
((type) == BMX_ERR_INT_ALL))
/** @defgroup BMX_TO_INT_TYPE
* @{
*/
#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
((type) == BMX_TO_INT_ALL))
/** @defgroup GLB_EM_TYPE
* @{
*/
#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \
((type) == GLB_EM_8KB) || \
((type) == GLB_EM_16KB))
/** @defgroup GLB_MTIMER_CLK_TYPE
* @{
*/
#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \
((type) == GLB_MTIMER_CLK_32K))
/** @defgroup GLB_ADC_CLK_TYPE
* @{
*/
#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_96M) || \
((type) == GLB_ADC_CLK_XCLK))
/** @defgroup GLB_DAC_CLK_TYPE
* @{
*/
#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \
((type) == GLB_DAC_CLK_XCLK))
/** @defgroup GLB_DIG_CLK_TYPE
* @{
*/
#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \
((type) == GLB_DIG_CLK_XCLK))
/** @defgroup GLB_512K_CLK_OUT_TYPE
* @{
*/
#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \
((type) == GLB_512K_CLK_OUT_256K) || \
((type) == GLB_512K_CLK_OUT_128K))
/** @defgroup GLB_BT_BANDWIDTH_TYPE
* @{
*/
#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
((type) == GLB_BT_BANDWIDTH_2M))
/** @defgroup GLB_UART_SIG_TYPE
* @{
*/
#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \
((type) == GLB_UART_SIG_1) || \
((type) == GLB_UART_SIG_2) || \
((type) == GLB_UART_SIG_3) || \
((type) == GLB_UART_SIG_4) || \
((type) == GLB_UART_SIG_5) || \
((type) == GLB_UART_SIG_6) || \
((type) == GLB_UART_SIG_7))
/** @defgroup GLB_UART_SIG_FUN_TYPE
* @{
*/
#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
((type) == GLB_UART_SIG_FUN_UART1_RXD))
/** @defgroup GLB_GPIO_REAL_MODE_TYPE
* @{
*/
#define IS_GLB_GPIO_REAL_MODE_TYPE(type) (((type) == GLB_GPIO_REAL_MODE_REG) || \
((type) == GLB_GPIO_REAL_MODE_SDIO) || \
((type) == GLB_GPIO_REAL_MODE_RF) || \
((type) == GLB_GPIO_REAL_MODE_JTAG) || \
((type) == GLB_GPIO_REAL_MODE_CCI))
/** @defgroup GLB_GPIO_INT_TRIG_TYPE
* @{
*/
#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \
((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \
((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \
((type) == GLB_GPIO_INT_TRIG_POS_LEVEL))
/** @defgroup GLB_GPIO_INT_CONTROL_TYPE
* @{
*/
#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \
((type) == GLB_GPIO_INT_CONTROL_ASYNC))
/** @defgroup GLB_PLL_XTAL_TYPE
* @{
*/
#define IS_GLB_PLL_XTAL_TYPE(type) (((type) == GLB_PLL_XTAL_NONE) || \
((type) == GLB_PLL_XTAL_24M) || \
((type) == GLB_PLL_XTAL_32M) || \
((type) == GLB_PLL_XTAL_38P4M) || \
((type) == GLB_PLL_XTAL_40M) || \
((type) == GLB_PLL_XTAL_26M) || \
((type) == GLB_PLL_XTAL_RC32M))
/** @defgroup GLB_PLL_CLK_TYPE
* @{
*/
#define IS_GLB_PLL_CLK_TYPE(type) (((type) == GLB_PLL_CLK_480M) || \
((type) == GLB_PLL_CLK_240M) || \
((type) == GLB_PLL_CLK_192M) || \
((type) == GLB_PLL_CLK_160M) || \
((type) == GLB_PLL_CLK_120M) || \
((type) == GLB_PLL_CLK_96M) || \
((type) == GLB_PLL_CLK_80M) || \
((type) == GLB_PLL_CLK_48M) || \
((type) == GLB_PLL_CLK_32M))
/*@} end of group GLB_Public_Constants */
/** @defgroup GLB_Public_Macros
* @{
*/
#define UART_SIG_SWAP_GPIO0_GPIO7 0x01 /* GPIO0-7 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
#define UART_SIG_SWAP_GPIO8_GPIO15 0x02 /* GPIO8-15 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
#define UART_SIG_SWAP_NONE 0x00 /* GPIO0-22 uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */
#define JTAG_SIG_SWAP_GPIO0_GPIO3 0x01 /* GPIO0-3 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO4_GPIO7 0x02 /* GPIO4-7 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO8_GPIO11 0x04 /* GPIO8-11 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */
/*@} end of group GLB_Public_Macros */
/** @defgroup GLB_Public_Functions
* @{
*/
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void BMX_ERR_IRQHandler(void);
void BMX_TO_IRQHandler(void);
void GPIO_INT0_IRQHandler(void);
#endif
/*----------*/
GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void);
BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv,uint8_t bclkDiv);
uint8_t GLB_Get_BCLK_Div(void);
uint8_t GLB_Get_HCLK_Div(void);
BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType);
BL_Err_Type GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq);
BL_Err_Type System_Core_Clock_Update_From_RC32M(void);
/*----------*/
BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable);
BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv);
BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv);
BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable,GLB_DMA_CLK_ID_Type clk);
BL_Err_Type GLB_Set_IR_CLK(uint8_t enable,GLB_IR_CLK_SRC_Type clkSel,uint8_t div);
BL_Err_Type GLB_Set_SF_CLK(uint8_t enable,GLB_SFLASH_CLK_Type clkSel,uint8_t div);
BL_Err_Type GLB_Set_UART_CLK(uint8_t enable,HBN_UART_CLK_Type clkSel,uint8_t div);
BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable,uint8_t div);
BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable,uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel);
BL_Err_Type GLB_SW_System_Reset(void);
BL_Err_Type GLB_SW_CPU_Reset(void);
BL_Err_Type GLB_SW_POR_Reset(void);
BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1);
BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable,BL_AHB_Slave1_Type slave1);
/*----------*/
BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg);
BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void);
BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void);
BL_Err_Type GLB_BMX_BusErrResponse_Enable(void);
BL_Err_Type GLB_BMX_BusErrResponse_Disable(void);
BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType);
uint32_t GLB_BMX_Get_Err_Addr(void);
BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType,intCallback_Type* cbFun);
BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType,intCallback_Type* cbFun);
/*----------*/
BL_Err_Type GLB_Set_OCRAM_Idle(void);
BL_Err_Type GLB_Set_SRAM_RET(uint32_t value);
uint32_t GLB_Get_SRAM_RET(void);
BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value);
uint32_t GLB_Get_SRAM_SLP(void);
BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value);
uint32_t GLB_Get_SRAM_PARM(void);
/*----------*/
BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType);
/*----------*/
BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel);
BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel);
BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
BL_Err_Type GLB_Select_Internal_Flash(void);
BL_Err_Type GLB_Select_External_Flash(void);
BL_Err_Type GLB_Deswap_Flash_Pin(void);
BL_Err_Type GLB_Swap_Flash_Pin(void);
/*----------*/
BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable,GLB_MTIMER_CLK_Type clkSel,uint32_t div);
/*----------*/
BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable,GLB_ADC_CLK_Type clkSel,uint8_t div);
BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable,GLB_DAC_CLK_Type clkSel,uint8_t div);
/*----------*/
BL_Err_Type GLB_Platform_Wakeup_Enable(void);
BL_Err_Type GLB_Platform_Wakeup_Disable(void);
/*----------*/
BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel);
BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable,uint8_t compensation,uint8_t div);
BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable,uint8_t compensation,uint8_t div);
/*----------*/
BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable,GLB_BT_BANDWIDTH_Type bandWidth,
uint8_t pti,uint8_t channel);
/*----------*/
BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig,GLB_UART_SIG_FUN_Type fun);
/*----------*/
BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio);
BL_Err_Type GLB_IR_LED_Driver_Enable(void);
BL_Err_Type GLB_IR_LED_Driver_Disable(void);
BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias);
/*----------*/
BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun,GLB_GPIO_Type *pinList,uint8_t cnt);
BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin,uint32_t val);
uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin,BL_Mask_Type intMask);
BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin,BL_Sts_Type intClear);
BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin,GLB_GPIO_INT_CONTROL_Type intCtlMod,
GLB_GPIO_INT_TRIG_Type intTrgMod);
GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin);
BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin,intCallback_Type* cbFun);
/*@} end of group GLB_Public_Functions */
/*@} end of group GLB */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_GLB_H__ */

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drivers/bl602_driver/std_drv/inc/bl602_gpio.h Normal file
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@ -0,0 +1,447 @@
/**
******************************************************************************
* @file bl602_gpio.h
* @version V1.2
* @date 2019-12-14
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_GPIO_H__
#define __BL602_GPIO_H__
typedef enum
{
GLB_GPIO_PIN_0 = 0,
GLB_GPIO_PIN_1,
GLB_GPIO_PIN_2,
GLB_GPIO_PIN_3,
GLB_GPIO_PIN_4,
GLB_GPIO_PIN_5,
GLB_GPIO_PIN_6,
GLB_GPIO_PIN_7,
GLB_GPIO_PIN_8,
GLB_GPIO_PIN_9,
GLB_GPIO_PIN_10,
GLB_GPIO_PIN_11,
GLB_GPIO_PIN_12,
GLB_GPIO_PIN_13,
GLB_GPIO_PIN_14,
GLB_GPIO_PIN_15,
GLB_GPIO_PIN_16,
GLB_GPIO_PIN_17,
GLB_GPIO_PIN_18,
GLB_GPIO_PIN_19,
GLB_GPIO_PIN_20,
GLB_GPIO_PIN_21,
GLB_GPIO_PIN_22,
GLB_GPIO_PIN_MAX,
}GLB_GPIO_Type;
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_AF ((uint32_t)0x00000002U) /*!< Alternate function */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function */
#define GPIO_PULL_UP ((uint32_t)0x00000000U) /*!< GPIO pull up */
#define GPIO_PULL_DOWN ((uint32_t)0x00000001U) /*!< GPIO pull down */
#define GPIO_PULL_NONE ((uint32_t)0x00000002U) /*!< GPIO no pull up or down */
typedef enum
{
GPIO_FUN_SDIO = 1,
GPIO_FUN_FLASH = 2,
GPIO_FUN_SPI = 4,
GPIO_FUN_I2C = 6,
GPIO_FUN_UART = 7,
GPIO_FUN_PWM = 8,
GPIO_FUN_EXT_PA = 9,
GPIO_FUN_ANALOG = 10,
GPIO_FUN_SWGPIO = 11,
GPIO_FUN_GPIO = 11,
GPIO_FUN_JTAG = 14,
GPIO_FUN_UART0_RTS = 0x70 ,
GPIO_FUN_UART0_CTS = 0x71 ,
GPIO_FUN_UART0_TX = 0x72 ,
GPIO_FUN_UART0_RX = 0x73 ,
GPIO_FUN_UART1_RTS = 0x74 ,
GPIO_FUN_UART1_CTS = 0x75 ,
GPIO_FUN_UART1_TX = 0x76 ,
GPIO_FUN_UART1_RX = 0x77 ,
GPIO_FUN_GPIO_OUTPUT = 0x80,
GPIO_FUN_GPIO_INPUT = 0x81,
GPIO_FUN_UNUSED = 255,
}GLB_GPIO_FUNC_Type;
typedef struct
{
uint8_t gpioPin;
uint8_t gpioFun;
uint8_t gpioMode;
uint8_t pullType;
uint8_t drive;
uint8_t smtCtrl;
}GLB_GPIO_Cfg_Type;
/* GPIO0 function definition */
#define GPIO0_FUN_SDIO_CLK 1
#define GPIO0_FUN_SF_D1 2
#define GPIO0_FUN_UNUSED3 3
#define GPIO0_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO0_FUN_UNUSED5 5
#define GPIO0_FUN_I2C_SCL 6
#define GPIO0_FUN_UART_SIG0 7
#define GPIO0_FUN_PWM_CH0 8
#define GPIO0_FUN_FEM_GPIO_0 9
#define GPIO0_FUN_ATEST_IN 10
#define GPIO0_FUN_SWGPIO_0 11
#define GPIO0_FUN_E21_TMS 14
/* GPIO1 function definition */
#define GPIO1_FUN_SDIO_CMD 1
#define GPIO1_FUN_SF_D2 2
#define GPIO1_FUN_UNUSED3 3
#define GPIO1_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO1_FUN_UNUSED5 5
#define GPIO1_FUN_I2C_SDA 6
#define GPIO1_FUN_UART_SIG1 7
#define GPIO1_FUN_PWM_CH1 8
#define GPIO1_FUN_FEM_GPIO_1 9
#define GPIO1_FUN_ATEST_IP 10
#define GPIO1_FUN_SWGPIO_1 11
#define GPIO1_FUN_E21_TDI 14
/* GPIO2 function definition */
#define GPIO2_FUN_SDIO_DAT0 1
#define GPIO2_FUN_SF_D3 2
#define GPIO2_FUN_UNUSED3 3
#define GPIO2_FUN_SPI_SS 4
#define GPIO2_FUN_UNUSED5 5
#define GPIO2_FUN_I2C_SCL 6
#define GPIO2_FUN_UART_SIG2 7
#define GPIO2_FUN_PWM_CH2 8
#define GPIO2_FUN_FEM_GPIO_2 9
#define GPIO2_FUN_ATEST_QN 10
#define GPIO2_FUN_SWGPIO_2 11
#define GPIO2_FUN_E21_TCK 14
/* GPIO3 function definition */
#define GPIO3_FUN_SDIO_DAT1 1
#define GPIO3_FUN_UNUSED2 2
#define GPIO3_FUN_UNUSED3 3
#define GPIO3_FUN_SPI_SCLK 4
#define GPIO3_FUN_UNUSED5 5
#define GPIO3_FUN_I2C_SDA 6
#define GPIO3_FUN_UART_SIG3 7
#define GPIO3_FUN_PWM_CH3 8
#define GPIO3_FUN_FEM_GPIO_3 9
#define GPIO3_FUN_ATEST_QP 10
#define GPIO3_FUN_SWGPIO_3 11
#define GPIO3_FUN_E21_TDO 14
/* GPIO4 function definition */
#define GPIO4_FUN_SDIO_DAT2 1
#define GPIO4_FUN_UNUSED2 2
#define GPIO4_FUN_UNUSED3 3
#define GPIO4_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO4_FUN_UNUSED5 5
#define GPIO4_FUN_I2C_SCL 6
#define GPIO4_FUN_UART_SIG4 7
#define GPIO4_FUN_PWM_CH4 8
#define GPIO4_FUN_FEM_GPIO_0 9
#define GPIO4_FUN_GPIP_CH1 10
#define GPIO4_FUN_SWGPIO_4 11
#define GPIO4_FUN_E21_TMS 14
/* GPIO5 function definition */
#define GPIO5_FUN_SDIO_DAT3 1
#define GPIO5_FUN_UNUSED2 2
#define GPIO5_FUN_UNUSED3 3
#define GPIO5_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO5_FUN_UNUSED5 5
#define GPIO5_FUN_I2C_SDA 6
#define GPIO5_FUN_UART_SIG5 7
#define GPIO5_FUN_PWM_CH0 8
#define GPIO5_FUN_FEM_GPIO_1 9
#define GPIO5_FUN_GPIP_CH4 10
#define GPIO5_FUN_SWGPIO_5 11
#define GPIO5_FUN_E21_TDI 14
/* GPIO6 function definition */
#define GPIO6_FUN_UNUSED1 1
#define GPIO6_FUN_UNUSED2 2
#define GPIO6_FUN_UNUSED3 3
#define GPIO6_FUN_SPI_SS 4
#define GPIO6_FUN_UNUSED5 5
#define GPIO6_FUN_I2C_SCL 6
#define GPIO6_FUN_UART_SIG6 7
#define GPIO6_FUN_PWM_CH1 8
#define GPIO6_FUN_FEM_GPIO_2 9
#define GPIO6_FUN_GPIP_CH5 10
#define GPIO6_FUN_SWGPIO_6 11
#define GPIO6_FUN_E21_TCK 14
/* GPIO7 function definition */
#define GPIO7_FUN_UNUSED1 1
#define GPIO7_FUN_UNUSED2 2
#define GPIO7_FUN_UNUSED3 3
#define GPIO7_FUN_SPI_SCLK 4
#define GPIO7_FUN_UNUSED5 5
#define GPIO7_FUN_I2C_SDA 6
#define GPIO7_FUN_UART_SIG7 7
#define GPIO7_FUN_PWM_CH2 8
#define GPIO7_FUN_FEM_GPIO_3 9
#define GPIO7_FUN_UNUSED10 10
#define GPIO7_FUN_SWGPIO_7 11
#define GPIO7_FUN_E21_TDO 14
/* GPIO8 function definition */
#define GPIO8_FUN_UNUSED1 1
#define GPIO8_FUN_UNUSED2 2
#define GPIO8_FUN_UNUSED3 3
#define GPIO8_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO8_FUN_UNUSED5 5
#define GPIO8_FUN_I2C_SCL 6
#define GPIO8_FUN_UART_SIG0 7
#define GPIO8_FUN_PWM_CH3 8
#define GPIO8_FUN_FEM_GPIO_0 9
#define GPIO8_FUN_UNUSED10 10
#define GPIO8_FUN_SWGPIO_8 11
#define GPIO8_FUN_E21_TMS 14
/* GPIO9 function definition */
#define GPIO9_FUN_UNUSED1 1
#define GPIO9_FUN_UNUSED2 2
#define GPIO9_FUN_UNUSED3 3
#define GPIO9_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO9_FUN_UNUSED5 5
#define GPIO9_FUN_I2C_SDA 6
#define GPIO9_FUN_UART_SIG1 7
#define GPIO9_FUN_PWM_CH4 8
#define GPIO9_FUN_FEM_GPIO_1 9
#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10
#define GPIO9_FUN_SWGPIO_9 11
#define GPIO9_FUN_E21_TDI 14
/* GPIO10 function definition */
#define GPIO10_FUN_UNUSED1 1
#define GPIO10_FUN_UNUSED2 2
#define GPIO10_FUN_UNUSED3 3
#define GPIO10_FUN_SPI_SS 4
#define GPIO10_FUN_UNUSED5 5
#define GPIO10_FUN_I2C_SCL 6
#define GPIO10_FUN_UART_SIG2 7
#define GPIO10_FUN_PWM_CH0 8
#define GPIO10_FUN_FEM_GPIO_2 9
#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10
#define GPIO10_FUN_SWGPIO_10 11
#define GPIO10_FUN_E21_TCK 14
/* GPIO11 function definition */
#define GPIO11_FUN_UNUSED1 1
#define GPIO11_FUN_UNUSED2 2
#define GPIO11_FUN_UNUSED3 3
#define GPIO11_FUN_SPI_SCLK 4
#define GPIO11_FUN_UNUSED5 5
#define GPIO11_FUN_I2C_SDA 6
#define GPIO11_FUN_UART_SIG3 7
#define GPIO11_FUN_PWM_CH1 8
#define GPIO11_FUN_FEM_GPIO_3 9
#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10
#define GPIO11_FUN_SWGPIO_11 11
#define GPIO11_FUN_E21_TDO 14
/* GPIO12 function definition */
#define GPIO12_FUN_UNUSED1 1
#define GPIO12_FUN_UNUSED2 2
#define GPIO12_FUN_UNUSED3 3
#define GPIO12_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO12_FUN_UNUSED5 5
#define GPIO12_FUN_I2C_SCL 6
#define GPIO12_FUN_UART_SIG4 7
#define GPIO12_FUN_PWM_CH2 8
#define GPIO12_FUN_FEM_GPIO_0 9
#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10
#define GPIO12_FUN_SWGPIO_12 11
#define GPIO12_FUN_E21_TMS 14
/* GPIO13 function definition */
#define GPIO13_FUN_UNUSED1 1
#define GPIO13_FUN_UNUSED2 2
#define GPIO13_FUN_UNUSED3 3
#define GPIO13_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO13_FUN_UNUSED5 5
#define GPIO13_FUN_I2C_SDA 6
#define GPIO13_FUN_UART_SIG5 7
#define GPIO13_FUN_PWM_CH3 8
#define GPIO13_FUN_FEM_GPIO_1 9
#define GPIO13_FUN_GPIP_CH3 10
#define GPIO13_FUN_SWGPIO_13 11
#define GPIO13_FUN_E21_TDI 14
/* GPIO14 function definition */
#define GPIO14_FUN_UNUSED1 1
#define GPIO14_FUN_UNUSED2 2
#define GPIO14_FUN_UNUSED3 3
#define GPIO14_FUN_SPI_SS 4
#define GPIO14_FUN_UNUSED5 5
#define GPIO14_FUN_I2C_SCL 6
#define GPIO14_FUN_UART_SIG6 7
#define GPIO14_FUN_PWM_CH4 8
#define GPIO14_FUN_FEM_GPIO_2 9
#define GPIO14_FUN_GPIP_CH2 10
#define GPIO14_FUN_SWGPIO_14 11
#define GPIO14_FUN_E21_TCK 14
/* GPIO15 function definition */
#define GPIO15_FUN_UNUSED1 1
#define GPIO15_FUN_UNUSED2 2
#define GPIO15_FUN_UNUSED3 3
#define GPIO15_FUN_SPI_SCLK 4
#define GPIO15_FUN_UNUSED5 5
#define GPIO15_FUN_I2C_SDA 6
#define GPIO15_FUN_UART_SIG7 7
#define GPIO15_FUN_PWM_CH0 8
#define GPIO15_FUN_FEM_GPIO_3 9
#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10
#define GPIO15_FUN_SWGPIO_15 11
#define GPIO15_FUN_E21_TDO 14
/* GPIO16 function definition */
#define GPIO16_FUN_UNUSED1 1
#define GPIO16_FUN_UNUSED2 2
#define GPIO16_FUN_UNUSED3 3
#define GPIO16_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO16_FUN_UNUSED5 5
#define GPIO16_FUN_I2C_SCL 6
#define GPIO16_FUN_UART_SIG0 7
#define GPIO16_FUN_PWM_CH1 8
#define GPIO16_FUN_FEM_GPIO_0 9
#define GPIO16_FUN_UNUSED10 10
#define GPIO16_FUN_SWGPIO_16 11
#define GPIO16_FUN_E21_TMS 14
/* GPIO17 function definition */
#define GPIO17_FUN_UNUSED1 1
#define GPIO17_FUN_SF_D3 2
#define GPIO17_FUN_UNUSED3 3
#define GPIO17_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO17_FUN_UNUSED5 5
#define GPIO17_FUN_I2C_SDA 6
#define GPIO17_FUN_UART_SIG1 7
#define GPIO17_FUN_PWM_CH2 8
#define GPIO17_FUN_FEM_GPIO_1 9
#define GPIO17_FUN_PMIP_DC_TP_OUT 10
#define GPIO17_FUN_SWGPIO_17 11
#define GPIO17_FUN_E21_TDI 14
/* GPIO18 function definition */
#define GPIO18_FUN_UNUSED1 1
#define GPIO18_FUN_SF_D2 2
#define GPIO18_FUN_UNUSED3 3
#define GPIO18_FUN_SPI_SS 4
#define GPIO18_FUN_UNUSED5 5
#define GPIO18_FUN_I2C_SCL 6
#define GPIO18_FUN_UART_SIG2 7
#define GPIO18_FUN_PWM_CH3 8
#define GPIO18_FUN_FEM_GPIO_2 9
#define GPIO18_FUN_UNUSED10 10
#define GPIO18_FUN_SWGPIO_18 11
#define GPIO18_FUN_E21_TCK 14
/* GPIO19 function definition */
#define GPIO19_FUN_UNUSED1 1
#define GPIO19_FUN_SF_D1 2
#define GPIO19_FUN_UNUSED3 3
#define GPIO19_FUN_SPI_SCLK 4
#define GPIO19_FUN_UNUSED5 5
#define GPIO19_FUN_I2C_SDA 6
#define GPIO19_FUN_UART_SIG3 7
#define GPIO19_FUN_PWM_CH4 8
#define GPIO19_FUN_FEM_GPIO_3 9
#define GPIO19_FUN_UNUSED10 10
#define GPIO19_FUN_SWGPIO_19 11
#define GPIO19_FUN_E21_TDO 14
/* GPIO20 function definition */
#define GPIO20_FUN_UNUSED1 1
#define GPIO20_FUN_SF_D0 2
#define GPIO20_FUN_UNUSED3 3
#define GPIO20_FUN_SPI_MISO_SPI_MOSI 4
#define GPIO20_FUN_UNUSED5 5
#define GPIO20_FUN_I2C_SCL 6
#define GPIO20_FUN_UART_SIG4 7
#define GPIO20_FUN_PWM_CH0 8
#define GPIO20_FUN_FEM_GPIO_0 9
#define GPIO20_FUN_UNUSED10 10
#define GPIO20_FUN_SWGPIO_20 11
#define GPIO20_FUN_E21_TMS 14
/* GPIO21 function definition */
#define GPIO21_FUN_UNUSED1 1
#define GPIO21_FUN_SF_CS 2
#define GPIO21_FUN_UNUSED3 3
#define GPIO21_FUN_SPI_MOSI_SPI_MISO 4
#define GPIO21_FUN_UNUSED5 5
#define GPIO21_FUN_I2C_SDA 6
#define GPIO21_FUN_UART_SIG5 7
#define GPIO21_FUN_PWM_CH1 8
#define GPIO21_FUN_FEM_GPIO_1 9
#define GPIO21_FUN_UNUSED10 10
#define GPIO21_FUN_SWGPIO_21 11
#define GPIO21_FUN_E21_TDI 14
/* GPIO22 function definition */
#define GPIO22_FUN_UNUSED1 1
#define GPIO22_FUN_SF_CLK_OUT 2
#define GPIO22_FUN_UNUSED3 3
#define GPIO22_FUN_SPI_SS 4
#define GPIO22_FUN_UNUSED5 5
#define GPIO22_FUN_I2C_SCL 6
#define GPIO22_FUN_UART_SIG6 7
#define GPIO22_FUN_PWM_CH2 8
#define GPIO22_FUN_FEM_GPIO_2 9
#define GPIO22_FUN_UNUSED10 10
#define GPIO22_FUN_SWGPIO_22 11
#define GPIO22_FUN_E21_TCK 14
#endif /*__BL602_GPIO_H__ */

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drivers/bl602_driver/std_drv/inc/bl602_hbn.h Normal file
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/**
******************************************************************************
* @file bl602_hbn.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_HBN_H__
#define __BL602_HBN_H__
#include "hbn_reg.h"
#include "bl602_aon.h"
#include "bl602_sflash.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup HBN
* @{
*/
/** @defgroup HBN_Public_Types
* @{
*/
/**
* @brief HBN PIR interrupt configuration type definition
*/
typedef struct {
BL_Fun_Type lowIntEn; /*!< Low will trigger interrupt */
BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
}HBN_PIR_INT_CFG_Type;
/**
* @brief HBN PIR low pass filter type definition
*/
typedef enum {
HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
}HBN_PIR_LPF_Type;
/**
* @brief HBN PIR high pass filter type definition
*/
typedef enum {
HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
}HBN_PIR_HPF_Type;
/**
* @brief HBN BOR threshold type definition
*/
typedef enum {
HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */
HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */
}HBN_BOR_THRES_Type;
/**
* @brief HBN BOR mode type definition
*/
typedef enum {
HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */
HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */
}HBN_BOR_MODE_Type;
/**
* @brief HBN 32K clock type definition
*/
typedef enum {
HBN_32K_RC=0, /*!< HBN use rc 32k */
HBN_32K_XTAL, /*!< HBN use xtal 32k */
HBN_32K_DIG=3, /*!< HBN use dig 32k */
}HBN_32K_CLK_Type;
/**
* @brief HBN xclk clock type definition
*/
typedef enum {
HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */
HBN_XCLK_CLK_XTAL, /*!< use XTAL as xclk clock */
}HBN_XCLK_CLK_Type;
/**
* @brief HBN root clock type definition
*/
typedef enum {
HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */
HBN_ROOT_CLK_XTAL, /*!< use XTAL as root clock */
HBN_ROOT_CLK_PLL, /*!< use PLL as root clock */
}HBN_ROOT_CLK_Type;
/**
* @brief HBN UART clock type definition
*/
typedef enum {
HBN_UART_CLK_FCLK=0, /*!< Select FCLK as UART clock */
HBN_UART_CLK_160M, /*!< Select 160M as UART clock */
}HBN_UART_CLK_Type;
/**
* @brief HBN RTC interrupt delay type definition
*/
typedef enum {
HBN_RTC_INT_DELAY_32T=0, /*!< HBN RTC interrupt delay 32T */
HBN_RTC_INT_DELAY_0T=1, /*!< HBN RTC interrupt delay 0T */
}HBN_RTC_INT_Delay_Type;
/**
* @brief HBN interrupt type definition
*/
typedef enum {
HBN_INT_GPIO7=0, /*!< HBN interrupt type: GPIO7 */
HBN_INT_GPIO8=1, /*!< HBN interrupt type: GPIO8 */
HBN_INT_RTC=16, /*!< HBN interrupt type: RTC */
HBN_INT_PIR=17, /*!< HBN interrupt type: PIR */
HBN_INT_BOR=18, /*!< HBN interrupt type: BOR */
HBN_INT_ACOMP0=20, /*!< HBN interrupt type: ACOMP0 */
HBN_INT_ACOMP1=22, /*!< HBN interrupt type: ACOMP1 */
}HBN_INT_Type;
/**
* @brief HBN acomp interrupt type definition
*/
typedef enum {
HBN_ACOMP_INT_EDGE_POSEDGE=0, /*!< HBN acomp interrupt edge posedge */
HBN_ACOMP_INT_EDGE_NEGEDGE=1, /*!< HBN acomp interrupt edge negedge */
}HBN_ACOMP_INT_EDGE_Type;
/**
* @brief HBN GPIO interrupt trigger type definition
*/
typedef enum {
HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: sync falling edge trigger */
HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: sync rising edge trigger */
HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: sync low level trigger */
HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: sync high level trigger */
HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */
HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< HBN GPIO INT trigger type: async rising edge trigger */
HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< HBN GPIO INT trigger type: async low level trigger */
HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< HBN GPIO INT trigger type: async high level trigger */
}HBN_GPIO_INT_Trigger_Type;
/**
* @brief HBN OUT0 interrupt type definition
*/
typedef enum {
HBN_OUT0_INT_GPIO7=0, /*!< HBN out 0 interrupt type: GPIO7 */
HBN_OUT0_INT_GPIO8, /*!< HBN out 0 interrupt type: GPIO8 */
HBN_OUT0_INT_RTC, /*!< HBN out 0 interrupt type: RTC */
}HBN_OUT0_INT_Type;
/**
* @brief HBN OUT0 interrupt type definition
*/
typedef enum {
HBN_OUT1_INT_PIR, /*!< HBN out 1 interrupt type: PIR */
HBN_OUT1_INT_BOR, /*!< HBN out 1 interrupt type: BOR */
HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
}HBN_OUT1_INT_Type;
/**
* @brief HBN LDO level type definition
*/
typedef enum {
HBN_LDO_LEVEL_0P60V=0, /*!< HBN LDO voltage 0.60V */
HBN_LDO_LEVEL_0P65V=1, /*!< HBN LDO voltage 0.65V */
HBN_LDO_LEVEL_0P70V=2, /*!< HBN LDO voltage 0.70V */
HBN_LDO_LEVEL_0P75V=3, /*!< HBN LDO voltage 0.75V */
HBN_LDO_LEVEL_0P80V=4, /*!< HBN LDO voltage 0.80V */
HBN_LDO_LEVEL_0P85V=5, /*!< HBN LDO voltage 0.85V */
HBN_LDO_LEVEL_0P90V=6, /*!< HBN LDO voltage 0.90V */
HBN_LDO_LEVEL_0P95V=7, /*!< HBN LDO voltage 0.95V */
HBN_LDO_LEVEL_1P00V=8, /*!< HBN LDO voltage 1.00V */
HBN_LDO_LEVEL_1P05V=9, /*!< HBN LDO voltage 1.05V */
HBN_LDO_LEVEL_1P10V=10, /*!< HBN LDO voltage 1.10V */
HBN_LDO_LEVEL_1P15V=11, /*!< HBN LDO voltage 1.15V */
HBN_LDO_LEVEL_1P20V=12, /*!< HBN LDO voltage 1.20V */
HBN_LDO_LEVEL_1P25V=13, /*!< HBN LDO voltage 1.25V */
HBN_LDO_LEVEL_1P30V=14, /*!< HBN LDO voltage 1.30V */
HBN_LDO_LEVEL_1P35V=15, /*!< HBN LDO voltage 1.35V */
}HBN_LDO_LEVEL_Type;
/**
* @brief HBN level type definition
*/
typedef enum {
HBN_LEVEL_0, /*!< HBN pd_core */
HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
}HBN_LEVEL_Type;
/**
* @brief HBN BOR configuration type definition
*/
typedef struct {
uint8_t enableBor; /*!< Enable BOR or not */
uint8_t enableBorInt; /*!< Enable BOR interrupt or not */
uint8_t borThreshold; /*!< BOR threshold */
uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */
}HBN_BOR_CFG_Type;
/**
* @brief HBN APP configuration type definition
*/
typedef struct {
uint8_t useXtal32k; /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
uint32_t sleepTime; /*!< HBN sleep time */
uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */
HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */
HBN_LEVEL_Type hbnLevel; /*!< HBN level */
HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
}HBN_APP_CFG_Type;
/*@} end of group HBN_Public_Types */
/** @defgroup HBN_Public_Constants
* @{
*/
/** @defgroup HBN_PIR_LPF_TYPE
* @{
*/
#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
((type) == HBN_PIR_LPF_DIV2))
/** @defgroup HBN_PIR_HPF_TYPE
* @{
*/
#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
((type) == HBN_PIR_HPF_METHOD1) || \
((type) == HBN_PIR_HPF_METHOD2))
/** @defgroup HBN_BOR_THRES_TYPE
* @{
*/
#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \
((type) == HBN_BOR_THRES_2P4V))
/** @defgroup HBN_BOR_MODE_TYPE
* @{
*/
#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \
((type) == HBN_BOR_MODE_POR_RELEVANT))
/** @defgroup HBN_32K_CLK_TYPE
* @{
*/
#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) || \
((type) == HBN_32K_XTAL) || \
((type) == HBN_32K_DIG))
/** @defgroup HBN_XCLK_CLK_TYPE
* @{
*/
#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \
((type) == HBN_XCLK_CLK_XTAL))
/** @defgroup HBN_ROOT_CLK_TYPE
* @{
*/
#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \
((type) == HBN_ROOT_CLK_XTAL) || \
((type) == HBN_ROOT_CLK_PLL))
/** @defgroup HBN_UART_CLK_TYPE
* @{
*/
#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \
((type) == HBN_UART_CLK_160M))
/** @defgroup HBN_RTC_INT_DELAY_TYPE
* @{
*/
#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
((type) == HBN_RTC_INT_DELAY_0T))
/** @defgroup HBN_INT_TYPE
* @{
*/
#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO7) || \
((type) == HBN_INT_GPIO8) || \
((type) == HBN_INT_RTC) || \
((type) == HBN_INT_PIR) || \
((type) == HBN_INT_BOR) || \
((type) == HBN_INT_ACOMP0) || \
((type) == HBN_INT_ACOMP1))
/** @defgroup HBN_ACOMP_INT_EDGE_TYPE
* @{
*/
#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
((type) == HBN_ACOMP_INT_EDGE_NEGEDGE))
/** @defgroup HBN_GPIO_INT_TRIGGER_TYPE
* @{
*/
#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \
((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \
((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \
((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \
((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \
((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \
((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
/** @defgroup HBN_OUT0_INT_TYPE
* @{
*/
#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO7) || \
((type) == HBN_OUT0_INT_GPIO8) || \
((type) == HBN_OUT0_INT_RTC))
/** @defgroup HBN_OUT1_INT_TYPE
* @{
*/
#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) || \
((type) == HBN_OUT1_INT_BOR) || \
((type) == HBN_OUT1_INT_ACOMP0) || \
((type) == HBN_OUT1_INT_ACOMP1))
/** @defgroup HBN_LDO_LEVEL_TYPE
* @{
*/
#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \
((type) == HBN_LDO_LEVEL_0P65V) || \
((type) == HBN_LDO_LEVEL_0P70V) || \
((type) == HBN_LDO_LEVEL_0P75V) || \
((type) == HBN_LDO_LEVEL_0P80V) || \
((type) == HBN_LDO_LEVEL_0P85V) || \
((type) == HBN_LDO_LEVEL_0P90V) || \
((type) == HBN_LDO_LEVEL_0P95V) || \
((type) == HBN_LDO_LEVEL_1P00V) || \
((type) == HBN_LDO_LEVEL_1P05V) || \
((type) == HBN_LDO_LEVEL_1P10V) || \
((type) == HBN_LDO_LEVEL_1P15V) || \
((type) == HBN_LDO_LEVEL_1P20V) || \
((type) == HBN_LDO_LEVEL_1P25V) || \
((type) == HBN_LDO_LEVEL_1P30V) || \
((type) == HBN_LDO_LEVEL_1P35V))
/** @defgroup HBN_LEVEL_TYPE
* @{
*/
#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
((type) == HBN_LEVEL_1) || \
((type) == HBN_LEVEL_2) || \
((type) == HBN_LEVEL_3))
/*@} end of group HBN_Public_Constants */
/** @defgroup HBN_Public_Macros
* @{
*/
#define HBN_RAM_SIZE (4*1024)
#define HBN_RTC_COMP_BIT0_39 0x01
#define HBN_RTC_COMP_BIT0_23 0x02
#define HBN_RTC_COMP_BIT13_39 0x04
#define HBN_STATUS_ENTER_FLAG 0x4e424845
#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
#define HBN_WAKEUP_GPIO_NONE 0x00
#define HBN_WAKEUP_GPIO_7 0x01
#define HBN_WAKEUP_GPIO_8 0x02
#define HBN_WAKEUP_GPIO_ALL 0x03
/*@} end of group HBN_Public_Macros */
/** @defgroup HBN_Public_Functions
* @{
*/
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void HBN_OUT0_IRQHandler(void);
void HBN_OUT1_IRQHandler(void);
#endif
/*----------*/
void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg);
void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg);
void HBN_Enable(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel);
void HBN_Enable_Ext(uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel);
BL_Err_Type HBN_Reset(void);
BL_Err_Type HBN_App_Reset(uint8_t npXtalType,uint8_t bclkDiv,uint8_t apXtalType,uint8_t fclkDiv);
BL_Err_Type HBN_Disable(void);
/*----------*/
BL_Err_Type HBN_PIR_Enable(void);
BL_Err_Type HBN_PIR_Disable(void);
BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type* pirIntCfg);
BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
uint16_t HBN_Get_PIR_Threshold(void);
BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
uint16_t HBN_Get_PIR_Interval(void);
/*----------*/
BL_Sts_Type HBN_Get_BOR_OUT_State(void);
BL_Err_Type HBN_Set_BOR_Config(uint8_t enable,HBN_BOR_THRES_Type threshold,HBN_BOR_MODE_Type mode);
/*----------*/
BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
/*----------*/
BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk);
BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk);
/*----------*/
BL_Err_Type HBN_Set_HRAM_slp(void);
BL_Err_Type HBN_Set_HRAM_Ret(void);
/*----------*/
uint32_t HBN_Get_Status_Flag(void);
BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
uint32_t HBN_Get_Wakeup_Addr(void);
BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
/*----------*/
BL_Err_Type HBN_Clear_RTC_Counter(void);
BL_Err_Type HBN_Enable_RTC_Counter(void);
BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay,uint32_t compValLow,uint32_t compValHigh,uint8_t compMode);
BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow,uint32_t *valHigh);
BL_Err_Type HBN_Clear_RTC_IRQ(void);
/*----------*/
BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
BL_Err_Type HBN_GPIO_INT_Disable(void);
BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
uint8_t HBN_Get_Pin_Wakeup_Mode(void);
BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg);
BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
/*----------*/
BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
/*----------*/
BL_Err_Type HBN_Enable_BOR_IRQ(void);
BL_Err_Type HBN_Disable_BOR_IRQ(void);
/*----------*/
BL_Err_Type HBN_Out0_IRQHandler_Install(void);
BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType,intCallback_Type* cbFun);
BL_Err_Type HBN_Out1_IRQHandler_Install(void);
BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType,intCallback_Type* cbFun);
/*----------*/
BL_Err_Type HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn,BL_Fun_Type iesmtEn,
BL_Fun_Type dlyEn,uint8_t dlySec);
/*----------*/
BL_Err_Type HBN_Power_On_Xtal_32K(void);
BL_Err_Type HBN_Power_Off_Xtal_32K(void);
BL_Err_Type HBN_Power_On_RC32K(void);
BL_Err_Type HBN_Power_Off_RC32K(void);
BL_Err_Type HBN_Trim_RC32K(void);
BL_Err_Type HBN_Set_Embedded_Flash_Pullup(uint8_t enable);
BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg);
/*@} end of group HBN_Public_Functions */
/*@} end of group HBN */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_HBN_H__ */

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/**
******************************************************************************
* @file bl602_i2c.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_I2C_H__
#define __BL602_I2C_H__
#include "i2c_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Public_Types
* @{
*/
/**
* @brief I2C No. type definition
*/
typedef enum {
I2C0_ID = 0, /*!< I2C0 define */
I2C_ID_MAX, /*!< I2C max define */
}I2C_ID_Type;
/**
* @brief I2C read/write type definition
*/
typedef enum {
I2C_WRITE = 0, /*!< I2C write direction */
I2C_READ, /*!< I2C read direction */
}I2C_Direction_Type;
/**
* @brief I2C interrupt type definition
*/
typedef enum {
I2C_TRANS_END_INT, /*!< I2C transfer end interrupt */
I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */
I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */
I2C_NACK_RECV_INT, /*!< I2C nack received interrupt */
I2C_ARB_LOST_INT, /*!< I2C arbitration lost interrupt */
I2C_FIFO_ERR_INT, /*!< I2C TX/RX FIFO error interrupt */
I2C_INT_ALL, /*!< I2C interrupt all type */
}I2C_INT_Type;
/**
* @brief I2S start condition phase structure type definition
*/
typedef struct {
uint8_t len0; /*!< Length of START condition phase 0 */
uint8_t len1; /*!< Length of START condition phase 1 */
uint8_t len2; /*!< Length of START condition phase 2 */
uint8_t len3; /*!< Length of START condition phase 3 */
}I2C_Start_Condition_Phase_Type;
/**
* @brief I2S stop condition phase structure type definition
*/
typedef struct {
uint8_t len0; /*!< Length of STOP condition phase 0 */
uint8_t len1; /*!< Length of STOP condition phase 1 */
uint8_t len2; /*!< Length of STOP condition phase 2 */
uint8_t len3; /*!< Length of STOP condition phase 3 */
}I2C_Stop_Condition_Phase_Type;
/**
* @brief I2S data phase structure type definition
*/
typedef struct {
uint8_t len0; /*!< Length of DATA phase 0 */
uint8_t len1; /*!< Length of DATA phase 1 */
uint8_t len2; /*!< Length of DATA phase 2 */
uint8_t len3; /*!< Length of DATA phase 3 */
}I2C_Data_Phase_Type;
/**
* @brief I2S transfer structure type definition
*/
typedef struct {
uint8_t slaveAddr; /*!< I2C slave address */
BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */
uint8_t subAddrSize; /*!< Specifies the size of I2C sub address section */
uint32_t subAddr; /*!< I2C sub address */
uint16_t dataSize; /*!< Specifies the size of I2C data section */
uint8_t* data; /*!< Specifies the pointer of I2C R/W data */
}I2C_Transfer_Cfg;
/*@} end of group I2C_Public_Types */
/** @defgroup I2C_Public_Constants
* @{
*/
/** @defgroup I2C_ID_TYPE
* @{
*/
#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID ) || \
((type) == I2C_ID_MAX))
/** @defgroup I2C_DIRECTION_TYPE
* @{
*/
#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE ) || \
((type) == I2C_READ))
/** @defgroup I2C_INT_TYPE
* @{
*/
#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) || \
((type) == I2C_TX_FIFO_READY_INT) || \
((type) == I2C_RX_FIFO_READY_INT) || \
((type) == I2C_NACK_RECV_INT) || \
((type) == I2C_ARB_LOST_INT) || \
((type) == I2C_FIFO_ERR_INT) || \
((type) == I2C_INT_ALL))
/*@} end of group I2C_Public_Constants */
/** @defgroup I2C_Public_Macros
* @{
*/
/*@} end of group I2C_Public_Macros */
/** @defgroup I2C_Public_Functions
* @{
*/
/**
* @brief I2C Functions
*/
#ifndef BFLB_USE_HAL_DRIVER
void I2C_IRQHandler(void);
void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type* cbFun);
#endif
void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data);
uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo);
void I2C_Enable(I2C_ID_Type i2cNo);
void I2C_Disable(I2C_ID_Type i2cNo);
BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo);
void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase);
void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk);
void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable);
void I2C_Init(I2C_ID_Type i2cNo,I2C_Direction_Type direct,I2C_Transfer_Cfg *cfg);
BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo);
BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg);
BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg);
void I2C_IntMask(I2C_ID_Type i2cNo,I2C_INT_Type intType, BL_Mask_Type intMask);
/*@} end of group I2C_Public_Functions */
/*@} end of group I2C */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_I2C_H__ */

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/**
******************************************************************************
* @file bl602_ir.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_IR_H__
#define __BL602_IR_H__
#include "ir_reg.h"
#include "bl602_common.h"
#include "bl602_hbn.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup IR
* @{
*/
/** @defgroup IR_Public_Types
* @{
*/
/**
* @brief IR direction type definition
*/
typedef enum {
IR_TX, /*!< IR TX direction */
IR_RX, /*!< IR RX direction */
IR_TXRX, /*!< IR TX and RX direction */
}IR_Direction_Type;
/**
* @brief IR word type definition
*/
typedef enum {
IR_WORD_0, /*!< IR data word 0 */
IR_WORD_1, /*!< IR data word 1 */
}IR_Word_Type;
/**
* @brief IR RX mode type definition
*/
typedef enum {
IR_RX_NEC, /*!< IR RX NEC mode */
IR_RX_RC5, /*!< IR RX RC5 mode */
IR_RX_SWM, /*!< IR RX software pulse-width detection mode */
}IR_RxMode_Type;
/**
* @brief IR interrupt type definition
*/
typedef enum {
IR_INT_TX, /*!< IR TX transfer end interrupt */
IR_INT_RX, /*!< IR RX transfer end interrupt */
IR_INT_ALL, /*!< IR all interrupt */
}IR_INT_Type;
/**
* @brief IR fifo underflow or overflow type definition
*/
typedef enum {
IR_RX_FIFO_UNDERFLOW, /*!< Underflow flag of rx fifo */
IR_RX_FIFO_OVERFLOW, /*!< Overflow flag of rx fifo */
}IR_FifoStatus_Type;
/**
* @brief IR TX configuration structure type definition
*/
typedef struct {
uint8_t dataBits; /*!< Bit count of data phase */
BL_Fun_Type tailPulseInverse; /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */
BL_Fun_Type tailPulse; /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */
BL_Fun_Type headPulseInverse; /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */
BL_Fun_Type headPulse; /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */
BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */
BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */
BL_Fun_Type dataPulse; /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */
BL_Fun_Type outputModulation; /*!< Enable or disable signal of output modulation */
BL_Fun_Type outputInverse; /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */
}IR_TxCfg_Type;
/**
* @brief IR TX pulse width configuration structure type definition
*/
typedef struct {
uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */
uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */
uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */
uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */
uint8_t headPulseWidth_1; /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */
uint8_t headPulseWidth_0; /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */
uint8_t tailPulseWidth_1; /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */
uint8_t tailPulseWidth_0; /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */
uint8_t moduWidth_1; /*!< Modulation phase 1 width */
uint8_t moduWidth_0; /*!< Modulation phase 0 width */
uint16_t pulseWidthUnit; /*!< Pulse width unit */
}IR_TxPulseWidthCfg_Type;
/**
* @brief IR TX software mode pulse width(multiples of pulse width unit) configuration structure type definition
*/
typedef struct {
uint32_t swmData0; /*!< SWM pulse width data 0~7,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData1; /*!< SWM pulse width data 8~15,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData2; /*!< SWM pulse width data 16~23,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData3; /*!< SWM pulse width data 24~31,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData4; /*!< SWM pulse width data 32~39,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData5; /*!< SWM pulse width data 40~47,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData6; /*!< SWM pulse width data 48~55,multiples of pulse width unit,each pulse is represented by 4-bit */
uint32_t swmData7; /*!< SWM pulse width data 56~63,multiples of pulse width unit,each pulse is represented by 4-bit */
}IR_TxSWMPulseWidthCfg_Type;
/**
* @brief IR RX configuration structure type definition
*/
typedef struct {
IR_RxMode_Type rxMode; /*!< Set ir rx mode */
BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */
uint16_t endThreshold; /*!< Pulse width threshold to trigger end condition */
uint16_t dataThreshold; /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */
BL_Fun_Type rxDeglitch; /*!< Enable or disable signal of rx input de-glitch function */
uint8_t DeglitchCnt; /*!< De-glitch function cycle count */
}IR_RxCfg_Type;
/*@} end of group IR_Public_Types */
/** @defgroup IR_Public_Constants
* @{
*/
/** @defgroup IR_DIRECTION_TYPE
* @{
*/
#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \
((type) == IR_RX) || \
((type) == IR_TXRX))
/** @defgroup IR_WORD_TYPE
* @{
*/
#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \
((type) == IR_WORD_1))
/** @defgroup IR_RXMODE_TYPE
* @{
*/
#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \
((type) == IR_RX_RC5) || \
((type) == IR_RX_SWM))
/** @defgroup IR_INT_TYPE
* @{
*/
#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX) || \
((type) == IR_INT_RX) || \
((type) == IR_INT_ALL))
/** @defgroup IR_FIFOSTATUS_TYPE
* @{
*/
#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_RX_FIFO_UNDERFLOW) || \
((type) == IR_RX_FIFO_OVERFLOW))
/*@} end of group IR_Public_Constants */
/** @defgroup IR_Public_Macros
* @{
*/
#define IR_RX_FIFO_SIZE 64
/*@} end of group IR_Public_Macros */
/** @defgroup IR_Public_Functions
* @{
*/
/**
* @brief IR Functions
*/
#ifndef BFLB_USE_HAL_DRIVER
void IRRX_IRQHandler(void);
void IRTX_IRQHandler(void);
#endif
BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg);
BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg);
BL_Err_Type IR_TxSWMPulseWidthConfig(IR_TxSWMPulseWidthCfg_Type *irTxSWMPulseWidthCfg);
BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg);
BL_Err_Type IR_DeInit(void);
BL_Err_Type IR_Enable(IR_Direction_Type direct);
BL_Err_Type IR_Disable(IR_Direction_Type direct);
BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM);
BL_Err_Type IR_RxFIFOClear(void);
BL_Err_Type IR_SendData(IR_Word_Type irWord,uint32_t data);
BL_Err_Type IR_SWMSendData(uint16_t *data,uint8_t length);
BL_Err_Type IR_SendCommand(uint32_t word1,uint32_t word0);
BL_Err_Type IR_SWMSendCommand(uint16_t *data,uint8_t length);
BL_Err_Type IR_SendNEC(uint8_t address,uint8_t command);
BL_Err_Type IR_IntMask(IR_INT_Type intType,BL_Mask_Type intMask);
BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType);
BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType,intCallback_Type *cbFun);
BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType);
BL_Sts_Type IR_GetRxFIFOStatus(IR_FifoStatus_Type fifoSts);
uint32_t IR_ReceiveData(IR_Word_Type irWord);
uint8_t IR_SWMReceiveData(uint16_t *data,uint8_t length);
BL_Err_Type IR_ReceiveNEC(uint8_t *address,uint8_t *command);
uint8_t IR_GetRxDataBitCount(void);
uint8_t IR_GetRxFIFOCount(void);
IR_RxMode_Type IR_LearnToInit(uint32_t *data,uint8_t *length);
BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode,uint32_t *data,uint8_t length);
uint8_t IR_LearnToReceive(IR_RxMode_Type mode,uint32_t *data);
BL_Sts_Type IR_LEDInit(HBN_XCLK_CLK_Type clk,uint8_t div,uint8_t unit,uint8_t code0H,uint8_t code0L,uint8_t code1H,
uint8_t code1L);
BL_Sts_Type IR_LEDSend(uint32_t data);
/*@} end of group IR_Public_Functions */
/*@} end of group IR */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_IR_H__ */

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#ifndef __BL602_IT_H__
#define __BL602_IT_H__
#include "bl602.h"
#include "bl_common.h"
/** @addtogroup BL606_Peripheral_Driver
* @{
*/
/** @addtogroup COMMON
* @{
*/
/** @defgroup COMMON_Public_Types
* @{
*/
/*@} end of group COMMON_Public_Types */
/** @defgroup COMMON_Public_Constants
* @{
*/
/** @defgroup DRIVER_INT_PERIPH
* @{
*/
#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
/*@} end of group DRIVER_INT_PERIPH */
/** @defgroup DRIVER_INT_MASK
* @{
*/
#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
/*@} end of group COMMON_Public_Constants */
/*@} end of group DRIVER_Public_Macro */
/** @defgroup DRIVER_Public_FunctionDeclaration
* @brief DRIVER functions declaration
* @{
*/
void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun);
/*@} end of group DRIVER_COMMON */
#endif /* __BL602_COMMON_H__ */

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/**
******************************************************************************
* @file bl602_l1c.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_L1C_H__
#define __BL602_L1C_H__
#include "l1c_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup L1C
* @{
*/
/** @defgroup L1C_Public_Types
* @{
*/
/**
* @brief L1C configuration structure type definition
*/
typedef struct {
BL_Fun_Type wrapDis; /*!< wrap disable */
BL_Fun_Type bypassEn; /*!< bypass cache enable */
uint8_t wayDis; /*!< Disable part of cache ways & used as ITCM */
BL_Fun_Type cntEn; /*!< l1c count enable */
}L1C_CACHE_Cfg_Type;
/**
* @brief L1C BMX arb mode type definition
*/
typedef enum {
L1C_BMX_ARB_FIX, /*!< 0->fix */
L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
L1C_BMX_ARB_RANDOM, /*!< 3->random */
}L1C_BMX_ARB_Type;
/**
* @brief L1C BMX configuration structure type definition
*/
typedef struct {
uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
BL_Fun_Type errEn; /*!< Bus error response enable */
L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
}L1C_BMX_Cfg_Type;
/**
* @brief L1C BMX bus err type definition
*/
typedef enum {
L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
L1C_BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */
}L1C_BMX_BUS_ERR_Type;
/**
* @brief L1C BMX bus err interrupt type definition
*/
typedef enum {
L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */
L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */
}L1C_BMX_ERR_INT_Type;
/**
* @brief L1C BMX time out interrupt type definition
*/
typedef enum {
L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */
L1C_BMX_TO_INT_ALL, /*!< L1C_BMX timeout interrupt max num */
}L1C_BMX_TO_INT_Type;
/*@} end of group L1C_Public_Types */
/** @defgroup L1C_Public_Constants
* @{
*/
/** @defgroup L1C_BMX_ARB_TYPE
* @{
*/
#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) || \
((type) == L1C_BMX_ARB_ROUND_ROBIN) || \
((type) == L1C_BMX_ARB_RANDOM))
/** @defgroup L1C_BMX_BUS_ERR_TYPE
* @{
*/
#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \
((type) == L1C_BMX_BUS_ERR_ADDR_DECODE))
/** @defgroup L1C_BMX_ERR_INT_TYPE
* @{
*/
#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \
((type) == L1C_BMX_ERR_INT_ALL))
/** @defgroup L1C_BMX_TO_INT_TYPE
* @{
*/
#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \
((type) == L1C_BMX_TO_INT_ALL))
/*@} end of group L1C_Public_Constants */
/** @defgroup L1C_Public_Macros
* @{
*/
#if 1
/*NP config address */
#define L1C_CONF_REG_NP (L1C_BASE+0x00)
#define L1C_HIT_CNT_LSB_REG_NP (L1C_BASE+0x04)
#define L1C_HIT_CNT_MSB_REG_NP (L1C_BASE+0x08)
#define L1C_MISS_CNT_REG_NP (L1C_BASE+0x0C)
/* Get miss and hit count */
#define L1C_Get_Miss_Cnt_NP() BL602_REG_RD(L1C_MISS_CNT_REG_NP)
#define L1C_Get_Hit_Cnt_LSB_NP() BL602_REG_RD(L1C_HIT_CNT_LSB_REG_NP)
#define L1C_Get_Hit_Cnt_MSB_NP() BL602_REG_RD(L1C_HIT_CNT_MSB_REG_NP)
#endif
/*@} end of group L1C_Public_Macros */
/** @defgroup L1C_Public_Functions
* @{
*/
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void L1C_BMX_ERR_IRQHandler(void);
void L1C_BMX_TO_IRQHandler(void);
#endif
/*----------*/
BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap);
BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal);
BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable);
/*----------*/
BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg);
BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void);
BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void);
BL_Err_Type L1C_BMX_BusErrResponse_Enable(void);
BL_Err_Type L1C_BMX_BusErrResponse_Disable(void);
BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType);
uint32_t L1C_BMX_Get_Err_Addr(void);
BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType,intCallback_Type* cbFun);
BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,
intCallback_Type* cbFun);
/*----------*/;
/*@} end of group L1C_Public_Functions */
/*@} end of group L1C */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_L1C_H__ */

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#ifndef __BL602_MFG_EFUSE_H__
#define __BL602_MFG_EFUSE_H__
#include "stdint.h"
uint8_t mfg_efuse_get_rf_cal_slots(void);
void mfg_efuse_set_rf_cal_slots(uint8_t slots);
uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload);
int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode,uint8_t program);
void mfg_efuse_write_xtal_capcode(void);
int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode,uint8_t reload);
uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload);
int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program);
void mfg_efuse_write_poweroffset(void);
int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14],uint8_t reload);
uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload);
int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program);
void mfg_efuse_write_macaddr(void);
int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload);
int8_t mfg_efuse_read(uint32_t addr,uint32_t *data,uint32_t countInword,uint8_t reload);
int8_t mfg_efuse_program(void);
int8_t mfg_efuse_write_pre(uint32_t addr,uint32_t *data,uint32_t countInword);
#endif/*__MFG_GPIO_API_H__*/

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/**
******************************************************************************
* @file bl602_pds.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_PDS_H__
#define __BL602_PDS_H__
#include "pds_reg.h"
#include "bl602_ef_ctrl.h"
#include "bl602_aon.h"
#include "bl602_hbn.h"
#include "bl602_sflash.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup PDS
* @{
*/
/** @defgroup PDS_Public_Types
* @{
*/
/**
* @brief PDS LDO level type definition
*/
typedef enum {
PDS_LDO_LEVEL_0P60V=0, /*!< PDS LDO voltage 0.60V */
PDS_LDO_LEVEL_0P65V=1, /*!< PDS LDO voltage 0.65V */
PDS_LDO_LEVEL_0P70V=2, /*!< PDS LDO voltage 0.70V */
PDS_LDO_LEVEL_0P75V=3, /*!< PDS LDO voltage 0.75V */
PDS_LDO_LEVEL_0P80V=4, /*!< PDS LDO voltage 0.80V */
PDS_LDO_LEVEL_0P85V=5, /*!< PDS LDO voltage 0.85V */
PDS_LDO_LEVEL_0P90V=6, /*!< PDS LDO voltage 0.90V */
PDS_LDO_LEVEL_0P95V=7, /*!< PDS LDO voltage 0.95V */
PDS_LDO_LEVEL_1P00V=8, /*!< PDS LDO voltage 1.00V */
PDS_LDO_LEVEL_1P05V=9, /*!< PDS LDO voltage 1.05V */
PDS_LDO_LEVEL_1P10V=10, /*!< PDS LDO voltage 1.10V */
PDS_LDO_LEVEL_1P15V=11, /*!< PDS LDO voltage 1.15V */
PDS_LDO_LEVEL_1P20V=12, /*!< PDS LDO voltage 1.20V */
PDS_LDO_LEVEL_1P25V=13, /*!< PDS LDO voltage 1.25V */
PDS_LDO_LEVEL_1P30V=14, /*!< PDS LDO voltage 1.30V */
PDS_LDO_LEVEL_1P35V=15, /*!< PDS LDO voltage 1.35V */
}PDS_LDO_LEVEL_Type;
/**
* @brief PDS configuration type definition
*/
typedef struct {
uint32_t pdsStart : 1; /*!< [0]PDS Start */
uint32_t sleepForever : 1; /*!< [1]PDS sleep forever */
uint32_t xtalForceOff : 1; /*!< [2]Power off xtal force */
uint32_t saveWiFiState : 1; /*!< [3]Save WIFI State Before Enter PDS */
uint32_t dcdc18Off : 1; /*!< [4]power down dcdc18 during PDS */
uint32_t bgSysOff : 1; /*!< [5]power down bg_sys during PDS */
uint32_t rsv6_7 : 2; /*!< [7:6]reserve */
uint32_t clkOff : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
uint32_t memStby : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
uint32_t rsv10 : 1; /*!< [10]reserve */
uint32_t isolation : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
uint32_t waitXtalRdy : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
uint32_t pdsPwrOff : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
uint32_t xtalOff : 1; /*!< [14]xtal power down during PDS */
uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */
uint32_t pdsRstSocEn : 1; /*!< [16]pds_rst controlled by PDS */
uint32_t pdsRC32mOn : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
uint32_t pdsLdoVselEn : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
uint32_t rsv19_20 : 2; /*!< [20:19]reserve */
uint32_t wfiMask : 1; /*!< [21]pds start condition mask np_wfi */
uint32_t ldo11Off : 1; /*!< [22]power down ldo11 during PDS */
uint32_t rsv23 : 1; /*!< [23]reserve */
uint32_t pdsLdoVol : 4; /*!< [27:24]LDO voltage value in PDS mode */
uint32_t pdsCtlRfSel : 2; /*!< [29:28]select the way RF controlled by PDS */
uint32_t pdsCtlPllSel : 2; /*!< [31:30]select the way PLL controlled by PDS */
}PDS_CTL_Type;
/**
* @brief PDS force configuration type definition
*/
typedef struct {
uint32_t cpuPwrOff : 1; /*!< [0] */
uint32_t cpuRst : 1; /*!< [1] */
uint32_t cpuMemStby : 1; /*!< [2] */
uint32_t cpuGateClk : 1; /*!< [3] */
uint32_t rsv4_11 : 8; /*!< [11:4]reserve */
uint32_t WbPwrOff : 1; /*!< [12] */
uint32_t WbRst : 1; /*!< [13] */
uint32_t WbMemStby : 1; /*!< [14] */
uint32_t WbGateClk : 1; /*!< [15] */
uint32_t rsv16_23 : 8; /*!< [23:16]reserve */
uint32_t MiscPwrOff : 1; /*!< [24] */
uint32_t MiscRst : 1; /*!< [25] */
uint32_t MiscMemStby : 1; /*!< [26] */
uint32_t MiscGateClk : 1; /*!< [27] */
uint32_t rsv28_31 : 4; /*!< [31:28]reserve */
}PDS_CTL4_Type;
/**
* @brief PDS interrupt type definition
*/
typedef enum {
PDS_INT_WAKEUP=0, /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
PDS_INT_HBN_GPIO_IRRX_BLE_WIFI=1, /*!< PDS in interrupt source HBN_Wakeup_Source/All_GPIO_Wakeup/IRRX/BLE_Wakeup_Eveent/WIFI_Wakeup_Event */
PDS_INT_RF_DONE=2, /*!< PDS RF done interrupt */
PDS_INT_PLL_DONE=3, /*!< PDS PLL done interrupt */
PDS_INT_MAX=4, /*!< PDS int max number */
}PDS_INT_Type;
/**
* @brief PDS force configuration type definition
*/
typedef struct {
uint32_t forceCpuPwrOff : 1; /*!< [0]manual force NP power off */
uint32_t rsv1 : 1; /*!< [1]reserve */
uint32_t forceWbPwrOff : 1; /*!< [2]manual force WB power off */
uint32_t rsv3 : 1; /*!< [3]reserve */
uint32_t forceCpuIsoPwrOff : 1; /*!< [4]manual force NP isolation */
uint32_t rsv5 : 1; /*!< [5]reserve */
uint32_t forceWbIsoPwrOff : 1; /*!< [6]manual force WB isolation */
uint32_t rsv7 : 1; /*!< [7]reserve */
uint32_t forceCpuPdsRst : 1; /*!< [8]manual force NP pds reset */
uint32_t rsv9 : 1; /*!< [9]reserve */
uint32_t forceWbPdsRst : 1; /*!< [10]manual force WB pds reset */
uint32_t rsv11 : 1; /*!< [11]reserve */
uint32_t forceCpuMemStby : 1; /*!< [12]manual force NP memory sleep */
uint32_t rsv13 : 1; /*!< [13]reserve */
uint32_t forceWbMemStby : 1; /*!< [14]manual force WB memory sleep */
uint32_t rsv15 : 1; /*!< [15]reserve */
uint32_t forceCpuGateClk : 1; /*!< [16]manual force NP clock gated */
uint32_t rsv17 : 1; /*!< [17]reserve */
uint32_t forceWbGateClk : 1; /*!< [18]manual force WB clock gated */
uint32_t rsv19_31 : 12; /*!< [31:19]reserve */
}PDS_CTL2_Type;
/**
* @brief PDS force configuration type definition
*/
typedef struct {
uint32_t rsv0 : 1; /*!< [0]reserve */
uint32_t forceMiscPwrOff : 1; /*!< [1]manual force MISC pwr_off */
uint32_t rsv2_3 : 2; /*!< [3:2]reserve */
uint32_t forceMiscIsoEn : 1; /*!< [4]manual force MISC iso_en */
uint32_t rsv5_6 : 2; /*!< [6:5]reserve */
uint32_t forceMiscPdsRst : 1; /*!< [7]manual force MISC pds_rst */
uint32_t rsv8_9 : 2; /*!< [9:8]reserve */
uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */
uint32_t rsv11_12 : 2; /*!< [12:11]reserve */
uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */
uint32_t rsv14_23 : 10; /*!< [23:14]reserve */
uint32_t CpuIsoEn : 1; /*!< [24]make NP isolated at PDS Sleep state */
uint32_t rsv25_26 : 2; /*!< [26:25]reserve */
uint32_t WbIsoEn : 1; /*!< [27]make WB isolated at PDS Sleep state */
uint32_t rsv28_29 : 2; /*!< [29:28]reserve */
uint32_t MiscIsoEn : 1; /*!< [30]make misc isolated at PDS Sleep state */
uint32_t rsv31 : 1; /*!< [31]reserve */
}PDS_CTL3_Type;
/**
* @brief PDS default level configuration type definition
*/
typedef struct {
PDS_CTL_Type pdsCtl; /*!< PDS_CTL configuration */
PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
}PDS_DEFAULT_LV_CFG_Type;
/**
* @brief PDS PLL status type definition
*/
typedef enum {
PDS_PLL_STS_OFF=0, /*!< 2'b00 */
PDS_PLL_STS_SFREG=1, /*!< 2'b01 */
PDS_PLL_STS_PU=2, /*!< 2'b10 */
PDS_PLL_STS_RDY=3, /*!< 2'b11 */
}PDS_PLL_STS_Type;
/**
* @brief PDS RF status type definition
*/
typedef enum {
PDS_RF_STS_OFF=0, /*!< 4'b0000 */
PDS_RF_STS_PU_MBG=1, /*!< 4'b0001 */
PDS_RF_STS_PU_LDO15RF=3, /*!< 4'b0011 */
PDS_RF_STS_PU_SFREG=7, /*!< 4'b0111 */
PDS_RF_STS_WB_EN_AON=15, /*!< 4'b1111 */
}PDS_RF_STS_Type;
/**
* @brief PDS status type definition
*/
typedef enum {
PDS_STS_IDLE=0, /*!< 4'b0000 */
PDS_STS_ECG=8, /*!< 4'b1000 */
PDS_STS_ERST=12, /*!< 4'b1100 */
PDS_STS_EISO=15, /*!< 4'b1111 */
PDS_STS_POFF=7, /*!< 4'b0111 */
PDS_STS_PRE_BGON=3, /*!< 4'b0011 */
PDS_STS_PRE_BGON1=1, /*!< 4'b0001 */
PDS_STS_BGON=5, /*!< 4'b0101 */
PDS_STS_CLK_SW_32M=4, /*!< 4'b0100 */
PDS_STS_PON_DCDC=6, /*!< 4'b0110 */
PDS_STS_PON_LDO11_MISC=14, /*!< 4'b1110 */
PDS_STS_PON=10, /*!< 4'b1010 */
PDS_STS_DISO=2, /*!< 4'b0010 */
PDS_STS_DCG=13, /*!< 4'b1101 */
PDS_STS_DRST=11, /*!< 4'b1011 */
PDS_STS_WAIT_EFUSE=9, /*!< 4'b1001 */
}PDS_STS_Type;
/**
* @brief PDS RAM configuration type definition
*/
typedef struct {
uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET : 1; /*!< [0] 0~16KB cpu_ram RET */
uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET : 1; /*!< [1] 16~32KB cpu_ram RET */
uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET : 1; /*!< [2] 32~48KB cpu_ram RET */
uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET : 1; /*!< [3] 48~64KB cpu_ram RET */
uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP : 1; /*!< [4] 0~16KB cpu_ram SLP */
uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP : 1; /*!< [5] 16~32KB cpu_ram SLP */
uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP : 1; /*!< [6] 32~48KB cpu_ram SLP */
uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP : 1; /*!< [7] 48~64KB cpu_ram SLP */
uint32_t PDS_RAM_CFG_RSV : 24; /*!< [31:8]reserve */
}PDS_RAM_CFG_Type;
/**
* @brief PLL XTAL type definition
*/
typedef enum {
PDS_PLL_XTAL_NONE, /*!< XTAL is none */
PDS_PLL_XTAL_24M, /*!< XTAL is 24M */
PDS_PLL_XTAL_32M, /*!< XTAL is 32M */
PDS_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */
PDS_PLL_XTAL_40M, /*!< XTAL is 40M */
PDS_PLL_XTAL_26M, /*!< XTAL is 26M */
PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
}PDS_PLL_XTAL_Type;
/**
* @brief PLL output clock type definition
*/
typedef enum {
PDS_PLL_CLK_480M, /*!< PLL output clock:480M */
PDS_PLL_CLK_240M, /*!< PLL output clock:240M */
PDS_PLL_CLK_192M, /*!< PLL output clock:192M */
PDS_PLL_CLK_160M, /*!< PLL output clock:160M */
PDS_PLL_CLK_120M, /*!< PLL output clock:120M */
PDS_PLL_CLK_96M, /*!< PLL output clock:96M */
PDS_PLL_CLK_80M, /*!< PLL output clock:80M */
PDS_PLL_CLK_48M, /*!< PLL output clock:48M */
PDS_PLL_CLK_32M, /*!< PLL output clock:32M */
}PDS_PLL_CLK_Type;
/**
* @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition
*/
typedef enum {
PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */
PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */
PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */
PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */
PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */
PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */
PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */
PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */
}PDS_AON_GPIO_INT_Trigger_Type;
/**
* @brief PDS APP configuration type definition
*/
typedef struct {
uint8_t pdsLevel; /*!< PDS level */
uint8_t turnOffRF; /*!< Wheather turn off RF */
uint8_t useXtal32k; /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
uint8_t pdsAonGpioWakeupSrc; /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */
PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */
uint8_t powerDownFlash; /*!< Whether power down flash */
uint8_t turnOffFlashPad; /*!< Whether turn off embedded flash pad */
uint8_t ocramRetetion; /*!< Whether OCRAM Retention */
uint8_t turnoffPLL; /*!< Whether trun off PLL */
uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
uint8_t flashContRead; /*!< Whether enable flash continue read */
uint32_t sleepTime; /*!< PDS sleep time */
SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */
PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
void (*preCbFun)(void); /*!< Pre callback function */
void (*postCbFun)(void); /*!< Post callback function */
}PDS_APP_CFG_Type;
/*@} end of group PDS_Public_Types */
/** @defgroup PDS_Public_Constants
* @{
*/
/** @defgroup PDS_LDO_LEVEL_TYPE
* @{
*/
#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \
((type) == PDS_LDO_LEVEL_0P65V) || \
((type) == PDS_LDO_LEVEL_0P70V) || \
((type) == PDS_LDO_LEVEL_0P75V) || \
((type) == PDS_LDO_LEVEL_0P80V) || \
((type) == PDS_LDO_LEVEL_0P85V) || \
((type) == PDS_LDO_LEVEL_0P90V) || \
((type) == PDS_LDO_LEVEL_0P95V) || \
((type) == PDS_LDO_LEVEL_1P00V) || \
((type) == PDS_LDO_LEVEL_1P05V) || \
((type) == PDS_LDO_LEVEL_1P10V) || \
((type) == PDS_LDO_LEVEL_1P15V) || \
((type) == PDS_LDO_LEVEL_1P20V) || \
((type) == PDS_LDO_LEVEL_1P25V) || \
((type) == PDS_LDO_LEVEL_1P30V) || \
((type) == PDS_LDO_LEVEL_1P35V))
/** @defgroup PDS_INT_TYPE
* @{
*/
#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) || \
((type) == PDS_INT_HBN_GPIO_IRRX_BLE_WIFI) || \
((type) == PDS_INT_RF_DONE) || \
((type) == PDS_INT_PLL_DONE) || \
((type) == PDS_INT_MAX))
/** @defgroup PDS_PLL_STS_TYPE
* @{
*/
#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) || \
((type) == PDS_PLL_STS_SFREG) || \
((type) == PDS_PLL_STS_PU) || \
((type) == PDS_PLL_STS_RDY))
/** @defgroup PDS_RF_STS_TYPE
* @{
*/
#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) || \
((type) == PDS_RF_STS_PU_MBG) || \
((type) == PDS_RF_STS_PU_LDO15RF) || \
((type) == PDS_RF_STS_PU_SFREG) || \
((type) == PDS_RF_STS_WB_EN_AON))
/** @defgroup PDS_STS_TYPE
* @{
*/
#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) || \
((type) == PDS_STS_ECG) || \
((type) == PDS_STS_ERST) || \
((type) == PDS_STS_EISO) || \
((type) == PDS_STS_POFF) || \
((type) == PDS_STS_PRE_BGON) || \
((type) == PDS_STS_PRE_BGON1) || \
((type) == PDS_STS_BGON) || \
((type) == PDS_STS_CLK_SW_32M) || \
((type) == PDS_STS_PON_DCDC) || \
((type) == PDS_STS_PON_LDO11_MISC) || \
((type) == PDS_STS_PON) || \
((type) == PDS_STS_DISO) || \
((type) == PDS_STS_DCG) || \
((type) == PDS_STS_DRST) || \
((type) == PDS_STS_WAIT_EFUSE))
/** @defgroup PDS_PLL_XTAL_TYPE
* @{
*/
#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \
((type) == PDS_PLL_XTAL_24M) || \
((type) == PDS_PLL_XTAL_32M) || \
((type) == PDS_PLL_XTAL_38P4M) || \
((type) == PDS_PLL_XTAL_40M) || \
((type) == PDS_PLL_XTAL_26M) || \
((type) == PDS_PLL_XTAL_RC32M))
/** @defgroup PDS_PLL_CLK_TYPE
* @{
*/
#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \
((type) == PDS_PLL_CLK_240M) || \
((type) == PDS_PLL_CLK_192M) || \
((type) == PDS_PLL_CLK_160M) || \
((type) == PDS_PLL_CLK_120M) || \
((type) == PDS_PLL_CLK_96M) || \
((type) == PDS_PLL_CLK_80M) || \
((type) == PDS_PLL_CLK_48M) || \
((type) == PDS_PLL_CLK_32M))
/** @defgroup PDS_AON_GPIO_INT_TRIGGER_TYPE
* @{
*/
#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) || \
((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
/*@} end of group PDS_Public_Constants */
/** @defgroup PDS_Public_Macros
* @{
*/
#define PDS_LDO_MIN_PU_CNT (25) /* LDO need 25 cycles to power up */
#define PDS_WARMUP_LATENCY_CNT (38) /* LDO hw warmup compensation latency cycles */
#define PDS_FORCE_PWR_OFF_OFFSET (0)
#define PDS_FORCE_ISO_EN_OFFSET (4)
#define PDS_FORCE_PDS_RST_OFFSET (8)
#define PDS_FORCE_MEM_STBY_OFFSET (12)
#define PDS_FORCE_GATE_CLK_OFFSET (16)
#define PDS_INT_MASK_BIT_OFFSET (8)
#define PDS_AON_WAKEUP_GPIO_NONE (0x00)
#define PDS_AON_WAKEUP_GPIO_7 (0x01)
#define PDS_AON_WAKEUP_GPIO_8 (0x02)
#define PDS_AON_WAKEUP_GPIO_ALL (0x03)
/*@} end of group PDS_Public_Macros */
/** @defgroup PDS_Public_Functions
* @{
*/
/*----------*/
#ifndef BFLB_USE_HAL_DRIVER
void PDS_WAKEUP_IRQHandler(void);
#endif
/*----------*/
BL_Err_Type PDS_Reset(void);
BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt);
BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2,PDS_CTL3_Type *cfg3);
BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg);
/*----------*/
BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,
PDS_RAM_CFG_Type *ramCfg,uint32_t pdsSleepCnt);
/*----------*/
BL_Err_Type PDS_IntMask(PDS_INT_Type intType,BL_Mask_Type intMask);
BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
BL_Err_Type PDS_IntClear(void);
PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void);
PDS_RF_STS_Type PDS_Get_PdsRfStstus(void);
PDS_STS_Type PDS_Get_PdsStstus(void);
BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void);
BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType,intCallback_Type* cbFun);
/*----------*/
BL_Err_Type PDS_Trim_RC32M(void);
BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void);
BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void);
BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType);
BL_Err_Type PDS_Fix_Xtal_Settig(void);
BL_Err_Type PDS_Enable_PLL_All_Clks(void);
BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
BL_Err_Type PDS_Disable_PLL_All_Clks(void);
BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
BL_Err_Type PDS_Power_Off_PLL(void);
/*----------*/;
/*@} end of group PDS_Public_Functions */
/*@} end of group PDS */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_PDS_H__ */

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drivers/bl602_driver/std_drv/inc/bl602_pwm.h Normal file
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/**
******************************************************************************
* @file bl602_pwm.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_PWM_H__
#define __BL602_PWM_H__
#include "pwm_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup PWM
* @{
*/
/** @defgroup PWM_Public_Types
* @{
*/
/**
* @brief PWM No. type definition
*/
typedef enum {
PWM_CH0 = 0, /*!< PWM Channel 0 define */
PWM_CH1, /*!< PWM Channel 1 define */
PWM_CH2, /*!< PWM Channel 2 define */
PWM_CH3, /*!< PWM Channel 3 define */
PWM_CH4, /*!< PWM Channel 4 define */
PWM_CH_MAX, /*!< */
}PWM_CH_ID_Type;
/**
* @brief PWM Clock definition
*/
typedef enum {
PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */
PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */
PWM_CLK_32K, /*!< PWM Clock source :32K CLK */
}PWM_Clk_Type;
/**
* @brief PWM Stop Mode definition
*/
typedef enum {
PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */
PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */
}PWM_Stop_Mode_Type;
/**
* @brief PWM mode type def
*/
typedef enum {
PWM_POL_NORMAL = 0, /*!< PWM normal polarity mode define */
PWM_POL_INVERT, /*!< PWM invert polarity mode define */
}PWM_Polarity_Type;
/**
* @brief PWM interrupt type def
*/
typedef enum {
PWM_INT_PULSE_CNT = 0, /*!< PWM Pulse count interrupt define */
PWM_INT_ALL, /*!< */
}PWM_INT_Type;
/**
* @brief PWM configuration structure type definition
*/
typedef struct {
PWM_CH_ID_Type ch; /*!< PWM channel */
PWM_Clk_Type clk; /*!< PWM Clock */
PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */
PWM_Polarity_Type pol; /*!< PWM mode type */
uint16_t clkDiv; /*!< PWM clkDiv num */
uint16_t period; /*!< PWM period set */
uint16_t threshold1; /*!< PWM threshold1 num */
uint16_t threshold2; /*!< PWM threshold2 num */
uint16_t intPulseCnt; /*!< PWM interrupt pulse count */
}PWM_CH_CFG_Type;
/*@} end of group PWM_Public_Types */
/** @defgroup PWM_Public_Constants
* @{
*/
/** @defgroup PWM_CH_ID_TYPE
* @{
*/
#define IS_PWM_CH_ID_TYPE(type) (((type) == PWM_CH0 ) || \
((type) == PWM_CH1) || \
((type) == PWM_CH2) || \
((type) == PWM_CH3) || \
((type) == PWM_CH4) || \
((type) == PWM_CH_MAX))
/** @defgroup PWM_CLK_TYPE
* @{
*/
#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK ) || \
((type) == PWM_CLK_BCLK) || \
((type) == PWM_CLK_32K))
/** @defgroup PWM_STOP_MODE_TYPE
* @{
*/
#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT ) || \
((type) == PWM_STOP_GRACEFUL))
/** @defgroup PWM_POLARITY_TYPE
* @{
*/
#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_NORMAL ) || \
((type) == PWM_POL_INVERT))
/** @defgroup PWM_INT_TYPE
* @{
*/
#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_PULSE_CNT ) || \
((type) == PWM_INT_ALL))
/*@} end of group PWM_Public_Constants */
/** @defgroup PWM_Public_Macros
* @{
*/
#define IS_PWM_CH(CH) ((CH) < PWM_CH_MAX)
/*@} end of group PWM_Public_Macros */
/** @defgroup PWM_Public_Functions
* @{
*/
/**
* @brief PWM Functions
*/
#ifndef BFLB_USE_HAL_DRIVER
void PWM_IRQHandler(void);
#endif
BL_Err_Type PWM_Channel_Init(PWM_CH_CFG_Type *chCfg);
void PWM_Channel_Update(PWM_CH_ID_Type ch,uint16_t period,uint16_t threshold1,uint16_t threshold2);
void PWM_Channel_Set_Div(PWM_CH_ID_Type ch,uint16_t div);
void PWM_Channel_Set_Threshold1(PWM_CH_ID_Type ch,uint16_t threshold1);
void PWM_Channel_Set_Threshold2(PWM_CH_ID_Type ch,uint16_t threshold2);
void PWM_Channel_Set_Period(PWM_CH_ID_Type ch,uint16_t period);
void PWM_Channel_Get(PWM_CH_ID_Type ch,uint16_t *period,uint16_t *threshold1,uint16_t *threshold2);
void PWM_IntMask(PWM_CH_ID_Type ch,PWM_INT_Type intType,BL_Mask_Type intMask);
void PWM_Channel_Enable(PWM_CH_ID_Type ch);
void PWM_Channel_Disable(PWM_CH_ID_Type ch);
void PWM_SW_Mode(PWM_CH_ID_Type ch,BL_Fun_Type enable);
void PWM_SW_Force_Value(PWM_CH_ID_Type ch,uint8_t value);
void PWM_Int_Callback_Install(PWM_CH_ID_Type ch,uint32_t intType,intCallback_Type* cbFun);
BL_Err_Type PWM_Smart_Configure(PWM_CH_ID_Type ch,uint32_t frequency,uint8_t dutyCycle);
/*@} end of group PWM_Public_Functions */
/*@} end of group PWM */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_PWM_H__ */

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drivers/bl602_driver/std_drv/inc/bl602_romdriver.h Normal file
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/**
******************************************************************************
* @file bl602_romdriver.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_ROMDRIVER_H__
#define __BL602_ROMDRIVER_H__
#include "bl602_common.h"
#include "bl602_aon.h"
#include "bl602_glb.h"
#include "bl602_hbn.h"
#include "bl602_xip_sflash.h"
#include "bl602_sflash.h"
#include "bl602_sf_ctrl.h"
#include "bl602_sec_eng.h"
#include "softcrc.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup ROMDRIVER
* @{
*/
/** @defgroup ROMDRIVER_Public_Types
* @{
*/
#define ROMAPI_INDEX_SECT_SIZE (0x800)
#define ROMAPI_INDEX_MAX (ROMAPI_INDEX_SECT_SIZE / 4 - 1)
typedef enum {
ROM_API_INDEX_VERSION = 0,
ROM_API_INDEX_RSVD_0 ,
ROM_API_INDEX_RSVD_1,
ROM_API_INDEX_RSVD_LAST,
ROM_API_INDEX_AON_Power_On_MBG,
ROM_API_INDEX_AON_Power_Off_MBG,
ROM_API_INDEX_AON_Power_On_XTAL,
ROM_API_INDEX_AON_Set_Xtal_CapCode,
ROM_API_INDEX_AON_Get_Xtal_CapCode,
ROM_API_INDEX_AON_Power_Off_XTAL,
ROM_API_INDEX_AON_Power_On_BG,
ROM_API_INDEX_AON_Power_Off_BG,
ROM_API_INDEX_AON_Power_On_LDO11_SOC,
ROM_API_INDEX_AON_Power_Off_LDO11_SOC,
ROM_API_INDEX_AON_Power_On_LDO15_RF,
ROM_API_INDEX_AON_Power_Off_LDO15_RF,
ROM_API_INDEX_AON_Power_On_SFReg,
ROM_API_INDEX_AON_Power_Off_SFReg,
ROM_API_INDEX_AON_LowPower_Enter_PDS0,
ROM_API_INDEX_AON_LowPower_Exit_PDS0,
ROM_API_INDEX_ASM_Delay_Us,
ROM_API_INDEX_BL602_Delay_US,
ROM_API_INDEX_BL602_Delay_MS,
ROM_API_INDEX_BL602_MemCpy,
ROM_API_INDEX_BL602_MemCpy4,
ROM_API_INDEX_BL602_MemCpy_Fast,
ROM_API_INDEX_BL602_MemSet,
ROM_API_INDEX_BL602_MemSet4,
ROM_API_INDEX_BL602_MemCmp,
ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,
ROM_API_INDEX_EF_Ctrl_Program_Efuse_0,
ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,
ROM_API_INDEX_EF_Ctrl_Busy,
ROM_API_INDEX_EF_Ctrl_AutoLoad_Done,
ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,
ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,
ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,
ROM_API_INDEX_EF_Ctrl_Clear,
ROM_API_INDEX_GLB_Get_Root_CLK_Sel,
ROM_API_INDEX_GLB_Set_System_CLK_Div,
ROM_API_INDEX_GLB_Get_BCLK_Div,
ROM_API_INDEX_GLB_Get_HCLK_Div,
ROM_API_INDEX_Update_SystemCoreClockWith_XTAL,
ROM_API_INDEX_GLB_Set_System_CLK,
ROM_API_INDEX_System_Core_Clock_Update_From_RC32M,
ROM_API_INDEX_GLB_Set_SF_CLK,
ROM_API_INDEX_GLB_Set_PKA_CLK_Sel,
ROM_API_INDEX_GLB_SW_System_Reset,
ROM_API_INDEX_GLB_SW_CPU_Reset,
ROM_API_INDEX_GLB_SW_POR_Reset,
ROM_API_INDEX_GLB_Select_Internal_Flash,
ROM_API_INDEX_GLB_Select_External_Flash,
ROM_API_INDEX_GLB_Deswap_Flash_Pin,
ROM_API_INDEX_GLB_Swap_Flash_Pin,
ROM_API_INDEX_GLB_GPIO_Init,
ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable,
ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable,
ROM_API_INDEX_GLB_GPIO_Set_HZ,
ROM_API_INDEX_GLB_GPIO_Get_Fun,
ROM_API_INDEX_HBN_Mode_Enter,
ROM_API_INDEX_HBN_Power_Down_Flash,
ROM_API_INDEX_HBN_Enable,
ROM_API_INDEX_HBN_Reset,
ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout,
ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout,
ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout,
ROM_API_INDEX_HBN_32K_Sel,
ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel,
ROM_API_INDEX_HBN_Power_On_Xtal_32K,
ROM_API_INDEX_HBN_Power_Off_Xtal_32K,
ROM_API_INDEX_HBN_Power_On_RC32K,
ROM_API_INDEX_HBN_Power_Off_RC32K,
ROM_API_INDEX_HBN_Trim_RC32K,
ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg,
ROM_API_INDEX_HBN_Pin_WakeUp_Mask,
ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg,
ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup,
ROM_API_INDEX_L1C_Set_Wrap,
ROM_API_INDEX_L1C_Set_Way_Disable,
ROM_API_INDEX_L1C_IROM_2T_Access_Set,
ROM_API_INDEX_PDS_Reset,
ROM_API_INDEX_PDS_Enable,
ROM_API_INDEX_PDS_Force_Config,
ROM_API_INDEX_PDS_RAM_Config,
ROM_API_INDEX_PDS_Default_Level_Config,
ROM_API_INDEX_PDS_Trim_RC32M,
ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref,
ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref,
ROM_API_INDEX_PDS_Power_On_PLL,
ROM_API_INDEX_PDS_Enable_PLL_All_Clks,
ROM_API_INDEX_PDS_Disable_PLL_All_Clks,
ROM_API_INDEX_PDS_Enable_PLL_Clk,
ROM_API_INDEX_PDS_Disable_PLL_Clk,
ROM_API_INDEX_PDS_Power_Off_PLL,
ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring,
ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring,
ROM_API_INDEX_SFlash_Init,
ROM_API_INDEX_SFlash_SetSPIMode,
ROM_API_INDEX_SFlash_Read_Reg,
ROM_API_INDEX_SFlash_Write_Reg,
ROM_API_INDEX_SFlash_Busy,
ROM_API_INDEX_SFlash_Write_Enable,
ROM_API_INDEX_SFlash_Qspi_Enable,
ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,
ROM_API_INDEX_SFlash_Chip_Erase,
ROM_API_INDEX_SFlash_Sector_Erase,
ROM_API_INDEX_SFlash_Blk32_Erase,
ROM_API_INDEX_SFlash_Blk64_Erase,
ROM_API_INDEX_SFlash_Erase,
ROM_API_INDEX_SFlash_Program,
ROM_API_INDEX_SFlash_GetUniqueId,
ROM_API_INDEX_SFlash_GetJedecId,
ROM_API_INDEX_SFlash_GetDeviceId,
ROM_API_INDEX_SFlash_Powerdown,
ROM_API_INDEX_SFlash_Releae_Powerdown,
ROM_API_INDEX_SFlash_SetBurstWrap,
ROM_API_INDEX_SFlash_DisableBurstWrap,
ROM_API_INDEX_SFlash_Software_Reset,
ROM_API_INDEX_SFlash_Reset_Continue_Read,
ROM_API_INDEX_SFlash_Set_IDbus_Cfg,
ROM_API_INDEX_SFlash_IDbus_Read_Enable,
ROM_API_INDEX_SFlash_Cache_Enable_Set,
ROM_API_INDEX_SFlash_Cache_Flush,
ROM_API_INDEX_SFlash_Cache_Read_Enable,
ROM_API_INDEX_SFlash_Cache_Hit_Count_Get,
ROM_API_INDEX_SFlash_Cache_Miss_Count_Get,
ROM_API_INDEX_SFlash_Cache_Read_Disable,
ROM_API_INDEX_SFlash_Read,
ROM_API_INDEX_SFlash_Read_Reg_With_Cmd,
ROM_API_INDEX_SFlash_Write_Reg_With_Cmd,
ROM_API_INDEX_SFlash_Restore_From_Powerdown,
ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,
ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio,
ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,
ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun,
ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,
ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,
ROM_API_INDEX_SF_Cfg_Flash_Identify,
ROM_API_INDEX_SF_Ctrl_Enable,
ROM_API_INDEX_SF_Ctrl_Select_Pad,
ROM_API_INDEX_SF_Ctrl_Set_Owner,
ROM_API_INDEX_SF_Ctrl_Disable,
ROM_API_INDEX_SF_Ctrl_AES_Enable_BE,
ROM_API_INDEX_SF_Ctrl_AES_Enable_LE,
ROM_API_INDEX_SF_Ctrl_AES_Set_Region,
ROM_API_INDEX_SF_Ctrl_AES_Set_Key,
ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE,
ROM_API_INDEX_SF_Ctrl_AES_Set_IV,
ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE,
ROM_API_INDEX_SF_Ctrl_AES_Enable,
ROM_API_INDEX_SF_Ctrl_AES_Disable,
ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset,
ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset,
ROM_API_INDEX_SF_Ctrl_Select_Clock,
ROM_API_INDEX_SF_Ctrl_SendCmd,
ROM_API_INDEX_SF_Ctrl_Icache_Set,
ROM_API_INDEX_SF_Ctrl_Icache2_Set,
ROM_API_INDEX_SF_Ctrl_GetBusyState,
ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,
ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay,
ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay,
ROM_API_INDEX_XIP_SFlash_State_Save,
ROM_API_INDEX_XIP_SFlash_State_Restore,
ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock,
ROM_API_INDEX_XIP_SFlash_Write_Need_Lock,
ROM_API_INDEX_XIP_SFlash_Read_Need_Lock,
ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock,
ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock,
ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock,
ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock,
ROM_API_INDEX_XIP_SFlash_Read_With_Lock,
ROM_API_INDEX_XIP_SFlash_Write_With_Lock,
ROM_API_INDEX_XIP_SFlash_Erase_With_Lock,
ROM_API_INDEX_XIP_SFlash_Opt_Enter,
ROM_API_INDEX_XIP_SFlash_Opt_Exit,
ROM_API_INDEX_BFLB_Soft_CRC32,
ROM_API_INDEX_FUNC_EMPTY_START,
ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX
} ROM_API_INDEX_e;
/*@} end of group ROMDRIVER_Public_Types */
/** @defgroup ROMDRIVER_Public_Constants
* @{
*/
/*@} end of group ROMDRIVER_Public_Constants */
/** @defgroup ROMDRIVER_Public_Macros
* @{
*/
#define ROM_APITABLE ((uint32_t *)0x21010800)
#define RomDriver_AON_Power_On_MBG \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG])
#define RomDriver_AON_Power_Off_MBG \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG])
#define RomDriver_AON_Power_On_XTAL \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])
#define RomDriver_AON_Set_Xtal_CapCode \
((BL_Err_Type (*) (uint8_t capIn,uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])
#define RomDriver_AON_Get_Xtal_CapCode \
((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode])
#define RomDriver_AON_Power_Off_XTAL \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL])
#define RomDriver_AON_Power_On_BG \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG])
#define RomDriver_AON_Power_Off_BG \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG])
#define RomDriver_AON_Power_On_LDO11_SOC \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO11_SOC])
#define RomDriver_AON_Power_Off_LDO11_SOC \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO11_SOC])
#define RomDriver_AON_Power_On_LDO15_RF \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO15_RF])
#define RomDriver_AON_Power_Off_LDO15_RF \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO15_RF])
#define RomDriver_AON_Power_On_SFReg \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg])
#define RomDriver_AON_Power_Off_SFReg \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg])
#define RomDriver_AON_LowPower_Enter_PDS0 \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0])
#define RomDriver_AON_LowPower_Exit_PDS0 \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0])
#define RomDriver_ASM_Delay_Us \
((void (*) (uint32_t core,uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])
#define RomDriver_BL602_Delay_US \
((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_US])
#define RomDriver_BL602_Delay_MS \
((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_MS])
#define RomDriver_BL602_MemCpy \
((void* (*) (void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy])
#define RomDriver_BL602_MemCpy4 \
((uint32_t* (*) (uint32_t *dst, const uint32_t *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy4])
#define RomDriver_BL602_MemCpy_Fast \
((void* (*) (void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy_Fast])
#define RomDriver_BL602_MemSet \
((void* (*) (void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet])
#define RomDriver_BL602_MemSet4 \
((uint32_t* (*) (uint32_t *dst, const uint32_t val, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet4])
#define RomDriver_BL602_MemCmp \
((int (*) (const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCmp])
#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])
#define RomDriver_EF_Ctrl_Program_Efuse_0 \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0])
#define RomDriver_EF_Ctrl_Load_Efuse_R0 \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])
#define RomDriver_EF_Ctrl_Busy \
((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy])
#define RomDriver_EF_Ctrl_AutoLoad_Done \
((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done])
#define RomDriver_EF_Ctrl_Get_Trim_Parity \
((uint8_t (*) (uint32_t val,uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity])
#define RomDriver_EF_Ctrl_Read_RC32M_Trim \
((void (*) ( Efuse_Ana_RC32M_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim])
#define RomDriver_EF_Ctrl_Read_RC32K_Trim \
((void (*) ( Efuse_Ana_RC32K_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])
#define RomDriver_EF_Ctrl_Clear \
((void (*) (uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
#define RomDriver_GLB_Get_Root_CLK_Sel \
((GLB_ROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel])
#define RomDriver_GLB_Set_System_CLK_Div \
((BL_Err_Type (*) (uint8_t hclkDiv,uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div])
#define RomDriver_GLB_Get_BCLK_Div \
((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div])
#define RomDriver_GLB_Get_HCLK_Div \
((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div])
#define RomDriver_Update_SystemCoreClockWith_XTAL \
((BL_Err_Type (*) (GLB_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL])
#define RomDriver_GLB_Set_System_CLK \
((BL_Err_Type (*) (GLB_PLL_XTAL_Type xtalType,GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK])
#define RomDriver_System_Core_Clock_Update_From_RC32M \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M])
#define RomDriver_GLB_Set_SF_CLK \
((BL_Err_Type (*) (uint8_t enable,GLB_SFLASH_CLK_Type clkSel,uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])
#define RomDriver_GLB_Set_PKA_CLK_Sel \
((BL_Err_Type (*) (GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel])
#define RomDriver_GLB_SW_System_Reset \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])
#define RomDriver_GLB_SW_CPU_Reset \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])
#define RomDriver_GLB_SW_POR_Reset \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset])
#define RomDriver_GLB_Select_Internal_Flash \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash])
#define RomDriver_GLB_Select_External_Flash \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash])
#define RomDriver_GLB_Deswap_Flash_Pin \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin])
#define RomDriver_GLB_Swap_Flash_Pin \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin])
#define RomDriver_GLB_GPIO_Init \
((BL_Err_Type (*) (GLB_GPIO_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init])
#define RomDriver_GLB_GPIO_OUTPUT_Enable \
((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable])
#define RomDriver_GLB_GPIO_OUTPUT_Disable \
((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable])
#define RomDriver_GLB_GPIO_Set_HZ \
((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ])
#define RomDriver_GLB_GPIO_Get_Fun \
((uint8_t (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun])
#define RomDriver_HBN_Mode_Enter \
((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter])
#define RomDriver_HBN_Power_Down_Flash \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
#define RomDriver_HBN_Enable \
((void (*) (uint8_t aGPIOIeCfg,HBN_LDO_LEVEL_Type ldoLevel,HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
#define RomDriver_HBN_Reset \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset])
#define RomDriver_HBN_Set_Ldo11_Aon_Vout \
((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout])
#define RomDriver_HBN_Set_Ldo11_Rt_Vout \
((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout])
#define RomDriver_HBN_Set_Ldo11_Soc_Vout \
((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout])
#define RomDriver_HBN_32K_Sel \
((BL_Err_Type (*) (HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel])
#define RomDriver_HBN_Set_ROOT_CLK_Sel \
((BL_Err_Type (*) (HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel])
#define RomDriver_HBN_Power_On_Xtal_32K \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K])
#define RomDriver_HBN_Power_Off_Xtal_32K \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K])
#define RomDriver_HBN_Power_On_RC32K \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K])
#define RomDriver_HBN_Power_Off_RC32K \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K])
#define RomDriver_HBN_Trim_RC32K \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])
#define RomDriver_HBN_Hw_Pu_Pd_Cfg \
((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg])
#define RomDriver_HBN_Pin_WakeUp_Mask \
((BL_Err_Type (*) (uint8_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask])
#define RomDriver_HBN_GPIO7_Dbg_Pull_Cfg \
((BL_Err_Type (*) (BL_Fun_Type pupdEn,BL_Fun_Type iesmtEn,BL_Fun_Type dlyEn,uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg])
#define RomDriver_HBN_Set_Embedded_Flash_Pullup \
((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup])
#define RomDriver_L1C_Set_Wrap \
((BL_Err_Type (*) (BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])
#define RomDriver_L1C_Set_Way_Disable \
((BL_Err_Type (*) (uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable])
#define RomDriver_L1C_IROM_2T_Access_Set \
((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set])
#define RomDriver_PDS_Reset \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset])
#define RomDriver_PDS_Enable \
((BL_Err_Type (*) (PDS_CTL_Type *cfg,PDS_CTL4_Type *cfg4,uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Enable])
#define RomDriver_PDS_Force_Config \
((BL_Err_Type (*) (PDS_CTL2_Type *cfg2,PDS_CTL3_Type *cfg3))ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config])
#define RomDriver_PDS_RAM_Config \
((BL_Err_Type (*) (PDS_RAM_CFG_Type *ramCfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config])
#define RomDriver_PDS_Default_Level_Config \
((BL_Err_Type (*) (PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,PDS_RAM_CFG_Type *ramCfg,uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config])
#define RomDriver_PDS_Trim_RC32M \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M])
#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref])
#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref])
#define RomDriver_PDS_Power_On_PLL \
((BL_Err_Type (*) (PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL])
#define RomDriver_PDS_Enable_PLL_All_Clks \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks])
#define RomDriver_PDS_Disable_PLL_All_Clks \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks])
#define RomDriver_PDS_Enable_PLL_Clk \
((BL_Err_Type (*) (PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk])
#define RomDriver_PDS_Disable_PLL_Clk \
((BL_Err_Type (*) (PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk])
#define RomDriver_PDS_Power_Off_PLL \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL])
#define RomDriver_SEC_Eng_Turn_On_Sec_Ring \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring])
#define RomDriver_SEC_Eng_Turn_Off_Sec_Ring \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring])
#define RomDriver_SFlash_Init \
((void (*) (const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
#define RomDriver_SFlash_SetSPIMode \
((BL_Err_Type (*) (SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
#define RomDriver_SFlash_Read_Reg \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
#define RomDriver_SFlash_Write_Reg \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
#define RomDriver_SFlash_Busy \
((BL_Sts_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
#define RomDriver_SFlash_Write_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
#define RomDriver_SFlash_Qspi_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
#define RomDriver_SFlash_Chip_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
#define RomDriver_SFlash_Sector_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
#define RomDriver_SFlash_Blk32_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
#define RomDriver_SFlash_Blk64_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
#define RomDriver_SFlash_Erase \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint32_t startaddr,uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
#define RomDriver_SFlash_Program \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
#define RomDriver_SFlash_GetUniqueId \
((void (*) (uint8_t *data,uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
#define RomDriver_SFlash_GetJedecId \
((void (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
#define RomDriver_SFlash_GetDeviceId \
((void (*) (uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
#define RomDriver_SFlash_Powerdown \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
#define RomDriver_SFlash_Releae_Powerdown \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
#define RomDriver_SFlash_SetBurstWrap \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
#define RomDriver_SFlash_DisableBurstWrap \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
#define RomDriver_SFlash_Software_Reset \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
#define RomDriver_SFlash_Reset_Continue_Read \
((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
#define RomDriver_SFlash_Set_IDbus_Cfg \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
#define RomDriver_SFlash_IDbus_Read_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
#define RomDriver_SFlash_Cache_Enable_Set \
((BL_Err_Type (*) (uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set])
#define RomDriver_SFlash_Cache_Flush \
((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush])
#define RomDriver_SFlash_Cache_Read_Enable \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
#define RomDriver_SFlash_Cache_Hit_Count_Get \
((void (*) (uint32_t *hitCountLow,uint32_t *hitCountHigh))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get])
#define RomDriver_SFlash_Cache_Miss_Count_Get \
((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Miss_Count_Get])
#define RomDriver_SFlash_Cache_Read_Disable \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable])
#define RomDriver_SFlash_Read \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
#define RomDriver_SFlash_Read_Reg_With_Cmd \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t readRegCmd,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
#define RomDriver_SFlash_Write_Reg_With_Cmd \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg,uint8_t writeRegCmd,uint8_t *regValue,uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
#define RomDriver_SFlash_Restore_From_Powerdown \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t flashContRead))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
((void (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio])
#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
((void (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Restore_GPIO17_Fun \
((void (*) (uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun])
#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
((BL_Err_Type (*) (uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
#define RomDriver_SF_Cfg_Init_Flash_Gpio \
((void (*) (uint8_t flashPinCfg,uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
#define RomDriver_SF_Cfg_Flash_Identify \
((uint32_t (*) (uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
#define RomDriver_SF_Ctrl_Enable \
((void (*) (const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
#define RomDriver_SF_Ctrl_Select_Pad \
((void (*) (SF_Ctrl_Pad_Sel sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
#define RomDriver_SF_Ctrl_Set_Owner \
((void (*) (SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
#define RomDriver_SF_Ctrl_Disable \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
#define RomDriver_SF_Ctrl_AES_Enable_BE \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE])
#define RomDriver_SF_Ctrl_AES_Enable_LE \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE])
#define RomDriver_SF_Ctrl_AES_Set_Region \
((void (*) (uint8_t region,uint8_t enable,uint8_t hwKey,uint32_t startAddr,uint32_t endAddr,uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
#define RomDriver_SF_Ctrl_AES_Set_Key \
((void (*) (uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
((void (*) (uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
#define RomDriver_SF_Ctrl_AES_Set_IV \
((void (*) (uint8_t region,uint8_t *iv,uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])
#define RomDriver_SF_Ctrl_AES_Set_IV_BE \
((void (*) (uint8_t region,uint8_t *iv,uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
#define RomDriver_SF_Ctrl_AES_Enable \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable])
#define RomDriver_SF_Ctrl_AES_Disable \
((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable])
#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \
((void (*) (uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \
((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Select_Clock \
((void (*) (SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
#define RomDriver_SF_Ctrl_SendCmd \
((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
#define RomDriver_SF_Ctrl_Icache_Set \
((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set])
#define RomDriver_SF_Ctrl_Icache2_Set \
((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set])
#define RomDriver_SF_Ctrl_GetBusyState \
((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
#define RomDriver_SF_Ctrl_Is_AES_Enable \
((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
#define RomDriver_SF_Ctrl_Get_Clock_Delay \
((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
#define RomDriver_SF_Ctrl_Set_Clock_Delay \
((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
#define RomDriver_XIP_SFlash_State_Save \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
#define RomDriver_XIP_SFlash_State_Restore \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
#define RomDriver_XIP_SFlash_Erase_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
#define RomDriver_XIP_SFlash_Write_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
((BL_Err_Type (*) (uint32_t addr,uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
#define RomDriver_XIP_SFlash_Read_With_Lock \
((int (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock])
#define RomDriver_XIP_SFlash_Write_With_Lock \
((int (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock])
#define RomDriver_XIP_SFlash_Erase_With_Lock \
((int (*) (SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock])
#define RomDriver_XIP_SFlash_Opt_Enter \
((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter])
#define RomDriver_XIP_SFlash_Opt_Exit \
((void (*) (uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit])
#define RomDriver_BFLB_Soft_CRC32 \
((uint32_t (*) (void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32])
/*@} end of group ROMDRIVER_Public_Macros */
/** @defgroup ROMDRIVER_Public_Functions
* @{
*/
/*@} end of group ROMDRIVER_Public_Functions */
/*@} end of group ROMDRIVER */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_ROMDRIVER_H__ */

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#ifndef __BL602_SDU_H__
#define __BL602_SDU_H__
#include "bl602.h"
#include "bl602_common.h"
#define NUM_FUNC 1
#define FUNC_WIFI 0
// SDIO I/O Enable
#define BL_SDIO_IO_ENABLE SDU_BASE + 0x00000002
//CCCR (Fn0) Registers
// SDIO Device Sleep
#define BL_SDIO_DEV_SLEEP SDU_BASE + 0x00000092
// Start Address of CCR
#define BL_SDIO_CCR_BASE SDU_BASE + 0x00000100
// Address offset of CCR between two functions
#define BL_SDIO_CCR_FUNC_OFFSET 0x00000100
// Address for sdio block size information
#define SDIO_FN1_BLK_SIZE_0 (SDU_BASE + 0x00000028)
#define SDIO_FN1_BLK_SIZE_1 (SDU_BASE + 0x00000029)
#define SDIO_FN1_BLK_SIZE_1_MASK 0x01
#define BL_FUNC_SCRATCH_BASE SDU_BASE + 0x00000160
typedef struct
{
uint8_t HostToCardEvent; // 0x100/200
uint8_t HostIntCause; // 0x101/201
uint8_t HostIntMask; // 0x102/202
uint8_t HostIntStatus; // 0x103/203
uint16_t RdBitMap; // 0x104/204
uint16_t WrBitMap; // 0x106/206
uint16_t RdLen[16]; // 0x108/208
uint8_t HostTransferStatus;// 0x128/228
uint8_t reserved1[0x130-0x128-1];
uint8_t CardToHostEvent; // 0x130/230
uint8_t reserved2[3];
uint8_t CardIntMask; // 0x134/234
uint8_t reserved3[3];
uint8_t CardIntStatus; // 0x138/238
uint8_t reserved4[3];
uint8_t CardIntMode; // 0x13C/23C
uint8_t reserved5[3];
uint32_t SqReadBase; // 0x140/240
uint32_t SqWriteBase; // 0x144/244
uint8_t RdIdx; // 0x148/248
uint8_t WrIdx; // 0x149/249
uint8_t DnldQueueWrPtr; // 0x14A/24A
uint8_t UpldQueueWrPtr; // 0x14B/24B
uint8_t DnldQueue[8]; // 0x14C/24C
uint8_t UpldQueue[8]; // 0x154/254
uint8_t ChipRev; // 0x15C //RO
uint8_t reserved6; // 0x15D //NOT_DEFINE
uint8_t IPRev0; // 0x15E //RO
uint8_t IPRev1; // 0x15F //RO
uint8_t reserved7[4]; // 0x160/260
uint16_t Scratch2; // 0x164/264
uint16_t Scratch1; // 0x166/266
uint8_t Ocr0; // 0x168/268
uint8_t Ocr1; // 0x169/269
uint8_t Ocr2; // 0x16A/26A
uint8_t Config; // 0x16B/26B
uint32_t Config2; // 0x16C/26C
uint32_t Debug; // 0x170/270
uint32_t DmaAddr; // 0x174/274
uint8_t IoPort[3]; // 0x178/278
} __attribute__((packed)) HidSdio_RegMap_t, *pHidSdio_RegMap_t;
// Common I/O Area Registers (CIA) Offset
//
// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
#define SDIO_HCR_CONFIG_HostPwrUp (1<<1)
// Bit Def. Host Transfer Status (Offset 0x128/228)
#define SDIO_CCR_HOST_INT_DnLdReStart (1<<0)
#define SDIO_CCR_HOST_INT_UpLdReStart (1<<1)
#define SDIO_CCR_HOST_INT_DnLdCRC_err (1<<2)
// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
#define SDIO_CCR_CS_DnLdRdy (1<<0)
#define SDIO_CCR_CS_UpLdRdy (1<<1)
#define SDIO_CCR_CS_ReadCISRdy (1<<2)
#define SDIO_CCR_CS_IORdy (1<<3)
// Bit Def. Card Interrupt Mask (Offset 0x134/234)
#define SDIO_CCR_CIM_DnLdOvr (1<<0)
#define SDIO_CCR_CIM_UpLdOvr (1<<1)
#define SDIO_CCR_CIM_Abort (1<<2)
#define SDIO_CCR_CIM_PwrDn (1<<3)
#define SDIO_CCR_CIM_PwrUp (1<<4)
#define SDIO_CCR_CIM_MASK 0x0007
// Bit Def. Card Interrupt Status (Offset 0x138/238)
#define SDIO_CCR_CIC_DnLdOvr (1<<0)
#define SDIO_CCR_CIC_UpLdOvr (1<<1)
#define SDIO_CCR_CIC_Abort (1<<2)
#define SDIO_CCR_CIC_PwrDn (1<<3)
#define SDIO_CCR_CIC_PwrUp (1<<4)
#define SDIO_CCR_CIC_MASK 0x001F
// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
#define SDIO_CCR_CIO_DnLdOvr (1<<0)
#define SDIO_CCR_CIO_UpLdOvr (1<<1)
#define SDIO_CCR_CIO_Abort (1<<2)
#define SDIO_CCR_CIO_PwrDn (1<<3)
#define SDIO_CCR_CIO_PwrUp (1<<4)
#define SDIO_CCR_CIO_MASK 0x001F
//Config2 register mask
#define CONFIG2_MSK 0x00000C00
//CardIntMode register mask
#define CARD_INT_MODE_MSK 0x00000003
#define HOST_INT_MSK 0x00000002
//=============================================================================
// PUBLIC MACROS
//=============================================================================
#define BL_REGS8(x) (*(volatile unsigned char *)(x))
#define BL_REGS16(x) (*(volatile unsigned short *)(x))
#define BL_REGS32(x) (*(volatile unsigned long *)(x))
#define BL_READ_REGS8(reg,val) ((val) = BL_REGS8(reg))
#define BL_READ_REGS16(reg,val) ((val) = BL_REGS16(reg))
#define BL_READ_REGS32(reg,val) ((val) = BL_REGS32(reg))
#define BL_READ_BYTE(reg,val) ((val) = BL_REGS8(reg))
#define BL_READ_HWORD(reg,val) ((val) = BL_REGS16(reg)) /*half word; */
#define BL_READ_WORD(reg,val) ((val) = BL_REGS32(reg)) /*32 bits */
#define BL_WRITE_REGS8(reg,val) (BL_REGS8(reg) = (val))
#define BL_WRITE_REGS16(reg,val) (BL_REGS16(reg) = (val))
#define BL_WRITE_REGS32(reg,val) (BL_REGS32(reg) = (val))
#define BL_WRITE_BYTE(reg,val) (BL_REGS8(reg) = (val))
#define BL_WRITE_HWORD(reg,val) (BL_REGS16(reg) = (val)) /*half word; */
#define BL_WRITE_WORD(reg,val) (BL_REGS32(reg) = (val)) /*32 bits */
// Write uint32 to a low 16-bit register and a high 16-bit register
#define WRITE2REGS(lo,hi,u32) \
BL_WRITE_HWORD(lo, (uint16_t)((u32) & 0xffff)); \
BL_WRITE_HWORD(hi, (uint16_t)(((u32) >> 16) & 0xffff))
#define BL_REGS8_SETBITS(reg, val) (BL_REGS8(reg) |= (uint8)(val))
#define BL_REGS16_SETBITS(reg, val) (BL_REGS16(reg) |= (uint16)(val))
#define BL_REGS32_SETBITS(reg, val) (BL_REGS32(reg) |= (val))
#define BL_REGS8_CLRBITS(reg, val) (BL_REGS8(reg) = (uint8)(BL_REGS8(reg)&~(val)))
#define BL_REGS16_CLRBITS(reg, val) (BL_REGS16(reg) = (uint16)(BL_REGS16(reg)&~(val)))
#define BL_REGS32_CLRBITS(reg, val) (BL_REGS32(reg) = (BL_REGS32(reg)&~(val)))
//=============================================================================
// ENUM TYPE DEFINITION
//=============================================================================
/******************************************************************/
/*!
* \enum SDIO_CMD_TYPE
*
*******************************************************************/
typedef enum
{
IOCTL_GET_CONFIG = 0, /*!< Get configuration info */
/* HID IOCTLs*/
IOCTL_HID_GET_BLOCK_SIZE, /*!< Get Block size */
} SDIO_CMD_TYPE;
//=============================================================================
// FUNCTION DECLARATION
//=============================================================================
extern void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value);
extern uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg);
//=============================================================================
// Variable DECLARATION
//=============================================================================
extern volatile pHidSdio_RegMap_t SdioFuncReg[];
extern uint8_t flag_mport[];
#endif /* __BL602_SDU_H__ */

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/**
******************************************************************************
* @file bl602_sec_dbg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SEC_DBG_H__
#define __BL602_SEC_DBG_H__
#include "sec_dbg_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SEC_DBG
* @{
*/
/** @defgroup SEC_DBG_Public_Types
* @{
*/
/*@} end of group SEC_DBG_Public_Types */
/** @defgroup SEC_DBG_Public_Constants
* @{
*/
/*@} end of group SEC_DBG_Public_Constants */
/** @defgroup SEC_DBG_Public_Macros
* @{
*/
/*@} end of group SEC_DBG_Public_Macros */
/** @defgroup SEC_DBG_Public_Functions
* @{
*/
void Sec_Dbg_Read_Chip_ID(uint8_t id[8]);
void Sec_Dbg_Read_WiFi_MAC(uint8_t macAddr[6]);
uint32_t Sec_Dbg_Read_Dbg_Mode(void);
uint32_t Sec_Dbg_Read_Dbg_Enable(void);
/*@} end of group SEC_DBG_Public_Functions */
/*@} end of group SEC_DBG */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SEC_DBG_H__ */

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/**
******************************************************************************
* @file bl602_sec_eng.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SEC_ENG_H__
#define __BL602_SEC_ENG_H__
#include "sec_eng_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SEC_ENG
* @{
*/
/** @defgroup SEC_ENG_Public_Types
* @{
*/
/**
* @brief AES port type definition
*/
typedef enum {
SEC_ENG_AES_ID0, /*!< AES0 port define */
}SEC_ENG_AES_ID_Type;
/**
* @brief SHA port type definition
*/
typedef enum {
SEC_ENG_SHA_ID0, /*!< SHA0 port define */
}SEC_ENG_SHA_ID_Type;
/**
* @brief SHA type definition
*/
typedef enum {
SEC_ENG_SHA256, /*!< SHA type:SHA256 */
SEC_ENG_SHA224, /*!< SHA type:SHA224 */
SEC_ENG_SHA1, /*!< SHA type:SHA1 */
SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */
}SEC_ENG_SHA_Type;
/**
* @brief AES type definition
*/
typedef enum {
SEC_ENG_AES_ECB, /*!< AES mode type:ECB */
SEC_ENG_AES_CTR, /*!< AES mode type:CTR */
SEC_ENG_AES_CBC, /*!< AES mode type:CBC */
}SEC_ENG_AES_Type;
/**
* @brief AES KEY type definition
*/
typedef enum {
SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */
SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */
SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */
SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */
}SEC_ENG_AES_Key_Type;
/**
* @brief AES CTR mode counter type definition
*/
typedef enum {
SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */
SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */
SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */
SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */
}SEC_ENG_AES_Counter_Type;
/**
* @brief AES use new or old value type definition
*/
typedef enum {
SEC_ENG_AES_USE_NEW, /*!< Use new value */
SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */
}SEC_ENG_AES_ValueUsed_Type;
/**
* @brief AES KEY source type definition
*/
typedef enum {
SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */
SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */
}SEC_ENG_AES_Key_Src_Type;
/**
* @brief AES KEY source type definition
*/
typedef enum {
SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */
SEC_ENG_AES_DECRYPTION, /*!< AES decryption */
}SEC_ENG_AES_EnDec_Type;
/**
* @brief AES PKA register size type definition
*/
typedef enum {
SEC_ENG_PKA_REG_SIZE_8=1, /*!< Register size is 8 Bytes */
SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */
SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */
SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */
SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */
SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */
SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */
SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */
SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */
SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */
}SEC_ENG_PKA_REG_SIZE_Type;
/**
* @brief AES PKA register size type definition
*/
typedef enum {
SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */
SEC_ENG_PKA_OP_MOD2N=0x11, /*!< PKA operation type */
SEC_ENG_PKA_OP_LDIV2N=0x12, /*!< PKA operation type */
SEC_ENG_PKA_OP_LMUL2N=0x13, /*!< PKA operation type */
SEC_ENG_PKA_OP_LDIV=0x14, /*!< PKA operation type */
SEC_ENG_PKA_OP_LSQR=0x15, /*!< PKA operation type */
SEC_ENG_PKA_OP_LMUL=0x16, /*!< PKA operation type */
SEC_ENG_PKA_OP_LSUB=0x17, /*!< PKA operation type */
SEC_ENG_PKA_OP_LADD=0x18, /*!< PKA operation type */
SEC_ENG_PKA_OP_LCMP=0x19, /*!< PKA operation type */
SEC_ENG_PKA_OP_MDIV2=0x21, /*!< PKA operation type */
SEC_ENG_PKA_OP_MINV=0x22, /*!< PKA operation type */
SEC_ENG_PKA_OP_MEXP=0x23, /*!< PKA operation type */
SEC_ENG_PKA_OP_MSQR=0x24, /*!< PKA operation type */
SEC_ENG_PKA_OP_MMUL=0x25, /*!< PKA operation type */
SEC_ENG_PKA_OP_MREM=0x26, /*!< PKA operation type */
SEC_ENG_PKA_OP_MSUB=0x27, /*!< PKA operation type */
SEC_ENG_PKA_OP_MADD=0x28, /*!< PKA operation type */
SEC_ENG_PKA_OP_RESIZE =0x31, /*!< PKA operation type */
SEC_ENG_PKA_OP_MOVDAT=0x32, /*!< PKA operation type */
SEC_ENG_PKA_OP_NLIR=0x33, /*!< PKA operation type */
SEC_ENG_PKA_OP_SLIR=0x34, /*!< PKA operation type */
SEC_ENG_PKA_OP_CLIR=0x35, /*!< PKA operation type */
SEC_ENG_PKA_OP_CFLIRI_BUFFER=0x36, /*!< PKA operation type */
SEC_ENG_PKA_OP_CTLIRI_PLD=0x37, /*!< PKA operation type */
SEC_ENG_PKA_OP_CFLIR_BUFFER=0x38, /*!< PKA operation type */
SEC_ENG_PKA_OP_CTLIR_PLD=0x39, /*!< PKA operation type */
}SEC_ENG_PKA_OP_Type;
/**
* @brief Sec Eng Interrupt Type Def
*/
typedef enum {
SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */
SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */
SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */
SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */
SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */
SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */
SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */
}SEC_ENG_INT_Type;
/**
* @brief SEC_ENG SHA context
*/
typedef struct {
uint32_t total[2]; /*!< Number of bytes processed */
uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */
uint32_t *shaPadding; /*!< Padding data */
uint8_t shaFeed; /*!< Sha has feed data */
}SEC_Eng_SHA256_Ctx;
/**
* @brief SEC_ENG SHA link mode context
*/
typedef struct {
uint32_t total[2]; /*!< Number of bytes processed */
uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */
uint32_t *shaPadding; /*!< Padding data */
uint32_t linkAddr; /*!< Link configure address */
}SEC_Eng_SHA256_Link_Ctx;
/**
* @brief SEC_ENG AES context
*/
typedef struct {
uint8_t aesFeed; /*!< AES has feed data */
SEC_ENG_AES_Type mode; /*!< AES mode */
}SEC_Eng_AES_Ctx;
/**
* @brief SEC_ENG SHA link config structure type definition
*/
typedef struct {
uint32_t :2; /*!< [1:0]reserved */
uint32_t shaMode:3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1 */
uint32_t :1; /*!< [5]reserved */
uint32_t shaHashSel:1; /*!< [6]New hash or accumulate last hash */
uint32_t :2; /*!< [8:7]reserved */
uint32_t shaIntClr:1; /*!< [9]Clear interrupt */
uint32_t shaIntSet:1; /*!< [10]Set interrupt */
uint32_t :5; /*!< [15:11]reserved */
uint32_t shaMsgLen:16; /*!< [31:16]Number of 512-bit block */
uint32_t shaSrcAddr; /*!< Message source address */
uint32_t result[8]; /*!< Result of SHA */
}__attribute__ ((aligned(4)))SEC_Eng_SHA_Link_Config_Type;
/**
* @brief SEC_ENG AES link config structure type definition
*/
typedef struct {
uint32_t :3; /*!< [2:0]Reserved */
uint32_t aesMode:2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
uint32_t aesDecEn:1; /*!< [5]Encode or decode */
uint32_t aesDecKeySel:1; /*!< [6]Use new key or use same key as last one */
uint32_t aesHwKeyEn:1; /*!< [7]Enable or disable using hardware hey */
uint32_t :1; /*!< [8]Reserved */
uint32_t aesIntClr:1; /*!< [9]Clear interrupt */
uint32_t aesIntSet:1; /*!< [10]Set interrupt */
uint32_t :1; /*!< [11]Reserved */
uint32_t aesBlockMode:2; /*!< [13:12]ECB/CTR/CBC mode select */
uint32_t aesIVSel:1; /*!< [14]Use new iv or use same iv as last one */
uint32_t :1; /*!< [15]Reserved */
uint32_t aesMsgLen:16; /*!< [31:16]Number of 128-bit block */
uint32_t aesSrcAddr; /*!< Message source address */
uint32_t aesDstAddr; /*!< Message destination address */
uint32_t aesIV0; /*!< Big endian initial vector(MSB) */
uint32_t aesIV1; /*!< Big endian initial vector */
uint32_t aesIV2; /*!< Big endian initial vector */
uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */
uint32_t aesKey1; /*!< Big endian aes key */
uint32_t aesKey2; /*!< Big endian aes key */
uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */
uint32_t aesKey4; /*!< Big endian aes key */
uint32_t aesKey5; /*!< Big endian aes key */
uint32_t aesKey6; /*!< Big endian aes key */
uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */
}__attribute__ ((aligned(4)))SEC_Eng_AES_Link_Config_Type;
/**
* @brief SEC_ENG GMAC link config structure type definition
*/
typedef struct {
uint32_t :9; /*!< [8:0]reserved */
uint32_t gmacIntClr:1; /*!< [9]Clear interrupt */
uint32_t gmacIntSet:1; /*!< [10]Set interrupt */
uint32_t :5; /*!< [15:11]reserved */
uint32_t gmacMsgLen:16; /*!< [31:16]Number of 128-bit block */
uint32_t gmacSrcAddr; /*!< Message source address */
uint32_t gmacKey0; /*!< GMAC key */
uint32_t gmacKey1; /*!< GMAC key */
uint32_t gmacKey2; /*!< GMAC key */
uint32_t gmacKey3; /*!< GMAC key */
uint32_t result[4]; /*!< Result of GMAC */
}__attribute__ ((aligned(4)))SEC_Eng_GMAC_Link_Config_Type;
/*@} end of group SEC_ENG_Public_Types */
/** @defgroup SEC_ENG_Public_Constants
* @{
*/
/** @defgroup SEC_ENG_AES_ID_TYPE
* @{
*/
#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0))
/** @defgroup SEC_ENG_SHA_ID_TYPE
* @{
*/
#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0))
/** @defgroup SEC_ENG_SHA_TYPE
* @{
*/
#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \
((type) == SEC_ENG_SHA224) || \
((type) == SEC_ENG_SHA1) || \
((type) == SEC_ENG_SHA1_RSVD))
/** @defgroup SEC_ENG_AES_TYPE
* @{
*/
#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \
((type) == SEC_ENG_AES_CTR) || \
((type) == SEC_ENG_AES_CBC))
/** @defgroup SEC_ENG_AES_KEY_TYPE
* @{
*/
#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \
((type) == SEC_ENG_AES_KEY_256BITS) || \
((type) == SEC_ENG_AES_KEY_192BITS) || \
((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS))
/** @defgroup SEC_ENG_AES_COUNTER_TYPE
* @{
*/
#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \
((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \
((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \
((type) == SEC_ENG_AES_COUNTER_BYTE_3))
/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE
* @{
*/
#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \
((type) == SEC_ENG_AES_USE_OLD))
/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE
* @{
*/
#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \
((type) == SEC_ENG_AES_KEY_HW))
/** @defgroup SEC_ENG_AES_ENDEC_TYPE
* @{
*/
#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \
((type) == SEC_ENG_AES_DECRYPTION))
/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE
* @{
*/
#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \
((type) == SEC_ENG_PKA_REG_SIZE_16) || \
((type) == SEC_ENG_PKA_REG_SIZE_32) || \
((type) == SEC_ENG_PKA_REG_SIZE_64) || \
((type) == SEC_ENG_PKA_REG_SIZE_96) || \
((type) == SEC_ENG_PKA_REG_SIZE_128) || \
((type) == SEC_ENG_PKA_REG_SIZE_192) || \
((type) == SEC_ENG_PKA_REG_SIZE_256) || \
((type) == SEC_ENG_PKA_REG_SIZE_384) || \
((type) == SEC_ENG_PKA_REG_SIZE_512))
/** @defgroup SEC_ENG_PKA_OP_TYPE
* @{
*/
#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \
((type) == SEC_ENG_PKA_OP_MOD2N) || \
((type) == SEC_ENG_PKA_OP_LDIV2N) || \
((type) == SEC_ENG_PKA_OP_LMUL2N) || \
((type) == SEC_ENG_PKA_OP_LDIV) || \
((type) == SEC_ENG_PKA_OP_LSQR) || \
((type) == SEC_ENG_PKA_OP_LMUL) || \
((type) == SEC_ENG_PKA_OP_LSUB) || \
((type) == SEC_ENG_PKA_OP_LADD) || \
((type) == SEC_ENG_PKA_OP_LCMP) || \
((type) == SEC_ENG_PKA_OP_MDIV2) || \
((type) == SEC_ENG_PKA_OP_MINV) || \
((type) == SEC_ENG_PKA_OP_MEXP) || \
((type) == SEC_ENG_PKA_OP_MSQR) || \
((type) == SEC_ENG_PKA_OP_MMUL) || \
((type) == SEC_ENG_PKA_OP_MREM) || \
((type) == SEC_ENG_PKA_OP_MSUB) || \
((type) == SEC_ENG_PKA_OP_MADD) || \
((type) == SEC_ENG_PKA_OP_RESIZE ) || \
((type) == SEC_ENG_PKA_OP_MOVDAT) || \
((type) == SEC_ENG_PKA_OP_NLIR) || \
((type) == SEC_ENG_PKA_OP_SLIR) || \
((type) == SEC_ENG_PKA_OP_CLIR) || \
((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \
((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \
((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \
((type) == SEC_ENG_PKA_OP_CTLIR_PLD))
/** @defgroup SEC_ENG_INT_TYPE
* @{
*/
#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \
((type) == SEC_ENG_INT_AES) || \
((type) == SEC_ENG_INT_SHA) || \
((type) == SEC_ENG_INT_PKA) || \
((type) == SEC_ENG_INT_CDET) || \
((type) == SEC_ENG_INT_GMAC) || \
((type) == SEC_ENG_INT_ALL))
/*@} end of group SEC_ENG_Public_Constants */
/** @defgroup SEC_ENG_Public_Macros
* @{
*/
#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24
#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000
/*@} end of group SEC_ENG_Public_Macros */
/** @defgroup SEC_ENG_Public_Functions
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
void SEC_GMAC_IRQHandler(void);
void SEC_CDET_IRQHandler(void);
void SEC_TRNG_IRQHandler(void);
void SEC_PKA_IRQHandler(void);
void SEC_AES_IRQHandler(void);
void SEC_SHA_IRQHandler(void);
#endif
void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,SEC_ENG_SHA_Type type,
uint32_t shaTmpBuf[16],
uint32_t padding[16]);
void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo);
BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,const uint8_t *input,
uint32_t len);
BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint8_t *hash);
void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo);
void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo);
void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,uint32_t linkAddr,
uint32_t shaTmpBuf[16],uint32_t padding[16]);
BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,
const uint8_t *input, uint32_t len);
BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx,SEC_ENG_SHA_ID_Type shaNo,
uint8_t *hash);
BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx,SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Type aesType,
SEC_ENG_AES_Key_Type keyType,SEC_ENG_AES_EnDec_Type enDecType);
void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo);
void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo);
void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo);
void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo);
BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo,uint32_t linkAddr,const uint8_t *in,uint32_t len,
uint8_t *out);
void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo,uint8_t src);
void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Key_Src_Type keySrc,const uint8_t *key,
const uint8_t *iv);
void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Key_Src_Type keySrc,const uint8_t *key,
const uint8_t *iv);
void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo,SEC_ENG_AES_Counter_Type counterType);
BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx,SEC_ENG_AES_ID_Type aesNo,const uint8_t *in, uint32_t len,
uint8_t *out);
BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo);
BL_Err_Type Sec_Eng_Trng_Enable(void);
void Sec_Eng_Trng_Int_Enable(void);
void Sec_Eng_Trng_Int_Disable(void);
BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]);
void Sec_Eng_Trng_Int_Read_Trigger(void);
void Sec_Eng_Trng_Int_Read(uint8_t data[32]);
void Sec_Eng_Trng_Disable(void);
void Sec_Eng_PKA_Reset(void);
void Sec_Eng_PKA_BigEndian_Enable(void);
void Sec_Eng_PKA_LittleEndian_Enable(void);
void Sec_Eng_PKA_Write_Data( SEC_ENG_PKA_REG_SIZE_Type regType,uint8_t regIndex,const uint32_t *data,uint16_t size,
uint8_t lastOp);
void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize);
void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size,uint8_t lastOp);
void Sec_Eng_PKA_Write_Immediate( SEC_ENG_PKA_REG_SIZE_Type regType,uint8_t regIndex,uint32_t data,uint8_t lastOp);
void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s2RegType,
uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s2RegType,
uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s2RegType,
uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s2RegType,
uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx);
void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s1RegType,
uint8_t s1RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint8_t s2RegType,
uint8_t s2RegIdx,uint8_t lastOp);
void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint16_t bit_shift,
uint8_t lastOp);
void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint16_t bit_shift,
uint8_t lastOp);
void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx,
uint16_t bit_shift,
uint8_t lastOp);
void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx,uint32_t size,
uint8_t tRegType, uint8_t tRegIdx,uint8_t pRegType, uint8_t pRegIdx);
void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType,
uint8_t invrRegIdx,
uint8_t tRegType, uint8_t tRegIdx,uint8_t pRegType, uint8_t pRegIdx);
void Sec_Eng_GMAC_Enable_LE(void);
void Sec_Eng_GMAC_Enable_BE(void);
void Sec_Eng_GMAC_Enable_Link(void);
void Sec_Eng_GMAC_Disable_Link(void);
BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr,const uint8_t *in,uint32_t len,uint8_t *out);
void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask);
void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType);
void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType,intCallback_Type* cbFun);
BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType);
/*----------*/
void SEC_Eng_Turn_On_Sec_Ring(void);
void SEC_Eng_Turn_Off_Sec_Ring(void);
/*----------*/;
/*@} end of group SEC_ENG_Public_Functions */
/*@} end of group SEC_ENG */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SEC_ENG_H__ */

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drivers/bl602_driver/std_drv/inc/bl602_sf_cfg.h Normal file
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/**
******************************************************************************
* @file bl602_sf_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SF_CFG_H__
#define __BL602_SF_CFG_H__
#include "string.h"
#include "bl602_sflash.h"
#include "bl602_sf_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CFG
* @{
*/
/** @defgroup SF_CFG_Public_Types
* @{
*/
/*@} end of group SF_CFG_Public_Types */
/** @defgroup SF_CFG_Public_Constants
* @{
*/
/*@} end of group SF_CFG_Public_Constants */
/** @defgroup SF_CFG_Public_Macros
* @{
*/
/*Flash option 0*/
/*Flash CLK*/
#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_22
/*FLASH CS*/
#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_21
/*FLASH DATA*/
#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_20
#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_19
#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_18
#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_17
/*Flash option 1*/
/*Flash CLK*/
#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_22
/*FLASH CS*/
#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_21
/*FLASH DATA*/
#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_20
#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_0
#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_1
#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_2
#define BFLB_FLASH_CFG_DESWAP 1
#define BFLB_FLASH_CFG_EXT0_17_22 2
#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3
#define BFLB_FLASH_ID_VALID_FLAG 0x80000000
#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF
/*@} end of group SF_CFG_Public_Macros */
/** @defgroup SF_CFG_Public_Functions
* @{
*/
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg);
void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg,uint8_t restoreDefault);
void SF_Cfg_Restore_GPIO17_Fun(uint8_t fun);
uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault,
SPI_Flash_Cfg_Type * pFlashCfg);
void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin);
void SF_Cfg_Init_Internal_Flash_Gpio(void);
void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin);
/*@} end of group SF_CFG_Public_Functions */
/*@} end of group SF_CFG */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SF_CFG_H__ */

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/**
******************************************************************************
* @file bl602_sf_cfg_ext.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SF_CFG_EXT_H__
#define __BL602_SF_CFG_EXT_H__
#include "string.h"
#include "bl602_sflash.h"
#include "bl602_sf_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CFG_EXT
* @{
*/
/** @defgroup SF_CFG_EXT_Public_Types
* @{
*/
/*@} end of group SF_CFG_EXT_Public_Types */
/** @defgroup SF_CFG_EXT_Public_Constants
* @{
*/
/*@} end of group SF_CFG_EXT_Public_Constants */
/** @defgroup SF_CFG_EXT_Public_Macros
* @{
*/
/*@} end of group SF_CFG_EXT_Public_Macros */
/** @defgroup SF_CFG_EXT_Public_Functions
* @{
*/
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg);
uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash,uint32_t autoScan,uint32_t flashPinCfg,
uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg);
/*@} end of group SF_CFG_EXT_Public_Functions */
/*@} end of group SF_CFG_EXT */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SF_CFG_EXT_H__ */

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/**
******************************************************************************
* @file bl602_sf_ctrl.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SF_CTRL_H__
#define __BL602_SF_CTRL_H__
#include "sf_ctrl_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CTRL
* @{
*/
/** @defgroup SF_CTRL_Public_Types
* @{
*/
/**
* @brief Serial flash pad select type definition
*/
typedef enum {
SF_CTRL_EMBEDDED_SEL, /*!< Embedded flash select */
SF_CTRL_EXTERNAL_17TO22_SEL, /*!< External flash select gpio 17-22 */
SF_CTRL_EXTERNAL_0TO2_20TO22_SEL, /*!< External flash select gpio 0-2 and 20-22 */
}SF_Ctrl_Pad_Sel;
/**
* @brief Serial flash controller owner type definition
*/
typedef enum {
SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */
SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */
}SF_Ctrl_Owner_Type;
/**
* @brief Serial flash controller select clock type definition
*/
typedef enum {
SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */
SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */
}SF_Ctrl_Sahb_Type;
/**
* @brief Serial flash controller owner type definition
*/
typedef enum {
HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */
REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */
}SF_Ctrl_Ahb2sif_Type;
/**
* @brief Read and write type definition
*/
typedef enum {
SF_CTRL_READ, /*!< Serail flash read command flag */
SF_CTRL_WRITE, /*!< Serail flash write command flag */
}SF_Ctrl_RW_Type;
/**
* @brief Serail flash interface IO type definition
*/
typedef enum {
SF_CTRL_NIO_MODE, /*!< Normal IO mode define */
SF_CTRL_DO_MODE, /*!< Dual Output mode define */
SF_CTRL_QO_MODE, /*!< Quad Output mode define */
SF_CTRL_DIO_MODE, /*!< Dual IO mode define */
SF_CTRL_QIO_MODE, /*!< Quad IO mode define */
}SF_Ctrl_IO_Type;
/**
* @brief Serail flash controller interface mode type definition
*/
typedef enum {
SF_CTRL_SPI_MODE, /*!< SPI mode define */
SF_CTRL_QPI_MODE, /*!< QPI mode define */
}SF_Ctrl_Mode_Type;
/**
* @brief Serail flash controller command mode type definition
*/
typedef enum {
SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */
SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */
}SF_Ctrl_Cmd_Mode_Type;
/**
* @brief Serail flash controller address mode type definition
*/
typedef enum {
SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */
SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */
SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */
}SF_Ctrl_Addr_Mode_Type;
/**
* @brief Serail flash controller dummy mode type definition
*/
typedef enum {
SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */
SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */
SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */
}SF_Ctrl_Dmy_Mode_Type;
/**
* @brief Serail flash controller data mode type definition
*/
typedef enum {
SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */
SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */
SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */
}SF_Ctrl_Data_Mode_Type;
/**
* @brief Serail flash controller AES type definition
*/
typedef enum {
SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */
SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */
SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */
SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */
}SF_Ctrl_AES_Key_Type;
/**
* @brief Serail flash controller configuration structure type definition
*/
typedef struct {
SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */
SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */
SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */
uint8_t clkDelay; /*!< Clock count for read due to pad delay */
uint8_t clkInvert; /*!< Clock invert */
uint8_t rxClkInvert; /*!< RX clock invert */
uint8_t doDelay; /*!< Data out delay */
uint8_t diDelay; /*!< Data in delay */
uint8_t oeDelay; /*!< Output enable delay */
}SF_Ctrl_Cfg_Type;
/**
* @brief Serail flash command configuration structure type definition
*/
typedef struct {
uint8_t rwFlag; /*!< Read write flag */
SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */
SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */
uint8_t addrSize; /*!< Address size */
uint8_t dummyClks; /*!< Dummy clocks */
SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */
SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */
uint8_t rsv[1]; /*!< */
uint32_t nbData; /*!< Transfer number of bytes */
uint32_t cmdBuf[2]; /*!< Command buffer */
}SF_Ctrl_Cmd_Cfg_Type;
/*@} end of group SF_CTRL_Public_Types */
/** @defgroup SF_CTRL_Public_Constants
* @{
*/
/** @defgroup SF_CTRL_PAD_SEL
* @{
*/
#define IS_SF_CTRL_PAD_SEL(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \
((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \
((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL))
/** @defgroup SF_CTRL_OWNER_TYPE
* @{
*/
#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \
((type) == SF_CTRL_OWNER_IAHB))
/** @defgroup SF_CTRL_SAHB_TYPE
* @{
*/
#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \
((type) == SF_CTRL_FLASH_CLOCK))
/** @defgroup SF_CTRL_AHB2SIF_TYPE
* @{
*/
#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \
((type) == REMOVE_CLOCK_CONSTRAIN))
/** @defgroup SF_CTRL_RW_TYPE
* @{
*/
#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \
((type) == SF_CTRL_WRITE))
/** @defgroup SF_CTRL_IO_TYPE
* @{
*/
#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \
((type) == SF_CTRL_DO_MODE) || \
((type) == SF_CTRL_QO_MODE) || \
((type) == SF_CTRL_DIO_MODE) || \
((type) == SF_CTRL_QIO_MODE))
/** @defgroup SF_CTRL_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \
((type) == SF_CTRL_QPI_MODE))
/** @defgroup SF_CTRL_CMD_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \
((type) == SF_CTRL_CMD_4_LINES))
/** @defgroup SF_CTRL_ADDR_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \
((type) == SF_CTRL_ADDR_2_LINES) || \
((type) == SF_CTRL_ADDR_4_LINES))
/** @defgroup SF_CTRL_DMY_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \
((type) == SF_CTRL_DUMMY_2_LINES) || \
((type) == SF_CTRL_DUMMY_4_LINES))
/** @defgroup SF_CTRL_DATA_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \
((type) == SF_CTRL_DATA_2_LINES) || \
((type) == SF_CTRL_DATA_4_LINES))
/** @defgroup SF_CTRL_AES_KEY_TYPE
* @{
*/
#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \
((type) == SF_CTRL_AES_256BITS) || \
((type) == SF_CTRL_AES_192BITS) || \
((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY))
/*@} end of group SF_CTRL_Public_Constants */
/** @defgroup SF_CTRL_Public_Macros
* @{
*/
#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF
#define FLASH_CTRL_BUF_SIZE 256
/*@} end of group SF_CTRL_Public_Macros */
/** @defgroup SF_CTRL_Public_Functions
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
void SF_Ctrl_IRQHandler(void);
#endif
void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg);
void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner);
void SF_Ctrl_Disable(void);
void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel);
void SF_Ctrl_AES_Enable_BE(void);
void SF_Ctrl_AES_Enable_LE(void);
void SF_Ctrl_AES_Set_Region(uint8_t region,uint8_t enable, uint8_t hwKey,uint32_t startAddr,
uint32_t endAddr,
uint8_t locked);
void SF_Ctrl_AES_Set_Key(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_Key_BE(uint8_t region,uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_IV(uint8_t region,uint8_t *iv,uint32_t addrOffset);
void SF_Ctrl_AES_Set_IV_BE(uint8_t region,uint8_t *iv,uint32_t addrOffset);
void SF_Ctrl_AES_Enable(void);
void SF_Ctrl_AES_Disable(void);
void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset);
uint32_t SF_Ctrl_Get_Flash_Image_Offset(void);
void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType);
void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg);
void SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid);
void SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg,uint8_t cmdValid);
BL_Sts_Type SF_Ctrl_GetBusyState(void);
uint8_t SF_Ctrl_Is_AES_Enable(void);
uint8_t SF_Ctrl_Get_Clock_Delay(void);
void SF_Ctrl_Set_Clock_Delay(uint8_t delay);
/*@} end of group SF_CTRL_Public_Functions */
/*@} end of group SF_CTRL */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SF_CTRL_H__ */

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/**
******************************************************************************
* @file bl602_sflah.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SFLAH_H__
#define __BL602_SFLAH_H__
#include "bl602_common.h"
#include "bl602_sf_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SFLAH
* @{
*/
/** @defgroup SFLAH_Public_Types
* @{
*/
/**
* @brief Serial flash configuration structure type definition
*/
typedef struct {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */
uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
}__attribute__ ((packed)) SPI_Flash_Cfg_Type;
/*@} end of group SFLAH_Public_Types */
/** @defgroup SFLAH_Public_Constants
* @{
*/
/*@} end of group SFLAH_Public_Constants */
/** @defgroup SFLAH_Public_Macros
* @{
*/
#define BFLB_SPIFLASH_BLK32K_SIZE (32*1024)
#define BFLB_SPIFLASH_BLK64K_SIZE (64*1024)
#define BFLB_SPIFLASH_CMD_INVALID 0xff
/*@} end of group SFLAH_Public_Macros */
/** @defgroup SFLAH_Public_Functions
* @{
*/
void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg);
BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);
BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen);
BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg,uint8_t regIndex,uint8_t *regValue,uint8_t regLen);
BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t secNum);
BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum);
BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t blkNum);
BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg,uint32_t startaddr,uint32_t endaddr);
BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint32_t addr,uint8_t *data, uint32_t len);
void SFlash_GetUniqueId(uint8_t *data,uint8_t idLen);
void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg,uint8_t *data);
void SFlash_GetDeviceId(uint8_t *data);
void SFlash_Powerdown(void);
void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,
uint32_t len);
BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead);
BL_Err_Type SFlash_Cache_Enable_Set(uint8_t wayDisable);
BL_Err_Type SFlash_Cache_Flush(void);
BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,
uint8_t wayDisable);
void SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow,uint32_t *hitCountHigh);
uint32_t SFlash_Cache_Miss_Count_Get(void);
void SFlash_Cache_Read_Disable(void);
BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg,SF_Ctrl_IO_Type ioMode,uint8_t contRead,uint32_t addr,uint8_t *data,
uint32_t len);
BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t readRegCmd,uint8_t *regValue,
uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg,uint8_t writeRegCmd,uint8_t *regValue,
uint8_t regLen);
/*@} end of group SFLAH_Public_Functions */
/*@} end of group SFLAH */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SFLAH_H__ */

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/**
******************************************************************************
* @file bl602_sflah_ext.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SFLAH_EXT_H__
#define __BL602_SFLAH_EXT_H__
#include "bl602_sflash.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SFLAH_EXT
* @{
*/
/** @defgroup SFLAH_EXT_Public_Types
* @{
*/
/**
* @brief Serial flash security register configuration
*/
typedef struct {
uint8_t eraseCmd; /*!< Erase security register command */
uint8_t programCmd; /*!< Program security register command */
uint8_t readCmd; /*!< Read security register command */
uint8_t enterSecOptCmd; /*!< Enter security register option mode command */
uint8_t exitSecOptCmd; /*!< Exit security register option mode command */
uint8_t blockNum; /*!< Security register block number */
uint8_t *data; /*!< Data pointer to be program/read */
uint32_t addr; /*!< Start address to be program/read */
uint32_t len; /*!< Data length to be program/read */
}SFlash_Sec_Reg_Cfg;
/*@} end of group SFLAH_EXT_Public_Types */
/** @defgroup SFLAH_EXT_Public_Constants
* @{
*/
/*@} end of group SFLAH_EXT_Public_Constants */
/** @defgroup SFLAH_EXT_Public_Macros
* @{
*/
/*@} end of group SFLAH_EXT_Public_Macros */
/** @defgroup SFLAH_EXT_Public_Functions
* @{
*/
BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t flashContRead);
BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos);
BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg,
SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg);
/*@} end of group SFLAH_EXT_Public_Functions */
/*@} end of group SFLAH_EXT */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SFLAH_EXT_H__ */

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/**
******************************************************************************
* @file bl602_spi.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SPI_H__
#define __BL602_SPI_H__
#include "spi_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Public_Types
* @{
*/
/**
* @brief SPI No. type definition
*/
typedef enum {
SPI_ID_0, /*!< SPI0 port define */
SPI_ID_MAX, /*!< SPI MAX ID define */
}SPI_ID_Type;
/**
* @brief SPI byte inverse type definition
*/
typedef enum {
SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */
SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */
}SPI_BYTE_INVERSE_Type;
/**
* @brief SPI bit inverse type definition
*/
typedef enum {
SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */
SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */
}SPI_BIT_INVERSE_Type;
/**
* @brief SPI clock phase inverse type definition
*/
typedef enum {
SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */
SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */
}SPI_CLK_PHASE_INVERSE_Type;
/**
* @brief SPI clock polarity type definition
*/
typedef enum {
SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */
SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */
}SPI_CLK_POLARITY_Type;
/**
* @brief SPI frame size(also the valid width for each fifo entry) type definition
*/
typedef enum {
SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */
SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */
SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */
SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */
}SPI_FrameSize_Type;
/**
* @brief SPI work mode select type definition
*/
typedef enum {
SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */
SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */
}SPI_WORK_MODE_Type;
/**
* @brief SPI enable or disable timeout judgment definition
*/
typedef enum {
SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */
SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */
}SPI_Timeout_Type;
/**
* @brief SPI fifo overflow/underflow flag type definition
*/
typedef enum {
SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */
SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */
SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */
SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */
}SPI_FifoStatus_Type;
/**
* @brief SPI interrupt type definition
*/
typedef enum {
SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */
SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */
SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */
SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */
SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */
SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */
SPI_INT_ALL, /*!< All the interrupt */
}SPI_INT_Type;
/**
* @brief SPI configuration type definition
*/
typedef struct {
BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */
BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */
SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */
SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */
SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */
SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */
SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */
}SPI_CFG_Type;
/**
* @brief SPI configuration type definition
*/
typedef struct {
uint8_t startLen; /*!< Length of start condition */
uint8_t stopLen; /*!< Length of stop condition */
uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */
uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */
uint8_t intervalLen; /*!< Length of interval between frame */
}SPI_ClockCfg_Type;
/**
* @brief SPI DMA configuration type definition
*/
typedef struct {
uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */
uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */
BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */
BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */
}SPI_FifoCfg_Type;
/*@} end of group SPI_Public_Types */
/** @defgroup SPI_Public_Constants
* @{
*/
/** @defgroup SPI_ID_TYPE
* @{
*/
#define IS_SPI_ID_TYPE(type) (((type) == SPI_ID_0) || \
((type) == SPI_ID_MAX))
/** @defgroup SPI_BYTE_INVERSE_TYPE
* @{
*/
#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \
((type) == SPI_BYTE_INVERSE_BYTE3_FIRST))
/** @defgroup SPI_BIT_INVERSE_TYPE
* @{
*/
#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \
((type) == SPI_BIT_INVERSE_LSB_FIRST))
/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE
* @{
*/
#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \
((type) == SPI_CLK_PHASE_INVERSE_1))
/** @defgroup SPI_CLK_POLARITY_TYPE
* @{
*/
#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \
((type) == SPI_CLK_POLARITY_HIGH))
/** @defgroup SPI_FRAMESIZE_TYPE
* @{
*/
#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \
((type) == SPI_FRAME_SIZE_16) || \
((type) == SPI_FRAME_SIZE_24) || \
((type) == SPI_FRAME_SIZE_32))
/** @defgroup SPI_WORK_MODE_TYPE
* @{
*/
#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \
((type) == SPI_WORK_MODE_MASTER))
/** @defgroup SPI_TIMEOUT_TYPE
* @{
*/
#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \
((type) == SPI_TIMEOUT_ENABLE))
/** @defgroup SPI_FIFOSTATUS_TYPE
* @{
*/
#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \
((type) == SPI_FIFO_TX_UNDERFLOW) || \
((type) == SPI_FIFO_RX_OVERFLOW) || \
((type) == SPI_FIFO_RX_UNDERFLOW))
/** @defgroup SPI_INT_TYPE
* @{
*/
#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \
((type) == SPI_INT_TX_FIFO_REQ) || \
((type) == SPI_INT_RX_FIFO_REQ) || \
((type) == SPI_INT_SLAVE_TIMEOUT) || \
((type) == SPI_INT_SLAVE_UNDERRUN) || \
((type) == SPI_INT_FIFO_ERROR) || \
((type) == SPI_INT_ALL))
/*@} end of group SPI_Public_Constants */
/** @defgroup SPI_Public_Macros
* @{
*/
#define SPI_RX_FIFO_SIZE 4
#define SPI_TX_FIFO_SIZE 4
/*@} end of group SPI_Public_Macros */
/** @defgroup SPI_Public_Functions
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
void SPI_IRQHandler(void);
#endif
BL_Err_Type SPI_Init(SPI_ID_Type spiNo,SPI_CFG_Type *spiCfg);
BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo,SPI_ClockCfg_Type *clockCfg);
BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo,SPI_FifoCfg_Type *fifoCfg);
BL_Err_Type SPI_Enable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType);
BL_Err_Type SPI_Disable(SPI_ID_Type spiNo,SPI_WORK_MODE_Type modeType);
BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo,uint16_t value);
BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo,uint8_t cnt);
BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo,uint8_t startPoint,uint8_t stopPoint);
BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo);
BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo,SPI_INT_Type intType);
BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo,SPI_INT_Type intType,BL_Mask_Type intMask);
BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo,SPI_INT_Type intType,intCallback_Type *cbFun);
BL_Err_Type SPI_SendData(SPI_ID_Type spiNo,uint32_t data);
BL_Err_Type SPI_Send_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Send_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Send_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Send_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_8bits(SPI_ID_Type spiNo,uint8_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_16bits(SPI_ID_Type spiNo,uint16_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_24bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_Recv_32bits(SPI_ID_Type spiNo,uint32_t *buff,uint32_t length,SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_8bits(SPI_ID_Type spiNo,uint8_t *sendBuff,uint8_t *recvBuff,uint32_t length,
SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_16bits(SPI_ID_Type spiNo,uint16_t *sendBuff,uint16_t *recvBuff,uint32_t length,
SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_24bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *recvBuff,uint32_t length,
SPI_Timeout_Type timeoutType);
BL_Err_Type SPI_SendRecv_32bits(SPI_ID_Type spiNo,uint32_t *sendBuff,uint32_t *recvBuff,uint32_t length,
SPI_Timeout_Type timeoutType);
uint32_t SPI_ReceiveData(SPI_ID_Type spiNo);
uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo);
uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo);
BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo,SPI_INT_Type intType);
BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo,SPI_FifoStatus_Type fifoSts);
BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo);
BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo,uint32_t clk);
/*@} end of group SPI_Public_Functions */
/*@} end of group SPI */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SPI_H__ */

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/**
******************************************************************************
* @file bl602_timer.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_TIMER_H__
#define __BL602_TIMER_H__
#include "timer_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup TIMER
* @{
*/
/** @defgroup TIMER_Public_Types
* @{
*/
/**
* @brief TIMER channel type definition
*/
typedef enum {
TIMER_CH0, /*!< TIMER channel 0 port define */
TIMER_CH1, /*!< TIMER channel 1 port define */
TIMER_CH_MAX, /*!< */
}TIMER_Chan_Type;
/**
* @brief TIMER clock source type definition
*/
typedef enum {
TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */
TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */
TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */
TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */
}TIMER_ClkSrc_Type;
/**
* @brief TIMER match compare ID type definition
*/
typedef enum {
TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */
TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */
TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */
}TIMER_Comp_ID_Type;
/**
* @brief TIMER preload source type definition
*/
typedef enum {
TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */
TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */
TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */
TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */
}TIMER_PreLoad_Trig_Type;
/**
* @brief TIMER count register run mode type definition
*/
typedef enum {
TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */
TIMER_COUNT_FREERUN, /*!< TIMER count register free run */
}TIMER_CountMode_Type;
/**
* @brief TIMER interrupt type definition
*/
typedef enum {
TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */
TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */
TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */
TIMER_INT_ALL, /*!< */
}TIMER_INT_Type;
/**
* @brief Watchdog timer interrupt type definition
*/
typedef enum {
WDT_INT, /*!< Comparator 0 match cause interrupt */
WDT_INT_ALL, /*!< */
}WDT_INT_Type;
/**
* @brief TIMER configuration structure type definition
*/
typedef struct {
TIMER_Chan_Type timerCh; /*!< Timer channel */
TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */
TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */
TIMER_CountMode_Type countMode; /*!< Timer count mode */
uint8_t clockDivision; /*!< Timer clock divison value */
uint32_t matchVal0; /*!< Timer match 0 value 0 */
uint32_t matchVal1; /*!< Timer match 1 value 0 */
uint32_t matchVal2; /*!< Timer match 2 value 0 */
uint32_t preLoadVal; /*!< Timer preload value */
}TIMER_CFG_Type;
/*@} end of group TIMER_Public_Types */
/** @defgroup TIMER_Public_Constants
* @{
*/
/** @defgroup TIMER_CHAN_TYPE
* @{
*/
#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \
((type) == TIMER_CH1) || \
((type) == TIMER_CH_MAX))
/** @defgroup TIMER_CLKSRC_TYPE
* @{
*/
#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \
((type) == TIMER_CLKSRC_32K) || \
((type) == TIMER_CLKSRC_1K) || \
((type) == TIMER_CLKSRC_XTAL))
/** @defgroup TIMER_COMP_ID_TYPE
* @{
*/
#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \
((type) == TIMER_COMP_ID_1) || \
((type) == TIMER_COMP_ID_2))
/** @defgroup TIMER_PRELOAD_TRIG_TYPE
* @{
*/
#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \
((type) == TIMER_PRELOAD_TRIG_COMP0) || \
((type) == TIMER_PRELOAD_TRIG_COMP1) || \
((type) == TIMER_PRELOAD_TRIG_COMP2))
/** @defgroup TIMER_COUNTMODE_TYPE
* @{
*/
#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \
((type) == TIMER_COUNT_FREERUN))
/** @defgroup TIMER_INT_TYPE
* @{
*/
#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \
((type) == TIMER_INT_COMP_1) || \
((type) == TIMER_INT_COMP_2) || \
((type) == TIMER_INT_ALL))
/** @defgroup WDT_INT_TYPE
* @{
*/
#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \
((type) == WDT_INT_ALL))
/*@} end of group TIMER_Public_Constants */
/** @defgroup TIMER_Public_Macros
* @{
*/
#define WDT_ENABLE_ACCESS() {BL_WR_REG(TIMER_BASE,TIMER_WFAR,BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE,TIMER_WFAR),TIMER_WFAR,0xBABA));\
BL_WR_REG(TIMER_BASE,TIMER_WSAR,BL_SET_REG_BITS_VAL(BL_RD_REG(TIMER_BASE,TIMER_WSAR),TIMER_WSAR,0xEB10));}
/*@} end of group TIMER_Public_Macros */
/** @defgroup TIMER_Public_Functions
* @{
*/
/**
* @brief UART Functions
*/
#ifndef BFLB_USE_HAL_DRIVER
void TIMER_CH0_IRQHandler(void);
void TIMER_CH1_IRQHandler(void);
void TIMER_WDT_IRQHandler(void);
#endif
BL_Err_Type TIMER_Init(TIMER_CFG_Type* timerCfg);
uint32_t TIMER_GetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
void TIMER_SetCompValue(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val);
uint32_t TIMER_GetCounterValue(TIMER_Chan_Type timerCh);
BL_Sts_Type TIMER_GetMatchStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
uint32_t TIMER_GetPreloadValue(TIMER_Chan_Type timerCh);
void TIMER_SetPreloadValue(TIMER_Chan_Type timerCh,uint32_t val);
void TIMER_SetPreloadSrc(TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc);
void TIMER_SetCountMode(TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode);
void TIMER_ClearIntStatus(TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo);
void TIMER_Enable(TIMER_Chan_Type timerCh);
void TIMER_Disable(TIMER_Chan_Type timerCh);
void TIMER_IntMask(TIMER_Chan_Type timerCh,TIMER_INT_Type intType, BL_Mask_Type intMask);
void WDT_Set_Clock(TIMER_ClkSrc_Type clkSrc,uint8_t div);
uint16_t WDT_GetMatchValue(void);
void WDT_SetCompValue(uint16_t val);
uint16_t WDT_GetCounterValue(void);
void WDT_ResetCounterValue(void);
BL_Sts_Type WDT_GetResetStatus(void);
void WDT_ClearResetStatus(void);
void WDT_Enable(void);
void WDT_Disable(void);
void WDT_IntMask(WDT_INT_Type intType, BL_Mask_Type intMask);
void Timer_Int_Callback_Install(TIMER_Chan_Type timerChan,TIMER_INT_Type intType,intCallback_Type* cbFun);
void WDT_Int_Callback_Install(WDT_INT_Type wdtInt,intCallback_Type* cbFun);
/*@} end of group TIMER_Public_Functions */
/*@} end of group TIMER */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_TIMER_H__ */

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/**
******************************************************************************
* @file bl602_tzc_sec.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_TZC_SEC_H__
#define __BL602_TZC_SEC_H__
#include "tzc_sec_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup TZC_SEC
* @{
*/
/** @defgroup TZC_SEC_Public_Types
* @{
*/
/*@} end of group TZC_SEC_Public_Types */
/** @defgroup TZC_SEC_Public_Constants
* @{
*/
/*@} end of group TZC_SEC_Public_Constants */
/** @defgroup TZC_SEC_Public_Macros
* @{
*/
/*@} end of group TZC_SEC_Public_Macros */
/** @defgroup TZC_SEC_Public_Functions
* @{
*/
void TZC_Sboot_Set(uint8_t Val);
void TZC_Set_Rom0_R0_Protect(uint32_t start,uint32_t end);
/*@} end of group TZC_SEC_Public_Functions */
/*@} end of group TZC_SEC */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_TZC_SEC_H__ */

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/**
******************************************************************************
* @file bl602_uart.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_UART_H__
#define __BL602_UART_H__
#include "uart_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/** @defgroup UART_Public_Types
* @{
*/
/**
* @brief UART port type definition
*/
typedef enum {
UART0_ID, /*!< UART0 port define */
UART1_ID, /*!< UART1 port define */
UART_ID_MAX, /*!< UART MAX ID define */
}UART_ID_Type;
/**
* @brief UART direction type definition
*/
typedef enum {
UART_TX, /*!< UART TX Direction */
UART_RX, /*!< UART RX Direction */
UART_TXRX, /*!< UART TX and RX Direction */
}UART_Direction_Type;
/**
* @brief UART parity type definition
*/
typedef enum {
UART_PARITY_NONE, /*!< UART parity none define */
UART_PARITY_ODD, /*!< UART parity odd define */
UART_PARITY_EVEN, /*!< UART parity even define */
}UART_Parity_Type;
/**
* @brief UART data bits type definiton
*/
typedef enum {
UART_DATABITS_5, /*!< UART data bits length:5 bits */
UART_DATABITS_6, /*!< UART data bits length:6 bits */
UART_DATABITS_7, /*!< UART data bits length:7 bits */
UART_DATABITS_8, /*!< UART data bits length:8 bits */
}UART_DataBits_Type;
/**
* @brief UART stop bits type definiton
*/
typedef enum {
UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */
UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */
UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */
}UART_StopBits_Type;
/**
* @brief UART each data byte is send out LSB-first or MSB-first type definiton
*/
typedef enum {
UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */
UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */
}UART_ByteBitInverse_Type;
/**
* @brief UART auto baudrate detection using codeword 0x55 or start bit definiton
*/
typedef enum {
UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */
UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */
}UART_AutoBaudDetection_Type;
/**
* @brief UART interrupt type definition
*/
typedef enum {
UART_INT_TX_END, /*!< UART tx transfer end interrupt */
UART_INT_RX_END, /*!< UART rx transfer end interrupt */
UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */
UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */
UART_INT_RTO, /*!< UART rx time-out interrupt */
UART_INT_PCE, /*!< UART rx parity check error interrupt */
UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */
UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */
UART_INT_ALL, /*!< All the interrupt */
}UART_INT_Type;
/**
* @brief UART overflow or underflow type definition
*/
typedef enum {
UART_TX_OVERFLOW, /*!< UART tx fifo overflow */
UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */
UART_RX_OVERFLOW, /*!< UART rx fifo overflow */
UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */
}UART_Overflow_Type;
/**
* @brief UART configuration structure type definition
*/
typedef struct {
uint32_t uartClk; /*!< Uart module clock */
uint32_t baudRate; /*!< Uart baudrate */
UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */
UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */
UART_Parity_Type parity; /*!< Uart parity check type */
BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */
BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */
BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */
UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */
}UART_CFG_Type;
/**
* @brief UART FIFO configuration structure type definition
*/
typedef struct {
uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */
uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */
BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */
BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */
}UART_FifoCfg_Type;
/**
* @brief UART infrared configuration structure type definition
*/
typedef struct {
BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */
BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */
BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */
BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */
uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */
uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */
uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */
}UART_IrCfg_Type;
/*@} end of group UART_Public_Types */
/** @defgroup UART_Public_Constants
* @{
*/
/** @defgroup UART_ID_TYPE
* @{
*/
#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \
((type) == UART1_ID) || \
((type) == UART_ID_MAX))
/** @defgroup UART_DIRECTION_TYPE
* @{
*/
#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \
((type) == UART_RX) || \
((type) == UART_TXRX))
/** @defgroup UART_PARITY_TYPE
* @{
*/
#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \
((type) == UART_PARITY_ODD) || \
((type) == UART_PARITY_EVEN))
/** @defgroup UART_DATABITS_TYPE
* @{
*/
#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \
((type) == UART_DATABITS_6) || \
((type) == UART_DATABITS_7) || \
((type) == UART_DATABITS_8))
/** @defgroup UART_STOPBITS_TYPE
* @{
*/
#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \
((type) == UART_STOPBITS_1_5) || \
((type) == UART_STOPBITS_2))
/** @defgroup UART_BYTEBITINVERSE_TYPE
* @{
*/
#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \
((type) == UART_MSB_FIRST))
/** @defgroup UART_AUTOBAUDDETECTION_TYPE
* @{
*/
#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \
((type) == UART_AUTOBAUD_STARTBIT))
/** @defgroup UART_INT_TYPE
* @{
*/
#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \
((type) == UART_INT_RX_END) || \
((type) == UART_INT_TX_FIFO_REQ) || \
((type) == UART_INT_RX_FIFO_REQ) || \
((type) == UART_INT_RTO) || \
((type) == UART_INT_PCE) || \
((type) == UART_INT_TX_FER) || \
((type) == UART_INT_RX_FER) || \
((type) == UART_INT_ALL))
/** @defgroup UART_OVERFLOW_TYPE
* @{
*/
#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \
((type) == UART_TX_UNDERFLOW) || \
((type) == UART_RX_OVERFLOW) || \
((type) == UART_RX_UNDERFLOW))
/*@} end of group UART_Public_Constants */
/** @defgroup UART_Public_Macros
* @{
*/
#define UART_RX_FIFO_SIZE 32
#define UART_TX_FIFO_SIZE 32
#define UART_DEFAULT_RECV_TIMEOUT 80
/*@} end of group UART_Public_Macros */
/** @defgroup UART_Public_Functions
* @{
*/
/**
* @brief UART Functions
*/
#if 1//(!defined BFLB_USE_HAL_DRIVER)||(defined BFLB_EFLASH_LOADER)
void UART0_IRQHandler(void);
void UART1_IRQHandler(void);
#endif
BL_Err_Type UART_Init(UART_ID_Type uartId,UART_CFG_Type* uartCfg);
BL_Err_Type UART_DeInit(UART_ID_Type uartId);
BL_Err_Type UART_FifoConfig(UART_ID_Type uartId,UART_FifoCfg_Type* fifoCfg);
BL_Err_Type UART_IrConfig(UART_ID_Type uartId,UART_IrCfg_Type* irCfg);
BL_Err_Type UART_Enable(UART_ID_Type uartId,UART_Direction_Type direct);
BL_Err_Type UART_Disable(UART_ID_Type uartId,UART_Direction_Type direct);
BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId,uint16_t length);
BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId,uint16_t length);
BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId,uint8_t time);
BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId,uint8_t deglitchCnt);
BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId,UART_AutoBaudDetection_Type autoBaudDet);
BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId,BL_Fun_Type txFreeRun);
BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId,BL_Fun_Type autoBaud);
BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId);
BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId);
BL_Err_Type UART_IntMask(UART_ID_Type uartId,UART_INT_Type intType,BL_Mask_Type intMask);
BL_Err_Type UART_IntClear(UART_ID_Type uartId,UART_INT_Type intType);
BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId,UART_INT_Type intType,intCallback_Type* cbFun);
BL_Err_Type UART_SendData(UART_ID_Type uartId,uint8_t* data,uint32_t len);
BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId,uint8_t* data,uint32_t len);
uint32_t UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen);
uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId,UART_AutoBaudDetection_Type autoBaudDet);
uint8_t UART_GetTxFifoCount(UART_ID_Type uartId);
uint8_t UART_GetRxFifoCount(UART_ID_Type uartId);
BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId,UART_INT_Type intType);
BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId);
BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId);
BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId,UART_Overflow_Type overflow);
uint32_t UART_GetBaudrate(UART_ID_Type uartId);
/*@} end of group UART_Public_Functions */
/*@} end of group UART */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_UART_H__ */

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/**
******************************************************************************
* @file bl602_xip_sflash.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_XIP_SFLASH_H__
#define __BL602_XIP_SFLASH_H__
#include "bl602_common.h"
#include "bl602_sflash.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup XIP_SFLASH
* @{
*/
/** @defgroup XIP_SFLASH_Public_Types
* @{
*/
/*@} end of group XIP_SFLASH_Public_Types */
/** @defgroup XIP_SFLASH_Public_Constants
* @{
*/
/*@} end of group XIP_SFLASH_Public_Constants */
/** @defgroup XIP_SFLASH_Public_Macros
* @{
*/
/*@} end of group XIP_SFLASH_Public_Macros */
/** @defgroup XIP_SFLASH_Public_Functions
* @{
*/
BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset);
BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset);
BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,uint32_t endaddr);
BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data,
uint32_t len);
BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data,uint32_t len);
BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data);
BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data);
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,uint8_t idLen);
BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,uint8_t *data,uint32_t len);
int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len);
int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len);
int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len);
void XIP_SFlash_Opt_Enter(uint8_t *aesEnable);
void XIP_SFlash_Opt_Exit(uint8_t aesEnable);
/*@} end of group XIP_SFLASH_Public_Functions */
/*@} end of group XIP_SFLASH */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_XIP_SFLASH_H__ */

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/**
******************************************************************************
* @file bl602_xip_sflash_ext.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_XIP_SFLASH_EXT_H__
#define __BL602_XIP_SFLASH_EXT_H__
#include "bl602_common.h"
#include "bl602_sflash.h"
#include "bl602_xip_sflash.h"
#include "bl602_sf_cfg.h"
#include "bl602_sf_cfg_ext.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup XIP_SFLASH
* @{
*/
/** @defgroup XIP_SFLASH_EXT_Public_Types
* @{
*/
/*@} end of group XIP_SFLASH_EXT_Public_Types */
/** @defgroup XIP_SFLASH_EXT_Public_Constants
* @{
*/
/*@} end of group XIP_SFLASH_EXT_Public_Constants */
/** @defgroup XIP_SFLASH_EXT_Public_Macros
* @{
*/
/*@} end of group XIP_SFLASH_EXT_Public_Macros */
/** @defgroup XIP_SFLASH_EXT_Public_Functions
* @{
*/
BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg);
int XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len);
int XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len);
int XIP_SFlash_Erase(uint32_t addr, int len);
/*@} end of group XIP_SFLASH_EXT_Public_Functions */
/*@} end of group XIP_SFLASH */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_XIP_SFLASH_EXT_H__ */

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/**
******************************************************************************
* @file bl602_acomp.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl602_acomp.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup ACOMP
* @{
*/
/** @defgroup ACOMP_Private_Macros
* @{
*/
/*@} end of group ACOMP_Private_Macros */
/** @defgroup ACOMP_Private_Types
* @{
*/
/*@} end of group ACOMP_Private_Types */
/** @defgroup ACOMP_Private_Variables
* @{
*/
/*@} end of group ACOMP_Private_Variables */
/** @defgroup ACOMP_Global_Variables
* @{
*/
/*@} end of group ACOMP_Global_Variables */
/** @defgroup ACOMP_Private_Fun_Declaration
* @{
*/
/*@} end of group ACOMP_Private_Fun_Declaration */
/** @defgroup ACOMP_Private_Functions
* @{
*/
/*@} end of group ACOMP_Private_Functions */
/** @defgroup ACOMP_Public_Functions
* @{
*/
/****************************************************************************//**
* @brief Analog compare init
*
* @param acompNo: Compare ID
* @param cfg: Compare consideration pointer
*
* @return None
*
*******************************************************************************/
void AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo,AON_ACOMP_CFG_Type *cfg)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
if(acompNo==AON_ACOMP0_ID){
/* Disable ACOMP first */
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP0_CTRL);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_ACOMP0_EN);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal);
/* Set ACOMP config */
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_MUXEN,cfg->muxEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_POS_SEL,cfg->posChanSel);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_NEG_SEL,cfg->negChanSel);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_LEVEL_SEL,cfg->levelFactor);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_BIAS_PROG,cfg->biasProg);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_HYST_SELP,cfg->hysteresisPosVolt);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP0_HYST_SELN,cfg->hysteresisNegVolt);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal);
}else{
/* Disable ACOMP first */
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP1_CTRL);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_ACOMP1_EN);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal);
/* Set ACOMP config */
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_MUXEN,cfg->muxEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_POS_SEL,cfg->posChanSel);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_NEG_SEL,cfg->negChanSel);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_LEVEL_SEL,cfg->levelFactor);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_BIAS_PROG,cfg->biasProg);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_HYST_SELP,cfg->hysteresisPosVolt);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_ACOMP1_HYST_SELN,cfg->hysteresisNegVolt);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal);
}
}
/****************************************************************************//**
* @brief Analog compare enable
*
* @param acompNo: Compare ID
*
* @return None
*
*******************************************************************************/
void AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
if(acompNo==AON_ACOMP0_ID){
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP0_CTRL);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_ACOMP0_EN);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP0_CTRL,tmpVal);
}else{
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP1_CTRL);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_ACOMP1_EN);
tmpVal=BL_WR_REG(AON_BASE,AON_ACOMP1_CTRL,tmpVal);
}
}
/****************************************************************************//**
* @brief Analog compare enable
*
* @param acompNo: Compare ID
*
* @return SET or RESET
*
*******************************************************************************/
BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo)
{
uint32_t tmpVal = 0;
/* Check the parameters */
CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo));
tmpVal=BL_RD_REG(AON_BASE,AON_ACOMP_CTRL);
/* Disable ACOMP first */
if(acompNo==AON_ACOMP0_ID){
if(BL_IS_REG_BIT_SET(tmpVal,AON_ACOMP0_OUT_RAW)){
return SET;
}else{
return RESET;
}
}else{
if(BL_IS_REG_BIT_SET(tmpVal,AON_ACOMP1_OUT_RAW)){
return SET;
}else{
return RESET;
}
}
}
/*@} end of group ACOMP_Public_Functions */
/*@} end of group ACOMP */
/*@} end of group BL602_Peripheral_Driver */

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drivers/bl602_driver/std_drv/src/bl602_adc.c Normal file
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drivers/bl602_driver/std_drv/src/bl602_aon.c Normal file
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/**
******************************************************************************
* @file bl602_aon.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl602_aon.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup AON
* @{
*/
/** @defgroup AON_Private_Macros
* @{
*/
#define AON_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();}
/*@} end of group AON_Private_Macros */
/** @defgroup AON_Private_Types
* @{
*/
/*@} end of group AON_Private_Types */
/** @defgroup AON_Private_Variables
* @{
*/
/*@} end of group AON_Private_Variables */
/** @defgroup AON_Global_Variables
* @{
*/
/*@} end of group AON_Global_Variables */
/** @defgroup AON_Private_Fun_Declaration
* @{
*/
/*@} end of group AON_Private_Fun_Declaration */
/** @defgroup AON_Private_Functions
* @{
*/
/*@} end of group AON_Private_Functions */
/** @defgroup AON_Public_Functions
* @{
*/
/****************************************************************************//**
* @brief Power on MXX band gap
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
{
uint32_t tmpVal = 0;
/* Power up RF for PLL to work */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_MBG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power off MXX band gap
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
{
uint32_t tmpVal = 0;
/* Power OFF */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_MBG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power on XTAL
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
{
uint32_t tmpVal = 0;
uint32_t timeOut=0;
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_XTAL_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_XTAL_BUF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
/* Polling for ready */
do{
BL602_Delay_US(10);
timeOut++;
tmpVal=BL_RD_REG(AON_BASE,AON_TSEN);
}while(!BL_IS_REG_BIT_SET(tmpVal,AON_XTAL_RDY)&&timeOut<120);
if(timeOut>=120){
return TIMEOUT;
}
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Set XTAL cap code
*
* @param capIn: Cap code in
* @param capOut: Cap code out
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn,uint8_t capOut)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_XTAL_CFG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_IN_AON,capIn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_OUT_AON,capOut);
BL_WR_REG(AON_BASE,AON_XTAL_CFG,tmpVal);
BL602_Delay_US(100);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Get XTAL cap code
*
* @param None
*
* @return Cap code
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_XTAL_CFG);
return BL_GET_REG_BITS_VAL(tmpVal,AON_XTAL_CAPCODE_IN_AON);
}
#endif
/****************************************************************************//**
* @brief Power off XTAL
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_XTAL_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_XTAL_BUF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power on bandgap system
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
{
uint32_t tmpVal = 0;
/* power up RF for PLL to work */
tmpVal=BL_RD_REG(AON_BASE,AON_BG_SYS_TOP);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_BG_SYS_AON);
BL_WR_REG(AON_BASE,AON_BG_SYS_TOP,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power off bandgap system
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
{
uint32_t tmpVal = 0;
/* power up RF for PLL to work */
tmpVal=BL_RD_REG(AON_BASE,AON_BG_SYS_TOP);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_BG_SYS_AON);
BL_WR_REG(AON_BASE,AON_BG_SYS_TOP,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power on LDO11
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO11SOC_AON);
BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power off LDO11
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO11SOC_AON);
BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal);
BL602_Delay_US(55);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power on LDO15_RF
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
{
uint32_t tmpVal = 0;
/* ldo15rf power on */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO15RF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(90);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power off LDO15_RF
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
{
uint32_t tmpVal = 0;
/* ldo15rf power off */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO15RF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief power on source follow regular
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
{
uint32_t tmpVal = 0;
/* power on sfreg */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_SFREG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(10);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief power off source follow regular
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
{
uint32_t tmpVal = 0;
/* power off sfreg */
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_SFREG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power off the power can be shut down in PDS0
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
{
uint32_t tmpVal = 0;
/* power off sfreg */
tmpVal=BL_RD_REG(AON_BASE,AON_MISC);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_SW_WB_EN_AON);
BL_WR_REG(AON_BASE,AON_MISC,tmpVal);
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_SFREG_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO15RF_AON);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_MBG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
/* gating Clock */
tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
tmpVal=tmpVal&(~(1<<6));
tmpVal=tmpVal&(~(1<<7));
BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power on the power powered down in PDS0
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
{
uint32_t tmpVal = 0;
tmpVal=BL_RD_REG(AON_BASE,AON_RF_TOP_AON);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_MBG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(20);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_LDO15RF_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(60);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_PU_SFREG_AON);
BL_WR_REG(AON_BASE,AON_RF_TOP_AON,tmpVal);
BL602_Delay_US(20);
/* power on wb */
tmpVal=BL_RD_REG(AON_BASE,AON_MISC);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_SW_WB_EN_AON);
BL_WR_REG(AON_BASE,AON_MISC,tmpVal);
/* ungating Clock */
tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
tmpVal=tmpVal|((1<<6));
tmpVal=tmpVal|((1<<7));
BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
return SUCCESS;
}
#endif
/****************************************************************************//**
* @brief Power on the power powered down in PDS0
*
* @param delay: None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
{
uint32_t tmpVal = 0;
CHECK_PARAM((delay<=0x3));
/* config ldo11soc_sstart_delay_aon */
tmpVal=BL_RD_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_LDO11SOC_SSTART_DELAY_AON,delay);
BL_WR_REG(AON_BASE,AON_LDO11SOC_AND_DCTEST,tmpVal);
return SUCCESS;
}
/*@} end of group AON_Public_Functions */
/*@} end of group AON */
/*@} end of group BL602_Peripheral_Driver */

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drivers/bl602_driver/std_drv/src/bl602_common.c Normal file
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#include "l1c_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Periph_Driver
* @{
*/
/** @defgroup DRIVER_COMMON DRIVER_COMMON
* @brief Digger driver common functions
* @{
*/
/** @defgroup DRIVER_Private_Type
* @{
*/
/*@} end of group DRIVER_Private_Type*/
/** @defgroup DRIVER_Private_Defines
* @{
*/
/*@} end of group DRIVER_Private_Defines */
/** @defgroup DRIVER_Private_Variables
* @{
*/
pFunc __Interrupt_Handlers[IRQn_LAST]={0};
/*@} end of group DRIVER_Private_Variables */
/** @defgroup DRIVER_Global_Variables
* @{
*/
/*@} end of group DRIVER_Global_Variables */
/** @defgroup DRIVER_Private_FunctionDeclaration
* @{
*/
/*@} end of group DRIVER_Private_FunctionDeclaration */
/** @defgroup DRIVER_Private_Functions
* @{
*/
/*@} end of group DRIVER_Private_Functions */
/** @defgroup DRIVER_Public_Functions
* @{
*/
void Trap_Handler(void){
unsigned long cause;
unsigned long epc;
unsigned long tval;
MSG("Trap_Handler\r\n");
cause = read_csr(mcause);
MSG("mcause=%08x\r\n",(uint32_t)cause);
epc=read_csr(mepc);
MSG("mepc:%08x\r\n",(uint32_t)epc);
tval=read_csr(mtval);
MSG("mtval:%08x\r\n",(uint32_t)tval);
cause=(cause&0x3ff);
switch(cause){
case 1:
MSG("Instruction access fault\r\n");
break;
case 2:
MSG("Illegal instruction\r\n");
break;
case 3:
MSG("Breakpoint\r\n");
break;
case 4:
MSG("Load address misaligned\r\n");
break;
case 5:
MSG("Load access fault\r\n");
break;
case 6:
MSG("Store/AMO address misaligned\r\n");
break;
case 7:
MSG("Store/AMO access fault\r\n");
break;
case 8:
MSG("Environment call from U-mode\r\n");
epc+=4;
write_csr(mepc,epc);
break;
case 9:
MSG("Environment call from M-mode\r\n");
epc+=4;
write_csr(mepc,epc);
break;
default:
MSG("Cause num=%d\r\n",(uint32_t)cause);
epc+=4;
write_csr(mepc,epc);
break;
}
while(1);
}
void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun)
{
if(irq<IRQn_LAST){
__Interrupt_Handlers[irq]=interruptFun;
}
}
void Interrupt_Handler(void)
{
pFunc interruptFun;
uint32_t num=0;
volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL;
/* Store a few register values that might be useful when determining why this
function was called. */
__asm volatile( "csrr %0, mepc" : "=r"( ulMEPC ) );
__asm volatile( "csrr %0, mcause" : "=r"( ulMCAUSE ) );
if((ulMCAUSE&0x80000000)==0){
/*Exception*/
MSG("Exception should not be here\r\n");
}else{
num=ulMCAUSE&0x3FF;
if(num<IRQn_LAST){
interruptFun=__Interrupt_Handlers[num];
if(NULL!=interruptFun){
interruptFun();
}else{
MSG("Interrupt num:%d IRQHandler not installed\r\n",(unsigned int)num);
if(num>=IRQ_NUM_BASE){
MSG("Peripheral Interrupt num:%d \r\n",(unsigned int)num-IRQ_NUM_BASE);
}
while(1);
}
}else{
MSG("Unexpected interrupt num:%d\r\n",(unsigned int)num);
}
}
}
void FreeRTOS_Interrupt_Handler(void)
{
Interrupt_Handler();
}
/****************************************************************************//**
* @brief delay us
*
* @param[in] core: systemcoreclock
*
* @param[in] cnt: delay cnt us
*
* @return none
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
#ifdef ARCH_ARM
#ifndef __GNUC__
__WEAK
__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt)
{
lsrs r0,#0x10
muls r0,r1,r0
mov r2,r0
lsrs r2,#0x04
lsrs r2,#0x03
cmp r2,#0x01
beq end
cmp r2,#0x00
beq end
loop
mov r0,r0
mov r0,r0
mov r0,r0
mov r0,r0
mov r0,r0
subs r2,r2,#0x01
cmp r2,#0x00
bne loop
end
bx lr
}
#else
__WEAK
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt)
{
__asm__ __volatile__(
"lsr r0,#0x10\n\t"
"mul r0,r1,r0\n\t"
"mov r2,r0\n\t"
"lsr r2,#0x04\n\t"
"lsr r2,#0x03\n\t"
"cmp r2,#0x01\n\t"
"beq end\n\t"
"cmp r2,#0x00\n\t"
"beq end\n"
"loop :"
"mov r0,r0\n\t"
"mov r0,r0\n\t"
"mov r0,r0\n\t"
"mov r0,r0\n\t"
"mov r0,r0\n\t"
"sub r2,r2,#0x01\n\t"
"cmp r2,#0x00\n\t"
"bne loop\n"
"end :"
"mov r0,r0\n\t"
);
}
#endif
#endif
#ifdef ARCH_RISCV
__WEAK
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core,uint32_t cnt)
{
uint32_t codeAddress = 0;
uint32_t divVal = 40;
codeAddress = (uint32_t)&ASM_Delay_Us;
/* 1M=100K*10, so multiple is 10 */
/* loop function take 4 instructions, so instructionNum is 4 */
/* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
/* divVal = multiple*instructionNum*irom2TAccess */
if(((codeAddress&(0xF<<24))>>24)==0x01){
/* IROM space */
if(BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE,L1C_CONFIG),L1C_IROM_2T_ACCESS)){
/* instruction 2T */
divVal = 80;
}
}
__asm__ __volatile__(
".align 4\n\t"
"lw a4,%1\n\t"
"lui a5,0x18\n\t"
"addi a5,a5,1696\n\t"
"divu a5,a4,a5\n\t"
"sw a5,%1\n\t"
"lw a4,%1\n\t"
"lw a5,%0\n\t"
"mul a5,a4,a5\n\t"
"sw a5,%1\n\t"
"lw a4,%1\n\t"
"lw a5,%2\n\t"
"divu a5,a4,a5\n\t"
"sw a5,%1\n\t"
"lw a5,%1\n\t"
"li a4,0x1\n\t"
"beq a5,zero,end\n\t"
"beq a5,a4,end\n\t"
"nop\n\t"
"nop\n\t"
".align 4\n\t"
"loop :\n"
"addi a4,a5,-1\n\t"
"mv a5,a4\n\t"
"bnez a5,loop\n\t"
"nop\n\t"
"end :\n\t"
"nop\n"
: /* output */
:"m"(cnt),"m"(core),"m"(divVal) /* input */
:"t1","a4","a5" /* destruct description */
);
}
#endif
/****************************************************************************//**
* @brief delay us
*
* @param[in] cnt: delay cnt us
*
* @return none
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt)
{
ASM_Delay_Us(SystemCoreClockGet(),cnt);
}
/****************************************************************************//**
* @brief delay ms
*
* @param[in] cnt: delay cnt ms
*
* @return none
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt)
{
uint32_t i = 0;
uint32_t count = 0;
if(cnt>=1024){
/* delay (n*1024) ms */
count = 1024;
for(i=0;i<(cnt/1024);i++){
BL602_Delay_US(1024*1000);
}
}
if(cnt&0x3FF){
/* delay (1-1023)ms */
count = cnt & 0x3FF;
BL602_Delay_US(count*1000);
}
//BL602_Delay_US((count<<10)-(count<<4)-(count<<3));
}
#endif
/*@} end of group DRIVER_Public_Functions */
/*@} end of group DRIVER_COMMON */
/*@} end of group BL602_Periph_Driver */

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@ -0,0 +1,527 @@
/**
******************************************************************************
* @file bl602_dac.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl602_dac.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_Private_Macros
* @{
*/
#define GPIP_CLK_SET_DUMMY_WAIT {__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();}
/*@} end of group DAC_Private_Macros */
/** @defgroup DAC_Private_Types
* @{
*/
/*@} end of group DAC_Private_Types */
/** @defgroup DAC_Private_Variables
* @{
*/
/*@} end of group DAC_Private_Variables */
/** @defgroup DAC_Global_Variables
* @{
*/
/*@} end of group DAC_Global_Variables */
/** @defgroup DAC_Private_Fun_Declaration
* @{
*/
/*@} end of group DAC_Private_Fun_Declaration */
/** @defgroup DAC_Private_Functions
* @{
*/
/*@} end of group DAC_Private_Functions */
/** @defgroup DAC_Public_Functions
* @{
*/
/****************************************************************************//**
* @brief DAC initialization
*
* @param cfg: DAC configuration pointer
*
* @return None
*
*******************************************************************************/
void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
/* Set DAC config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_REF_SEL,cfg->refSel);
if(ENABLE==cfg->resetChanA){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
}
if(ENABLE==cfg->resetChanB){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
}
/* Clear reset */
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
}
/****************************************************************************//**
* @brief DAC channel A initialization
*
* @param cfg: DAC channel configuration pointer
*
* @return None
*
*******************************************************************************/
void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));
/* Set channel A config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_ACTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_OUTMUX,cfg->outMux);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOA_EN,cfg->outputEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_EN,cfg->chanEn);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_ACTRL,tmpVal);
}
/****************************************************************************//**
* @brief DAC channel B initialization
*
* @param cfg: DAC channel configuration pointer
*
* @return None
*
*******************************************************************************/
void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg)
{
uint32_t tmpVal;
/* Check the parameters */
CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux));
/* Set channel A config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_BCTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_OUTMUX,cfg->outMux);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOB_EN,cfg->outputEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_EN,cfg->chanEn);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_BCTRL,tmpVal);
}
/****************************************************************************//**
* @brief Select DAC channel B source
*
* @param src: DAC channel B source selection type
*
* @return None
*
*******************************************************************************/
void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_B_SEL,src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Select DAC channel A source
*
* @param src: DAC channel A source selection type
*
* @return None
*
*******************************************************************************/
void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_A_SEL,src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Select DAC mode
*
* @param mod: DAC mode selection type
*
* @return None
*
*******************************************************************************/
void GPIP_Set_DAC_Mod_SEL(GPIP_DAC_MOD_Type mod)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(mod));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_MODE,mod);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Enable DAC channel B
*
* @param None
*
* @return None
*
*******************************************************************************/
void GPIP_DAC_ChanB_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_EN2);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Disable DAC channel B
*
* @param None
*
* @return None
*
*******************************************************************************/
void GPIP_DAC_ChanB_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_EN2);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Enable DAC channel A
*
* @param None
*
* @return None
*
*******************************************************************************/
void GPIP_DAC_ChanA_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Disable DAC channel A
*
* @param None
*
* @return None
*
*******************************************************************************/
void GPIP_DAC_ChanA_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Select DAC DMA TX format
*
* @param fmt: DAC DMA TX format selection type
*
* @return None
*
*******************************************************************************/
void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt));
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_FORMAT,fmt);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Enable DAC DMA TX
*
* @param None
*
* @return None
*
*******************************************************************************/
void GPIP_Set_DAC_DMA_TX_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_SET_REG_BIT(tmpVal,GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Disable DAC DMA TX
*
* @param None
*
* @return None
*
*******************************************************************************/
void GPIP_Set_DAC_DMA_TX_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_CLR_REG_BIT(tmpVal,GPIP_GPDAC_DMA_TX_EN);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
}
/****************************************************************************//**
* @brief Disable DAC DMA TX
*
* @param data: The data to be send
*
* @return None
*
*******************************************************************************/
void GPIP_DAC_DMA_WriteData(uint32_t data)
{
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_WDATA,data);
}
/****************************************************************************//**
* @brief AON and GPIP DAC config
*
* @param cfg: AON and GPIP DAC configuration
*
* @return config success or not
*
*******************************************************************************/
BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type* cfg)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel));
CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->mod));
CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt));
/* AON Set DAC config */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_CTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_REF_SEL,cfg->refSel);
if(ENABLE==cfg->resetChanA){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
}
if(ENABLE==cfg->resetChanB){
tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
__NOP();
__NOP();
__NOP();
__NOP();
}
/* AON Clear reset */
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACA_RSTN_ANA);
tmpVal=BL_SET_REG_BIT(tmpVal,GLB_GPDACB_RSTN_ANA);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_CTRL,tmpVal);
if(cfg->dmaEn == DISABLE && cfg->mod == GPIP_DAC_MOD_512K){
return ERROR;/*512K mode only used in DMA mode*/
}
/* GPIP Set DAC config */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_MODE,cfg->mod);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* GPIP Set DMA config */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_TX_EN,cfg->dmaEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_DMA_FORMAT,cfg->dmaFmt);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_DMA_CONFIG,tmpVal);
return SUCCESS;
}
/****************************************************************************//**
* @brief AON and GPIP DAC channel A config
*
* @param cfg: AON and GPIP DAC channel A configuration
*
* @return None
*
*******************************************************************************/
void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src));
/* GPIP select source */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_A_SEL,cfg->src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* GPIP enable or disable channel */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_EN,cfg->chanEn);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* AON enable or disable channel */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_ACTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOA_EN,cfg->outputEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_EN,cfg->chanCovtEn);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_ACTRL,tmpVal);
}
/****************************************************************************//**
* @brief AON and GPIP DAC channel B config
*
* @param cfg: AON and GPIP DAC channel B configuration
*
* @return None
*
*******************************************************************************/
void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg)
{
uint32_t tmpVal;
CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src));
/* GPIP select source */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_CH_B_SEL,cfg->src);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* GPIP enable or disable channel */
tmpVal=BL_RD_REG(GPIP_BASE,GPIP_GPDAC_CONFIG);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GPIP_GPDAC_EN2,cfg->chanEn);
BL_WR_REG(GPIP_BASE,GPIP_GPDAC_CONFIG,tmpVal);
/* AON enable or disable channel */
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_BCTRL);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_IOB_EN,cfg->outputEn);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_EN,cfg->chanCovtEn);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_BCTRL,tmpVal);
}
/****************************************************************************//**
* @brief DAC channel A set value
*
* @param val: DAC value
*
* @return None
*
*******************************************************************************/
void GLB_DAC_Set_ChanA_Value(uint16_t val)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_DATA);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_A_DATA,val);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_DATA,tmpVal);
}
/****************************************************************************//**
* @brief DAC channel B set value
*
* @param val: DAC value
*
* @return None
*
*******************************************************************************/
void GLB_DAC_Set_ChanB_Value(uint16_t val)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPDAC_DATA);
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_GPDAC_B_DATA,val);
tmpVal=BL_WR_REG(GLB_BASE,GLB_GPDAC_DATA,tmpVal);
}
/*@} end of group DAC_Public_Functions */
/*@} end of group DAC */
/*@} end of group BL602_Peripheral_Driver */

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/**
******************************************************************************
* @file bl602_dma.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl602.h"
#include "bl602_dma.h"
#include "string.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_Private_Macros
* @{
*/
#define DMA_CHANNEL_OFFSET 0x100
#define DMA_Get_Channel(ch) (DMA_BASE+DMA_CHANNEL_OFFSET+(ch)*0x100)
static intCallback_Type * dmaIntCbfArra[DMA_CH_MAX][DMA_INT_ALL]= {
{NULL, NULL},
{NULL, NULL},
{NULL, NULL},
{NULL, NULL}
};
static DMA_LLI_Ctrl_Type PingPongListArra[DMA_CH_MAX][2];
/*@} end of group DMA_Private_Macros */
/** @defgroup DMA_Private_Types
* @{
*/
/*@} end of group DMA_Private_Types */
/** @defgroup DMA_Private_Variables
* @{
*/
/*@} end of group DMA_Private_Variables */
/** @defgroup DMA_Global_Variables
* @{
*/
/*@} end of group DMA_Global_Variables */
/** @defgroup DMA_Private_Fun_Declaration
* @{
*/
/*@} end of group DMA_Private_Fun_Declaration */
/** @defgroup DMA_Private_Functions
* @{
*/
/****************************************************************************//**
* @brief DMA interrupt handler
*
* @param None
*
* @return None
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void DMA_ALL_IRQHandler(void)
{
uint32_t tmpVal;
uint32_t intClr;
uint8_t ch;
/* Get DMA register */
uint32_t DMAChs = DMA_BASE;
for(ch=0;ch<DMA_CH_MAX;ch++){
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) {
/* Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR);
intClr |= (1 << ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr);
BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal);
if(dmaIntCbfArra[ch][DMA_INT_TCOMPLETED] != NULL) {
/* Call the callback function */
dmaIntCbfArra[ch][DMA_INT_TCOMPLETED]();
}
}
}
for(ch=0;ch<DMA_CH_MAX;ch++){
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) {
/*Clear interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR);
intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR);
intClr |= (1 << ch);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr);
BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal);
if(dmaIntCbfArra[ch][DMA_INT_ERR] != NULL) {
/* Call the callback function */
dmaIntCbfArra[ch][DMA_INT_ERR]();
}
}
}
}
#endif
/*@} end of group DMA_Private_Functions */
/** @defgroup DMA_Public_Functions
* @{
*/
/****************************************************************************//**
* @brief DMA enable
*
* @param None
*
* @return None
*
*******************************************************************************/
void DMA_Enable(void)
{
uint32_t tmpVal;
/* Get DMA register */
uint32_t DMAChs = DMA_BASE;
tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);
BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);
#ifndef BFLB_USE_HAL_DRIVER
Interrupt_Handler_Register(DMA_ALL_IRQn,DMA_ALL_IRQHandler);
#endif
}
/****************************************************************************//**
* @brief DMA disable
*
* @param None
*
* @return None
*
*******************************************************************************/
void DMA_Disable(void)
{
uint32_t tmpVal;
/* Get DMA register */
uint32_t DMAChs = DMA_BASE;
tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);
BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief DMA channel init
*
* @param chCfg: DMA configuration
*
* @return None
*
*******************************************************************************/
void DMA_Channel_Init(DMA_Channel_Cfg_Type *chCfg)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(chCfg->ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch));
CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth));
CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth));
CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSzie));
CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSzie));
CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir));
CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph));
CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph));
/* Config channel config */
BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr);
BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr);
tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSzie);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSzie);
/* FIXME: how to deal with SLargerD */
tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_SLARGERD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief DMA channel update source memory address and len
*
* @param ch: DMA channel
* @param memAddr: source memoty address
* @param len: source memory data length
*
* @return None
*
*******************************************************************************/
void DMA_Channel_Update_SrcMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
/* config channel config*/
BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr);
tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}
/****************************************************************************//**
* @brief DMA channel update destination memory address and len
*
* @param ch: DMA channel
* @param memAddr: destination memoty address
* @param len: destination memory data length
*
* @return None
*
*******************************************************************************/
void DMA_Channel_Update_DstMemcfg(uint8_t ch, uint32_t memAddr, uint32_t len)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
/* config channel config*/
BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr);
tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}
/****************************************************************************//**
* @brief Get DMA channel tranfersize
*
* @param ch: DMA channel
*
* @return tranfersize size
*
*******************************************************************************/
uint32_t DMA_Channel_TranferSize(uint8_t ch)
{
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE);
}
/****************************************************************************//**
* @brief Get DMA channel busy status
*
* @param ch: DMA channel
*
* @return SET or RESET
*
*******************************************************************************/
BL_Sts_Type DMA_Channel_Is_Busy(uint8_t ch)
{
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET:RESET;
}
/****************************************************************************//**
* @brief DMA enable
*
* @param ch: DMA channel number
*
* @return None
*
*******************************************************************************/
void DMA_Channel_Enable(uint8_t ch)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief DMA disable
*
* @param ch: DMA channel number
*
* @return None
*
*******************************************************************************/
void DMA_Channel_Disable(uint8_t ch)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief DMA init LLI transfer
*
* @param ch: DMA channel number
* @param lliCfg: LLI configuration
*
* @return None
*
*******************************************************************************/
void DMA_LLI_Init(uint8_t ch,DMA_LLI_Cfg_Type *lliCfg)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir));
CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph));
CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph));
tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief DMA channel update LLI
*
* @param ch: DMA channel number
* @param LLI: LLI addr
*
* @return None
*
*******************************************************************************/
void DMA_LLI_Update(uint8_t ch, uint32_t LLI)
{
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
/* Config channel config */
//BL_WR_REG(DMAChs, DMA_LLI, LLI);
BL602_MemCpy4((uint32_t*)DMAChs,(uint32_t*)LLI,4);
}
/****************************************************************************//**
* @brief DMA LLI PingPong Structure Initial
*
* @param dmaPpStruct: DMA LLI PingPong Config Parameter
*
* @return start success or not
*
*******************************************************************************/
BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct)
{
//setup lliList
dmaPpStruct->dmaCtrlRegVal.I=1;
dmaPpStruct->trans_index = 0;
if(dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_M2P){
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[0];
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr= dmaPpStruct->operatePeriphAddr;
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->chache_buf_addr[1];
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr= dmaPpStruct->operatePeriphAddr;
}
else if(dmaPpStruct->DMA_LLI_Cfg->dir == DMA_TRNS_P2M){
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr= dmaPpStruct->chache_buf_addr[0];
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr;
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->chache_buf_addr[1];
}else{
return ERROR;
/*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/
}
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX];
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;
if(dmaPpStruct->is_single_mode == 1){
/*
* if is is_single_mode is 1 ping-pong will only run once atfer start singal
* or ping-pong will run forever unless stop singal occour
*/
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = 0;
}else{
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX];
}
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal;
DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg);
DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]);
return SUCCESS;
}
/****************************************************************************//**
* @brief DMA LLI PingPong Structure Start
*
* @param dmaPpStruct: None
*
* @return None
*
*******************************************************************************/
void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct){
if(dmaPpStruct->is_single_mode == 1){
DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]);
}
DMA_Channel_Enable(dmaPpStruct->dmaChan);
}
/****************************************************************************//**
* @brief DMA LLI PingPong Structure Stop
*
* @param dmaPpStruct: None
*
* @return None
*
*******************************************************************************/
void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct){
DMA_Channel_Disable(dmaPpStruct->dmaChan);
}
/****************************************************************************//**
* @brief DMA LLI PingPong Structure Start
*
* @param dmaPpStruct: dma pp struct pointer
* @param Ping_Transfer_len: ping len
* @param Pong_Transfer_len: pong len
*
* @return Succrss or not
*
*******************************************************************************/
BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct,uint16_t Ping_Transfer_len,uint16_t Pong_Transfer_len){
struct DMA_Control_Reg dmaCtrlRegVal_temp;
if(Ping_Transfer_len > 4096 || Pong_Transfer_len >4096){
return ERROR;
}
dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl ;
dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len;
PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl ;
dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len;
PingPongListArra[dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp;
DMA_LLI_Init(dmaPpStruct->dmaChan, dmaPpStruct->DMA_LLI_Cfg);
DMA_LLI_Update(dmaPpStruct->dmaChan, (uint32_t)&PingPongListArra[dmaPpStruct->dmaChan][PING_INDEX]);
return SUCCESS;
}
/****************************************************************************//**
* @brief DMA LLI Start New Transmit for Ping-Pong Buf
*
* @param dmaPpBuf: DMA LLI Ping-Pong Buf
*
* @return None
*
*******************************************************************************/
void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf)
{
NVIC_DisableIRQ(DMA_ALL_IRQn);
if(dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL){
DMA_LLI_Update(dmaPpBuf->dmaChan, (uint32_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]);
DMA_Channel_Enable(dmaPpBuf->dmaChan);
dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex==0)?1:0;
}
NVIC_EnableIRQ(DMA_ALL_IRQn);
}
/****************************************************************************//**
* @brief DMA LLI Remove Completed Ping-Pong Buf List
*
* @param dmaPpBuf: DMA LLI Ping-Pong Buf
*
* @return Next Ping-Pong Buf List Header
*
*******************************************************************************/
DMA_LLI_Ctrl_Type * DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf)
{
NVIC_DisableIRQ(DMA_ALL_IRQn);
dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL;
NVIC_EnableIRQ(DMA_ALL_IRQn);
return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex];
}
/****************************************************************************//**
* @brief DMA LLI Append Buf to List
*
* @param dmaPpBuf: DMA LLI Ping-Pong Buf
* @param dmaLliList: New LLI Buf to Append
*
* @return None
*
*******************************************************************************/
void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList)
{
DMA_LLI_Ctrl_Type *pLliList = NULL;
NVIC_DisableIRQ(DMA_ALL_IRQn);
pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex];
if(pLliList == NULL){
dmaLliList->nextLLI = 0;
dmaLliList->dmaCtrl.I = 1;
dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList;
}else{
/*Append to last */
while(pLliList->nextLLI != 0){
pLliList = (DMA_LLI_Ctrl_Type*)pLliList->nextLLI;
}
pLliList->nextLLI = (uint32_t)dmaLliList;
pLliList->dmaCtrl.I = 0;
dmaLliList->nextLLI = 0;
dmaLliList->dmaCtrl.I = 1;
}
if(DMA_Channel_Is_Busy(dmaPpBuf->dmaChan) == RESET){
/* DMA stopped: maybe stop just a few minutes ago(not enter INT due to NVIC_DisableIRQ)
or has already stopped before this function is called */
if(dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL){
/* DMA has already stopped before this function is called */
DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf);
}
}
NVIC_EnableIRQ(DMA_ALL_IRQn);
}
/****************************************************************************//**
* @brief DMA LLi Destroy Ping-Pong Buf
*
* @param dmaPpBuf: DMA LLI Ping-Pong Buf
*
* @return None
*
*******************************************************************************/
void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf)
{
/* DMA LLI Disable */
DMA_Channel_Disable(dmaPpBuf->dmaChan);
if(dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL){
dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]);
}
dmaPpBuf->lliListHeader[0] = NULL;
if(dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL){
dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]);
}
dmaPpBuf->lliListHeader[1] = NULL;
dmaPpBuf->idleIndex = 0;
}
/****************************************************************************//**
* @brief Mask/Unmask the DMA interrupt
*
* @param ch: DMA channel number
* @param intType: Specifies the interrupt type
* @param intMask: Enable/Disable Specified interrupt type
*
* @return None
*
*******************************************************************************/
void DMA_IntMask(uint8_t ch,DMA_INT_Type intType, BL_Mask_Type intMask)
{
uint32_t tmpVal;
/* Get channel register */
uint32_t DMAChs = DMA_Get_Channel(ch);
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(ch));
CHECK_PARAM(IS_DMA_INT_TYPE(intType));
switch(intType)
{
case DMA_INT_TCOMPLETED:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}
break;
case DMA_INT_ERR:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
}
break;
case DMA_INT_ALL:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC);
tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC);
tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE);
BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal);
tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL);
tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I);
BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal);
}
break;
default:
break;
}
}
/****************************************************************************//**
* @brief Install DMA interrupt callback function
*
* @param dmaChan: DMA Channel type
* @param intType: DMA interrupt type
* @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
*
* @return None
*
*******************************************************************************/
void DMA_Int_Callback_Install(DMA_Chan_Type dmaChan,DMA_INT_Type intType,intCallback_Type* cbFun)
{
/* Check the parameters */
CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan));
CHECK_PARAM(IS_DMA_INT_TYPE(intType));
dmaIntCbfArra[dmaChan][intType] = cbFun;
}
/*@} end of group DMA_Public_Functions */
/*@} end of group DMA */
/*@} end of group BL602_Peripheral_Driver */

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/**
******************************************************************************
* @file bl602_i2c.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl602_i2c.h"
#include "bl602_glb.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Private_Macros
* @{
*/
#define I2C_FIFO_STATUS_TIMEOUT (160*1000*2)
#define PUT_UINT32_LE(n,b,i) \
{ \
(b)[(i) ] = (uint8_t) ( (n) ); \
(b)[(i) + 1] = (uint8_t) ( (n) >> 8 ); \
(b)[(i) + 2] = (uint8_t) ( (n) >> 16 ); \
(b)[(i) + 3] = (uint8_t) ( (n) >> 24 ); \
}
/*@} end of group I2C_Private_Macros */
/** @defgroup I2C_Private_Types
* @{
*/
/*@} end of group I2C_Private_Types */
/** @defgroup I2C_Private_Variables
* @{
*/
intCallback_Type * i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL]= {{NULL}};
/*@} end of group I2C_Private_Variables */
/** @defgroup I2C_Global_Variables
* @{
*/
/*@} end of group I2C_Global_Variables */
/** @defgroup I2C_Private_Fun_Declaration
* @{
*/
/*@} end of group I2C_Private_Fun_Declaration */
/** @defgroup I2C_Private_Functions
* @{
*/
/****************************************************************************//**
* @brief I2C interrupt handler
*
* @param i2cNo: I2C ID type
*
* @return None
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
static void I2C_IntHandler(I2C_ID_Type i2cNo)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
if(BL_IS_REG_BIT_SET(tmpVal,I2C_END_INT)){
if(i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL){
/* Call the callback function */
i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT]();
}
}
if(BL_IS_REG_BIT_SET(tmpVal,I2C_TXF_INT)){
if(i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL){
/* Call the callback function */
i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT]();
}
}
if(BL_IS_REG_BIT_SET(tmpVal,I2C_RXF_INT)){
if(i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL){
/* Call the callback function */
i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT]();
}
}
if(BL_IS_REG_BIT_SET(tmpVal,I2C_NAK_INT)){
if(i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL){
/* Call the callback function */
i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT]();
}
}
if(BL_IS_REG_BIT_SET(tmpVal,I2C_ARB_INT)){
if(i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL){
/* Call the callback function */
i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT]();
}
}
if(BL_IS_REG_BIT_SET(tmpVal,I2C_FER_INT)){
if(i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL){
/* Call the callback function */
i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT]();
}
}
}
#endif
/*@} end of group I2C_Private_Functions */
/** @defgroup I2C_Public_Functions
* @{
*/
/****************************************************************************//**
* @brief I2C write word data
*
* @param i2cNo: I2C ID type
* @param data: Data word
*
* @return None
*
*******************************************************************************/
void I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data)
{
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data);
}
/****************************************************************************//**
* @brief I2C read word data
*
* @param i2cNo: I2C ID type
*
* @return word data
*
*******************************************************************************/
uint32_t I2C_RecieveWord(I2C_ID_Type i2cNo)
{
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
return BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
}
/****************************************************************************//**
* @brief I2C enable
*
* @param i2cNo: I2C ID type
*
* @return None
*
*******************************************************************************/
void I2C_Enable(I2C_ID_Type i2cNo)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR);
BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);
tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);
BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief I2C disable
*
* @param i2cNo: I2C ID type
*
* @return None
*
*******************************************************************************/
void I2C_Disable(I2C_ID_Type i2cNo)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN);
BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
/* Clear I2C fifo */
tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR);
BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal);
/* Clear I2C interrupt status */
tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR);
BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);
}
/****************************************************************************//**
* @brief I2C set global reset function
*
* @param i2cNo: I2C ID type
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type I2C_Reset(I2C_ID_Type i2cNo)
{
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2C);
return SUCCESS;
}
/****************************************************************************//**
* @brief I2C init function
*
* @param i2cNo: I2C ID type
* @param direct: I2C read or write direct
* @param cfg: I2C transfer config struct
*
* @return None
*
*******************************************************************************/
void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
/* I2C write config */
tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
if(direct == I2C_WRITE){
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);
}else{
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR);
}
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr);
if(cfg->subAddrSize > 0){
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize-1);
}else{
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN);
}
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize-1);
BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
/* Set sub address */
BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr);
#ifndef BFLB_USE_HAL_DRIVER
Interrupt_Handler_Register(I2C_IRQn,I2C_IRQHandler);
#endif
}
/****************************************************************************//**
* @brief Set i2c prd
*
* @param i2cNo: I2C ID type
* @param phase: I2C phase value
*
* @return None
*
*******************************************************************************/
void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
//phase_cycles = (32000000 / phase / 4) - 1;
tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase);
BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal);
tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase);
BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal);
tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase);
BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal);
}
/****************************************************************************//**
* @brief I2C set scl output clock
*
* @param i2cNo: I2C ID type
* @param clk: Clock set
*
* @return None
*
*******************************************************************************/
void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk)
{
uint8_t bclkDiv = 0;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
bclkDiv = GLB_Get_BCLK_Div();
if(clk >= 100000){
GLB_Set_I2C_CLK(1, 0);
I2C_SetPrd(i2cNo, (SystemCoreClockGet()/(bclkDiv+1)) / (clk*4)-1);
}else if(clk >= 8000){
GLB_Set_I2C_CLK(1, 9);
I2C_SetPrd(i2cNo, ((SystemCoreClockGet()/(bclkDiv+1))/10) / (clk*4)-1);
}else if(clk >= 800){
GLB_Set_I2C_CLK(1, 99);
I2C_SetPrd(i2cNo, ((SystemCoreClockGet()/(bclkDiv+1))/100) / (clk*4)-1);
}else{
GLB_Set_I2C_CLK(1, 255);
I2C_SetPrd(i2cNo, ((SystemCoreClockGet()/(bclkDiv+1))/256) / (clk*4)-1);
}
/* Disable i2c scl sync to get current i2c clock */
I2C_SetSclSync(i2cNo, 0);
}
/****************************************************************************//**
* @brief I2C set scl sync
*
* @param i2cNo: I2C ID type
* @param enable: Enable or disable I2C scl sync
*
* @return None
*
*******************************************************************************/
void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG);
if(enable){
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);
}else{
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN);
}
BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief Get i2c busy state
*
* @param i2cNo: I2C ID type
*
* @return RESET or SET
*
*******************************************************************************/
BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? RESET: SET);
}
/****************************************************************************//**
* @brief I2C master write block data
*
* @param i2cNo: I2C ID type
* @param cfg: I2C transfer config struct
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg)
{
uint8_t i;
uint32_t timeOut = 0;
uint32_t temp = 0;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
I2C_Disable(i2cNo);
I2C_Init(i2cNo, I2C_WRITE, cfg);
I2C_Enable(i2cNo);
/* Set I2C write data */
for(i=0; i<cfg->dataSize; i++){
temp += (cfg->data[i] << ((i % 4) * 8));
if((i + 1) % 4 == 0){
timeOut = I2C_FIFO_STATUS_TIMEOUT;
while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0){
timeOut--;
if(timeOut == 0){
I2C_Disable(i2cNo);
return TIMEOUT;
}
}
BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);
temp = 0;
}
}
if((cfg->dataSize%4) != 0){
timeOut = I2C_FIFO_STATUS_TIMEOUT;
while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0){
timeOut--;
if(timeOut == 0){
I2C_Disable(i2cNo);
return TIMEOUT;
}
}
BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp);
}
timeOut = I2C_FIFO_STATUS_TIMEOUT;
while(I2C_IsBusy(i2cNo)){
timeOut--;
if(timeOut == 0){
I2C_Disable(i2cNo);
return TIMEOUT;
}
}
I2C_Disable(i2cNo);
return SUCCESS;
}
/****************************************************************************//**
* @brief I2C master read block data
*
* @param i2cNo: I2C ID type
* @param cfg: I2C transfer config struct
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg)
{
uint8_t i = 0;
uint32_t timeOut = 0;
uint32_t temp = 0;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
I2C_Disable(i2cNo);
I2C_Init(i2cNo, I2C_READ, cfg);
I2C_Enable(i2cNo);
/* Read I2C data */
while(cfg->dataSize - i >= 4){
timeOut = I2C_FIFO_STATUS_TIMEOUT;
while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0){
timeOut--;
if(timeOut == 0){
I2C_Disable(i2cNo);
return TIMEOUT;
}
}
temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
PUT_UINT32_LE(temp, cfg->data, i);
i += 4;
}
if(i < cfg->dataSize){
timeOut = I2C_FIFO_STATUS_TIMEOUT;
while(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0){
timeOut--;
if(timeOut == 0){
I2C_Disable(i2cNo);
return TIMEOUT;
}
}
temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA);
while(i < cfg->dataSize){
cfg->data[i] = (temp & 0xff);
temp = (temp >> 8);
i ++;
}
}
timeOut = I2C_FIFO_STATUS_TIMEOUT;
while(I2C_IsBusy(i2cNo)){
timeOut--;
if(timeOut == 0){
I2C_Disable(i2cNo);
return TIMEOUT;
}
}
I2C_Disable(i2cNo);
return SUCCESS;
}
/****************************************************************************//**
* @brief Mask/Unmask the I2C interrupt
*
* @param i2cNo: I2C ID type
* @param intType: Specifies the interrupt type
* @param intMask: Enable/Disable Specified interrupt type
*
* @return None
*
*******************************************************************************/
void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask)
{
uint32_t tmpVal;
uint32_t I2Cx = I2C_BASE;
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
CHECK_PARAM(IS_I2C_INT_TYPE(intType));
CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS);
switch(intType)
{
case I2C_TRANS_END_INT:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
}
break;
case I2C_TX_FIFO_READY_INT:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
}
break;
case I2C_RX_FIFO_READY_INT:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
}
break;
case I2C_NACK_RECV_INT:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
}
break;
case I2C_ARB_LOST_INT:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
}
break;
case I2C_FIFO_ERR_INT:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
}
break;
case I2C_INT_ALL:
if(intMask == UNMASK)
{
/* UNMASK(Enable) this interrupt */
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
}
else
{
/* MASK(Disable) this interrupt */
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN);
tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK);
tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK);
}
break;
default:
break;
}
BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal);
}
/****************************************************************************//**
* @brief Install I2C interrupt callback function
*
* @param i2cNo: I2C ID type
* @param intType: Specifies the interrupt type
* @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
*
* @return None
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type* cbFun)
{
/* Check the parameters */
CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo));
CHECK_PARAM(IS_I2C_INT_TYPE(intType));
i2cIntCbfArra[i2cNo][intType] = cbFun;
}
#endif
/****************************************************************************//**
* @brief I2C IRQ handler
*
* @param None
*
* @return None
*
*******************************************************************************/
#ifndef BFLB_USE_HAL_DRIVER
void I2C_IRQHandler(void)
{
I2C_IntHandler(I2C0_ID);
}
#endif
/*@} end of group I2C_Public_Functions */
/*@} end of group I2C */
/*@} end of group BL602_Peripheral_Driver */

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