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[fix] fix hal driver

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This commit is contained in:
jzlv 2021-06-04 17:49:10 +08:00
parent 634de901bf
commit c2f3072455
56 changed files with 5242 additions and 2571 deletions
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10
drivers/bl702_driver/bl702_flash.ld
View file

@ -11,9 +11,9 @@
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* INPUT(-lc) */
/* link with the standard GCC library */
INPUT(-lgcc)
/* INPUT(-lgcc) */
/* configure the entry point */
ENTRY(_enter)
@ -22,10 +22,10 @@ HeapSize = 0x1000; /* 4KB */
MEMORY
{
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 4096K
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K
ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 48K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 16K
ram_memory (!rx) : ORIGIN = 0x4201C000, LENGTH = 96K
}
SECTIONS

193
drivers/bl702_driver/bl702_ram.ld Normal file
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@ -0,0 +1,193 @@
/****************************************************************************************
* @file map.txt
*
* @brief This file is the map file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2018
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
/* INPUT(-lc) */
/* link with the standard GCC library */
/* INPUT(-lgcc) */
/* configure the entry point */
ENTRY(_enter)
StackSize = 0x0400; /* 1KB */
HeapSize = 0x1000; /* 4KB */
MEMORY
{
itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 32K
dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 32K
ram_memory (!rx) : ORIGIN = 0x42020000, LENGTH = 48K
}
SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(.text.metal.init.enter))
KEEP (*(SORT_NONE(.init)))
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.srodata)
*(.srodata.*)
*(.tcm_code)
*(.tcm_const)
*(.sclock_rlt_code)
*(.sclock_rlt_const)
. = ALIGN(4);
__text_code_end__ = .;
} > itcm_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/* .heap_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of heap sections, and assign
* values to heap symbols later */
.heap_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + HeapSize;
. = ALIGN(0x4);
} > dtcm_memory
_HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
_HeapSize = HeapSize;
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
}

14
drivers/bl702_driver/cpu_flags.cmake Normal file
View file

@ -0,0 +1,14 @@
SET(CPU_ARCH "RISCV")
SET(MCPU "riscv-e24")
if(${SUPPORT_FLOAT} STREQUAL "y")
SET(MARCH "rv32imafc")
SET(MABI "ilp32f")
else()
SET(MARCH "rv32imac")
SET(MABI "ilp32")
endif()
list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI})
list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI})
SET(LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/bl702_flash.ld)

17
drivers/bl702_driver/hal_drv/default_config/power_config.h Normal file
View file

@ -0,0 +1,17 @@
#ifndef _POWER_CONFIG_H
#define _POWER_CONFIG_H
#define DEAULT_LP_XTAL_TYPE GLB_DLL_XTAL_32M
#define DEFAULT_LP_LDO_LEVEL PDS_LDO_LEVEL_1P10V
#define DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC PDS_AON_WAKEUP_GPIO_NONE
#define DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE
#define DEFAULT_LP_PDS_FLASH_POWER_DOWN 1
#define DEFAULT_LP_PDS_HOLD_GPIO 0
#define DEFAULT_LP_PDS_TURN_OFF_FLASH_PAD 1
#define DEFAULT_LP_PDS_TURN_OFF_XTAL_32M 1
#define DEFAULT_LP_PDS_TURN_OFF_DLL 1
#define DEFAULT_LP_PDS_TURN_OFF_RF 1
#define DEFAULT_LP_PDS_USE_XTAL_32K 0
#endif

6
drivers/bl702_driver/hal_drv/default_config/pwm_config.h
View file

@ -1,7 +1,7 @@
#ifndef _PWM_CONFIG_H
#define _PWM_CONFIG_H
#define PWM_STOP_MODE_SEL (1) /*PWM_STOP_GRACEFUL */
#define PWM_POL_SEL (0) /*!< PWM POL NORAML */
#define PWM_MAX_CHANNEL (5)
#define PWM_STOP_MODE_SEL (PWM_STOP_GRACEFUL)
#define PWM_POL_SEL (PWM_POL_NORMAL)
#endif

91
drivers/bl702_driver/hal_drv/inc/hal_adc.h
View file

@ -26,6 +26,14 @@
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_ADC_CHANNEL_START 0x10
#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11
#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12
#define DEVICE_CTRL_ADC_VBAT_ON 0x13
#define DEVICE_CTRL_ADC_VBAT_OFF 0x14
#define DEVICE_CTRL_ADC_TSEN_ON 0x15
#define DEVICE_CTRL_ADC_TSEN_OFF 0x16
enum adc_index_type
{
#ifdef BSP_USING_ADC0
@ -34,9 +42,9 @@ enum adc_index_type
ADC_MAX_INDEX
};
#define ADC_CLK_MAX (2000000)
#define LEFT_SHIFT_BIT(x) (1 << x)
#define adc_channel_start(dev) device_control(dev,DEVICE_CTRL_ADC_CHANNEL_START,NULL)
#define adc_channel_stop(dev) device_control(dev,DEVICE_CTRL_ADC_CHANNEL_STOP,NULL)
#define adc_channel_config(dev,list) device_control(dev,DEVICE_CTRL_ADC_CHANNEL_CONFIG,list)
typedef enum {
ADC_CHANNEL0, /* GPIO 0, ADC channel 0 */
@ -66,65 +74,84 @@ typedef enum {
}adc_channel_t;
typedef enum {
ADC_CLK_2MHZ,
ADC_CLK_1P3MHZ,
ADC_CLK_1MHZ,
ADC_CLK_500KHZ,
}adc_clk_t;
ADC_CLOCK_DIV_1, /*!< ADC clock:on 32M clock is 32M */
ADC_CLOCK_DIV_4, /*!< ADC clock:on 32M clock is 8M */
ADC_CLOCK_DIV_8, /*!< ADC clock:on 32M clock is 4M */
ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */
ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */
ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */
ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */
ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */
}adc_clk_div_t;
typedef enum {
ADC_VREF_3P2V = 0, /* ADC select 3.2V as reference voltage */
ADC_VREF_2P0V = 1, /* ADC select 2V as reference voltage */
}adc_vref_t;
typedef enum {
ADC_ONE_CONV = 0, /* ADC One shot conversion mode */
ADC_CON_CONV = 1, /* ADC Continuous conversion mode */
}adc_conv_t;
/**
* @brief ADC data width type definition
*/
typedef enum {
ADC_DATA_WD_12, /*!< ADC 12 bits */
ADC_DATA_WD_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */
ADC_DATA_WD_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */
ADC_DATA_WD_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
ADC_DATA_WD_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */
ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */
ADC_DATA_WIDTH_16B_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
}adc_data_width_t;
/**
* @brief ADC FIFO threshold type definition
*/
typedef enum {
ADC_SINGLE_ENDED_IN = 0, /* ADC signal is single-ended input */
ADC_DIFFERENTIAL_IN = 1, /* ADC signal is differential input*/
}adc_inputmode_t;
ADC_FIFO_THRESHOLD_1BYTE, /*!< ADC FIFO threshold is 1 */
ADC_FIFO_THRESHOLD_4BYTE, /*!< ADC FIFO threshold is 4 */
ADC_FIFO_THRESHOLD_8BYTE, /*!< ADC FIFO threshold is 8 */
ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */
}adc_fifo_threshold_t;
/**
* @brief ADC PGA gain type definition
*/
typedef enum {
ADC_GAIN_NONE, /*!< No PGA gain */
ADC_GAIN_1, /*!< PGA gain 1 */
ADC_GAIN_2, /*!< PGA gain 2 */
ADC_GAIN_4, /*!< PGA gain 4 */
ADC_GAIN_8, /*!< PGA gain 8 */
ADC_GAIN_16, /*!< PGA gain 16 */
ADC_GAIN_32, /*!< PGA gain 32 */
}adc_pga_gain_t;
typedef struct {
uint8_t *pinList;
uint8_t *posChList;
uint8_t *negChList;
uint8_t *pos_channel;
uint8_t *neg_channel;
uint8_t num;
uint8_t dma_en;
adc_conv_t conv_mode;
adc_inputmode_t in_mode;
} adc_user_cfg_t;
} adc_channel_cfg_t;
typedef struct {
int8_t posChan; /*!< Positive channel */
int8_t negChan; /*!< Negative channel */
uint16_t value; /*!< ADC value */
float volt; /*!< ADC voltage result */
}adc_res_val_t;
}adc_channel_val_t;
typedef struct adc_device
{
struct device parent;
adc_clk_t clk; /* CLK is not more than 2Mhz */
adc_clk_div_t clk_div; /* CLK is not more than 2Mhz */
adc_vref_t vref; /* ADC voltage reference*/
adc_data_width_t resWidth;
bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */
bool differential_mode; /** Channel type: single-ended or differential. */
adc_data_width_t data_width;
adc_fifo_threshold_t fifo_threshold;
adc_pga_gain_t gain;
} adc_device_t;
#define ADC_DEV(dev) ((adc_device_t*)dev)
int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc_user_cfg_t *adc_user_cfg);
int adc_register(enum adc_index_type index, const char *name, uint16_t flag);
int adc_trim_tsen(uint16_t * tsen_offset);
float adc_get_tsen(uint16_t tsen_offset);
#endif

78
drivers/bl702_driver/hal_drv/inc/hal_cam.h Normal file
View file

@ -0,0 +1,78 @@
/**
* @file hal_cam.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_CAM_H__
#define __HAL_CAM_H__
#include "drv_device.h"
#include "bl702_cam.h"
#include "bl702_config.h"
typedef enum
{
CAM_AUTO_MODE,
CAM_MANUAL_MODE,
} cam_software_mode_t;
typedef enum
{
CAM_FRAME_PLANAR_MODE,
CAM_FRAME_INTERLEAVE_MODE,
} cam_frame_mode_t;
typedef enum
{
CAM_YUV_FORMAT_YUV422,
CAM_YUV_FORMAT_YUV420_EVEN,
CAM_YUV_FORMAT_YUV420_ODD,
CAM_YUV_FORMAT_YUV400_EVEN,
CAM_YUV_FORMAT_YUV400_ODD,
} cam_yuv_format_t;
typedef struct cam_device
{
struct device parent;
cam_software_mode_t software_mode;
cam_frame_mode_t frame_mode;
cam_yuv_format_t yuv_format;
uint32_t cam_write_ram_addr;
uint32_t cam_write_ram_size;
uint32_t cam_frame_size;
// planar mode need use:
uint32_t cam_write_ram_addr1;
uint32_t cam_write_ram_size1;
uint32_t cam_frame_size1;
} cam_device_t;
void cam_init(cam_device_t *cam_cfg);
void cam_start(void);
void cam_stop(void);
uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len);
uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV);
void cam_drop_one_frame_interleave(void);
void cam_drop_one_frame_planar(void);
void cam_hsync_crop(uint16_t start, uint16_t end);
void cam_vsync_crop(uint16_t start, uint16_t end);
#endif

173
drivers/bl702_driver/hal_drv/inc/hal_camera.h
View file

@ -1,173 +0,0 @@
/**
* @file hal_camera.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __IMAGE_SENSOR_H__
#define __IMAGE_SENSOR_H__
#include "bl702_common.h"
#include "bl702_cam.h"
#include "bl702_mjpeg.h"
#define IMAGE_SENSOR_BF2013 0
#define IMAGE_SENSOR_GC0308 1
#define IMAGE_SENSOR_USE IMAGE_SENSOR_GC0308
#define ENDADDR (0x42030000)
#define CAMERA_RESOLUTION_X 640
#define CAMERA_RESOLUTION_Y 480
#define CAMERA_FRAME_SIZE (CAMERA_RESOLUTION_X * CAMERA_RESOLUTION_Y * 2)
#define MJPEG_READ_ADDR 0x42020800//0x42022000
#define MJPEG_READ_SIZE 2
#define YUV_USE 1
#if(YUV_USE == 1)
#define CAMERA_BUFFER_SIZE_WHEN_MJPEG (CAMERA_RESOLUTION_X * 2 * 8 * MJPEG_READ_SIZE)
#else
#define CAMERA_BUFFER_SIZE_WHEN_MJPEG (CAMERA_RESOLUTION_X * 8 * MJPEG_READ_SIZE)
#endif
#define MJPEG_WRITE_ADDR (MJPEG_READ_ADDR+CAMERA_BUFFER_SIZE_WHEN_MJPEG)
#define MJPEG_WRITE_SIZE (ENDADDR - MJPEG_READ_ADDR -CAMERA_BUFFER_SIZE_WHEN_MJPEG)
extern CAM_CFG_Type cameraCfg;
extern MJPEG_CFG_Type mjpegCfg;
void Image_Sensor_PSRAM_Init(void);
BL_Err_Type Image_Sensor_Init(BL_Fun_Type mjpegEn, CAM_CFG_Type *camCfg, MJPEG_CFG_Type *mjpegCfg);
void Image_Sensor_Dump_Register(void);
BL_Err_Type Image_Sensor_CAM_Get_Interleave(uint8_t **pic, uint32_t *len);
BL_Err_Type Image_Sensor_CAM_Get_Planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY,
uint8_t **picUV, uint32_t *lenUV);
uint8_t Image_Sensor_CAM_Frame_Count0(void);
uint8_t Image_Sensor_CAM_Frame_Count1(void);
void Image_Sensor_CAM_Release_Interleave(void);
void Image_Sensor_CAM_Release_Planar(void);
void Image_Sensor_CAM_Open(void);
void Image_Sensor_CAM_Close(void);
void Image_Sensor_CAM_Deinit(void);
BL_Err_Type Image_Sensor_MJPEG_Get(uint8_t **pic, uint32_t *len, uint8_t *q);
uint8_t Image_Sensor_MJPEG_Frame_Count(void);
void Image_Sensor_MJPEG_Release(void);
void Image_Sensor_MJPEG_Open(void);
void Image_Sensor_MJPEG_Close(void);
void Image_Sensor_MJPEG_Deinit(void);
void ClkOutInit(void);
BL_Err_Type Timer_Init(void);
void Test_H(void);
void Test_L(void);
void Timer_Match0_Cbf(void);
#endif
// #ifndef __HAL_CAM__H__
// #define __HAL_CAM__H__
// #include "drv_device.h"
// #include "bl702_config.h"
// #define DEVICE_CTRL_CONFIG_CAM_START 0x10
// #define DEVICE_CTRL_CONFIG_CAM_STOP 0x11
// typedef enum
// {
// CAMERA_PLANAR_MODE,
// CAMERA_INTERLEAVE_MODE,
// } camera_frame_mode_t;
// typedef enum
// {
// CAMERA_YUV422,
// CAMERA_YUV420_EVEN,
// CAMERA_YUV420_ODD,
// CAMERA_YUV400_EVEN,
// CAMERA_YUV400_ODD,
// } camera_yuv_mode_t;
// typedef struct
// {
// camera_frame_mode_t frame_mode;
// camera_yuv_mode_t yuv_mode;
// BL_Fun_Type mjpeg_enable;
// uint8_t mjpegQ;
// } camera_pic_format_t;
// typedef enum
// {
// CAMERA_LINE_ACTIVE_POLARITY_LOW, /*!< CAMERA line active polarity low */
// CAMERA_LINE_ACTIVE_POLARITY_HIGH, /*!< CAMERA line active polarity high */
// } camera_line_active_polarity;
// typedef enum
// {
// CAMERA_FRAME_ACTIVE_POLARITY_LOW, /*!< CAMERA frame active polarity low */
// CAMERA_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAMERA frame active polarity high */
// } camera_frame_active_polarity;
// typedef struct
// {
// uint8_t mclk;
// uint8_t pclk;
// uint8_t vsync;
// uint8_t hsync;
// uint8_t data0;
// uint8_t data1;
// uint8_t data2;
// uint8_t data3;
// uint8_t data4;
// uint8_t data5;
// uint8_t data6;
// uint8_t data7;
// BL_Fun_Type mclk_enable;
// } camera_pin_t;
// typedef struct
// {
// uint8_t *base1;
// uint8_t *addr1;
// uint32_t length1;
// uint8_t *base2;
// uint8_t *addr2;
// uint32_t length2;
// } camera_picture_t;
// typedef struct
// {
// struct device parent;
// uint8_t id;
// camera_pin_t pin;
// uint32_t pic_reso_x;
// uint32_t pic_reso_y;
// uint8_t *buffer;
// uint32_t length;
// camera_pic_format_t pic_format;
// camera_line_active_polarity line_pol;
// camera_frame_active_polarity frame_pol;
// uint8_t mjpeg_quality;
// camera_picture_t picture;
// } camera_device_t;
// void camera_register(camera_device_t *device, const char *name, uint16_t flag);
// int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size);
// extern camera_device_t camera_device;
// #endif

24
drivers/bl702_driver/hal_drv/inc/hal_clock.h
View file

@ -34,21 +34,26 @@
#define ROOT_CLOCK_SOURCE_RC_32M 2
#define ROOT_CLOCK_SOURCE_XTAL_32M 3
#define ROOT_CLOCK_SOURCE_DLL_57P6M 4
#define ROOT_CLOCK_SOURCE_DLL_96M 5
#define ROOT_CLOCK_SOURCE_DLL_144M 6
#define ROOT_CLOCK_SOURCE_PLL_57P6M 4
#define ROOT_CLOCK_SOURCE_PLL_96M 5
#define ROOT_CLOCK_SOURCE_PLL_144M 6
#define ROOT_CLOCK_SOURCE_XCLK ROOT_CLOCK_SOURCE_XTAL_32M
#define ROOT_CLOCK_SOURCE_FCLK 7
#define ROOT_CLOCK_SOURCE_HCLK 7
#define ROOT_CLOCK_SOURCE_BCLK 8
#define ROOT_CLOCK_SOURCE_DLL_FCLK 7
#define ROOT_CLOCK_SOURCE_DLL_HCLK 7
#define ROOT_CLOCK_SOURCE_DLL_BCLK 8
#define ROOT_CLOCK_SOURCE_DLL_XCLK 3
#define ROOT_CLOCK_SOURCE_AUPLL 9
#define AUDIO_PLL_CLOCK_12288000_HZ 0x90
#define AUDIO_PLL_CLOCK_11289600_HZ 0x91
#define AUDIO_PLL_CLOCK_5644800_HZ 0x92
#define AUDIO_PLL_CLOCK_24576000_HZ 0x93
#define AUDIO_PLL_CLOCK_24000000_HZ 0x94
#define OUTPUT_REF_CLOCK_SOURCE_NONE 0
#define OUTPUT_REF_CLOCK_SOURCE_I2S 1
#define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_DLL_144M
#if (BSP_ROOT_CLOCK_SOURCE > 2) && (BSP_ROOT_CLOCK_SOURCE < 7)
#define CLOCK_XTAL EXTERNAL_XTAL_32M
#else
@ -61,6 +66,7 @@ enum system_clock_type
SYSTEM_CLOCK_FCLK,
SYSTEM_CLOCK_BCLK,
SYSTEM_CLOCK_XCLK,
SYSTEM_CLOCK_AUPLL,
};
enum peripheral_clock_type
{
@ -70,6 +76,8 @@ enum peripheral_clock_type
PERIPHERAL_CLOCK_ADC,
PERIPHERAL_CLOCK_DAC,
PERIPHERAL_CLOCK_I2S,
PERIPHERAL_CLOCK_PWM,
PERIPHERAL_CLOCK_CAM,
};
void system_clock_init(void);

12
drivers/bl702_driver/hal_drv/inc/hal_dma.h
View file

@ -107,8 +107,16 @@ enum dma_index_type
#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */
#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */
#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */
#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC0 */
#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC1 */
#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:ADC0 */
#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:DAC0 */
#define DMA_REQUEST_USB_EP0 0x00000018 /*!< DMA request peripheral:USB EP0*/
#define DMA_REQUEST_USB_EP1 0x00000019 /*!< DMA request peripheral:USB EP1*/
#define DMA_REQUEST_USB_EP2 0x0000001A /*!< DMA request peripheral:USB EP2*/
#define DMA_REQUEST_USB_EP3 0x0000001B /*!< DMA request peripheral:USB EP3*/
#define DMA_REQUEST_USB_EP4 0x0000001C /*!< DMA request peripheral:USB EP4*/
#define DMA_REQUEST_USB_EP5 0x0000001D /*!< DMA request peripheral:USB EP5*/
#define DMA_REQUEST_USB_EP6 0x0000001E /*!< DMA request peripheral:USB EP6*/
#define DMA_REQUEST_USB_EP7 0x0000001F /*!< DMA request peripheral:USB EP7 */
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1

10
drivers/bl702_driver/hal_drv/inc/hal_flash.h
View file

@ -27,8 +27,10 @@
#define FLASH_NOT_DETECT 0x10
int flash_erase(uint32_t addr, uint32_t size);
int flash_read(uint32_t addr, uint8_t *data, uint32_t size);
int flash_write(uint32_t addr, uint8_t *data, uint32_t size);
int flash_init(void);
int flash_read_jedec_id(uint8_t *data);
BL_Err_Type flash_read_xip(uint32_t addr,uint8_t *data, uint32_t len);
BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase_xip(uint32_t startaddr,uint32_t endaddr);
BL_Err_Type flash_set_cache(uint8_t cont_read,uint8_t cache_enable,uint8_t cache_way_disable, uint32_t flash_offset);
#endif

2
drivers/bl702_driver/hal_drv/inc/hal_gpio.h
View file

@ -94,6 +94,6 @@ void gpio_set_mode(uint32_t pin, uint32_t mode);
void gpio_write(uint32_t pin, uint32_t value);
void gpio_toggle(uint32_t pin);
int gpio_read(uint32_t pin);
void gpio_attach_irq(uint32_t pin, void (*cbFun)(void));
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin));
void gpio_irq_enable(uint32_t pin,uint8_t enabled);
#endif

3
drivers/bl702_driver/hal_drv/inc/hal_i2c.h
View file

@ -30,9 +30,6 @@ enum i2c_index_type
{
#ifdef BSP_USING_I2C0
I2C0_INDEX,
#endif
#ifdef BSP_USING_I2C1
I2C1_INDEX,
#endif
I2C_MAX_INDEX
};

69
drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h Normal file
View file

@ -0,0 +1,69 @@
/**
* @file hal_mjpeg.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_MJPEG__H__
#define __HAL_MJPEG__H__
#include "drv_device.h"
#include "bl702_config.h"
#define MJPEG_PACKET_ADD_NONE 0
#define MJPEG_PACKET_ADD_DEFAULT 1 << 0
#define MJPEG_PACKET_ADD_FRAME_HEAD 1 << 1
#define MJPEG_PACKET_ADD_FRAME_TAIL 1 << 2
#define MJPEG_PACKET_ADD_END_TAIL 1 << 3
/**
* @brief MJPEG YUV format definition
*/
typedef enum {
MJPEG_YUV_FORMAT_YUV420, /*!< MJPEG YUV420 planar mode */
MJPEG_YUV_FORMAT_YUV400, /*!< MJPEG YUV400 grey scale mode */
MJPEG_YUV_FORMAT_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */
MJPEG_YUV_FORMAT_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */
}mjpeg_yuv_format_t;
typedef struct mjpeg_device
{
struct device parent;
uint8_t quality;
mjpeg_yuv_format_t yuv_format;
uint32_t write_buffer_addr; /*!< MJPEG buffer addr */
uint32_t write_buffer_size; /*!< MJPEG buffer size */
uint32_t read_buffer_addr;
uint32_t read_buffer_size;
uint16_t resolution_x; /*!< CAM RESOLUTION X */
uint16_t resolution_y; /*!< CAM RESOLUTION Y */
uint8_t packet_cut_mode;
uint16_t frame_head_length;
uint16_t packet_head_length;
uint16_t packet_body_length;
uint16_t packet_tail_length;
} mjpeg_device_t;
void mjpeg_init(mjpeg_device_t *mjpeg_cfg);
void mjpeg_start(void);
void mjpeg_stop(void);
uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q);
void mjpeg_drop_one_frame(void);
#endif

7
drivers/bl702_driver/hal_drv/inc/hal_mtimer.h
View file

@ -25,14 +25,9 @@
#include "stdint.h"
void mtimer_init(void);
void mtimer_deinit(void);
void mtimer_start(void);
void mtimer_stop();
void mtimer_clear_time(void);
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void));
uint64_t mtimer_get_time_ms();
uint64_t mtimer_get_time_us();
void mtimer_delay_ms(uint32_t time);
void mtimer_delay_us(uint32_t time);
void mtimer_set_alarm_time(uint64_t time, void (*interruptFun)(void));
#endif

56
drivers/bl702_driver/hal_drv/inc/hal_power.h Normal file
View file

@ -0,0 +1,56 @@
/**
* @file hal_pwm.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_POWER__H__
#define __HAL_POWER__H__
#include "drv_device.h"
#include "bl702_config.h"
typedef enum
{
CLOCK_AHB_UART0_GATE = 0x10,
CLOCK_AHB_UART1_GATE = 0x11,
CLOCK_AHB_SPI_GATE = 0x12,
CLOCK_AHB_I2C_GATE = 0x13,
CLOCK_AHB_PWM_GATE = 0x14,
CLOCK_AHB_TMR_GATE = 0x15,
CLOCK_AHB_IRR_GATE = 0x16,
CLOCK_AHB_CKS_GATE = 0x17,
CLOCK_AHB_QDEC_GATE = 0x18,
CLOCK_AHB_KYS_GATE = 0x19,
CLOCK_AHB_I2S_GATE = 0x1A,
CLOCK_AHB_USB_GATE = 0x1C,
CLOCK_AHB_CAM_GATE = 0x1D,
CLOCK_AHB_MJPEG_GATE = 0x1E,
CLOCK_AHB_ALL = 0x1F,
}Clock_Gate_Type;
int lp_set_clock_gate(uint8_t enable , Clock_Gate_Type clockType);
void lp_set_all_gpio_hz(void);
void lp_power_off_dll(void);
int lp_enter_wfi(void);
int lp_enter_pds(uint32_t sleep_time ,void (*preCbFun)(void),void (*postCbFun)(void));
int lp_enter_hbn(uint32_t sleepTime);
#endif

17
drivers/bl702_driver/hal_drv/inc/hal_pwm.h
View file

@ -26,6 +26,7 @@
#include "drv_device.h"
#include "bl702_config.h"
#define DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG 0x10
enum pwm_index_type
{
@ -47,17 +48,29 @@ enum pwm_index_type
PWM_MAX_INDEX
};
#define pwm_channel_start(dev) device_control(dev,DEVICE_CTRL_RESUME,NULL)
#define pwm_channel_stop(dev) device_control(dev,DEVICE_CTRL_SUSPEND,NULL)
#define pwm_channel_update(dev,cfg) device_control(dev,DEVICE_CTRL_CONFIG,cfg)
#define pwm_it_pulse_count_update(dev,count) device_control(dev,DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG,(void*)count)
enum pwm_event_type
{
PWM_EVENT_COMPLETE,
};
typedef struct
{
uint32_t frequency;
uint8_t dutyCycle;
uint8_t dutycycle;
} pwm_config_t;
typedef struct pwm_device
{
struct device parent;
uint8_t ch;
uint32_t frequency;
uint8_t dutyCycle;
uint8_t dutycycle;
uint16_t it_pulse_count;
} pwm_device_t;
#define PWM_DEV(dev) ((pwm_device_t*)dev)

58
drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h Normal file
View file

@ -0,0 +1,58 @@
/**
* @file hal_sec_aes.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_AES__H__
#define __HAL_SEC_AES__H__
#include "drv_device.h"
#include "bl702_config.h"
typedef enum{
SEC_ASE_CBC,
SEC_ASE_CTR,
SEC_ASE_ECB
}sec_aes_type;
typedef enum{
SEC_ASE_KEY_128,
SEC_ASE_KEY_256,
SEC_ASE_KEY_192
}sec_aes_key_type;
typedef struct sec_aes_handle_t
{
sec_aes_type aes_type;
sec_aes_key_type key_type;
}sec_aes_handle_t;
typedef enum{
SEC_AES_DIR_ENCRYPT,
SEC_AES_DIR_DECRYPT
}sec_aes_dir_type;
int sec_aes_init(sec_aes_handle_t *handle,sec_aes_type aes_tye,sec_aes_key_type key_type);
int sec_aes_setkey(sec_aes_handle_t *handle,const uint8_t *key,uint8_t key_len,const uint8_t *nonce,uint8_t dir);
int sec_aes_encrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len, size_t offset,uint8_t *out);
int sec_aes_decrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len, size_t offset,uint8_t *out);
int sec_aes_deinit(sec_aes_handle_t *handle);
#endif

59
drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h Normal file
View file

@ -0,0 +1,59 @@
/**
* @file hal_sec_dsa.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_DSA__H__
#define __HAL_SEC_DSA__H__
#include "drv_device.h"
#include "bl702_config.h"
typedef struct sec_dsa_crt_cfg_tag
{
uint32_t *dP;
uint32_t *dQ;
uint32_t *qInv;
uint32_t *p;
uint32_t *invR_p;
uint32_t *primeN_p;
uint32_t *q;
uint32_t *invR_q;
uint32_t *primeN_q;
}sec_dsa_crt_cfg_t;
typedef struct{
uint32_t size;
uint32_t crtSize;
uint32_t *n;
uint32_t *e;
uint32_t *d;
sec_dsa_crt_cfg_t crtCfg;
}sec_dsa_handle_t;
int sec_dsa_init(sec_dsa_handle_t * handle,uint32_t size);
int sec_dsa_mexp_binary(uint32_t size,const uint32_t *a,const uint32_t *b,const uint32_t *c,uint32_t *r);
int sec_dsa_mexp_mont(uint32_t size,uint32_t *a,uint32_t *b,uint32_t *c,uint32_t *invR_c,uint32_t *primeN_c,uint32_t *r);
int sec_dsa_decrypt_crt(uint32_t size,uint32_t *c,sec_dsa_crt_cfg_t *crtCfg,uint32_t *d,uint32_t *r);
int sec_dsa_sign(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *s);
int sec_dsa_verify(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,const uint32_t *s);
#endif

57
drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h Normal file
View file

@ -0,0 +1,57 @@
/**
* @file hal_sec_ecdsa.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_ECDSA__H__
#define __HAL_SEC_ECDSA__H__
#include "drv_device.h"
#include "bl702_config.h"
typedef enum{
ECP_SECP256R1=0,
}sec_ecp_type;
typedef struct{
sec_ecp_type ecpId;
uint32_t *privateKey;
uint32_t *publicKeyx;
uint32_t *publicKeyy;
}sec_ecdsa_handle_t;
typedef struct{
sec_ecp_type ecpId;
}sec_ecdh_handle_t;
int sec_ecdsa_init(sec_ecdsa_handle_t * handle,sec_ecp_type id);
int sec_ecdsa_deinit(sec_ecdsa_handle_t * handle);
int sec_ecdsa_sign(sec_ecdsa_handle_t * handle,const uint32_t *random_k,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *r,uint32_t *s);
int sec_ecdsa_verify(sec_ecdsa_handle_t * handle,const uint32_t *hash, uint32_t hashLen,const uint32_t *r, const uint32_t *s);
int sec_ecdsa_get_private_key(sec_ecdsa_handle_t * handle,uint32_t *private_key);
int sec_ecdsa_get_public_key(sec_ecdsa_handle_t * handle,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy);
int sec_ecdh_init(sec_ecdh_handle_t * handle,sec_ecp_type id);
int sec_ecdh_deinit(sec_ecdh_handle_t * handle);
int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle,const uint32_t *pkX,const uint32_t *pkY,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy);
int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle,const uint32_t *private_key,const uint32_t *pRx,const uint32_t *pRy);
int sec_ecc_get_random_value(uint32_t *randomData,uint32_t *maxRef,uint32_t size);
#endif

55
drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h Normal file
View file

@ -0,0 +1,55 @@
/**
* @file hal_sec_hash.h
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_SEC_HASH__H__
#define __HAL_SEC_HASH__H__
#include "drv_device.h"
#include "bl702_config.h"
enum sec_hash_index_type
{
SEC_HASH0_INDEX,
SEC_HASH_MAX_INDEX
};
enum sec_hash_type
{
SEC_HASH_SHA1,
SEC_HASH_SHA224,
SEC_HASH_SHA256,
SEC_HASH_SHA384,
SEC_HASH_SHA512,
SEC_HASH_UNKNOWN
};
typedef struct sec_hash_device
{
struct device parent;
uint32_t shaBuf[64/4]; /*!< Data not processed but in this temp buffer */
uint32_t shaPadding[64/4]; /*!< Padding data */
uint8_t type; /*!< Sha has feed data */
} sec_hash_device_t;
int sec_hash_register(enum sec_hash_index_type index, const char *name, uint16_t flag);
#endif

7
drivers/bl702_driver/hal_drv/inc/hal_spi.h
View file

@ -75,6 +75,13 @@ enum spi_index_type
#define SPI_TRANSFER_TPYE_24BIT 2
#define SPI_TRANSFER_TYPE_32BIT 3
enum spi_event_type
{
SPI_EVENT_TX_FIFO,
SPI_EVENT_RX_FIFO,
SPI_EVENT_UNKNOWN
};
typedef struct spi_device
{
struct device parent;

9
drivers/bl702_driver/hal_drv/inc/hal_timer.h
View file

@ -26,6 +26,12 @@
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_OFLAG_INT 0x01
#define DEVICE_OFLAG_POLL 0x02
#define DEVICE_CTRL_TIMER_CH_START 0x80
#define DEVICE_CTRL_TIMER_CH_STOP 0x81
#define DEVICE_CTRL_GET_MATCH_STATUS 0x82
enum timer_index_type
{
#ifdef BSP_USING_TIMER_CH0
@ -73,6 +79,7 @@ typedef enum{
typedef struct {
uint32_t timeout_val;
uint32_t comp_it;
}timer_user_cfg_t;
@ -88,7 +95,7 @@ typedef struct timer_device
#define TIMER_DEV(dev) ((timer_device_t*)dev)
int timer_register(enum timer_index_type index, const char *name, uint16_t flag, timer_user_cfg_t *timer_user_cfg);
int timer_register(enum timer_index_type index, const char *name, uint16_t flag);
#endif

13
drivers/bl702_driver/hal_drv/inc/hal_uart.h
View file

@ -36,15 +36,6 @@ enum uart_index_type
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
#ifdef BSP_USING_UART2
UART2_INDEX,
#endif
#ifdef BSP_USING_UART3
UART3_INDEX,
#endif
#ifdef BSP_USING_UART4
UART4_INDEX,
#endif
UART_MAX_INDEX
};
@ -70,8 +61,8 @@ typedef enum
typedef enum
{
UART_STOP_ONE = 0, /*!< One stop bit */
UART_STOP_ONE_D_FIVE = 0, /*!< 1.5 stop bit */
UART_STOP_TWO = 1 /*!< Two stop bits */
UART_STOP_ONE_D_FIVE = 1, /*!< 1.5 stop bit */
UART_STOP_TWO = 2 /*!< Two stop bits */
} uart_stopbits_t;
/*!

4
drivers/bl702_driver/hal_drv/inc/hal_usb.h
View file

@ -38,6 +38,8 @@
#define DEVICE_CTRL_USB_DC_GET_TX_FIFO_CNT 0x18
#define DEVICE_CTRL_USB_DC_GET_RX_FIFO_CNT 0x19
#define DEVICE_CTRL_USB_DC_GET_EP_FREE 0x20
#define DEVICE_CTRL_USB_DC_SET_TX_DMA 0x21
#define DEVICE_CTRL_USB_DC_SET_RX_DMA 0x22
enum usb_index_type
{
@ -207,6 +209,8 @@ typedef struct usb_dc_device
uint8_t id;
usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */
usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */
void *tx_dma;
void *rx_dma;
} usb_dc_device_t;
int usb_dc_register(enum usb_index_type index, const char *name, uint16_t flag);

118
drivers/bl702_driver/hal_drv/src/hal_adc.c
View file

@ -22,14 +22,15 @@
*/
#include "hal_adc.h"
#include "hal_gpio.h"
#include "hal_clock.h"
#include "bl702_glb.h"
#include "bl702_dma.h"
#include "bl702_adc.h"
#include "adc_config.h"
adc_device_t adcx_device[ADC_MAX_INDEX] = {
static adc_device_t adcx_device[ADC_MAX_INDEX] = {
#ifdef BSP_USING_ADC0
ADC_CONFIG,
ADC0_CONFIG,
#endif
};
@ -43,40 +44,17 @@ adc_device_t adcx_device[ADC_MAX_INDEX] = {
int adc_open(struct device *dev, uint16_t oflag)
{
adc_device_t *adc_device = (adc_device_t *)dev;
adc_user_cfg_t *adc_user_cfg = ((adc_user_cfg_t *)(adc_device->parent.handle));
ADC_CFG_Type adc_cfg;
ADC_FIFO_Cfg_Type adc_fifo_cfg;
ADC_CFG_Type adc_cfg = {0};
ADC_FIFO_Cfg_Type adc_fifo_cfg = {0};
ADC_Disable();
ADC_Reset();
GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)adc_user_cfg->pinList, adc_user_cfg->num);
switch (adc_device->clk)
{
case ADC_CLK_500KHZ:
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
adc_cfg.clkDiv = ADC_CLK_DIV_32;
break;
case ADC_CLK_1MHZ:
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
adc_cfg.clkDiv = ADC_CLK_DIV_16;
break;
case ADC_CLK_1P3MHZ:
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 2);
adc_cfg.clkDiv = ADC_CLK_DIV_8;
break;
case ADC_CLK_2MHZ:
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
adc_cfg.clkDiv = ADC_CLK_DIV_8;
break;
default:
break;
}
adc_cfg.clkDiv = adc_device->clk_div;
adc_cfg.vref = adc_device->vref;
adc_cfg.resWidth = adc_device->resWidth;
adc_cfg.inputMode = adc_user_cfg->in_mode;
adc_cfg.resWidth = adc_device->data_width;
adc_cfg.inputMode = adc_device->differential_mode;
adc_cfg.v18Sel = ADC_V18_SELECT;
adc_cfg.v11Sel = ADC_V11_SELECT;
@ -88,35 +66,31 @@ int adc_open(struct device *dev, uint16_t oflag)
adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN;
adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL;
if(adc_user_cfg->dma_en)
adc_fifo_cfg.dmaEn = DISABLE;
if (oflag & DEVICE_OFLAG_STREAM_TX)
{
}
if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX))
{
}
if (oflag & DEVICE_OFLAG_DMA_TX)
{
}
if (oflag & DEVICE_OFLAG_DMA_RX)
{
adc_fifo_cfg.dmaEn = ENABLE;
}
else
{
adc_fifo_cfg.dmaEn = DISABLE;
}
adc_fifo_cfg.fifoThreshold = ADC_FIFO_THRESHOLD_1;
adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold;
ADC_Init(&adc_cfg);
if(adc_user_cfg->num == 1)
{
ADC_Channel_Config((ADC_Chan_Type)adc_user_cfg->posChList[0],(ADC_Chan_Type)adc_user_cfg->negChList[0], adc_user_cfg->conv_mode);
}
else if(adc_user_cfg->num > 1)
{
ADC_Scan_Channel_Config((ADC_Chan_Type*)(adc_user_cfg->posChList), (ADC_Chan_Type*)(adc_user_cfg->negChList),adc_user_cfg->num,adc_user_cfg->conv_mode);
}
ADC_FIFO_Cfg(&adc_fifo_cfg);
if((ADC_Chan_Type)adc_user_cfg->posChList[0] == ADC_CHAN_VABT_HALF)
{
ADC_Vbat_Enable();
}
ADC_Enable();
return 0;
}
/**
@ -140,7 +114,8 @@ int adc_close(struct device *dev)
*/
int adc_control(struct device *dev, int cmd, void *args)
{
//adc_device_t *adc_device = (adc_device_t *)dev;
adc_device_t* adc_device = (adc_device_t *)dev;
adc_channel_cfg_t* adc_channel_cfg = (adc_channel_cfg_t *)args;
switch (cmd)
{
@ -148,8 +123,6 @@ int adc_control(struct device *dev, int cmd, void *args)
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
/* code */
/* Enable UART interrupt*/
break;
case DEVICE_CTRL_GET_INT /* constant-expression */:
@ -158,13 +131,33 @@ int adc_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_CONFIG /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
case DEVICE_CTRL_ADC_CHANNEL_CONFIG /* constant-expression */:
if(adc_channel_cfg->num == 1)
ADC_Channel_Config(*adc_channel_cfg->pos_channel,*adc_channel_cfg->neg_channel,adc_device->continuous_conv_mode);
else
{
ADC_Scan_Channel_Config(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel,adc_channel_cfg->num,adc_device->continuous_conv_mode);
}
break;
case DEVICE_CTRL_ADC_CHANNEL_START /* constant-expression */:
/* code */
ADC_Start();
break;
case DEVICE_CTRL_SUSPEND /* constant-expression */:
case DEVICE_CTRL_ADC_CHANNEL_STOP /* constant-expression */:
/* code */
ADC_Stop();
break;
case DEVICE_CTRL_ADC_VBAT_ON:
ADC_Vbat_Enable();
break;
case DEVICE_CTRL_ADC_VBAT_OFF:
ADC_Vbat_Disable();
break;
case DEVICE_CTRL_ADC_TSEN_ON:
ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE);
break;
case DEVICE_CTRL_ADC_TSEN_OFF:
break;
default:
break;
@ -205,6 +198,17 @@ int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
}
return 0;
}
int adc_trim_tsen(uint16_t * tsen_offset)
{
return ADC_Trim_TSEN(tsen_offset);
}
float adc_get_tsen(uint16_t tsen_offset)
{
return TSEN_Get_Temp(tsen_offset);
}
/**
* @brief
*
@ -214,7 +218,7 @@ int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
* @param adc_user_cfg
* @return int
*/
int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc_user_cfg_t *adc_user_cfg)
int adc_register(enum adc_index_type index, const char *name, uint16_t flag)
{
struct device *dev;
@ -231,7 +235,7 @@ int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_ADC;
dev->handle = adc_user_cfg;
dev->handle = NULL;
return device_register(dev, name, flag);
}

148
drivers/bl702_driver/hal_drv/src/hal_cam.c Normal file
View file

@ -0,0 +1,148 @@
/**
* @file hal_cam.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_cam.h"
#include "bl702_glb.h"
#include "hal_cam.h"
/**
* @brief
*
* @param cam_cfg
*/
void cam_init(cam_device_t *cam_cfg)
{
CAM_CFG_Type camera_cfg =
{
.swMode = cam_cfg->software_mode,
.swIntCnt = 0,
.frameMode = cam_cfg->frame_mode,
.yuvMode = cam_cfg->yuv_format,
.waitCount = 0x40,
.linePol = CAM_LINE_ACTIVE_POLARITY_HIGH,
.framePol = CAM_FRAME_ACTIVE_POLARITY_HIGH,
.burstType = CAM_BURST_TYPE_INCR16,
.camSensorMode = CAM_SENSOR_MODE_V_AND_H,
.memStart0 = cam_cfg->cam_write_ram_addr,
.memSize0 = cam_cfg->cam_write_ram_size,
.frameSize0 = cam_cfg->cam_frame_size,
/* planar mode*/
.memStart1 = cam_cfg->cam_write_ram_addr1,
.memSize1 = cam_cfg->cam_write_ram_size1,
.frameSize1 = cam_cfg->cam_frame_size1,
};
CAM_Init(&camera_cfg);
}
/**
* @brief
*
*/
void cam_start(void)
{
CAM_Enable();
}
/**
* @brief
*
*/
void cam_stop(void)
{
CAM_Disable();
}
/**
* @brief
*
* @param pic
* @param len
*/
uint8_t cam_get_one_frame_interleave(uint8_t **pic, uint32_t *len)
{
CAM_Interleave_Frame_Info info;
arch_memset(&info, 0, sizeof(info));
CAM_Interleave_Get_Frame_Info(&info);
if(info.validFrames == 0)
{
return ERROR;
}
*pic = (uint8_t *)(info.curFrameAddr);
*len = info.curFrameBytes;
return SUCCESS;
}
uint8_t cam_get_one_frame_planar(CAM_YUV_Mode_Type yuv, uint8_t **picYY, uint32_t *lenYY, uint8_t **picUV, uint32_t *lenUV)
{
CAM_Planar_Frame_Info info;
arch_memset(&info, 0, sizeof(info));
CAM_Planar_Get_Frame_Info(&info);
if(yuv == CAM_YUV400_EVEN || yuv == CAM_YUV400_ODD)
{
if(info.validFrames0 == 0 && info.validFrames1 == 0)
{
return ERROR;
}
}
else
{
if(info.validFrames0 == 0 || info.validFrames1 == 0)
{
return ERROR;
}
}
*picYY = (uint8_t*)(info.curFrameAddr0);
*lenYY = info.curFrameBytes0;
*picUV = (uint8_t*)(info.curFrameAddr1);
*lenUV = info.curFrameBytes1;
return SUCCESS;
}
void cam_drop_one_frame_interleave(void)
{
CAM_Interleave_Pop_Frame();
}
void cam_drop_one_frame_planar(void)
{
CAM_Planar_Pop_Frame();
}
void cam_hsync_crop(uint16_t start, uint16_t end)
{
CAM_Hsync_Crop(start, end);
}
void cam_vsync_crop(uint16_t start, uint16_t end)
{
CAM_Vsync_Crop(start, end);
}

1874
drivers/bl702_driver/hal_drv/src/hal_camera.c
View file

File diff suppressed because it is too large Load diff

111
drivers/bl702_driver/hal_drv/src/hal_clock.c
View file

@ -23,6 +23,12 @@
#include "bl702_glb.h"
#include "hal_clock.h"
#include "hal_mtimer.h"
static uint32_t mtimer_get_clk_src_div(void)
{
return ((SystemCoreClockGet()/(GLB_Get_BCLK_Div() + 1))/1000/1000-1);
}
void system_clock_init(void)
{
@ -31,32 +37,45 @@ void system_clock_init(void)
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_HCLK_DIV,BSP_BCLK_DIV);
/* Set MTimer the same frequency as SystemCoreClock */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7);
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE & 0x0f);
#endif
}
void peripheral_clock_init(void)
{
#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1)
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_96M
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_96M,BSP_UART_CLOCK_DIV);
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_FCLK
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
GLB_Set_UART_CLK(ENABLE,HBN_UART_CLK_FCLK,BSP_UART_CLOCK_DIV);
#else
#error "please select correct uart clock source"
#endif
#endif
#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
GLB_Set_I2C_CLK(ENABLE,BSP_I2C_CLOCK_DIV);
#else
#error "please select correct i2c clock source"
#endif
#endif
#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
GLB_Set_SPI_CLK(ENABLE,BSP_SPI_CLOCK_DIV);
#else
#error "please select correct spi clock source"
#endif
#endif
#if defined(BSP_USING_PWM)
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_RC_32K
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_BCLK
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_XCLK
#elif BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
#endif
#endif
@ -71,18 +90,35 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_ADC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_ADC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_XCLK
#endif
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_ADC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_ADC_CLOCK_DIV);
#else
#error "please select correct adc clock source"
#endif
#endif
#if defined(BSP_USING_DAC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_AUDIO_PLL,BSP_DAC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_XCLK
#endif
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_Set_DAC_CLK(ENABLE,GLB_ADC_CLK_XCLK,BSP_DAC_CLOCK_DIV);
#else
#error "please select correct dac clock source"
#endif
#endif
#if defined(BSP_USING_CAM)
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#else
#error "please select correct cam clock source"
#endif
#endif
@ -103,6 +139,19 @@ uint32_t system_clock_get(enum system_clock_type type)
return (SystemCoreClockGet()/((GLB_Get_HCLK_Div()+1)*(GLB_Get_BCLK_Div()+1)));
case SYSTEM_CLOCK_XCLK:
return 32000000;
case SYSTEM_CLOCK_AUPLL:
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_12288000_HZ)
return 12288000;
else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_11289600_HZ)
return 11289600;
else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_5644800_HZ)
return 5644800;
else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24576000_HZ)
return 24576000;
else if(BSP_AUDIO_PLL_CLOCK_SOURCE == AUDIO_PLL_CLOCK_24000000_HZ)
return 24000000;
#endif
default:
break;
}
@ -116,15 +165,15 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
{
case PERIPHERAL_CLOCK_UART:
#if defined(BSP_USING_UART0)||defined(BSP_USING_UART1)
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_96M
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
return 96000000;
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_FCLK
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
return system_clock_get(SYSTEM_CLOCK_FCLK)/(GLB_Get_HCLK_Div()+1));
#endif
#endif
case PERIPHERAL_CLOCK_SPI:
#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_BCLK
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal,GLB_SPI_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1);
@ -132,7 +181,7 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
#endif
case PERIPHERAL_CLOCK_I2C:
#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_DLL_BCLK
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal=BL_RD_REG(GLB_BASE,GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal,GLB_I2C_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK)/(div+1);
@ -141,9 +190,47 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
case PERIPHERAL_CLOCK_I2S:
return 0;
case PERIPHERAL_CLOCK_ADC:
return 32000000;
#if defined(BSP_USING_ADC0)
#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPADC_32M_SRC_CTRL);
div=BL_GET_REG_BITS_VAL(tmpVal,GLB_GPADC_32M_CLK_DIV);
return 32000000/div;
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
tmpVal=BL_RD_REG(GLB_BASE,GLB_GPADC_32M_SRC_CTRL);
div=BL_GET_REG_BITS_VAL(tmpVal,GLB_GPADC_32M_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_AUPLL)/div;
#endif
#endif
case PERIPHERAL_CLOCK_DAC:
#if defined(BSP_USING_DAC0)
#if BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
tmpVal=BL_RD_REG(GLB_BASE,GLB_DIG32K_WAKEUP_CTRL);
div=BL_GET_REG_BITS_VAL(tmpVal,GLB_DIG_512K_DIV);
return 32000000/(div+1);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL
tmpVal=BL_RD_REG(GLB_BASE,GLB_DIG32K_WAKEUP_CTRL);
div=BL_GET_REG_BITS_VAL(tmpVal,GLB_DIG_512K_DIV);
return system_clock_get(SYSTEM_CLOCK_AUPLL)/div;
#endif
#endif
case PERIPHERAL_CLOCK_PWM:
return system_clock_get(SYSTEM_CLOCK_BCLK);
break;
case PERIPHERAL_CLOCK_CAM:
#if defined(BSP_USING_CAM)
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
return (96000000 / (div + 1));
#endif
#endif
break;
default:
break;
}
(void)(tmpVal);
(void)(div);
return 0;
}

6
drivers/bl702_driver/hal_drv/src/hal_dac.c
View file

@ -29,7 +29,7 @@
#include "bl702_glb.h"
#include "dac_config.h"
dac_device_t dacx_device[] = {
static dac_device_t dacx_device[] = {
#ifdef BSP_USING_DAC0
DAC_CONFIG,
#endif
@ -37,8 +37,8 @@ dac_device_t dacx_device[] = {
int dac_open(struct device *dev, uint16_t oflag)
{
GLB_GPIP_DAC_ChanA_Cfg_Type chCfg;
GLB_GPIP_DAC_Cfg_Type dacCfg ;
GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = {0};
GLB_GPIP_DAC_Cfg_Type dacCfg = {0} ;
dac_device_t *dac_device = (dac_device_t *)dev;
uint8_t dac_ext_ref_pin =0;

14
drivers/bl702_driver/hal_drv/src/hal_dma.c
View file

@ -24,11 +24,11 @@
#include "drv_mmheap.h"
#include "bl702_dma.h"
dma_control_data_t dma_ctrl_cfg;
static dma_control_data_t dma_ctrl_cfg;
void DMA0_IRQ(void);
static void DMA0_IRQ(void);
dma_device_t dmax_device[DMA_MAX_INDEX] =
static dma_device_t dmax_device[DMA_MAX_INDEX] =
{
#ifdef BSP_USING_DMA0_CH0
DMA0_CH0_CONFIG,
@ -66,7 +66,7 @@ int dma_open(struct device *dev, uint16_t oflag)
{
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_LLI_Cfg_Type lliCfg;
DMA_LLI_Cfg_Type lliCfg = {0};
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
@ -129,7 +129,7 @@ int dma_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_CONFIG /* constant-expression */:
{
dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args;
DMA_LLI_Cfg_Type lliCfg;
DMA_LLI_Cfg_Type lliCfg = {0};
lliCfg.dir = cfg->direction;
lliCfg.srcPeriph = cfg->src_req;
@ -429,7 +429,7 @@ void dma_isr(dma_device_t *handle)
if (handle->id == 0)
{
uint32_t DMAChs = DMA_BASE;
for (uint8_t i = 0; i < DMA_CH_MAX; i++)
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++)
{
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0)
@ -446,7 +446,7 @@ void dma_isr(dma_device_t *handle)
}
}
for (uint8_t i = 0; i < DMA_CH_MAX; i++)
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++)
{
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0)

163
drivers/bl702_driver/hal_drv/src/hal_flash.c
View file

@ -25,84 +25,123 @@
#include "bl702_glb.h"
#include "hal_flash.h"
/**
* @brief erase flash memory addr should be 4k aligned or will erase more than size Byte
* each block have 4K Byte
*
* @param addr flash memory block addr
* @param size erase bytes number
* @return int success or not
*/
int flash_erase(uint32_t addr, uint32_t size)
{
SPI_Flash_Cfg_Type flashCfg;
uint32_t ret = 0;
XIP_SFlash_Opt_Enter();
ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg);
XIP_SFlash_Opt_Exit();
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0)
{
return -FLASH_NOT_DETECT;
}
XIP_SFlash_Erase_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, size - 1);
return 0;
}
static SPI_Flash_Cfg_Type g_boot2_flash_cfg;
/**
* @brief read data form flash
* @brief flash_init
*
* @param addr read flash addr
* @param data read data pointer
* @param size read data size
* @return int
*/
int flash_read(uint32_t addr, uint8_t *data, uint32_t size)
int flash_init(void)
{
SPI_Flash_Cfg_Type flashCfg;
uint32_t ret = 0;
XIP_SFlash_Opt_Enter();
ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg);
XIP_SFlash_Opt_Exit();
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0)
{
return -FLASH_NOT_DETECT;
}
XIP_SFlash_Read_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, data, size);
L1C_Cache_Flush(0xf);
SF_Cfg_Get_Flash_Cfg_Need_Lock(0,&g_boot2_flash_cfg);
g_boot2_flash_cfg.ioMode=g_boot2_flash_cfg.ioMode&0x0f;
L1C_Cache_Flush(0xf);
return 0;
}
/**
* @brief write data to flash
* @brief read jedec id
*
* @param addr write flash addr
* @param data write data pointer
* @param size write data size
* @param data
* @return int
*/
int flash_write(uint32_t addr, uint8_t *data, uint32_t size)
int flash_read_jedec_id(uint8_t *data)
{
SPI_Flash_Cfg_Type flashCfg;
uint32_t ret = 0;
XIP_SFlash_Opt_Enter();
ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg);
XIP_SFlash_Opt_Exit();
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0)
{
return -FLASH_NOT_DETECT;
}
XIP_SFlash_Write_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, data, size);
uint32_t jid = 0;
XIP_SFlash_GetJedecId_Need_Lock(&g_boot2_flash_cfg,g_boot2_flash_cfg.ioMode & 0x0f,(uint8_t *)&jid);
jid &= 0xFFFFFF;
BL702_MemCpy(data, (void *)&jid, 4);
return 0;
}
/**
* @brief read xip data
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type flash_read_xip(uint32_t addr,uint8_t *data, uint32_t len)
{
BL702_MemCpy_Fast(data,
(uint8_t *)(BL702_FLASH_XIP_BASE+addr-SF_Ctrl_Get_Flash_Image_Offset()),
len);
return 0;
}
/**
* @brief write xip data
*
* @param addr
* @param data
* @param len
* @return BL_Err_Type
*/
BL_Err_Type flash_write_xip(uint32_t addr, uint8_t *data, uint32_t len)
{
return XIP_SFlash_Write_With_Lock(&g_boot2_flash_cfg,g_boot2_flash_cfg.ioMode & 0x0f,addr,data,len);
}
/**
* @brief erase xip data
*
* @param startaddr
* @param endaddr
* @return BL_Err_Type
*/
BL_Err_Type flash_erase_xip(uint32_t startaddr,uint32_t endaddr)
{
return XIP_SFlash_Erase_With_Lock(&g_boot2_flash_cfg,g_boot2_flash_cfg.ioMode & 0x0f,startaddr,endaddr-startaddr+1);
}
/**
* @brief set flash cache
*
* @param cont_read
* @param cache_enable
* @param cache_way_disable
* @param flash_offset
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read,uint8_t cache_enable,uint8_t cache_way_disable, uint32_t flash_offset)
{
uint32_t tmp[1];
BL_Err_Type stat;
/* To make it simple, exit cont read anyway */
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
SFlash_Reset_Continue_Read(&g_boot2_flash_cfg);
if(g_boot2_flash_cfg.cReadSupport==0){
cont_read=0;
}
if(cont_read==1){
stat=SFlash_Read(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
if(SUCCESS!=stat){
return 0xff;
}
}
/* Set default value */
L1C_Cache_Enable_Set(0xf);
if(cache_enable){
SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
SFlash_Cache_Read_Enable(&g_boot2_flash_cfg, g_boot2_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
}
return 0;
}

51
drivers/bl702_driver/hal_drv/src/hal_gpio.c
View file

@ -23,8 +23,21 @@
#include "bl702_glb.h"
#include "bl702_gpio.h"
#include "hal_gpio.h"
#include "drv_mmheap.h"
static gpio_device_t gpio_device;
static void GPIO_IRQ(void);
struct gpio_int_cfg_private
{
slist_t list;
uint32_t pin;
void (*cbfun)(uint32_t pin);
};
static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);
gpio_device_t gpio_device;
/**
* @brief
*
@ -71,7 +84,7 @@ void gpio_set_mode(uint32_t pin, uint32_t mode)
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
GLB_GPIO_INT0_IRQHandler_Install();
Interrupt_Handler_Register(GPIO_INT0_IRQn,GPIO_IRQ);
if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE)
{
gpio_cfg.pullType = GPIO_PULL_DOWN;
@ -163,9 +176,12 @@ int gpio_read(uint32_t pin)
* @param pin
* @param cbFun
*/
void gpio_attach_irq(uint32_t pin, void (*cbFun)(void))
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin))
{
GLB_GPIO_INT0_Callback_Install(pin, cbFun);
struct gpio_int_cfg_private* int_cfg = mmheap_alloc(sizeof(struct gpio_int_cfg_private));
int_cfg->cbfun = cbfun;
int_cfg->pin = pin;
slist_add_tail(&gpio_int_head,&int_cfg->list);
}
/**
* @brief
@ -186,6 +202,7 @@ void gpio_irq_enable(uint32_t pin, uint8_t enabled)
}
void pin_register(const char *name, uint16_t flag)
{
struct device *dev;
@ -203,3 +220,29 @@ void pin_register(const char *name, uint16_t flag)
device_register(dev, name, flag);
}
static void GPIO_IRQ(void)
{
slist_t *i;
uint32_t timeOut=0;
#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
slist_for_each(i,&gpio_int_head)
{
struct gpio_int_cfg_private* int_cfg = slist_entry(i,struct gpio_int_cfg_private,list);
if(SET==GLB_Get_GPIO_IntStatus(int_cfg->pin))
{
int_cfg->cbfun(int_cfg->pin);
GLB_GPIO_IntClear(int_cfg->pin,SET);
/* timeout check */
timeOut=GLB_GPIO_INT0_CLEAR_TIMEOUT;
do{
timeOut--;
}while((SET==GLB_Get_GPIO_IntStatus(int_cfg->pin))&&timeOut);
if(!timeOut){
MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
}
GLB_GPIO_IntClear(int_cfg->pin,RESET);
}
}
}

4
drivers/bl702_driver/hal_drv/src/hal_i2c.c
View file

@ -26,7 +26,7 @@
#include "bl702_i2c_gpio_sim.h"
#include "bl702_glb.h"
i2c_device_t i2cx_device[I2C_MAX_INDEX] =
static i2c_device_t i2cx_device[I2C_MAX_INDEX] =
{
#ifdef BSP_USING_I2C0
I2C0_CONFIG,
@ -141,7 +141,7 @@ int i2c_register(enum i2c_index_type index, const char *name, uint16_t flag)
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num)
{
i2c_msg_t *msg;
I2C_Transfer_Cfg i2cCfg;
I2C_Transfer_Cfg i2cCfg = {0};
i2c_device_t *i2c_device = (i2c_device_t *)dev;

6
drivers/bl702_driver/hal_drv/src/hal_i2s.c
View file

@ -26,7 +26,7 @@
#include "bl702_glb.h"
#include "i2s_config.h"
i2s_device_t i2sx_device[I2S_MAX_INDEX] =
static i2s_device_t i2sx_device[I2S_MAX_INDEX] =
{
#ifdef BSP_USING_I2S0
I2S0_CONFIG,
@ -36,8 +36,8 @@ i2s_device_t i2sx_device[I2S_MAX_INDEX] =
int i2s_open(struct device *dev, uint16_t oflag)
{
i2s_device_t *i2s_device = (i2s_device_t *)dev;
I2S_CFG_Type i2sCfg;
I2S_FifoCfg_Type fifoCfg;
I2S_CFG_Type i2sCfg = {0};
I2S_FifoCfg_Type fifoCfg = {0};
GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK);
GLB_Set_I2S_CLK(ENABLE,GLB_I2S_OUT_REF_CLK_SRC);

123
drivers/bl702_driver/hal_drv/src/hal_mjpeg.c Normal file
View file

@ -0,0 +1,123 @@
/**
* @file hal_mjpeg.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "bl702_mjpeg.h"
#include "bl702_glb.h"
#include "hal_mjpeg.h"
void mjpeg_init(mjpeg_device_t *mjpeg_cfg)
{
MJPEG_CFG_Type mjpegCfg =
{
.burst = MJPEG_BURST_INCR16,
.quality = mjpeg_cfg->quality,
.yuv = mjpeg_cfg->yuv_format,
.waitCount = 0x400,
.bufferMjpeg = mjpeg_cfg->write_buffer_addr,
.sizeMjpeg = mjpeg_cfg->write_buffer_size,
.bufferCamYY = mjpeg_cfg->read_buffer_addr,
.sizeCamYY = mjpeg_cfg->read_buffer_size,
.bufferCamUV = 0,
.sizeCamUV = 0,
.resolutionX = mjpeg_cfg->resolution_x,
.resolutionY = mjpeg_cfg->resolution_y,
.bitOrderEnable = ENABLE,
.evenOrderEnable = ENABLE,
.swapModeEnable = DISABLE,
.overStopEnable = ENABLE,
.reflectDmy = DISABLE,
.verticalDmy = DISABLE,
.horizationalDmy = DISABLE,
};
static MJPEG_Packet_Type packetCfg =
{
.packetEnable = DISABLE,
.endToTail = DISABLE,
.frameHead = 0,
.frameTail = DISABLE,
.packetHead = 0,
.packetBody = 0,
.packetTail = 0,
};
GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG);
MJPEG_Init(&mjpegCfg);
if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_DEFAULT)
{
packetCfg.packetEnable = ENABLE;
packetCfg.packetHead = mjpeg_cfg->packet_head_length;
packetCfg.packetBody = mjpeg_cfg->packet_body_length;
packetCfg.packetTail = mjpeg_cfg->packet_tail_length;
}
if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_HEAD)
{
packetCfg.frameHead = mjpeg_cfg->frame_head_length;
}
if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_FRAME_TAIL)
{
packetCfg.frameTail = ENABLE;
}
if(mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_END_TAIL)
{
packetCfg.endToTail = ENABLE;
}
MJPEG_Packet_Config(&packetCfg);
if(mjpeg_cfg->yuv_format == MJPEG_YUV_FORMAT_YUV422_INTERLEAVE)
MJPEG_Set_YUYV_Order_Interleave(1,0,3,2);
}
void mjpeg_start(void)
{
MJPEG_Enable();
}
void mjpeg_stop(void)
{
MJPEG_Disable();
}
uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q)
{
MJPEG_Frame_Info info;
arch_memset(&info, 0, sizeof(info));
MJPEG_Get_Frame_Info(&info);
if (info.validFrames == 0)
{
return ERROR;
}
*pic = (uint8_t *)(info.curFrameAddr);
*len = info.curFrameBytes;
*q = info.curFrameQ;
return SUCCESS;
}
void mjpeg_drop_one_frame(void)
{
MJPEG_Pop_Frame();
}

105
drivers/bl702_driver/hal_drv/src/hal_mtimer.c
View file

@ -22,69 +22,56 @@
*/
#include "hal_mtimer.h"
#include "bl702_glb.h"
/**
* @brief
*
*/
void mtimer_init(void)
static void (*systick_callback)(void);
static uint64_t next_compare_tick = 0;
static uint64_t current_set_ticks = 0;
static void Systick_Handler(void)
{
NVIC_DisableIRQ(MTIME_IRQn);
/* Set MTimer the same frequency as SystemCoreClock */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7);
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0;
}
/**
* @brief
*
*/
void mtimer_deinit()
{
NVIC_DisableIRQ(MTIME_IRQn);
mtimer_stop();
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
systick_callback();
next_compare_tick += current_set_ticks;
}
/**
* @brief
*
* @param time
* @param interruptFun
*/
void mtimer_set_alarm_time(uint64_t time, void (*interruptFun)(void))
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void))
{
uint32_t tmp;
NVIC_DisableIRQ(MTIME_IRQn);
tmp = (SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1));
tmp = (tmp >> 3) / 1000;
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME + 4 );
volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( CLIC_CTRL_ADDR + CLIC_MTIME );
volatile uint32_t ulHartId = 0;
time = time * tmp;
current_set_ticks = ticks;
systick_callback = interruptfun;
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = (*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) + time);
__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
do
{
ulCurrentTimeHigh = *pulTimeHigh;
ulCurrentTimeLow = *pulTimeLow;
} while( ulCurrentTimeHigh != *pulTimeHigh );
Interrupt_Handler_Register(MTIME_IRQn, interruptFun);
next_compare_tick = ( uint64_t ) ulCurrentTimeHigh;
next_compare_tick <<= 32ULL;
next_compare_tick |= ( uint64_t ) ulCurrentTimeLow;
next_compare_tick += ( uint64_t ) current_set_ticks;
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIMECMP) = next_compare_tick;
/* Prepare the time to use after the next tick interrupt. */
next_compare_tick += ( uint64_t ) current_set_ticks;
Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler);
NVIC_EnableIRQ(MTIME_IRQn);
}
/**
* @brief
*
*/
void mtimer_start()
{
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0;
}
/**
* @brief
*
*/
void mtimer_stop()
{
}
/**
* @brief
*
*/
void mtimer_clear_time()
{
*(volatile uint64_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0;
}
/**
* @brief
@ -103,33 +90,17 @@ uint64_t mtimer_get_time_ms()
uint64_t mtimer_get_time_us()
{
uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
uint32_t cnt = 0, tmp;
uint32_t tmpValLow, tmpValHigh, tmpValHigh1;
do
{
tmpValLow = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME);
tmpValHigh = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
tmpValLow1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME);
tmpValHigh1 = *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4);
cnt++;
if (cnt > 4)
{
break;
}
} while (tmpValLow > tmpValLow1 || tmpValHigh > tmpValHigh1);
} while (tmpValHigh != tmpValHigh1);
tmp = (SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1));
tmp = (tmp >> 3) / 1000 / 1000;
return (((uint64_t)tmpValHigh << 32) + tmpValLow);
if (tmpValHigh1 == 0)
{
return (uint64_t)(tmpValLow1 / tmp);
}
else
{
return (((uint64_t)tmpValHigh1 << 32) + tmpValLow1) / tmp;
}
}
/**
* @brief

1505
drivers/bl702_driver/hal_drv/src/hal_power.c Normal file
View file

File diff suppressed because it is too large Load diff

200
drivers/bl702_driver/hal_drv/src/hal_pwm.c
View file

@ -27,7 +27,7 @@
#include "bl702_glb.h"
#include "pwm_config.h"
pwm_device_t pwmx_device[PWM_MAX_INDEX] = {
static pwm_device_t pwmx_device[PWM_MAX_INDEX] = {
#ifdef BSP_USING_PWM_CH0
PWM_CH0_CONFIG,
#endif
@ -44,104 +44,81 @@ pwm_device_t pwmx_device[PWM_MAX_INDEX] = {
PWM_CH4_CONFIG,
#endif
};
static void PWM_IRQ(void);
typedef enum{
HZ=0,
KHZ,
MHZ,
}frequency_unit_t;
static void pwm_set(struct device *dev, PWM_CH_CFG_Type * pwmCfg ,uint32_t freq ,frequency_unit_t unit, uint8_t duty){
pwm_device_t *pwm_device = (pwm_device_t *)dev;
switch(unit)
static void pwm_channel_config(uint8_t ch,uint32_t frequence,uint8_t dutycycle)
{
case HZ:
if(freq <= 70){
pwmCfg->clkDiv = 1200;
pwmCfg->period = 60000/freq;
pwmCfg->threshold2 = 600*duty/freq;
}else if(freq <= 140){
pwmCfg->clkDiv = 16;
pwmCfg->period = 4500000/freq;
pwmCfg->threshold2 = 45000*duty/freq;
}else if(freq <= 275){
pwmCfg->clkDiv = 8;
pwmCfg->period = 9000000/freq;
pwmCfg->threshold2 = 90000*duty/freq;
}else if(freq <=550){
pwmCfg->clkDiv = 4;
pwmCfg->period = 18000000/freq;
pwmCfg->threshold2 = 180000*duty/freq;
}else if(freq <=1100){
pwmCfg->clkDiv = 2;
pwmCfg->period = 36000000/freq;
pwmCfg->threshold2 = 360000*duty/freq;
}else{
pwmCfg->clkDiv = 1;
pwmCfg->period = 72000000/freq;
pwmCfg->threshold2 = 720000*duty/freq;
PWM_CH_CFG_Type pwmCfg = {0};
if(frequence <= 70)
{
pwmCfg.clkDiv = 1200;
pwmCfg.period = 60000/frequence;
pwmCfg.threshold2 = 600*dutycycle/frequence;
}
break;
case KHZ:
if(freq <= 2){
pwmCfg->clkDiv = 2;
pwmCfg->period = 36000/freq;
pwmCfg->threshold2 = 360*duty/freq;
}else{
pwmCfg->clkDiv = 1;
pwmCfg->period = 72000/freq;
pwmCfg->threshold2 = 720*duty/freq;
else if(frequence <= 140)
{
pwmCfg.clkDiv = 16;
pwmCfg.period = 4500000/frequence;
pwmCfg.threshold2 = 45000*dutycycle/frequence;
}
break;
case MHZ:
pwmCfg->clkDiv = 1;
pwmCfg->period = 72/freq;
pwmCfg->threshold2 = 72*duty/freq/100;
break;
default:
break;
else if(frequence <= 275)
{
pwmCfg.clkDiv = 8;
pwmCfg.period = 9000000/frequence;
pwmCfg.threshold2 = 90000*dutycycle/frequence;
}
else if(frequence <= 550)
{
pwmCfg.clkDiv = 4;
pwmCfg.period = 18000000/frequence;
pwmCfg.threshold2 = 180000*dutycycle/frequence;
}
else if(frequence <= 1100)
{
pwmCfg.clkDiv = 2;
pwmCfg.period = 36000000/frequence;
pwmCfg.threshold2 = 360000*dutycycle/frequence;
}
else
{
pwmCfg.clkDiv = 1;
pwmCfg.period = 72000000/frequence;
pwmCfg.threshold2 = 720000*dutycycle/frequence;
}
PWM_Channel_Set_Div(pwm_device->ch ,pwmCfg->clkDiv);
PWM_Channel_Update(pwm_device->ch ,pwmCfg->period,0,pwmCfg->threshold2);
PWM_Channel_Set_Div(ch,pwmCfg.clkDiv);
PWM_Channel_Update(ch,pwmCfg.period,0,pwmCfg.threshold2);
}
int pwm_open(struct device *dev, uint16_t oflag)
{
PWM_CH_CFG_Type pwmCfg = {
0, /* PWM channel */
PWM_CLK_BCLK, /* PWM Clock */
PWM_STOP_GRACEFUL, /* PWM Stop Mode */
PWM_POL_NORMAL, /* PWM mode type */
1, /* PWM clkDiv num */
100, /* PWM period set */
0, /* PWM threshold1 num */
50, /* PWM threshold2 num */
0, /* PWM interrupt pulse count */
};
pwm_device_t *pwm_device = (pwm_device_t *)dev;
PWM_CH_CFG_Type pwmCfg = {0};
PWM_Channel_Disable(pwm_device->ch);
PWM_IntMask(pwm_device->ch,PWM_INT_ALL,MASK);
NVIC_DisableIRQ(PWM_IRQn);
pwmCfg.ch = pwm_device->ch;
/* todo clk init at clock tree now clk fix set as bclk*/
pwmCfg.clk = PWM_CLK_BCLK;
pwmCfg.stopMode = PWM_STOP_MODE_SEL;
pwmCfg.pol = PWM_POL_SEL;
PWM_Channel_Init(&pwmCfg);
pwm_channel_config(pwm_device->ch,pwm_device->frequency,pwm_device->dutycycle);
if(pwm_device->frequency < 1000){
pwm_set(dev,&pwmCfg,pwm_device->frequency,HZ,pwm_device->dutyCycle);
}else if(pwm_device->frequency < 999999){
pwm_set(dev,&pwmCfg,pwm_device->frequency /1000,KHZ,pwm_device->dutyCycle);
}else{
pwm_set(dev,&pwmCfg,pwm_device->frequency /1000000,MHZ,pwm_device->dutyCycle);
if (oflag & DEVICE_OFLAG_INT_TX)
{
pwmCfg.intPulseCnt = pwm_device->it_pulse_count;
Interrupt_Handler_Register(PWM_IRQn,PWM_IRQ);
PWM_IntMask(pwm_device->ch,PWM_INT_PULSE_CNT,UNMASK);
NVIC_EnableIRQ(PWM_IRQn);
}
PWM_Channel_Init(&pwmCfg);
PWM_Channel_Enable(pwm_device->ch);
return 0;
}
int pwm_close(struct device *dev)
@ -155,17 +132,10 @@ int pwm_control(struct device *dev, int cmd, void *args)
{
pwm_device_t *pwm_device = (pwm_device_t *)dev;
pwm_config_t *pwm_config = (pwm_config_t *)args;
PWM_CH_CFG_Type pwmCfg;
switch (cmd)
{
case DEVICE_CTRL_CONFIG/* constant-expression */:
if(pwm_device->frequency < 1000){
pwm_set(dev,&pwmCfg,pwm_config->frequency,HZ,pwm_config->dutyCycle);
}else if(pwm_device->frequency < 999999){
pwm_set(dev,&pwmCfg,pwm_config->frequency /1000,KHZ,pwm_config->dutyCycle);
}else{
pwm_set(dev,&pwmCfg,pwm_config->frequency /1000000,MHZ,pwm_config->dutyCycle);
}
pwm_channel_config(pwm_device->ch,pwm_config->frequency,pwm_config->dutycycle);
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
PWM_Channel_Enable(pwm_device->ch);
@ -173,6 +143,25 @@ int pwm_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_SUSPEND /* constant-expression */:
PWM_Channel_Disable(pwm_device->ch);
break;
case DEIVCE_CTRL_PWM_IT_PULSE_COUNT_CONFIG:
{
/* Config interrupt pulse count */
uint32_t pwm_ch_addr = PWM_BASE+PWM_CHANNEL_OFFSET+(pwm_device->ch)*0x20;
uint32_t tmpVal = BL_RD_REG(pwm_ch_addr, PWM_INTERRUPT);
BL_WR_REG(pwm_ch_addr, PWM_INTERRUPT, BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, (uint32_t)args));
if((uint32_t)args)
{
PWM_IntMask(pwm_device->ch,PWM_INT_PULSE_CNT,UNMASK);
NVIC_EnableIRQ(PWM_IRQn);
}
else
{
PWM_IntMask(pwm_device->ch,PWM_INT_PULSE_CNT,MASK);
NVIC_DisableIRQ(PWM_IRQn);
}
break;
}
default:
break;
}
@ -202,3 +191,44 @@ int pwm_register(enum pwm_index_type index, const char *name, uint16_t flag)
return device_register(dev, name, flag);
}
static void pwm_isr(pwm_device_t *handle)
{
uint32_t i;
uint32_t tmpVal;
uint32_t timeoutCnt = 160*1000;
/* Get channel register */
uint32_t PWMx = PWM_BASE;
for (i = 0; i < PWM_MAX_INDEX; i++) {
tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
if ((BL_GET_REG_BITS_VAL(tmpVal, PWM_INTERRUPT_STS) & (1 << handle[i].ch)) != 0) {
/* Clear interrupt */
tmpVal |= (1 << (handle[i].ch + PWM_INT_CLEAR_POS));
BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
/* FIXME: we need set pwm_int_clear to 0 by software and
before this,we must make sure pwm_interrupt_sts is 0*/
do{
tmpVal = BL_RD_REG(PWMx, PWM_INT_CONFIG);
timeoutCnt--;
if(timeoutCnt == 0){
break;
}
}while(BL_GET_REG_BITS_VAL(tmpVal,PWM_INTERRUPT_STS)&(1 << handle[i].ch));
tmpVal &= (~(1 << (handle[i].ch + PWM_INT_CLEAR_POS)));
BL_WR_REG(PWMx, PWM_INT_CONFIG, tmpVal);
if (handle[i].parent.callback)
{
handle[i].parent.callback(&handle[i].parent, NULL, 0, PWM_EVENT_COMPLETE);
}
}
}
}
static void PWM_IRQ(void)
{
pwm_isr(&pwmx_device[0]);
}

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/**
* @file hal_sec_aes.c
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_sec_aes.h"
#include "bl702_sec_eng.h"
static SEC_Eng_AES_Ctx aesCtx;
int sec_aes_init(sec_aes_handle_t *handle,sec_aes_type aes_tye,sec_aes_key_type key_type)
{
handle->aes_type=aes_tye;
handle->key_type=key_type;
return 0;
}
static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle)
{
SEC_ENG_AES_Key_Type type=0;
switch(handle->key_type)
{
case SEC_ASE_KEY_128:
type=SEC_ENG_AES_KEY_128BITS;
break;
case SEC_ASE_KEY_256:
type=SEC_ENG_AES_KEY_256BITS;
break;
case SEC_ASE_KEY_192:
type=SEC_ENG_AES_KEY_192BITS;
break;
default:
return SEC_ENG_AES_KEY_128BITS;
}
return type;
}
int sec_aes_setkey(sec_aes_handle_t *handle,const uint8_t *key,uint8_t key_len,const uint8_t *nonce,uint8_t dir)
{
SEC_ENG_AES_Key_Type type=sec_aes_get_key_type(handle);
switch(handle->aes_type)
{
case SEC_ASE_CBC:
Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
Sec_Eng_AES_Init(&aesCtx,SEC_ENG_AES_ID0,SEC_ENG_AES_CBC,type,
SEC_AES_DIR_ENCRYPT==dir?SEC_ENG_AES_ENCRYPTION:SEC_ENG_AES_DECRYPTION);
break;
case SEC_ASE_CTR:
Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
Sec_Eng_AES_Init(&aesCtx,SEC_ENG_AES_ID0,SEC_ENG_AES_CTR,type,
SEC_AES_DIR_ENCRYPT==dir?SEC_ENG_AES_ENCRYPTION:SEC_ENG_AES_DECRYPTION);
break;
case SEC_ASE_ECB:
break;
default:
return -1;
}
/* if key len is 0, means key is from efuse and *key value is key_sel value */
if(key_len==0){
Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0,SEC_ENG_AES_KEY_HW,key,nonce);
}else{
Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0,SEC_ENG_AES_KEY_SW,key,nonce);
}
return 0;
}
int sec_aes_encrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len, size_t offset,uint8_t *out)
{
if(SUCCESS!=Sec_Eng_AES_Crypt(&aesCtx,SEC_ENG_AES_ID0,in, len,out)){
return -1;
}
return 0;
}
int sec_aes_decrypt(sec_aes_handle_t *handle,const uint8_t *in,uint32_t len,size_t offset,uint8_t *out)
{
if(SUCCESS!=Sec_Eng_AES_Crypt(&aesCtx,SEC_ENG_AES_ID0,in, len,out)){
return -1;
}
return 0;
}
int sec_aes_deinit(sec_aes_handle_t *handle)
{
Sec_Eng_AES_Finish(SEC_ENG_AES_ID0);
memset(handle,0,sizeof(sec_aes_handle_t));
return 0;
}

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drivers/bl702_driver/hal_drv/src/hal_sec_dsa.c Normal file
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/**
* @file hal_sec_dsa.c
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_sec_dsa.h"
#include "bl702_sec_eng.h"
//#define DSA_DBG 1
//#define DSA_DBG_DETAIL 1
void bflb_platform_dump(uint8_t *data, uint32_t len);
#if (defined(DSA_DBG)||defined(DSA_DBG_DETAIL))
uint32_t pka_tmp[64]={0};
#endif
/*
n=p*q;
F(n)=(p-1)*(q-1)
e*d%F(n)=1[e is public key and d is private key]
dP=d%(p-1)
dQ=d%(q-1)
m1=c^(dP)%p
m2=c^(dQ)%q
h=qInv*(m1-m2)%p
m=m2+h*q
m=c^d
*/
static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size)
{
switch(size){
case 64:
return SEC_ENG_PKA_REG_SIZE_8;
case 128:
return SEC_ENG_PKA_REG_SIZE_16;
case 256:
return SEC_ENG_PKA_REG_SIZE_32;
case 512:
return SEC_ENG_PKA_REG_SIZE_64;
case 768:
return SEC_ENG_PKA_REG_SIZE_96;
case 1024:
return SEC_ENG_PKA_REG_SIZE_128;
case 1536:
return SEC_ENG_PKA_REG_SIZE_192;
case 2048:
return SEC_ENG_PKA_REG_SIZE_256;
case 3072:
return SEC_ENG_PKA_REG_SIZE_384;
case 4096:
return SEC_ENG_PKA_REG_SIZE_512;
default:
return SEC_ENG_PKA_REG_SIZE_32;
}
return SEC_ENG_PKA_REG_SIZE_32;
}
/* c code:
number = 1
base = a
while b:
if b & 1:
number = number * base % c
b >>= 1
base = base * base % c
return number
*/
int sec_dsa_mexp_binary(uint32_t size,const uint32_t *a,const uint32_t *b,const uint32_t *c,uint32_t *r)
{
uint32_t i,j,k;
uint32_t tmp;
uint32_t isOne=0;
uint8_t *p=(uint8_t *)b;
SEC_ENG_PKA_REG_SIZE_Type nregType=sec_dsa_get_reg_size(size);
SEC_ENG_PKA_REG_SIZE_Type lregType=sec_dsa_get_reg_size(size*2);
uint32_t dataSize=(size>>3)>>2;
#if 1
uint8_t oneBuf[128] ALIGN4 ={0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01};
#endif
/* 0:c
* 4:a
* 5:number
* 6&7:temp
*/
/* base = a */
Sec_Eng_PKA_Write_Data(nregType,4,(uint32_t *)a,dataSize,0);
/* number = 1 */
Sec_Eng_PKA_Write_Data(nregType,5,(uint32_t *)oneBuf,sizeof(oneBuf)/4,0);
//Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,5,(uint32_t *)pka_tmp,dataSize);
MSG("number:\r\n");
bflb_platform_dump(pka_tmp,dataSize*4);
#endif
Sec_Eng_PKA_Write_Data(nregType,0,(uint32_t *)c,dataSize,0);
Sec_Eng_PKA_CREG(nregType,6,dataSize,1);
Sec_Eng_PKA_CREG(nregType,7,dataSize,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize);
MSG("base:\r\n");
bflb_platform_dump(pka_tmp,dataSize*4);
#endif
/* Remove zeros bytes*/
k=0;
while(p[k]==0&&k<(size>>3)){
k++;
}
i=(size>>3)-1;
for(;i>=k;i--){
tmp=p[i];
j=0;
for(j=0;j<8;j++){
isOne=tmp&(1<<j);
if(isOne){
/* number = number * base % c */
Sec_Eng_PKA_LMUL(lregType,3,nregType,5,nregType,4,0);
Sec_Eng_PKA_MREM(nregType,5,lregType,3,nregType,0,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,5,(uint32_t *)pka_tmp,dataSize);
MSG("number:\r\n");
bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*/);
#endif
}
/* base = base * base % c */
Sec_Eng_PKA_LSQR(lregType,3,nregType,4,0);
Sec_Eng_PKA_MREM(nregType,4,lregType,3,nregType,0,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize);
MSG("base:\r\n");
bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*/);
#endif
}
}
Sec_Eng_PKA_Read_Data(nregType,5,(uint32_t *)r,dataSize);
#ifdef DSA_DBG
MSG("r:\r\n");
bflb_platform_dump(r,dataSize*4);
#endif
return 0;
}
/*r=a^b%c*/
int sec_dsa_mexp_mont(uint32_t size,uint32_t *a,uint32_t *b,uint32_t *c,uint32_t *invR_c,uint32_t *primeN_c,uint32_t *r)
{
SEC_ENG_PKA_REG_SIZE_Type nregType=sec_dsa_get_reg_size(size);
SEC_ENG_PKA_REG_SIZE_Type lregType=sec_dsa_get_reg_size(size*2);
uint32_t dataSize=(size>>3)>>2;
/* 0:c
* 1:NPrime_c
* 2:invR_c
* 4:a(mont domain)
* 5:b
* 6:a^b%c(mont domain)
* 7:a^b%c(gf domain)
* 10&11:2^size for GF2Mont*/
Sec_Eng_PKA_Write_Data(nregType,0,(uint32_t *)c,dataSize,0);
Sec_Eng_PKA_Write_Data(nregType,1,(uint32_t *)primeN_c,dataSize,1);
Sec_Eng_PKA_Write_Data(nregType,2,(uint32_t *)invR_c,dataSize,1);
/* change a into mont domain*/
Sec_Eng_PKA_Write_Data(nregType,4,(uint32_t *)a,dataSize,0);
Sec_Eng_PKA_CREG(nregType,10,dataSize,1);
Sec_Eng_PKA_CREG(nregType,11,dataSize,1);
Sec_Eng_PKA_GF2Mont(nregType,4,nregType,4,size,lregType,5,nregType,0);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize);
MSG("GF2Mont Result of a:\r\n");
bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*/);
#endif
Sec_Eng_PKA_Write_Data(nregType,5,(uint32_t *)b,dataSize,0);
/* a^b%c*/
Sec_Eng_PKA_MEXP(nregType,6,nregType,4,nregType,5,nregType,0,1);
/* change result into gf domain*/
Sec_Eng_PKA_CREG(nregType,10,dataSize,1);
Sec_Eng_PKA_CREG(nregType,11,dataSize,1);
/*index 2 is invertR*/
Sec_Eng_PKA_Mont2GF(nregType,7, nregType,6, nregType, 2,lregType,5,nregType,0);
Sec_Eng_PKA_Read_Data(nregType,7,(uint32_t *)r,dataSize);
#ifdef DSA_DBG
MSG("r:\r\n");
bflb_platform_dump(r,dataSize/*dataSize*4*/);
#endif
return 0;
}
/**
* dP=d%(p-1)
* dQ=d%(q-1)
* qInv=qp^(1-1):qInv*q%p=1
* invR_p*r%p=1(r is 1024/2048/256)
* invR_q*r%q=1(r is 1024/2048/256)
*/
int sec_dsa_decrypt_crt(uint32_t size,uint32_t *c,sec_dsa_crt_cfg_t* crtCfg,uint32_t *d,uint32_t *r)
{
/*
* m1 = pow(c, dP, p)
* m2 = pow(c, dQ, q)
* h = (qInv * (m1 - m2)) % p
* m = m2 + h * q
* */
SEC_ENG_PKA_REG_SIZE_Type nregType=sec_dsa_get_reg_size(size);
SEC_ENG_PKA_REG_SIZE_Type lregType=sec_dsa_get_reg_size(size*2);
uint32_t dataSize=(size>>3)>>2;
#if 0
uint8_t m1[64]={0x11,0xdd,0x19,0x7e,0x69,0x1a,0x40,0x0a,0x28,0xfc,0x3b,0x31,0x47,0xa2,0x6c,0x14,
0x4e,0xf6,0xb0,0xe6,0xcd,0x89,0x0b,0x4f,0x02,0xe4,0x86,0xe2,0xe5,0xbe,0xe1,0xaf,
0x91,0xd1,0x7b,0x59,0x8d,0xdc,0xb3,0x57,0x18,0xcb,0x80,0x05,0x1c,0xb5,0xa4,0x07,
0xde,0x31,0x94,0xa4,0x2f,0x45,0xc7,0x95,0x75,0x0f,0x91,0xf0,0x37,0x91,0x85,0xa5};
uint8_t m2[64]={0x63,0x89,0xa3,0xbb,0x64,0x63,0x87,0x4f,0x38,0xbd,0x9e,0x0e,0x93,0x29,0x58,0xee,
0xf8,0xe2,0x20,0x2d,0xe5,0x38,0x0a,0x7f,0x18,0x38,0x2f,0xa3,0xf5,0x48,0xf8,0xfd,
0xe5,0x78,0x4a,0x10,0x62,0x01,0x09,0x29,0xe3,0xe3,0x9f,0xad,0x9b,0xbe,0x20,0xd2,
0x68,0x90,0x57,0x97,0xfc,0x78,0xd5,0xdb,0x07,0x5b,0xfe,0x21,0x0a,0x2d,0x7f,0xc1};
#else
uint32_t m1[32];
uint32_t m2[32];
#endif
/*
* 4:m1
* 5:m2
* 6:qInv
* 7:p
* 8:q
* 9:h
* 10&11:qInv*(m1-m2)
*/
sec_dsa_mexp_mont(size,c,crtCfg->dP,crtCfg->p,crtCfg->invR_p,crtCfg->primeN_p,m1);
sec_dsa_mexp_mont(size,c,crtCfg->dQ,crtCfg->q,crtCfg->invR_q,crtCfg->primeN_q,m2);
Sec_Eng_PKA_Write_Data(nregType,4,(uint32_t *)m1,dataSize,0);
Sec_Eng_PKA_Write_Data(nregType,5,(uint32_t *)m2,dataSize,0);
Sec_Eng_PKA_Write_Data(nregType,6,(uint32_t *)crtCfg->qInv,dataSize,0);
Sec_Eng_PKA_Write_Data(nregType,7,(uint32_t *)crtCfg->p,dataSize,0);
Sec_Eng_PKA_Write_Data(nregType,8,(uint32_t *)crtCfg->q,dataSize,0);
/*(m1 - m2)%p*/
Sec_Eng_PKA_MSUB(nregType,4,nregType,4,nregType,5,nregType,7,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,4,(uint32_t *)pka_tmp,dataSize);
MSG("m1 - m2:\r\n");
bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*/);
#endif
/* (qInv * (m1 - m2)) % p*/
Sec_Eng_PKA_CREG(nregType,10,dataSize,1);
Sec_Eng_PKA_CREG(nregType,11,dataSize,1);
Sec_Eng_PKA_LMUL(lregType,5,nregType,6,nregType,4,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(lregType,5,(uint32_t *)pka_tmp,dataSize*2);
MSG("qInv * (m1 - m2):\r\n");
bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*2*/);
#endif
Sec_Eng_PKA_MREM(nregType,9,lregType,5,nregType,7,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(nregType,9,(uint32_t *)pka_tmp,dataSize);
MSG("h:\r\n");
bflb_platform_dump(pka_tmp,dataSize*4);
#endif
/* h*q */
Sec_Eng_PKA_CREG(nregType,10,dataSize,1);
Sec_Eng_PKA_CREG(nregType,11,dataSize,1);
Sec_Eng_PKA_LMUL(lregType,5,nregType,9,nregType,8,1);
#ifdef DSA_DBG
Sec_Eng_PKA_Read_Data(lregType,5,(uint32_t *)pka_tmp,dataSize*2);
MSG("h*q:\r\n");
bflb_platform_dump(pka_tmp,dataSize/*dataSize*4*2*/);
#endif
/* m2 + h*q*/
Sec_Eng_PKA_LADD(lregType,5,lregType,5,nregType,5,1);
Sec_Eng_PKA_Read_Data(lregType,5,(uint32_t *)r,dataSize*2);
#ifdef DSA_DBG
MSG("r:\r\n");
bflb_platform_dump(r,dataSize*4*2);
#endif
return 0;
}
int sec_dsa_init(sec_dsa_handle_t * handle,uint32_t size)
{
Sec_Eng_PKA_Reset();
Sec_Eng_PKA_BigEndian_Enable();
memset(handle,0,sizeof(sec_dsa_handle_t));
handle->size=size;
handle->crtSize=(size>>1);
return 0;
}
int sec_dsa_sign(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,uint32_t *s)
{
uint32_t dsa_tmp[64]={0};
Sec_Eng_PKA_Reset();
Sec_Eng_PKA_BigEndian_Enable();
memcpy(dsa_tmp+((handle->crtSize>>3)>>2)-hashLenInWord,hash,hashLenInWord*4);
if(0==sec_dsa_decrypt_crt(handle->crtSize,dsa_tmp,&handle->crtCfg,handle->d,s)){
return 0;
}else{
return -1;
}
}
/**
*/
int sec_dsa_verify(sec_dsa_handle_t * handle,const uint32_t *hash,uint32_t hashLenInWord,const uint32_t *s)
{
uint32_t dsa_tmp[64];
uint8_t i=0;
uint8_t resultOffset=0;
Sec_Eng_PKA_Reset();
Sec_Eng_PKA_BigEndian_Enable();
if(0==sec_dsa_mexp_binary(handle->size,s,handle->e,handle->n,dsa_tmp)){
resultOffset=(handle->size>>5)-hashLenInWord;
for(i=0;i<hashLenInWord;i++){
if(dsa_tmp[resultOffset+i]!=hash[i]){
return -1;
}
}
return 0;
}else{
return -1;
}
}

1202
drivers/bl702_driver/hal_drv/src/hal_sec_ecdsa.c Normal file
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243
drivers/bl702_driver/hal_drv/src/hal_sec_hash.c Normal file
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/**
* @file hal_sec_hash.c
* @brief
*
* Copyright 2019-2030 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_sec_hash.h"
#include "bl702_sec_eng.h"
void SEC_SHA_IRQHandler(void);
static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] =
{
0
};
static SEC_Eng_SHA256_Ctx shaCtx;
/**
* @brief
*
* @param dev
* @param oflag
* @return int
*/
int sec_hash_open(struct device *dev, uint16_t oflag)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
int ret=0;
switch(sec_hash_device->type)
{
case SEC_HASH_SHA1 :
ret=-1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Init(&shaCtx,SEC_ENG_SHA_ID0,SEC_ENG_SHA224,sec_hash_device->shaBuf,sec_hash_device->shaPadding);
Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
break;
case SEC_HASH_SHA256 :
Sec_Eng_SHA256_Init(&shaCtx,SEC_ENG_SHA_ID0,SEC_ENG_SHA256,sec_hash_device->shaBuf,sec_hash_device->shaPadding);
Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0);
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret=-1;
break;
default:
ret=-1;
break;
}
return ret;
}
/**
* @brief
*
* @param dev
* @return int
*/
int sec_hash_close(struct device *dev)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
memset(sec_hash_device,0,sizeof(sec_hash_device_t));
return 0;
}
/**
* @brief
*
* @param dev
* @param cmd
* @param args
* @return int
*/
int sec_hash_control(struct device *dev, int cmd, void *args)
{
return 0;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
int ret = 0;
switch(sec_hash_device->type)
{
case SEC_HASH_SHA1 :
ret=-1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Update(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t*)buffer, size);
break;
case SEC_HASH_SHA256 :
Sec_Eng_SHA256_Update(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t*)buffer, size);
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret=-1;
break;
default:
ret=-1;
break;
}
return ret;
}
/**
* @brief
*
* @param dev
* @param pos
* @param buffer
* @param size
* @return int
*/
int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev;
int ret = 0;
switch(sec_hash_device->type)
{
case SEC_HASH_SHA1 :
ret=-1;
break;
case SEC_HASH_SHA224:
Sec_Eng_SHA256_Finish(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t *)buffer);
ret=28;
break;
case SEC_HASH_SHA256 :
Sec_Eng_SHA256_Finish(&shaCtx,SEC_ENG_SHA_ID0,(uint8_t *)buffer);
ret=32;
break;
case SEC_HASH_SHA384:
case SEC_HASH_SHA512:
ret=-1;
break;
default:
ret=-1;
break;
}
return ret;
}
/**
* @brief
*
* @param index
* @param type
* @param name
* @param flag
* @return int
*/
static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type,const char *name, uint16_t flag)
{
struct device *dev;
if(SEC_HASH_MAX_INDEX == 0)
return -DEVICE_EINVAL;
dev = &(sec_hashx_device[index].parent);
sec_hashx_device[index].type=type;
dev->open = sec_hash_open;
dev->close = sec_hash_close;
dev->control = sec_hash_control;
dev->write = sec_hash_write;
dev->read = sec_hash_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_SEC_HASH;
dev->handle = NULL;
return device_register(dev, name, flag);
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name, uint16_t flag)
{
return sec_hash_sha_register(index,SEC_HASH_SHA256, name, flag);
}
/**
* @brief
*
* @param index
* @param name
* @param flag
* @return int
*/
int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name, uint16_t flag)
{
return sec_hash_sha_register(index,SEC_HASH_SHA224, name, flag);
}
/**
* @brief
*
* @param handle
*/
void sec_hash_isr(sec_hash_device_t *handle)
{
}
/**
* @brief
*
*/
void SEC_SHA_IRQ(void)
{
sec_hash_isr(&sec_hashx_device[0]);
}

8
drivers/bl702_driver/hal_drv/src/hal_spi.c
View file

@ -28,10 +28,10 @@
#include "spi_config.h"
#ifdef BSP_USING_SPI0
void SPI0_IRQ(void);
static void SPI0_IRQ(void);
#endif
spi_device_t spix_device[SPI_MAX_INDEX] =
static spi_device_t spix_device[SPI_MAX_INDEX] =
{
#ifdef BSP_USING_SPI0
SPI0_CONFIG,
@ -47,8 +47,8 @@ spi_device_t spix_device[SPI_MAX_INDEX] =
int spi_open(struct device *dev, uint16_t oflag)
{
spi_device_t *spi_device = (spi_device_t *)dev;
SPI_CFG_Type spiCfg;
SPI_FifoCfg_Type fifoCfg;
SPI_CFG_Type spiCfg = {0};
SPI_FifoCfg_Type fifoCfg = {0};
#if SPI_SWAP_ENABLE
GLB_Swap_SPI_0_MOSI_With_MISO(ENABLE);
#endif

87
drivers/bl702_driver/hal_drv/src/hal_timer.c
View file

@ -31,7 +31,7 @@
void TIMER_CH0_IRQ(void);
void TIMER_CH1_IRQ(void);
timer_device_t timerx_device[TIMER_MAX_INDEX] =
static timer_device_t timerx_device[TIMER_MAX_INDEX] =
{
#ifdef BSP_USING_TIMER_CH0
TIMER_CH0_CONFIG,
@ -51,7 +51,7 @@ timer_device_t timerx_device[TIMER_MAX_INDEX] =
int timer_open(struct device *dev, uint16_t oflag)
{
timer_device_t *timer_device = (timer_device_t *)dev;
TIMER_CFG_Type timer_cfg;
TIMER_CFG_Type timer_cfg = {0};
timer_cfg.timerCh = timer_device->ch;
timer_cfg.clkSrc = TIMER_CLK_SRC;
@ -77,10 +77,12 @@ int timer_open(struct device *dev, uint16_t oflag)
TIMER_ClearIntStatus(timer_device->ch,TIMER_COMP_ID_2);
#ifdef BSP_USING_TIMER_CH0
if(oflag == DEVICE_OFLAG_INT)
if( timer_device->ch == TIMER_CH0)
Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQ);
#endif
#ifdef BSP_USING_TIMER_CH1
if(oflag == DEVICE_OFLAG_INT)
if( timer_device->ch == TIMER_CH1)
Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQ);
#endif
@ -116,15 +118,6 @@ int timer_control(struct device *dev, int cmd, void *args)
{
case DEVICE_CTRL_SET_INT /* constant-expression */:
{
uint32_t offset = __builtin_ctz((uint32_t)args);
while((0 <= offset) && (offset < 4))
{
if((uint32_t)args & (1 << offset))
{
TIMER_IntMask(timer_device->ch, offset, UNMASK);
}
offset ++;
}
if(timer_device->ch == TIMER_CH0)
{
NVIC_ClearPendingIRQ(TIMER_CH0_IRQn);
@ -135,20 +128,13 @@ int timer_control(struct device *dev, int cmd, void *args)
NVIC_ClearPendingIRQ(TIMER_CH1_IRQn);
NVIC_EnableIRQ(TIMER_CH1_IRQn);
}
break;
}
case DEVICE_CTRL_CLR_INT /* constant-expression */:
{
uint32_t offset = __builtin_ctz((uint32_t)args);
while((0 <= offset) && (offset < 4))
{
if ((uint32_t)args & (1 << offset))
{
TIMER_IntMask(timer_device->ch, offset, MASK);
}
offset ++;
}
timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(args));
uint32_t offset = __builtin_ctz((uint32_t)timer_user_cfg->comp_it);
if(timer_device->ch == TIMER_CH0)
{
NVIC_DisableIRQ(TIMER_CH0_IRQn);
@ -157,7 +143,15 @@ int timer_control(struct device *dev, int cmd, void *args)
{
NVIC_DisableIRQ(TIMER_CH1_IRQn);
}
while((0 <= offset) && (offset < 4))
{
if ((uint32_t)timer_user_cfg->comp_it & (1 << offset))
{
TIMER_SetCompValue(timer_device->ch,offset,TIMER_MAX_VALUE);
TIMER_IntMask(timer_device->ch, offset, MASK);
}
offset ++;
}
break;
}
case DEVICE_CTRL_GET_INT /* constant-expression */:
@ -168,24 +162,26 @@ int timer_control(struct device *dev, int cmd, void *args)
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
{
uint32_t offset = __builtin_ctz((uint32_t)args);
timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(timer_device->parent.handle));
uint32_t timeout = (timer_user_cfg->timeout_val * 144 * 1000);
/* Enable timer */
TIMER_Enable(timer_device->ch);
break;
}
case DEVICE_CTRL_SUSPEND /* constant-expression */:
{
TIMER_Disable(timer_device->ch);
break;
}
case DEVICE_CTRL_TIMER_CH_START:
{
timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(args));
uint32_t offset = __builtin_ctz((uint32_t)timer_user_cfg->comp_it);
uint32_t timeout = (timer_user_cfg->timeout_val * 144);
TIMER_SetPreloadValue(timer_device->ch, 0);
if(timer_device->ch == TIMER_CH0)
{
NVIC_ClearPendingIRQ(TIMER_CH0_IRQn);
NVIC_EnableIRQ(TIMER_CH0_IRQn);
}
else if(timer_device->ch == TIMER_CH1)
{
NVIC_ClearPendingIRQ(TIMER_CH1_IRQn);
NVIC_EnableIRQ(TIMER_CH1_IRQn);
}
while((0 <= offset) && (offset < 4))
{
if((uint32_t)args & (1 << offset))
if((uint32_t)timer_user_cfg->comp_it & (1 << offset))
{
TIMER_SetCompValue(timer_device->ch,offset,timeout);
TIMER_IntMask(timer_device->ch, offset, UNMASK);
@ -196,10 +192,10 @@ int timer_control(struct device *dev, int cmd, void *args)
TIMER_Enable(timer_device->ch);
break;
}
case DEVICE_CTRL_SUSPEND /* constant-expression */:
case DEVICE_CTRL_TIMER_CH_STOP:
{
TIMER_Disable(timer_device->ch);
uint32_t offset = __builtin_ctz((uint32_t)args);
timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(args));
uint32_t offset = __builtin_ctz((uint32_t)timer_user_cfg->comp_it);
if(timer_device->ch == TIMER_CH0)
{
@ -211,18 +207,25 @@ int timer_control(struct device *dev, int cmd, void *args)
}
while((0 <= offset) && (offset < 4))
{
if ((uint32_t)args & (1 << offset))
if ((uint32_t)timer_user_cfg->comp_it & (1 << offset))
{
TIMER_SetCompValue(timer_device->ch,offset,TIMER_MAX_VALUE);
TIMER_IntMask(timer_device->ch, offset, MASK);
}
offset ++;
}
TIMER_Disable(timer_device->ch);
break;
}
case DEVICE_CTRL_GET_CONFIG:
return TIMER_GetCounterValue(timer_device->ch);
break;
case DEVICE_CTRL_GET_MATCH_STATUS:
{
uint32_t tmpval = (uint32_t)args;
return TIMER_GetMatchStatus(timer_device->ch, tmpval);
break;
}
default:
break;
}
@ -250,7 +253,7 @@ int timer_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
* @return int
*/
int timer_register(enum timer_index_type index, const char *name, uint16_t flag, timer_user_cfg_t *timer_user_cfg)
int timer_register(enum timer_index_type index, const char *name, uint16_t flag)
{
struct device *dev;
@ -267,7 +270,7 @@ int timer_register(enum timer_index_type index, const char *name, uint16_t flag,
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_TIMER;
dev->handle = timer_user_cfg;
dev->handle = NULL;
return device_register(dev, name, flag);
}

22
drivers/bl702_driver/hal_drv/src/hal_uart.c
View file

@ -29,13 +29,13 @@
#include "uart_config.h"
#ifdef BSP_USING_UART0
void UART0_IRQ(void);
static void UART0_IRQ(void);
#endif
#ifdef BSP_USING_UART1
void UART1_IRQ(void);
static void UART1_IRQ(void);
#endif
uart_device_t uartx_device[UART_MAX_INDEX] =
static uart_device_t uartx_device[UART_MAX_INDEX] =
{
#ifdef BSP_USING_UART0
UART0_CONFIG,
@ -54,8 +54,8 @@ uart_device_t uartx_device[UART_MAX_INDEX] =
int uart_open(struct device *dev, uint16_t oflag)
{
uart_device_t *uart_device = (uart_device_t *)dev;
UART_FifoCfg_Type fifoCfg;
UART_CFG_Type uart_cfg;
UART_FifoCfg_Type fifoCfg = {0};
UART_CFG_Type uart_cfg = {0};
/* disable all interrupt */
UART_IntMask(uart_device->id, UART_INT_ALL, MASK);
@ -184,6 +184,12 @@ int uart_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
break;
case DEVICE_CTRL_RESUME /* constant-expression */:
UART_Enable(uart_device->id, UART_TXRX);
break;
case DEVICE_CTRL_SUSPEND /* constant-expression */:
UART_Disable(uart_device->id, UART_TXRX);
break;
case DEVICE_CTRL_CONFIG /* constant-expression */:
{
uart_param_cfg_t* cfg = (uart_param_cfg_t *)args;
@ -305,7 +311,7 @@ int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t si
* @param size
* @return int
*/
int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
int ATTR_TCM_SECTION uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX)
@ -361,7 +367,7 @@ int uart_register(enum uart_index_type index, const char *name, uint16_t flag)
*
* @param handle
*/
void uart_isr(uart_device_t *handle)
void ATTR_TCM_SECTION uart_isr(uart_device_t *handle)
{
uint32_t tmpVal = 0;
uint32_t maskVal = 0;
@ -442,7 +448,7 @@ void uart_isr(uart_device_t *handle)
* @brief
*
*/
void UART0_IRQ(void)
void ATTR_TCM_SECTION UART0_IRQ(void)
{
uart_isr(&uartx_device[UART0_INDEX]);
}

127
drivers/bl702_driver/hal_drv/src/hal_usb.c
View file

@ -21,6 +21,7 @@
*
*/
#include "hal_usb.h"
#include "hal_dma.h"
#include "hal_mtimer.h"
#include "bl702_usb.h"
#include "bl702_glb.h"
@ -36,6 +37,24 @@
usb_dc_device_t usb_fs_device;
static dma_lli_ctrl_t usb_lli_list =
{
.src_addr = 0,
.dst_addr = 0,
.nextlli = 0,
.cfg.bits.fix_cnt = 0,
.cfg.bits.dst_min_mode = 0,
.cfg.bits.dst_add_mode = 0,
.cfg.bits.SI = 0,
.cfg.bits.DI = 0,
.cfg.bits.SWidth = DMA_TRANSFER_WIDTH_8BIT,
.cfg.bits.DWidth = DMA_TRANSFER_WIDTH_8BIT,
.cfg.bits.SBSize = 0,
.cfg.bits.DBSize = 0,
.cfg.bits.I = 0,
.cfg.bits.TransferSize = 0
};
static void usb_set_power_up(void)
{
uint32_t tmpVal = 0;
@ -192,7 +211,7 @@ static void usb_xcvr_config(BL_Fun_Type NewState)
*/
int usb_open(struct device *dev, uint16_t oflag)
{
USB_Config_Type usbCfg;
USB_Config_Type usbCfg = {0};
usb_set_power_off();
mtimer_delay_ms(10);
@ -305,6 +324,7 @@ int usb_close(struct device *dev)
*/
int usb_control(struct device *dev, int cmd, void *args)
{
struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
switch (cmd)
{
case DEVICE_CTRL_SET_INT /* constant-expression */:
@ -379,6 +399,18 @@ int usb_control(struct device *dev, int cmd, void *args)
return USB_Get_EPx_RX_FIFO_CNT(((uint32_t)args) & 0x7f);
case DEVICE_CTRL_USB_DC_GET_EP_FREE:
return USB_Is_EPx_RDY_Free(((uint32_t)args) & 0x7f);
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
usb_device->tx_dma = (struct device *)args;
break;
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
usb_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_USB_DC_SET_TX_DMA /* constant-expression */:
USB_Set_EPx_TX_DMA_Interface_Config(((uint32_t)args) & 0x7f,ENABLE);
break;
case DEVICE_CTRL_USB_DC_SET_RX_DMA /* constant-expression */:
USB_Set_EPx_RX_DMA_Interface_Config(((uint32_t)args) & 0x7f,ENABLE);
break;
default:
break;
}
@ -387,67 +419,57 @@ int usb_control(struct device *dev, int cmd, void *args)
int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
uint8_t ret = 0;
uint8_t *p = (uint8_t*)buffer;
struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
uint8_t ep_idx = USB_EP_GET_IDX(pos);
while(size)
if(usb_device->in_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC)
{
if(USB_Is_EPx_RDY_Free(pos & 0x7f))
{
uint8_t len = USB_Get_EPx_TX_FIFO_CNT(pos & 0x7f);
if(len)
{
if(len < size)
{
ret = usb_dc_ep_write(dev,pos,p,len,NULL);
size -= len;
p += len;
uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x10;
dma_channel_stop(usb_device->tx_dma);
usb_lli_list.src_addr = (uint32_t)buffer;
usb_lli_list.dst_addr = usb_ep_addr;
usb_lli_list.cfg.bits.TransferSize = size;
usb_lli_list.cfg.bits.DI = 0;
usb_lli_list.cfg.bits.SI = 1;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE;
device_control(usb_device->tx_dma,DMA_CHANNEL_UPDATE,(void*)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->tx_dma);
}
else
{
ret = usb_dc_ep_write(dev,pos,p,size,NULL);
p += size;
size = 0;
}
}
}
}
if(!(size%64))
{
ret = usb_dc_ep_write(dev,pos,NULL,0,NULL);
}
return ret;
return 0;
}
int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
uint32_t total_rx_len = 0;
uint8_t ret = 0;
uint8_t *p = (uint8_t*)buffer;
struct usb_dc_device *usb_device = (struct usb_dc_device *)dev;
uint8_t ep_idx = USB_EP_GET_IDX(pos);
while(total_rx_len < size)
if(usb_device->out_ep[ep_idx].ep_cfg.ep_type == USBD_EP_TYPE_ISOC)
{
if(USB_Is_EPx_RDY_Free(pos))
{
uint8_t len = USB_Get_EPx_RX_FIFO_CNT(pos);
if(len)
{
ret = usb_dc_ep_read(dev,pos,p,len,NULL);
ret = usb_dc_ep_read(dev,pos,NULL,0,NULL);
total_rx_len += len;
p += len;
uint32_t usb_ep_addr = USB_BASE + 0x308 + ep_idx * 0x1c;
dma_channel_stop(usb_device->tx_dma);
usb_lli_list.src_addr = usb_ep_addr;
usb_lli_list.dst_addr = (uint32_t)buffer;
usb_lli_list.cfg.bits.TransferSize = size;
usb_lli_list.cfg.bits.DI = 1;
usb_lli_list.cfg.bits.SI = 0;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE;
device_control(usb_device->rx_dma,DMA_CHANNEL_UPDATE,(void*)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->rx_dma);
}
else
{
ret = usb_dc_ep_read(dev,pos,NULL,0,NULL);
}
}
}
return ret;
}
return 0;
}
/**
* @brief
@ -675,7 +697,7 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
do
{
uint32_t avail_space = USB_Get_EPx_TX_FIFO_CNT(ep_idx);
if (avail_space == usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps)
if (avail_space >= usb_fs_device.in_ep[ep_idx].ep_cfg.ep_mps)
{
break;
}
@ -755,7 +777,7 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t
USB_DC_LOG_ERR("Not enabled endpoint\r\n");
return -1;
}
/*common process for other ep out*/
if(ep_idx)
{
while (!USB_Is_EPx_RDY_Free(ep_idx))
@ -768,6 +790,19 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t
}
}
}
/*special process for ep0 out*/
else if(read_bytes && data_len && (ep_idx == 0))
{
while(((BL_RD_WORD(0x4000D800) & (1 << 28)) >> 28))
{
timeout--;
if (!timeout)
{
USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep);
return -USB_DC_EP_TIMEOUT_ERR;
}
}
}
/* Allow to read 0 bytes */
if (!data_len)

32
drivers/bl702_driver/regs/bl702.h
View file

@ -10,38 +10,6 @@
/**
* @brief Configuration of the Processor and Core Peripherals
*/
/**
* @brief Memory access macro
*/
#define BL_RD_WORD(addr) (*((volatile uint32_t*)(addr)))
#define BL_WR_WORD(addr,val) ((*(volatile uint32_t*)(addr))=(val))
#define BL_RD_SHORT(addr) (*((volatile uint16_t*)(addr)))
#define BL_WR_SHORT(addr,val) ((*(volatile uint16_t*)(addr))=(val))
#define BL_RD_BYTE(addr) (*((volatile uint8_t*)(addr)))
#define BL_WR_BYTE(addr,val) ((*(volatile uint8_t*)(addr))=(val))
#define BL_RDWD_FRM_BYTEP(p) ((p[3]<<24)|(p[2]<<16)|(p[1]<<8)|(p[0]))
#define BL_WRWD_TO_BYTEP(p,val) {p[0]=val&0xff;p[1]=(val>>8)&0xff;p[2]=(val>>16)&0xff;p[3]=(val>>24)&0xff;}
/**
* @brief Register access macro
*/
#define BL_RD_REG16(addr,regname) BL_RD_SHORT(addr+regname##_OFFSET)
#define BL_WR_REG16(addr,regname,val) BL_WR_SHORT(addr+regname##_OFFSET,val)
#define BL_RD_REG(addr,regname) BL_RD_WORD(addr+regname##_OFFSET)
#define BL_WR_REG(addr,regname,val) BL_WR_WORD(addr+regname##_OFFSET,val)
#define BL_SET_REG_BIT(val,bitname) ( (val) |(1U<<bitname##_POS))
#define BL_CLR_REG_BIT(val,bitname) ( (val) & bitname##_UMSK )
#define BL_GET_REG_BITS_VAL(val,bitname) ( ((val) & bitname##_MSK) >> bitname##_POS )
#define BL_SET_REG_BITS_VAL(val,bitname,bitval) ( ((val)&bitname##_UMSK) | ((uint32_t)(bitval)<<bitname##_POS) )
#define BL_IS_REG_BIT_SET(val,bitname) ( ((val)&(1U<<(bitname##_POS))) !=0 )
#define BL_DRV_DUMMY {__NOP();__NOP();__NOP();__NOP();}
/* Std driver attribute macro*/
#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const")))
#define ATTR_TCM_SECTION __attribute__((section(".tcm_code")))
#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
/* fix 57.6M */
#define SystemCoreClockSet(val) if(val==57*6000*1000){ \

2
drivers/bl702_driver/startup/interrupt.c
View file

@ -103,7 +103,7 @@ const pFunc __Vectors[] __attribute__ ((section(".init"),aligned(64))) = {
clic_mtimer_handler_Wrapper, /* 7 */
(pFunc)0x00000001, /* */
0, /* */
(pFunc)0x00000000, /* */
(pFunc)0x00000100, /* */ //disable log as default
clic_mext_handler_Wrapper, /* 11 */
clic_csoft_handler_Wrapper, /* 12 */
0, /* */

3
drivers/bl702_driver/startup/system_bl702.c
View file

@ -168,6 +168,9 @@ void SystemInit (void)
//GLB_Power_On_LDO18_IO();
#endif
/* release 64K OCARAM for appliction */
GLB_Set_EM_Sel(GLB_EM_0KB);
}
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{

4
drivers/bl702_driver/std_drv/inc/bl702_adc.h
View file

@ -516,6 +516,7 @@ void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg);
uint8_t ADC_Get_FIFO_Count(void);
BL_Sts_Type ADC_FIFO_Is_Empty(void);
BL_Sts_Type ADC_FIFO_Is_Full(void);
void ADC_FIFO_Clear(void);
uint32_t ADC_Read_FIFO(void);
void ADC_Parse_Result(uint32_t *orgVal,uint32_t len,ADC_Result_Type *result);
void ADC_IntClr(ADC_INT_Type intType);
@ -525,6 +526,9 @@ void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask);
void ADC_SET_TSVBE_LOW(void);
void ADC_SET_TSVBE_HIGH(void);
void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod);
void ADC_Tsen_Enable(void);
void ADC_Tsen_Disable(void);
void ADC_PGA_Config(uint8_t pga_vcmi_enable , uint8_t pga_os_cal);
BL_Err_Type ADC_Mic_Init(ADC_MIC_Type * adc_mic_config);
void ADC_MIC_Bias_Disable(void);
void ADC_MIC_Bias_Enable(void);

4
drivers/bl702_driver/std_drv/inc/bl702_gpio.h
View file

@ -157,8 +157,8 @@ typedef enum
GPIO_FUN_UART1_CTS = 0x75 ,
GPIO_FUN_UART1_TX = 0x76 ,
GPIO_FUN_UART1_RX = 0x77 ,
GPIO_FUN_GPIO_OUTPUT = 0x80,
GPIO_FUN_GPIO_INPUT = 0x81,
GPIO_FUN_DAC = 0xa0,
GPIO_FUN_ADC = 0xa1,
GPIO_FUN_UNUSED = 255
}GLB_GPIO_FUNC_Type;

1
drivers/bl702_driver/std_drv/inc/bl702_sec_eng.h
View file

@ -482,6 +482,7 @@ BL_Err_Type Sec_Eng_Trng_Enable(void);
void Sec_Eng_Trng_Int_Enable(void);
void Sec_Eng_Trng_Int_Disable(void);
BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]);
BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data,uint32_t len);
void Sec_Eng_Trng_Int_Read_Trigger(void);
void Sec_Eng_Trng_Int_Read(uint8_t data[32]);
void Sec_Eng_Trng_Disable(void);

70
drivers/bl702_driver/std_drv/src/bl702_adc.c
View file

@ -1035,6 +1035,76 @@ void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod)
BL_WR_REG(AON_BASE,AON_GPADC_REG_CMD,tmpVal);
}
/****************************************************************************//**
* @brief ADC TSEN Enable
*
* @return None
*
*******************************************************************************/
void ADC_Tsen_Enable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2);
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_TS_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal);
}
/****************************************************************************//**
* @brief ADC TSEN Disable
*
* @return None
*
*******************************************************************************/
void ADC_Tsen_Disable(void)
{
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2);
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_TS_EN);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal);
}
/****************************************************************************//**
* @brief ADC Clear fifo
*
* @return None
*
*******************************************************************************/
void ADC_FIFO_Clear(void)
{
uint32_t tmpVal;
/* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/
tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR);
BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal);
}
/****************************************************************************//**
* @brief config pga
*
* @param pga_vcmi_enable: enable or not vcmi
* @param pga_os_cal: pga os cal value
* @return None
*
*******************************************************************************/
void ADC_PGA_Config(uint8_t pga_vcmi_enable , uint8_t pga_os_cal){
uint32_t tmpVal;
tmpVal=BL_RD_REG(AON_BASE,AON_GPADC_REG_CONFIG2);
if(pga_vcmi_enable){
tmpVal=BL_SET_REG_BIT(tmpVal,AON_GPADC_PGA_VCMI_EN);
}else{
tmpVal=BL_CLR_REG_BIT(tmpVal,AON_GPADC_PGA_VCMI_EN);
}
tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_GPADC_PGA_OS_CAL,pga_os_cal);
BL_WR_REG(AON_BASE,AON_GPADC_REG_CONFIG2,tmpVal);
}
/****************************************************************************//**
* @brief TSEN_Get_V_Error
*

33
drivers/bl702_driver/std_drv/src/bl702_sec_eng.c
View file

@ -1454,6 +1454,39 @@ BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32])
return SUCCESS;
}
/****************************************************************************//**
* @brief TRNG get random data out
*
* @param data: TRNG output data buffer
*
* @param len: total length to get in bytes
*
* @return SUCCESS
*
*******************************************************************************/
BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data,uint32_t len)
{
uint8_t tmpBuf[32];
uint32_t readLen = 0;
uint32_t i = 0, cnt = 0;
while(readLen < len){
if(Sec_Eng_Trng_Read(tmpBuf) != SUCCESS){
return -1;
}
cnt = len - readLen;
if(cnt > sizeof(tmpBuf)){
cnt = sizeof(tmpBuf);
}
for(i = 0; i < cnt; i ++){
data[readLen + i] = tmpBuf[i];
}
readLen += cnt;
}
return 0;
}
/****************************************************************************//**
* @brief TRNG Interrupt Read Trigger
*

4
drivers/bl702_driver/std_drv/src/bl702_uart.c
View file

@ -972,7 +972,7 @@ BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t* data,uint32_t len)
* @return The length of the received buffer
*
*******************************************************************************/
uint32_t UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen)
uint32_t ATTR_TCM_SECTION UART_ReceiveData(UART_ID_Type uartId,uint8_t* data,uint32_t maxLen)
{
uint32_t rxLen = 0;
uint32_t UARTx = uartAddr[uartId];
@ -1039,7 +1039,7 @@ uint8_t UART_GetTxFifoCount(UART_ID_Type uartId)
* @return Rx fifo occupied count value
*
*******************************************************************************/
uint8_t UART_GetRxFifoCount(UART_ID_Type uartId)
uint8_t ATTR_TCM_SECTION UART_GetRxFifoCount(UART_ID_Type uartId)
{
uint32_t UARTx = uartAddr[uartId];