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[sync] sync code from internal

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This commit is contained in:
jzlv 2023-02-24 21:33:12 +08:00
parent e70e482d21
commit dd161b698b
302 changed files with 36006 additions and 27903 deletions
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40
drivers/lhal/include/bflb_clock.h
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@ -144,13 +144,6 @@
} while (0)
#endif
#define PERIPHERAL_CLOCK_I2S_ENABLE() \
do { \
volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
regval |= (1 << 27); \
putreg32(regval, BFLB_GLB_CGEN1_BASE); \
} while (0)
#if defined(BL702)
#define PERIPHERAL_CLOCK_USB_ENABLE() \
do { \
@ -158,6 +151,14 @@
regval |= (1 << 28); \
putreg32(regval, BFLB_GLB_CGEN1_BASE); \
} while (0)
#define PERIPHERAL_CLOCK_I2S_ENABLE() \
do { \
volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
regval |= (1 << 26); \
putreg32(regval, BFLB_GLB_CGEN1_BASE); \
} while (0)
#elif defined(BL616) || defined(BL606P) || defined(BL808)
#define PERIPHERAL_CLOCK_USB_ENABLE() \
do { \
@ -166,6 +167,13 @@
putreg32(regval, BFLB_GLB_CGEN1_BASE); \
} while (0)
#define PERIPHERAL_CLOCK_I2S_ENABLE() \
do { \
volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
regval |= (1 << 27); \
putreg32(regval, BFLB_GLB_CGEN1_BASE); \
} while (0)
#endif
#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
@ -177,7 +185,14 @@
} while (0)
#endif
#if defined(BL616)
#if defined(BL702)
#define PERIPHERAL_CLOCK_EMAC_ENABLE() \
do { \
volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
regval |= (1 << 13); \
putreg32(regval, BFLB_GLB_CGEN1_BASE); \
} while (0)
#elif defined(BL616) || defined(BL606P) || defined(BL808)
#define PERIPHERAL_CLOCK_EMAC_ENABLE() \
do { \
volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
@ -186,6 +201,15 @@
} while (0)
#endif
#if defined(BL616)
#define PERIPHERAL_CLOCK_AUDIO_ENABLE() \
do { \
volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
regval |= (1 << 21); \
putreg32(regval, BFLB_GLB_CGEN2_BASE); \
} while (0)
#endif
#ifdef __cplusplus
extern "C" {
#endif