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Remove unused patches
This commit is contained in:
zador-blood-stained
parent
808462e1fd
commit
0273c09ded
5 changed files with 0 additions and 460 deletions
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@ -1,78 +0,0 @@
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Add binding documentation for the generic ARM SMC mailbox.
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This is not describing hardware, but a firmware interface.
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Signed-off-by: Andre Przywara <andre.p...@arm.com>
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---
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.../devicetree/bindings/mailbox/arm-smc.txt | 61 ++++++++++++++++++++++
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1 file changed, 61 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.txt
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diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.txt b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
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new file mode 100644
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index 0000000..90c5926
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
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@@ -0,0 +1,61 @@
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+ARM SMC Mailbox Driver
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+======================
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+
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+This mailbox uses the ARM smc (secure monitor call) instruction to
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+trigger a mailbox-connected activity in firmware, executing on the very same
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+core as the caller. By nature this operation is synchronous and this
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+mailbox provides no way for asynchronous messages to be delivered the other
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+way round, from firmware to the OS. However the value of r0/w0/x0 the firmware
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+returns after the smc call is delivered as a received message to the
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+mailbox framework, so a synchronous communication can be established.
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+
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+One use case of this mailbox is the SCP interface, which uses shared memory
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+to transfer commands and parameters, and a mailbox to trigger a function
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+call. This allows SoCs without a separate management processor (or
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+when such a processor is not available or used) to use this standardized
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+interface anyway.
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+
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+This binding describes no hardware, but establishes a firmware interface.
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+The communication follows the ARM SMC calling convention[1].
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+Any core which supports the SMC or HVC instruction can be used, as long as
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+a firmware component running in EL3 or EL2 is handling these calls.
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+
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+Mailbox Device Node:
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+====================
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+
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+Required properties:
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+--------------------
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+- compatible: Shall be "arm,smc-mbox"
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+- #mbox-cells Shall be 1 - the index of the channel needed.
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+- arm,smc-func-ids An array of 32-bit values specifying the function
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+ IDs used by each mailbox channel. Those function IDs
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+ follow the ARM SMC calling convention standard [1].
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+ There is one identifier per channel and the number
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+ of supported channels is determined by the length
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+ of this array.
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+
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+Optional properties:
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+--------------------
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+- method: A string, either:
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+ "hvc": if the driver shall use an HVC call, or
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+ "smc": if the driver shall use an SMC call
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+ If omitted, defaults to an SMC call.
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+
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+Example:
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+--------
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+
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+ mailbox: smc_mbox {
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+ #mbox-cells = <1>;
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+ compatible = "arm,smc-mbox";
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+ identifiers = <0x82000001>, <0x82000002>;
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+ };
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+
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+ scpi {
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+ compatible = "arm,scpi";
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+ mboxes = <&mailbox 0>;
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+ shmem = <&cpu_scp_shmem>;
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+ };
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+
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+
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+[1]
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+http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/index.html
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--
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2.9.0
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@ -1,225 +0,0 @@
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This mailbox driver implements a mailbox which signals transmitted data
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via an ARM smc (secure monitor call) instruction. The mailbox receiver
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is implemented in firmware and can synchronously return data when it
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returns execution to the non-secure world again.
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An asynchronous receive path is not implemented.
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This allows the usage of a mailbox to trigger firmware actions on SoCs
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which either don't have a separate management processor or on which such
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a core is not available. A user of this mailbox could be the SCP
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interface.
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Signed-off-by: Andre Przywara <andre.p...@arm.com>
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---
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drivers/mailbox/Kconfig | 8 ++
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drivers/mailbox/Makefile | 2 +
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drivers/mailbox/arm-smc-mailbox.c | 172 ++++++++++++++++++++++++++++++++++++++
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3 files changed, 182 insertions(+)
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create mode 100644 drivers/mailbox/arm-smc-mailbox.c
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diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
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index c5731e5..5664b7f 100644
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--- a/drivers/mailbox/Kconfig
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+++ b/drivers/mailbox/Kconfig
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@@ -170,4 +170,12 @@ config BCM_FLEXRM_MBOX
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Mailbox implementation of the Broadcom FlexRM ring manager,
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which provides access to various offload engines on Broadcom
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SoCs. Say Y here if you want to use the Broadcom FlexRM.
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+
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+config ARM_SMC_MBOX
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+ tristate "Generic ARM smc mailbox"
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+ depends on OF && HAVE_ARM_SMCCC
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+ help
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+ Generic mailbox driver which uses ARM smc calls to call into
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+ firmware for triggering mailboxes.
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+
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endif
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diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
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index d54e412..8ec6869 100644
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--- a/drivers/mailbox/Makefile
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+++ b/drivers/mailbox/Makefile
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@@ -35,3 +35,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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+
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+obj-$(CONFIG_ARM_SMC_MBOX) += arm-smc-mailbox.o
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diff --git a/drivers/mailbox/arm-smc-mailbox.c b/drivers/mailbox/arm-smc-mailbox.c
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new file mode 100644
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index 0000000..578aed2
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--- /dev/null
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+++ b/drivers/mailbox/arm-smc-mailbox.c
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@@ -0,0 +1,172 @@
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+/*
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+ * Copyright (C) 2016,2017 ARM Ltd.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This device provides a mechanism for emulating a mailbox by using
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+ * smc calls, allowing a "mailbox" consumer to sit in firmware running
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+ * on the same core.
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/kernel.h>
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+#include <linux/mailbox_controller.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/arm-smccc.h>
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+
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+#define ARM_SMC_MBOX_SMC (0 << 0)
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+#define ARM_SMC_MBOX_HVC (1 << 0)
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+#define ARM_SMC_MBOX_METHOD_MASK (1 << 0)
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+
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+struct arm_smc_chan_data {
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+ u32 function_id;
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+ u32 flags;
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+};
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+
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+static int arm_smc_send_data(struct mbox_chan *link, void *data)
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+{
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+ struct arm_smc_chan_data *chan_data = link->con_priv;
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+ u32 function_id = chan_data->function_id;
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+ struct arm_smccc_res res;
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+ u32 msg = *(u32 *)data;
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+
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+ if ((chan_data->flags & ARM_SMC_MBOX_METHOD_MASK) == ARM_SMC_MBOX_SMC)
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+ arm_smccc_smc(function_id, msg, 0, 0, 0, 0, 0, 0, &res);
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+ else
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+ arm_smccc_hvc(function_id, msg, 0, 0, 0, 0, 0, 0, &res);
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+
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+ mbox_chan_received_data(link, (void *)res.a0);
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+
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+ return 0;
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+}
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+
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+static int arm_smc_startup(struct mbox_chan *link)
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+{
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+ return 0;
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+}
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+
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+static void arm_smc_shutdown(struct mbox_chan *link)
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+{
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+}
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+
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+/* This mailbox is synchronous, so we are always done. */
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+static bool arm_smc_last_tx_done(struct mbox_chan *link)
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+{
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+ return true;
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+}
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+
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+static const struct mbox_chan_ops arm_smc_mbox_chan_ops = {
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+ .send_data = arm_smc_send_data,
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+ .startup = arm_smc_startup,
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+ .shutdown = arm_smc_shutdown,
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+ .last_tx_done = arm_smc_last_tx_done
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+};
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+
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+static int arm_smc_mbox_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct mbox_controller *mbox;
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+ struct arm_smc_chan_data *chan_data;
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+ const char *method;
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+ bool use_hvc = false;
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+ int ret = 0, i;
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+
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+ ret = of_property_count_elems_of_size(dev->of_node, "arm,smc-func-ids",
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+ sizeof(u32));
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+ if (ret < 0)
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+ return ret;
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+
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+ if (!of_property_read_string(dev->of_node, "method", &method)) {
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+ if (!strcmp("hvc", method)) {
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+ use_hvc = true;
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+ } else if (!strcmp("smc", method)) {
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+ use_hvc = false;
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+ } else {
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+ dev_warn(dev, "invalid \"method\" property: %s\n",
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+ method);
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+
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+ return -EINVAL;
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+ }
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+ }
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+
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+ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
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+ if (!mbox)
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+ return -ENOMEM;
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+
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+ mbox->num_chans = ret;
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+ mbox->chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*mbox->chans),
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+ GFP_KERNEL);
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+ if (!mbox->chans)
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+ return -ENOMEM;
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+
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+ chan_data = devm_kcalloc(dev, mbox->num_chans, sizeof(*chan_data),
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+ GFP_KERNEL);
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+ if (!chan_data)
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+ return -ENOMEM;
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+
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+ for (i = 0; i < mbox->num_chans; i++) {
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+ u32 function_id;
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+
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+ ret = of_property_read_u32_index(dev->of_node,
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+ "arm,smc-func-ids", i,
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+ &function_id);
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+ if (ret)
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+ return ret;
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+
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+ chan_data[i].function_id = function_id;
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+ if (use_hvc)
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+ chan_data[i].flags |= ARM_SMC_MBOX_HVC;
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+ mbox->chans[i].con_priv = &chan_data[i];
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+ }
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+
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+ mbox->txdone_poll = true;
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+ mbox->txdone_irq = false;
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+ mbox->txpoll_period = 1;
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+ mbox->ops = &arm_smc_mbox_chan_ops;
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+ mbox->dev = dev;
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+
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+ ret = mbox_controller_register(mbox);
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+ if (ret)
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+ return ret;
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+
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+ platform_set_drvdata(pdev, mbox);
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+ dev_info(dev, "ARM SMC mailbox enabled with %d chan%s.\n",
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+ mbox->num_chans, mbox->num_chans == 1 ? "" : "s");
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+
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+ return ret;
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+}
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+
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+static int arm_smc_mbox_remove(struct platform_device *pdev)
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+{
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+ struct mbox_controller *mbox = platform_get_drvdata(pdev);
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+
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+ mbox_controller_unregister(mbox);
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+ return 0;
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+}
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+
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+static const struct of_device_id arm_smc_mbox_of_match[] = {
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+ { .compatible = "arm,smc-mbox", },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, arm_smc_mbox_of_match);
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+
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+static struct platform_driver arm_smc_mbox_driver = {
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+ .driver = {
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+ .name = "arm-smc-mbox",
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+ .of_match_table = arm_smc_mbox_of_match,
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+ },
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+ .probe = arm_smc_mbox_probe,
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+ .remove = arm_smc_mbox_remove,
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+};
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+module_platform_driver(arm_smc_mbox_driver);
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+
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+MODULE_AUTHOR("Andre Przywara <andre.p...@arm.com>");
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+MODULE_DESCRIPTION("Generic ARM smc mailbox driver");
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+MODULE_LICENSE("GPL v2");
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--
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2.9.0
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|
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@ -1,50 +0,0 @@
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This adds support for the SCPI protocol using an SMC mailbox and some
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shared memory in SRAM.
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The SCPI provider is implemented in the ARM Trusted Firmware layer
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(running in EL3 on the application processor cores), triggered by an smc
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call.
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Signed-off-by: Andre Przywara <andre.p...@arm.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
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index 9d00622..ef6f10e 100644
|
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
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@@ -124,6 +124,32 @@
|
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
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};
|
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|
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+ mailbox: mbox@0 {
|
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+ compatible = "arm,smc-mbox";
|
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+ #mbox-cells = <1>;
|
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+ arm,smc-func-ids = <0x82000001>;
|
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+ };
|
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+
|
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+ sram: sram@10000{
|
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+ compatible = "mmio-sram";
|
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+ reg = <0x10000 0x8000>;
|
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+
|
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+ #address-cells = <1>;
|
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+ #size-cells = <1>;
|
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+ ranges = <0 0x10000 0x8000>;
|
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+
|
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+ cpu_scp_mem: scp-shmem@7e00 {
|
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+ compatible = "mmio-sram";
|
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+ reg = <0x7e00 0x200>;
|
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+ };
|
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+ };
|
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+
|
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+ scpi {
|
||||
+ compatible = "arm,scpi";
|
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+ mboxes = <&mailbox 0>;
|
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+ shmem = <&cpu_scp_mem>;
|
||||
+ };
|
||||
+
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
--
|
||||
2.9.0
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
One functionality provided by the SCPI handler is frequency scaling,
|
||||
which allows to switch the one CPU cluster between several operating
|
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points, each specifying a matching frequency and CPU voltage.
|
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The actual table is specified in firmware and can be queried by Linux
|
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using standardised SCPI calls.
|
||||
|
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Signed-off-by: Andre Przywara <andre.p...@arm.com>
|
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---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
index ef6f10e..58c3675 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -61,6 +61,7 @@
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
+ clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@@ -68,6 +69,7 @@
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
enable-method = "psci";
|
||||
+ clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
@@ -75,6 +77,7 @@
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
enable-method = "psci";
|
||||
+ clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
@@ -82,6 +85,7 @@
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
enable-method = "psci";
|
||||
+ clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -148,6 +152,17 @@
|
||||
compatible = "arm,scpi";
|
||||
mboxes = <&mailbox 0>;
|
||||
shmem = <&cpu_scp_mem>;
|
||||
+
|
||||
+ scpi-clocks {
|
||||
+ compatible = "arm,scpi-clocks";
|
||||
+
|
||||
+ scpi_dvfs: scpi_dvfs_clocks {
|
||||
+ compatible = "arm,scpi-dvfs-clocks";
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-indices = <0>;
|
||||
+ clock-output-names = "cpu_clk";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
soc {
|
||||
--
|
||||
2.9.0
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
The SCPI protocol allows various sensors to be exposed to the OS. The
|
||||
list of supported sensors (and their kind) is provided by the SCPI
|
||||
provider, which is in ARM Trusted Firmware. The current implementation
|
||||
exports the temperature sensors, for instance.
|
||||
Since the temperature sensor requires a clock to be running, we set
|
||||
a fixed clock rate for this particular clock to prevent the Linux driver
|
||||
from turning it off.
|
||||
|
||||
Signed-off-by: Andre Przywara <andre.p...@arm.com>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
index 58c3675..7cb1b04 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -163,6 +163,11 @@
|
||||
clock-output-names = "cpu_clk";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ scpi_sensors0: sensors {
|
||||
+ compatible = "arm,scpi-sensors";
|
||||
+ #thermal-sensor-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
soc {
|
||||
@@ -307,6 +312,8 @@
|
||||
clock-names = "hosc", "losc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
+ assigned-clocks = <&ccu CLK_THS>;
|
||||
+ assigned-clock-rates = <4000000>;
|
||||
};
|
||||
|
||||
pio: pinctrl@1c20800 {
|
||||
--
|
||||
2.9.0
|
||||
Loading…
Add table
Reference in a new issue