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Reorganized rockchip patches

Browse source 
no mingling of dts and driver patches, etc.
This commit is contained in:
Tonymac32 2017-05-05 02:04:31 -04:00 • committed by GitHub
parent 0ccd88ae03
commit 1a70a0538b
4 changed files with 305614 additions and 0 deletions
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767
patch/kernel/rockchip-default/100_miniarm_dts_RK3288_dtsi_updates.patch Normal file
View file

@ -0,0 +1,767 @@
diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
index e1177dd..3aefd31 100644
--- a/arch/arm/boot/dts/rk3288-miniarm.dts
+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
@@ -39,16 +39,54 @@
*/
/dts-v1/;
+
+#include <dt-bindings/clock/rockchip,rk808.h>
#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
/ {
compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288";
+ ion {
+ compatible = "rockchip,ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cma-heap {
+ reg = <0x78000000 0x08000000>;
+ };
+
+ system-heap {
+ };
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x80000000>;
};
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default","rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_gpios>;
+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "8723bs";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -56,6 +94,29 @@
#clock-cells = <0>;
};
+ io_domains: io-domains {
+ compatible = "rockchip,rk3288-io-voltage-domain";
+ rockchip,grf = <&grf>;
+ wifi-supply = <&vcc_18>;
+ sdcard-supply = <&vccio_sd>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 RK808_CLKOUT1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -84,8 +145,13 @@
};
act-led {
- gpios=<&gpio2 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger="mmc0";
+ gpios = <&gpio1 0x18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ heartbeat-led {
+ gpios = <&gpio1 0x19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
};
};
@@ -111,18 +177,12 @@
regulator-boot-on;
};
- io_domains: io-domains {
- compatible = "rockchip,rk3288-io-voltage-domain";
- rockchip,grf = <&grf>;
-
- sdcard-supply = <&vccio_sd>;
- };
-
/*
* NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from
* vcc_io directly. Those boards won't be able to power cycle SD cards
* but it shouldn't hurt to toggle this pin there anyway.
*/
+
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
@@ -134,6 +194,13 @@
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
+
+ vdd_log: vdd_log {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_logic";
+ };
};
&cpu0 {
@@ -167,6 +234,12 @@
#sound-dai-cells = <0>;
ddc-i2c-bus = <&i2c5>;
status = "okay";
+ /* Don't use vopl for HDMI */
+ ports {
+ hdmi_in: port {
+ /delete-node/ endpoint@1;
+ };
+ };
};
&i2c0 {
@@ -180,6 +253,10 @@
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int &global_pwroff>;
+
+ dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+ <&gpio0 12 GPIO_ACTIVE_HIGH>;
+
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@@ -191,12 +268,12 @@
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
- vcc8-supply = <&vcc_18>;
+ vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_io>;
vcc10-supply = <&vcc_io>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc_io>;
- vddio-supply = <&vcc18_ldo1>;
+ vddio-supply = <&vcc_io>;
regulators {
vdd_cpu: DCDC_REG1 {
@@ -205,6 +282,7 @@
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_arm";
+ regulator-ramp-delay = <6000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -340,7 +418,6 @@
};
vcc33_sd: SWITCH_REG1 {
- regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_sd";
regulator-state-mem {
@@ -362,6 +439,20 @@
&i2c2 {
status = "okay";
+
+ eeprom:m24c08@50 {
+ compatible = "at,24c08";
+ reg = <0x50>;
+ };
+
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
};
&i2c5 {
@@ -373,6 +464,24 @@
status = "okay";
};
+&sdio0 {
+ status = "okay";
+ clock-frequency = <50000000>;
+ clock-freq-min-max = <200000 50000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>; /*Look here if issue */
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+ sd-uhs-sdr104;
+ supports-sdio;
+};
+
&pwm0 {
status = "okay";
};
@@ -386,6 +495,10 @@
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
card-detect-delay = <200>;
disable-wp; /* wp not hooked up */
num-slots = <1>;
@@ -393,7 +506,7 @@
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
supports-sd;
- vmmc-supply = <&vcc_sd>;
+ vmmc-supply = <&vcc33_sd>;
vqmmc-supply = <&vccio_sd>;
};
@@ -404,6 +517,10 @@
};
&uart0 {
+ dmas = <&dmac_peri 1>, <&dmac_peri 2>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
status = "okay";
};
@@ -428,6 +545,8 @@
};
&usb_host0_ehci {
+
+ no-relinquish-port;
status = "okay";
};
@@ -449,13 +568,22 @@
&vopl {
status = "okay";
+ /* Don't use vopl for hdmi */
+ vopl_out: port {
+ /delete-node/ endpoint@0;
+ };
};
&vopl_mmu {
status = "okay";
+
};
-&vpu {
+&hevc_service {
+ status = "okay";
+};
+
+&vpu_service {
status = "okay";
};
@@ -495,6 +623,23 @@
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
+ dvs_1: dvs-1 {
+ rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ chip_enable_h: chip-enable-h {
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
sdmmc {
@@ -504,9 +649,9 @@
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
- <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+ <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+ <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
};
sdmmc_clk: sdmmc-clk {
@@ -531,4 +676,46 @@
rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ wireless-bluetooth {
+ uart0_gpios: uart0-gpios {
+ rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ cam_pins {
+ cam0_default_pins:cam0_default_pins {
+ rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>,/*sensor power pin: GPIO0_C1 */
+ <2 0 RK_FUNC_GPIO &pcfg_pull_none>,/*sensor power down pin: GPIO2_A0*/
+ <2 11 RK_FUNC_1 &pcfg_pull_none>;/*sensor mclk: cif_clkout*/
+ };
+
+ cam0_sleep_pins:cam0_sleep_pins {
+ rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>,/*sensor power pin: GPIO0_C1 */
+ <2 0 RK_FUNC_GPIO &pcfg_pull_none>,/* cif power down pin */
+ <2 11 RK_FUNC_GPIO &pcfg_pull_none>;/* cif_clkout */
+ };
+ };
+};
+
+&dmc {
+ status = "okay";
+ logic-supply = <&vdd_log>;
+ rockchip,odt-disable-freq = <666000000>;
+ rockchip,dll-disable-freq = <333000000>;
+ rockchip,sr-enable-freq = <333000000>;
+ rockchip,auto-self-refresh-cnt = <0>;
+ rockchip,auto-power-down-cnt = <64>;
+ rockchip,ddr-speed-bin = <21>;
+ rockchip,trcd = <10>;
+ rockchip,trp = <10>;
+ rockchip,pd-enable-freq = <333000000>;
+ operating-points = <
+ /* KHz uV */
+ 200000 1000000
+ 333000 1000000
+ 533000 1000000
+ >;
+
+ #cooling-cells = <2>; /* min followed by max */
};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index f65e406..8ef0393 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -94,23 +94,8 @@
compatible = "arm,cortex-a12";
reg = <0x500>;
resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHz uV */
- 1608000 1350000
- 1512000 1300000
- 1416000 1200000
- 1200000 1100000
- 1008000 1050000
- 816000 1000000
- 696000 950000
- 600000 900000
- 408000 900000
- 312000 900000
- 216000 900000
- 126000 900000
- >;
+ operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
- clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu1: cpu@501 {
@@ -118,18 +103,83 @@
compatible = "arm,cortex-a12";
reg = <0x501>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@502 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x502>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@503 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x503>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@126000000 {
+ opp-hz = /bits/ 64 <126000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@696000000 {
+ opp-hz = /bits/ 64 <696000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1050000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1200000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1300000>;
+ clock-latency-ns = <40000>;
+ };
+ opp@1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1350000>;
+ clock-latency-ns = <40000>;
};
};
@@ -549,6 +599,26 @@
status = "disabled";
};
+ dmc: dmc@ff610000 {
+ compatible = "rockchip,rk3288-dmc", "syscon";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmu>;
+ rockchip,sgrf = <&sgrf>;
+ rockchip,noc = <&noc>;
+ reg = <0xff610000 0x3fc
+ 0xff620000 0x294
+ 0xff630000 0x3fc
+ 0xff640000 0x294>;
+ rockchip,sram = <&ddr_sram>;
+ clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
+ <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
+ <&cru ARMCLK>;
+ clock-names = "pclk_ddrupctl0", "pclk_publ0",
+ "pclk_ddrupctl1", "pclk_publ1",
+ "arm_clk";
+ };
+
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff650000 0x1000>;
@@ -629,6 +699,10 @@
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
};
+ ddr_sram: ddr-sram@1000 {
+ compatible = "rockchip,rk3288-ddr-sram";
+ reg = <0x1000 0x4000>;
+ };
};
sram@ff720000 {
@@ -636,6 +710,76 @@
reg = <0xff720000 0x1000>;
};
+ qos_gpu_r: qos@ffaa0000 {
+ compatible = "syscon";
+ reg = <0xffaa0000 0x20>;
+ };
+
+ qos_gpu_w: qos@ffaa0080 {
+ compatible = "syscon";
+ reg = <0xffaa0080 0x20>;
+ };
+
+ qos_vio1_vop: qos@ffad0000 {
+ compatible = "syscon";
+ reg = <0xffad0000 0x20>;
+ };
+
+ qos_vio1_isp_w0: qos@ffad0100 {
+ compatible = "syscon";
+ reg = <0xffad0100 0x20>;
+ };
+
+ qos_vio1_isp_w1: qos@ffad0180 {
+ compatible = "syscon";
+ reg = <0xffad0180 0x20>;
+ };
+
+ qos_vio0_vop: qos@ffad0400 {
+ compatible = "syscon";
+ reg = <0xffad0400 0x20>;
+ };
+
+ qos_vio0_vip: qos@ffad0480 {
+ compatible = "syscon";
+ reg = <0xffad0480 0x20>;
+ };
+
+ qos_vio0_iep: qos@ffad0500 {
+ compatible = "syscon";
+ reg = <0xffad0500 0x20>;
+ };
+
+ qos_vio2_rga_r: qos@ffad0800 {
+ compatible = "syscon";
+ reg = <0xffad0800 0x20>;
+ };
+
+ qos_vio2_rga_w: qos@ffad0880 {
+ compatible = "syscon";
+ reg = <0xffad0880 0x20>;
+ };
+
+ qos_vio1_isp_r: qos@ffad0900 {
+ compatible = "syscon";
+ reg = <0xffad0900 0x20>;
+ };
+
+ qos_video: qos@ffae0000 {
+ compatible = "syscon";
+ reg = <0xffae0000 0x20>;
+ };
+
+ qos_hevc_r: qos@ffaf0000 {
+ compatible = "syscon";
+ reg = <0xffaf0000 0x20>;
+ };
+
+ qos_hevc_w: qos@ffaf0080 {
+ compatible = "syscon";
+ reg = <0xffaf0080 0x20>;
+ };
+
pmu: power-management@ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff730000 0x100>;
@@ -696,6 +840,15 @@
<&cru SCLK_ISP_JPE>,
<&cru SCLK_ISP>,
<&cru SCLK_RGA>;
+ pm_qos = <&qos_vio0_iep>,
+ <&qos_vio1_vop>,
+ <&qos_vio1_isp_w0>,
+ <&qos_vio1_isp_w1>,
+ <&qos_vio0_vop>,
+ <&qos_vio0_vip>,
+ <&qos_vio2_rga_r>,
+ <&qos_vio2_rga_w>,
+ <&qos_vio1_isp_r>;
};
/*
@@ -707,6 +860,8 @@
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
+ pm_qos = <&qos_hevc_r>,
+ <&qos_hevc_w>;
};
/*
@@ -718,6 +873,7 @@
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
+ pm_qos = <&qos_video>;
};
/*
@@ -727,6 +883,8 @@
pd_gpu {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu_r>,
+ <&qos_gpu_w>;
};
};
@@ -1056,6 +1214,11 @@
status = "disabled";
};
+ noc: syscon@ffac0000 {
+ compatible = "rockchip,rk3288-noc", "syscon";
+ reg = <0xffac0000 0x2000>;
+ };
+
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
reg = <0xff9a0000 0x800>;
@@ -1071,6 +1234,26 @@
status = "disabled";
};
+ vpu_service: vpu-service@ff9a0000 {
+ compatible = "rockchip,vpu_service";
+ reg = <0xff9a0000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_enc", "irq_dec";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ power-domains = <&power RK3288_PD_VIDEO>;
+ rockchip,grf = <&grf>;
+ resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+ reset-names = "video_a", "video_h";
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ dev_mode = <0>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0xff9a0800 0x100>;
@@ -1093,6 +1276,47 @@
interrupts = <GIC_PPI 9 0xf04>;
};
+ hevc_service: hevc-service@ff9c0000 {
+ compatible = "rockchip,hevc_service";
+ reg = <0xff9c0000 0x400>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
+ "clk_cabac";
+ /*
+ * The 4K hevc would also work well with 500/125/300/300,
+ * no more err irq and reset request.
+ */
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+
+ resets = <&cru SRST_HEVC>;
+ reset-names = "video";
+ power-domains = <&power RK3288_PD_HEVC>;
+ rockchip,grf = <&grf>;
+ dev_mode = <1>;
+ iommus = <&hevc_mmu>;
+ iommu_enabled = <1>;
+ status = "disabled";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ };
+
+ hevc_mmu: iommu@ff9c0440 {
+ compatible = "rockchip,iommu";
+ reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hevc_mmu";
+ power-domains = <&power RK3288_PD_HEVC>;
+ #iommu-cells = <0>;
+ };
+
efuse: efuse@ffb40000 {
compatible = "rockchip,rockchip-efuse";
reg = <0xffb40000 0x20>;
@@ -1703,5 +1927,21 @@
rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+ cif {
+ cif_dvp_d2d9:cif-dvp-d2d9 {
+ rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,/* cif_data2 */
+ <2 1 RK_FUNC_1 &pcfg_pull_none>,/* cif_data3 */
+ <2 2 RK_FUNC_1 &pcfg_pull_none>,/* cif_data4 */
+ <2 3 RK_FUNC_1 &pcfg_pull_none>,/* cif_data5 */
+ <2 4 RK_FUNC_1 &pcfg_pull_none>,/* cif_data6 */
+ <2 5 RK_FUNC_1 &pcfg_pull_none>,/* cif_data7 */
+ <2 6 RK_FUNC_1 &pcfg_pull_none>,/* cif_data8 */
+ <2 7 RK_FUNC_1 &pcfg_pull_none>,/* cif_data9 */
+ <2 8 RK_FUNC_1 &pcfg_pull_none>,/* cif_vsync */
+ <2 9 RK_FUNC_1 &pcfg_pull_none>,/* cif_href */
+ <2 11 RK_FUNC_1 &pcfg_pull_none>;/* cif_clkin */
+ };
+ };
};
};

304748
patch/kernel/rockchip-default/110_rtl8723bs-v4.4.0.patch Normal file
View file

File diff suppressed because it is too large Load diff

44
patch/kernel/rockchip-default/120_workaround_tinker_board_reboot.patch Normal file
View file

@ -0,0 +1,44 @@
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 29e3ae9..7f35aa4 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -13,7 +13,9 @@
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
#include <linux/of_address.h>
+#include <linux/regulator/consumer.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
@@ -285,6 +287,21 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
return dw_mci_pltfm_register(pdev, drv_data);
}
+static void dw_mci_rockchip_platfm_shutdown(struct platform_device *pdev)
+{
+ struct dw_mci *host = platform_get_drvdata(pdev);
+ struct mmc_host *mmc = host->cur_slot->mmc;
+ int ret;
+
+ mdelay(20);
+
+ if (!IS_ERR(mmc->supply.vmmc))
+ ret = regulator_enable(mmc->supply.vmmc);
+
+ if (!IS_ERR(mmc->supply.vqmmc))
+ regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
+}
+
#ifdef CONFIG_PM_SLEEP
static int dw_mci_rockchip_suspend(struct device *dev)
{
@@ -308,6 +325,7 @@ static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
static struct platform_driver dw_mci_rockchip_pltfm_driver = {
.probe = dw_mci_rockchip_probe,
.remove = dw_mci_pltfm_remove,
+ .shutdown = dw_mci_rockchip_platfm_shutdown,
.driver = {
.name = "dwmmc_rockchip",
.of_match_table = dw_mci_rockchip_match,

55
patch/kernel/rockchip-default/130_Clk_RK3288_assignment_fixes.patch Normal file
View file

@ -0,0 +1,55 @@
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 07469dc..adff1a3 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -291,13 +291,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 6, GFLAGS),
- COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
+ COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 7, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 8, GFLAGS),
- GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
+ GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 9, GFLAGS),
GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 10, GFLAGS),
@@ -627,7 +627,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
RK3288_CLKSEL_CON(22), 7, IFLAGS),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(4), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
@@ -636,7 +636,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
- GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
+ GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 9, GFLAGS),
DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
@@ -809,7 +809,15 @@ static const char *const rk3288_critical_clocks[] __initconst = {
"aclk_cpu",
"aclk_peri",
"hclk_peri",
- "pclk_pd_pmu",
+ "pclk_alive_niu",
+ "pclk_pd_pmu",
+ "pclk_pmu_niu",
+ "pclk_core_niu",
+ "pclk_ddrupctl0",
+ "pclk_publ0",
+ "pclk_ddrupctl1",
+ "pclk_publ1",
+ "pmu_hclk_otg0"
};
static void __iomem *rk3288_cru_base;