Introducing Rockchip RK322X SoC support (#2032)

* Introducing Rockchip rk322x SoC support

Main features:

- Legacy kernel flavour based upon stable v2.x rk3288 Rockchip branch (https://github.com/rockchip-linux/kernel/tree/stable-4.4-rk3288-linux-v2.x)
- Current kernel flavour based on mainline 5.6.y kernel
- Mainline u-boot (v2020.04)
- Single generic tv box target (rk322x-box) which boots on all the known tv boxes
- Hardware devices (eMMC/NAND, led wiring configuration, SoC variant selection) modulation done by user at runtime via device tree overlays - a script (rk322x-config) is provided for autodetection and simple configuration by inexperienced users;
- Bits added to armbian-hardware-optimization to set affinity for irq handlers
- rk322x-box targets already added to targets.conf for automatic image creation

* Removed disabled patches
* Restored mysteriously removed comment character

config/boards/rk322x-box.tvb

@@ -0,0 +1,8 @@
+# RK322X TVBox quad core 1GB/2GB DDR2/DDR3 eMMC/NAND SoC FE WiFi
+BOARD_NAME="rk322x-box"
+BOARDFAMILY="rk322x"
+BOOTCONFIG="rk322x-box_defconfig"
+BOOT_FDT_FILE="rk322x-box.dtb"
+MODULES_LEGACY="hci_uart rfcomm hidp"
+MODULES_BLACKLIST_LEGACY="ssv6051 8723cs r8188eu"
+KERNEL_TARGET="legacy,current"

config/bootenv/rk322x-default.txt

@@ -0,0 +1,2 @@
+verbosity=1
+extraargs=coherent_pool=2M

config/bootscripts/boot-rk322x.cmd

@@ -0,0 +1,68 @@
+# DO NOT EDIT THIS FILE
+#
+# Please edit /boot/armbianEnv.txt to set supported parameters
+#
+
+setenv ramdisk_addr_r "0x64000000"
+setenv load_addr "0x600f0000"
+setenv overlay_error "false"
+# default values
+setenv rootdev "/dev/mmcblk0p1"
+setenv verbosity "1"
+setenv console "both"
+setenv rootfstype "ext4"
+setenv docker_optimizations "on"
+
+echo "Boot script loaded from ${devtype} ${devnum}"
+
+if test -e ${devtype} ${devnum} ${prefix}armbianEnv.txt; then
+	load ${devtype} ${devnum} ${load_addr} ${prefix}armbianEnv.txt
+	env import -t ${load_addr} ${filesize}
+fi
+
+if test "${logo}" = "disabled"; then setenv logo "logo.nologo"; fi
+
+# get PARTUUID of first partition on SD/eMMC the boot script was loaded from
+if test "${devtype}" = "mmc"; then part uuid mmc ${devnum}:1 partuuid; fi
+
+setenv bootargs "earlyprintk root=${rootdev} console=ttyS2,115200n8 console=tty1 rootwait rootfstype=${rootfstype} ${consoleargs} consoleblank=0 loglevel=${verbosity} ubootpart=${partuuid} usb-storage.quirks=${usbstoragequirks} ${extraargs} ${extraboardargs}"
+
+if test "${docker_optimizations}" = "on"; then setenv bootargs "${bootargs} cgroup_enable=cpuset cgroup_memory=1 cgroup_enable=memory swapaccount=1"; fi
+
+load ${devtype} ${devnum} ${ramdisk_addr_r} ${prefix}uInitrd
+load ${devtype} ${devnum} ${kernel_addr_r} ${prefix}zImage
+
+load ${devtype} ${devnum} ${fdt_addr_r} ${prefix}dtb/${fdtfile}
+fdt addr ${fdt_addr_r}
+fdt resize 65536
+for overlay_file in ${overlays}; do
+	if load ${devtype} ${devnum} ${load_addr} ${prefix}dtb/overlay/${overlay_prefix}-${overlay_file}.dtbo; then
+		echo "Applying kernel provided DT overlay ${overlay_prefix}-${overlay_file}.dtbo"
+		fdt apply ${load_addr} || setenv overlay_error "true"
+	fi
+done
+for overlay_file in ${user_overlays}; do
+	if load ${devtype} ${devnum} ${load_addr} ${prefix}overlay-user/${overlay_file}.dtbo; then
+		echo "Applying user provided DT overlay ${overlay_file}.dtbo"
+		fdt apply ${load_addr} || setenv overlay_error "true"
+	fi
+done
+if test "${overlay_error}" = "true"; then
+	echo "Error applying DT overlays, restoring original DT"
+	load ${devtype} ${devnum} ${fdt_addr_r} ${prefix}dtb/${fdtfile}
+else
+	if load ${devtype} ${devnum} ${load_addr} ${prefix}dtb/overlay/${overlay_prefix}-fixup.scr; then
+		echo "Applying kernel provided DT fixup script (${overlay_prefix}-fixup.scr)"
+		source ${load_addr}
+	fi
+	if test -e ${devtype} ${devnum} ${prefix}fixup.scr; then
+		load ${devtype} ${devnum} ${load_addr} ${prefix}fixup.scr
+		echo "Applying user provided fixup script (fixup.scr)"
+		source ${load_addr}
+	fi
+fi
+
+bootz ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
+
+# Recompile with:
+# mkimage -C none -A arm -T script -d /boot/boot.cmd /boot/boot.scr

config/sources/families/rk322x.conf

@@ -0,0 +1,120 @@
+BOOTSCRIPT="boot-rk322x.cmd:boot.cmd"
+BOOTENV_FILE='rk322x-default.txt'
+OVERLAY_PREFIX='rk322x'
+UBOOT_TARGET_MAP="all u-boot.itb;;u-boot-rk322x-with-spl.bin"
+UBOOT_USE_GCC='< 9.0'
+BOOTDELAY=0
+BOOTBRANCH='tag:v2020.04'
+
+SERIALCON=ttyS2
+
+case $BRANCH in
+
+	legacy)
+
+		KERNELSOURCE='https://github.com/rockchip-linux/kernel.git'
+		KERNELBRANCH='branch:stable-4.4-rk3288-linux-v2.x'
+		KERNELDIR='linux-rockchip'
+		KERNEL_USE_GCC='> 8.0'
+
+	;;
+
+	current)
+
+		KERNELBRANCH='branch:linux-5.6.y'
+		AUFS=no
+
+	;;
+
+	dev)
+
+		KERNELBRANCH='branch:master'
+
+	;;
+
+esac
+
+CPUMIN="600000"
+CPUMAX="1500000"
+GOVERNOR="ondemand"
+
+write_uboot_platform()
+{
+	dd if=/dev/zero of=$2 bs=1k count=1023 seek=1 status=noxfer > /dev/null 2>&1
+	dd if=$1/u-boot-rk322x-with-spl.bin of=$2 seek=64 conv=notrunc > /dev/null 2>&1
+}
+
+uboot_custom_postprocess()
+{
+
+	# We use the rockchip proprietary blob to initialize memory chips
+	# instead of letting u-boot doing the job. Such devices, like xt-mx4vr-v01, have DDR2
+	# or LPDDR2 memories and the blob is better suited for the job.
+	# Also it may come handy when there are different memory flavours among boards, with
+	# different timings, specs and frequencies.
+	# The rockchip proprietary blob is a drop-in substitute for the u-boot tpl.
+	# In case you want to use the u-boot TPL remember to set the proper timing
+	# registers in device tree and this command line instead of the other one:
+	#
+	# 	tools/mkimage -n rk322x -T rksd -d tpl/u-boot-tpl.bin u-boot-rk322x-with-spl.bin
+	#
+	
+	tools/mkimage -n rk322x -T rksd -d $SRC/packages/blobs/rockchip/rk322x_ddr2_300_ddr3_600_v1.09.bin u-boot-rk322x-with-spl.bin
+	cat spl/u-boot-spl.bin >> u-boot-rk322x-with-spl.bin
+	dd if=u-boot.itb of=u-boot-rk322x-with-spl.bin seek=$((0x200 - 0x40)) conv=notrunc
+
+}
+
+family_tweaks()
+{
+
+	true
+
+}
+
+family_tweaks_bsp()
+{
+	#Graphics and media
+	mkdir -p $destination/etc/udev/rules.d
+	mkdir -p $destination/usr/local/bin
+	cp $SRC/packages/bsp/rockchip/hdmi.rules $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/rockchip/50-hevc.rules $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/rockchip/50-mali.rules $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/rockchip/50-vpu.rules $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/rk322x/50-rkvdec.rules $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/rockchip/60-media.rules $destination/etc/udev/rules.d
+	install -m 755 $SRC/packages/bsp/rockchip/hdmi-hotplug $destination/usr/local/bin
+
+	# Peripheral access for specific groups
+	addgroup --system --quiet --gid 997 gpio
+	addgroup --system --quiet --gid 998 i2c
+	cp $SRC/packages/bsp/rockchip/70-gpio.rules $destination/etc/udev/rules.d
+	cp $SRC/packages/bsp/rockchip/71-i2c.rules $destination/etc/udev/rules.d
+
+	# Bluetooth
+	install -m 755 $SRC/packages/bsp/rockchip/rtk_hciattach $destination/usr/bin
+	install -m 755 $SRC/packages/bsp/rockchip/start_bt.sh $destination/usr/local/bin
+	cp $SRC/packages/bsp/rockchip/tinker-bluetooth.service $destination/lib/systemd/system/
+
+	# Sound
+	cp $SRC/packages/bsp/rockchip/asound.conf $destination/etc/
+	cp $SRC/packages/bsp/rockchip/89-pulseaudio-usb.rules $destination/etc/udev/rules.d
+
+	# For rk322x boards copy ssv6051 wifi firmware files to /etc/firmware
+	# We don't want to copy it into /lib/firmware to not interfere with armbian
+	# firmware deb package, so for now put them in a separate position
+	mkdir -p $destination/etc/firmware
+	cp $SRC/packages/blobs/ssv6051/ssv6051-wifi.cfg $destination/etc/firmware
+	cp $SRC/packages/blobs/ssv6051/ssv6051-sw.bin $destination/etc/firmware
+	echo "options ssv6051 stacfgpath=/etc/firmware/ssv6051-wifi.cfg cfgfirmwarepath=/etc/firmware/" > $destination/etc/modprobe.d/ssv6051.conf
+
+	# Board selection script
+	install -m 755 $SRC/packages/bsp/rk322x/rk322x-config $destination/usr/local/bin
+
+	# Fix for bad device detection for x.org when lima driver is in use
+	if [[ "$BRANCH" != "legacy" ]]; then
+		mkdir -p $destination/etc/X11/xorg.conf.d
+		cp $SRC/packages/bsp/rk322x/40-serverflags.conf $destination/etc/X11/xorg.conf.d
+	fi
+
+}

config/targets.conf

@@ -738,6 +738,13 @@ renegade			current			focal		desktop			stable	yes
 renegade			legacy			bionic		desktop			stable	yes
 renegade			current			bionic		desktop			stable	yes
 
+# rk322x-box 
+
+rk322x-box			legacy			buster		cli			stable yes
+rk322x-box			legacy			focal		desktop			stable yes
+rk322x-box			current			buster		minimal			stable yes
+rk322x-box			current			focal		desktop			stable yes
+
 # Rock64
 
 rock64				legacy			buster		cli			stable	yes
@@ -845,3 +852,5 @@ xt-q8l-v10			current			focal		cli			stable	yes
 z28pro				legacy			buster		cli			stable	yes
 z28pro				legacy			bionic		desktop			stable	yes
 z28pro				legacy			focal		desktop			stable	yes
+
+

lib/compilation-prepare.sh

@@ -57,7 +57,7 @@ compilation_prepare()
 		process_patch_file "${SRC}/patch/misc/general-packaging-4.4.y-rockchip64.patch" "applying"
 	fi
 
-	if [[ $version == "4.4."* ]] && [[ "$LINUXFAMILY" == rockchip ]]; then
+	if [[ $version == "4.4."* ]] && [[ "$LINUXFAMILY" == rockchip || "$LINUXFAMILY" == rk322x ]]; then
                 display_alert "Adjustin" "packaging" "info"
                 cd ${SRC}/cache/sources/${LINUXSOURCEDIR}
                 process_patch_file "${SRC}/patch/misc/general-packaging-4.4.y.patch" "applying"

packages/blobs/ssv6051/ssv6051-wifi.cfg

@@ -0,0 +1,91 @@
+############################################################
+# ROCKCHIP RK3X28 & RK322X
+# WIFI-CONFIGURATION
+##################################################
+
+##################################################
+# Firmware setting
+# Priority.1 insmod parameter "cfgfirmwarepath"
+# Priority.2 firmware_path
+# Priority.3 default firmware
+##################################################
+firmware_path = /vendor/etc/firmware/
+
+############################################################
+# MAC address
+#
+# Priority 1. From wifi.cfg [ hw_mac & hw_mac_2 ]
+#
+# Priority 2. From e-fuse[ON/OFF switch by wifi.cfg]
+#
+# Priority 3. From insert module parameter
+#
+# Priority 4. From external file path
+#   path only support some special charater "_" ":" "/" "." "-"
+#
+# Priority 5. Default[Software mode]
+#
+#   0. => 00:33:33:33:33:33
+#   1. => Always random
+#   2. => First random and write to file[Default path mac_output_path]
+#
+############################################################
+ignore_efuse_mac = 0
+#mac_address_path = /xxxx/xxxx
+mac_address_mode = 2
+mac_output_path = /data/wifimac
+
+##################################################
+# Hardware setting
+#
+#volt regulator(DCDC-0 LDO-1)
+#
+##################################################
+xtal_clock = 24
+volt_regulator = 1
+
+##################################################
+# Default channel after wifi on
+# value range: [1 ~ 14]
+##################################################
+def_chan = 6
+##################################################
+# Hardware Capability Settings:
+##################################################
+hw_cap_ht = on
+hw_cap_gf = off
+hw_cap_2ghz = on
+hw_cap_5ghz = off
+hw_cap_security = on
+hw_cap_sgi_20 = on
+hw_cap_sgi_40 = off
+hw_cap_ap = on
+hw_cap_p2p = on
+hw_cap_ampdu_rx = on
+hw_cap_ampdu_tx = on
+use_wpa2_only = 1
+##################################################
+# TX power level setting [0-14]
+# The larger the number the smaller the TX power
+# 0 - The maximum power
+# 1 level = -0.5db
+#
+# 6051Z .. 4 or 4
+# 6051Q .. 2 or 5
+# 6051P .. 0 or 0
+#
+##################################################
+#wifi_tx_gain_level_b = 2
+#wifi_tx_gain_level_gn = 5
+################################################
+# Signal strength control
+# rssi control
+#rssi_ctl = 10
+
+
+##################################################
+# Import extenal configuration(UP to 64 groups)
+# example:
+#    register = CE010010:91919191
+#    register = 00CC0010:00091919
+##################################################

packages/bsp/common/usr/lib/armbian/armbian-hardware-optimization

@@ -139,6 +139,27 @@ prepare_board() {
 				echo 8 >/proc/irq/$i/smp_affinity
 			done
 			;;
+		rk322x) # RK322x: usb otg on cpu1, usb2,3,4 (EHCI), usb5,6,7 (OHCI) on cpu2, eth and GPU on cpu3
+			echo 2 >/proc/irq/$(awk -F":" "/:usb1/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 4 >/proc/irq/$(awk -F":" "/:usb2/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 4 >/proc/irq/$(awk -F":" "/:usb3/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 4 >/proc/irq/$(awk -F":" "/:usb4/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 4 >/proc/irq/$(awk -F":" "/:usb5/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 4 >/proc/irq/$(awk -F":" "/:usb6/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 4 >/proc/irq/$(awk -F":" "/:usb7/ {print \$1}" </proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 8 >/proc/irq/$(awk -F":" "/eth0/ {print \$1}" </proc/interrupts | sed 's/\ //g' | head -n1)/smp_affinity
+			echo 7 >/sys/class/net/eth0/queues/rx-0/rps_cpus
+
+			# Mali in 4.4 kernel
+			for i in $(awk -F':' '/Mali_/{print $1}' /proc/interrupts | sed 's/\ //g'); do
+				echo 8 >/proc/irq/$i/smp_affinity
+			done
+
+			# Lima in mainline kernel
+			echo 8 >/proc/irq/$(awk -F':' '/gp$/{print $1}' /proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 8 >/proc/irq/$(awk -F':' '/gpmmu/{print $1}' /proc/interrupts | sed 's/\ //g')/smp_affinity
+			echo 8 >/proc/irq/$(awk -F':' '/pp0/{print $1}' /proc/interrupts | sed 's/\ //g')/smp_affinity
+			;;
 		rockchip64) # Rock64 and Renegade: GPU on cpu1, USB3 on cpu2, Ethernet on cpu3
 			for i in $(awk -F':' '/Mali/{print $1}' </proc/interrupts | sed 's/\ //g'); do
 				echo 2 >/proc/irq/$i/smp_affinity

packages/bsp/rk322x/40-serverflags.conf

@@ -0,0 +1,10 @@
+Section "ServerFlags"
+        Option "AutoAddGPU" "off"
+EndSection
+
+Section "Device"
+    Identifier "meson"
+    Driver "modesetting"
+    Option "kmsdev" "/dev/dri/card0"
+EndSection
+

packages/bsp/rk322x/50-rkvdec.rules

@@ -0,0 +1 @@
+KERNEL=="rkvdec", MODE="0660", GROUP="video"

packages/bsp/rk322x/rk322x-config

@@ -0,0 +1,405 @@
+#!/bin/bash
+
+DEVICE_TREE_PATH="/boot/dtb"
+DEVICE_TREE_GLOB="rk322*-box*.dtb"
+ARMBIAN_ENV_TXT="/boot/armbianEnv.txt"
+BLACKLIST_MODPROBE_CONF="/etc/modprobe.d/blacklist-rk322x-box.conf"
+
+BACKTITLE="Armbian RK322x device tree board selection | Paolo Sabatino"
+TITLE="Board configuration"
+MENU_TITLE="Please choose your board"
+
+CONFIRM_FLASH_MISMATCH="\nYour board has a type of internal memory but you \
+selected a board without support for that.\n\nYou will not be able to detect \
+the internal memory and your system may not boot anymore\n\nAre you sure?"
+
+COLOR_RED="\Z1"
+COLOR_BLACK="\Z0"
+
+EFUSE_PATH="/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
+SDIO_WIFI_PATH="/sys/bus/sdio/devices/mmc1:0001:1"
+
+EMMC_DEVICE_PATH="/sys/bus/mmc/devices/mmc2:0001"
+NAND_DEVICE_PATH="/sys/block/rknand0/device"
+
+declare -A CHIP_IDS
+declare -A WIFI_NAMES
+declare -A WIFI_CHIPS
+
+declare -A DT_FLASH_OVERLAYS
+declare -A DT_LED_OVERLAYS
+declare -A DT_CPU_OVERLAYS
+
+# Declarations for the various SoCs IDs
+CHIP_IDS+=(["524b2382"]="RK3228A/B")
+CHIP_IDS+=(["524b2392"]="RK3229")
+
+# Declarations for the various Wifi IDs
+WIFI_NAMES+=(["3030:3030"]="South Silicon Valley 6051p/6256p")
+WIFI_NAMES+=(["024c:b703"]="Realtek RTL8703bs")
+WIFI_NAMES+=(["024c:8179"]="Realtek RTL8189ES/ETV")
+
+# Declarations for the various wifi IDs -> kernel modules
+WIFI_CHIPS+=(["3030:3030"]=ssv6051)
+WIFI_CHIPS+=(["024c:b703"]=8723cs)
+WIFI_CHIPS+=(["024c:8179"]=8189es)
+
+# Declarations for device tree overlays
+DT_FLASH_OVERLAYS+=(["emmc"]="eMMC only flash memory")
+DT_FLASH_OVERLAYS+=(["nand"]="NAND only flash memory")
+DT_FLASH_OVERLAYS+=(["emmc-nand"]="eMMC or NAND flash memory")
+
+DT_LED_OVERLAYS+=(["led-conf1"]="LED configuration #1 (Chiptrip)")
+DT_LED_OVERLAYS+=(["led-conf2"]="LED configuration #2 (R329q)")
+
+DT_CPU_OVERLAYS+=(["cpu-hs"]="RK3228B or RK3229")
+
+KERNEL_VERSION=$(uname -r | cut -d "-" -f 1)
+if [[ "$KERNEL_VERSION" < "4.5.0" ]]; then
+	LEGACY_KERNEL=1
+else
+	LEGACY_KERNEL=0
+fi
+
+DT_OVERLAY_PREFIX="$(grep overlay_prefix /boot/armbianEnv.txt | cut -d "=" -f 2)-"
+
+# Query the efuse to get the chip type.
+# Not always reliable, but often.
+function get_chip_type() {
+
+	CHIP_ID=$(od -A none -N 4 -tx1 $EFUSE_PATH | tr -d " ")
+
+	CHIP_TYPE=${CHIP_IDS[$CHIP_ID]}
+	CHIP_TYPE=${CHIP_TYPE:-"unknown"}
+
+	echo $CHIP_TYPE
+
+	return 0
+
+}
+
+# Get the chip serial, from bytes 7 to 22 of the efuse
+function get_chip_serial() {
+
+	ASCII_PART=$(od -A none -j 7 -N 9 -tc $EFUSE_PATH | tr -d " ")
+	BIN_PART=$(od -A none -j 16 -N 7 -tx1 $EFUSE_PATH | tr -d " ")
+
+	echo "$ASCII_PART $BIN_PART"
+
+	return 0
+
+}
+
+# Get the cpu leakage, byte 23 of the efuse
+function get_cpu_leakage() {
+
+	LEAKAGE=$(od -A none -j 23 -N 1 -tx1 $EFUSE_PATH | tr -d " ")
+
+	echo $LEAKAGE
+
+	return 0
+
+}
+
+# Get the logic leakage, byte 25 of the efuse
+function get_logic_leakage() {
+
+	LEAKAGE=$(od -A none -j 25 -N 1 -tx1 $EFUSE_PATH | tr -d " ")
+
+	echo $LEAKAGE
+
+	return 0
+
+}
+
+# Get the vendor and device ids of the wifi chip
+function get_wifi_chip_id() {
+
+	if [ -d "$SDIO_WIFI_PATH" ]; then
+		
+		VENDOR=$(cut -c 3- "$SDIO_WIFI_PATH/vendor")
+		DEVICE=$(cut -c 3- "$SDIO_WIFI_PATH/device")
+
+		echo "$VENDOR:$DEVICE"
+
+		return 0
+
+	fi
+
+	return 1
+
+}
+
+function get_internal_flash_type() {
+
+	if [ -d "$EMMC_DEVICE_PATH" ]; then
+		echo "eMMC"
+	elif [ -d "$NAND_DEVICE_PATH" ]; then
+		echo "NAND"
+	fi
+
+	return 0
+
+}
+
+# Blacklists all the modules buth whitelist only that one
+# that has been detected
+function apply_wifi_blacklist() {
+
+	WIFI_ID=$1
+
+	# Detect wifi chip on legacy kernel and unblacklist it
+	WIFI_MODULE=""
+
+	if [ -n "$WIFI_ID" ]; then
+
+		# blacklist all the modules and unblacklist only the one which is matching
+		WIFI_MODULE="${WIFI_CHIPS[$WIFI_ID]}"
+
+		if [ ! -f $BLACKLIST_MODPROBE_CONF ]; then
+			touch $BLACKLIST_MODPROBE_CONF
+		fi
+
+		if [ -n "$WIFI_MODULE" ]; then
+
+			for MODULE in "${WIFI_CHIPS[@]}"; do
+				sed -i "/blacklist $MODULE/d" $BLACKLIST_MODPROBE_CONF
+			done
+
+			declare -A BLACKLIST_MODULES
+
+			for VALUE in "${WIFI_CHIPS[@]}"; do
+				if [ "$VALUE" != "$WIFI_MODULE" ]; then
+					BLACKLIST_MODULES+=([$VALUE]=1)
+				fi
+			done
+
+			for MODULE in "${!BLACKLIST_MODULES[@]}"; do
+				echo "blacklist $MODULE" >> $BLACKLIST_MODPROBE_CONF
+			done
+
+			echo "#blacklist $WIFI_MODULE" >> $BLACKLIST_MODPROBE_CONF
+
+		fi
+
+	fi
+
+	# unsupported wifi_chip_type: blacklist all known wifi
+	# modules if the blacklist file exists. If the blacklist file does not exist just skip over
+	if [ -z $WIFI_MODULE ]; then
+
+		if [ -f $BLACKLIST_MODPROBE_CONF ]; then
+		
+			for MODULE in "${WIFI_CHIPS[@]}"; do
+				sed -i "s/#blacklist $MODULE/blacklist $MODULE/g" $BLACKLIST_MODPROBE_CONF
+			done
+
+		fi
+
+	fi
+
+	echo $WIFI_MODULE
+
+	return 0
+
+}
+
+function select_soc() {
+
+    declare -a DIALOG_ENTRIES
+
+    # SoC section
+
+    SELECTION="0"
+    [[ "$CHIP_TYPE" = "RK3229" ]] && SELECTION="2"
+
+    DIALOG_ENTRIES=("0" "RK3228A (max 1.2Ghz)")
+    DIALOG_ENTRIES+=("1" "RK3228B (max 1.4Ghz)")
+    DIALOG_ENTRIES+=("2" "RK3229 (max 1.4Ghz)")
+
+    MENU_TITLE="${BOARD_INFO}Select the SoC type\n"
+
+    MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --default-item "$SELECTION" --menu "$MENU_TITLE" 24 0 20)
+
+    SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
+
+    RET=$?
+
+    if [ "$RET" -eq 1 ]; then
+        echo "Cancelled"
+        return 1
+    fi
+
+    if [ "$RET" -ne 0 ]; then
+        echo "dialog utility returned an unexpected error code: $RET"
+        return 1
+    fi
+
+    [[ "$SELECTION" -eq 0 ]] && SELECTION=""
+    [[ "$SELECTION" -eq 1 ]] && SELECTION="cpu-hs"
+    [[ "$SELECTION" -eq 2 ]] && SELECTION="cpu-hs"
+    
+    echo $SELECTION
+    
+    return 0
+
+
+}
+
+function select_flash() {
+
+    declare -a DIALOG_ENTRIES
+
+    SELECTION="emmc-nand"
+    [[ "$FLASH_TYPE" = "eMMC" ]] && SELECTION="emmc"
+    [[ "$FLASH_TYPE" = "NAND" ]] && SELECTION="nand"
+
+    for KEY in "${!DT_FLASH_OVERLAYS[@]}"; do
+        DIALOG_ENTRIES+=($KEY "${DT_FLASH_OVERLAYS[$KEY]}")
+    done
+
+    MENU_TITLE="${BOARD_INFO}Select the internal flash type\n"
+
+    MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --default-item "$SELECTION" --menu "$MENU_TITLE" 24 0 20)
+
+    SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
+
+    RET=$?
+
+    if [ "$RET" -eq 1 ]; then
+        echo "Cancelled"
+        return 1
+    fi
+
+    if [ "$RET" -ne 0 ]; then
+        echo "dialog utility returned an unexpected error code: $RET"
+        return 1
+    fi
+
+    echo $SELECTION
+    
+    return 0
+
+}
+
+function select_led_configuration() {
+
+    declare -a DIALOG_ENTRIES
+
+    for KEY in "${!DT_LED_OVERLAYS[@]}"; do
+        DIALOG_ENTRIES+=($KEY "${DT_LED_OVERLAYS[$KEY]}")
+    done
+
+    MENU_TITLE="${BOARD_INFO}Select the led wiring configuation\n"
+
+    MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --default-item "$SELECTION" --menu "$MENU_TITLE" 24 0 20)
+
+    SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
+
+    RET=$?
+
+    if [ "$RET" -eq 1 ]; then
+        echo "Cancelled"
+        return 1 
+    fi
+
+    if [ "$RET" -ne 0 ]; then
+        echo "dialog utility returned an unexpected error code: $RET"
+        return 1
+    fi
+
+    echo $SELECTION
+    
+    return 0
+
+
+}
+
+
+# ----- Entry point -----
+
+USER_ID=$(id -u)
+if [ $USER_ID -ne 0 ]; then
+	echo "Please run this script with administrative privileges"
+	exit 2
+fi
+
+declare -a DT_OVERLAYS_TO_APPLY
+
+CHIP_TYPE=$(get_chip_type)
+CHIP_SERIAL=$(get_chip_serial)
+CPU_LEAKAGE=$(get_cpu_leakage)
+LOGIC_LEAKAGE=$(get_logic_leakage)
+WIFI_ID=$(get_wifi_chip_id)
+FLASH_TYPE=$(get_internal_flash_type)
+
+if [ -z "$WIFI_ID" ]; then
+	WIFI_NAME="not available"
+else
+	WIFI_NAME="${WIFI_NAMES[$WIFI_ID]:-"unknown"} - Device ID: ${WIFI_ID}"
+fi
+
+if [ -z "$FLASH_TYPE" ]; then
+	FLASH_NAME="not detected"
+else
+	FLASH_NAME="$FLASH_TYPE"
+fi
+
+BOARD_INFO="\nDetected board features:\n\
+Chip type: ${COLOR_RED}\Zb${CHIP_TYPE}\Zn${COLOR_BLACK} - \
+Serial: $CHIP_SERIAL\n\
+CPU Leakage: 0x$CPU_LEAKAGE - Logic Leakage: 0x$LOGIC_LEAKAGE\n\
+Internal flash: ${COLOR_RED}\Zb${FLASH_NAME}\Zn${COLOR_BLACK}\n\
+Wifi device: $WIFI_NAME\n\n"
+
+### --- SOC selection ---
+
+SELECTION=$(select_soc) || exit 1
+DT_OVERLAYS_TO_APPLY+=($SELECTION)
+
+SELECTION=$(select_flash) || exit 1
+DT_OVERLAYS_TO_APPLY+=($SELECTION)
+
+SELECTION=$(select_led_configuration) || exit 1
+DT_OVERLAYS_TO_APPLY+=($SELECTION)
+
+sed -i '/^overlays=/d' $ARMBIAN_ENV_TXT
+
+if [ $? -ne 0 ]; then
+	echo "An error occurred while removing existing fdtfile entry from $ARMBIAN_ENV_TXT"
+	exit 1
+fi
+
+echo "overlays=${DT_OVERLAYS_TO_APPLY[@]}" >> $ARMBIAN_ENV_TXT
+
+if [ $? -ne 0 ]; then
+	echo "An error occurred while adding overlays entry in $ARMBIAN_ENV_TXT"
+	exit 1
+fi
+
+# Apply the wifi blacklist only with legacy kernel
+if [[ $LEGACY_KERNEL -eq 1 ]]; then
+	WIFI_MODULE=$(apply_wifi_blacklist "$WIFI_ID")
+fi
+
+echo ""
+echo ""
+echo "Device tree overlays enabled: ${DT_OVERLAYS_TO_APPLY[@]}"
+
+# Print the outcome of wifi chip selection only with legacy kernel
+# Mainline kernel is supposed to work ok by itself with hardware recognition
+if [[ $LEGACY_KERNEL -eq 1 ]]; then
+
+	if [ -n "$WIFI_MODULE" ]; then
+		echo "Enabled wifi module $WIFI_MODULE"
+	fi
+
+	if [ -n "$WIFI_ID" ] && [ -z "$WIFI_MODULE" ]; then
+		echo "Wifi chip $WIFI_ID has been detected, but currently it is unsupported"
+		echo "Please report to: https://forum.armbian.com/topic/12656-wip-armbian-for-rk322x-devices/"
+	fi
+
+fi
+
+echo "Reboot the device to make changes effective!"
+echo ""

packages/bsp/rockchip/50-mali.rules

@@ -1 +1,2 @@
-KERNEL=="mali0", MODE="0660", GROUP="video"
+KERNEL=="mali0", MODE="0660", GROUP="video"
+KERNEL=="mali", MODE="0660", GROUP="video"

patch/kernel/rk322x-current/01-linux-0013-v4l2-from-list.patch

@@ -0,0 +1,319 @@
+diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
+index 28313c0f4e7c..d472a54d1c4d 100644
+--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
+@@ -2028,6 +2028,18 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type -
+     * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
+       - 0x00000004
+       - The DPB entry is a long term reference frame
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE``
++      - 0x00000008
++      - The DPB entry is a field picture
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_TOP``
++      - 0x00000010
++      - The DPB entry is a top field reference
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM``
++      - 0x00000020
++      - The DPB entry is a bottom field reference
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME``
++      - 0x00000030
++      - The DPB entry is a reference frame
+ 
+ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)``
+     Specifies the decoding mode to use. Currently exposes slice-based and
+diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h
+index e877bf1d537c..76020ebd1e6c 100644
+--- a/include/media/h264-ctrls.h
++++ b/include/media/h264-ctrls.h
+@@ -185,6 +185,10 @@ struct v4l2_ctrl_h264_slice_params {
+ #define V4L2_H264_DPB_ENTRY_FLAG_VALID		0x01
+ #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE		0x02
+ #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM	0x04
++#define V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE	0x08
++#define V4L2_H264_DPB_ENTRY_FLAG_REF_TOP	0x10
++#define V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM	0x20
++#define V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME	0x30
+ 
+ struct v4l2_h264_dpb_entry {
+ 	__u64 reference_ts;
+-- 
+2.17.1
+
+
+From ef240de60cedea0264ca954a8e8e2fa25db097ae Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 29 Oct 2019 01:26:02 +0000
+Subject: [PATCH] RFC: media: hantro: Fix H264 decoding of field encoded
+ content
+
+This still need code cleanup and formatting
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ .../staging/media/hantro/hantro_g1_h264_dec.c |  17 +--
+ drivers/staging/media/hantro/hantro_h264.c    | 122 ++++++++++++------
+ drivers/staging/media/hantro/hantro_hw.h      |   2 +
+ 3 files changed, 85 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
+index 424c648ce9fc..89cf5741280e 100644
+--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
+@@ -132,25 +132,12 @@ static void set_ref(struct hantro_ctx *ctx)
+ 	struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+ 	const u8 *b0_reflist, *b1_reflist, *p_reflist;
+ 	struct hantro_dev *vpu = ctx->dev;
+-	u32 dpb_longterm = 0;
+-	u32 dpb_valid = 0;
+ 	int reg_num;
+ 	u32 reg;
+ 	int i;
+ 
+-	/*
+-	 * Set up bit maps of valid and long term DPBs.
+-	 * NOTE: The bits are reversed, i.e. MSb is DPB 0.
+-	 */
+-	for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
+-		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+-			dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+-
+-		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
+-			dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+-	}
+-	vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
+-	vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
++	vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
++	vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
+ 
+ 	/*
+ 	 * Set up reference frame picture numbers.
+diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c
+index f2d3e81fb6ce..4db779354e89 100644
+--- a/drivers/staging/media/hantro/hantro_h264.c
++++ b/drivers/staging/media/hantro/hantro_h264.c
+@@ -225,17 +225,65 @@ static void prepare_table(struct hantro_ctx *ctx)
+ {
+ 	const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
+ 	const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
++	const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
+ 	struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
+ 	const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
++	u32 dpb_longterm = 0;
++	u32 dpb_valid = 0;
+ 	int i;
+ 
++	/*
++	 * Set up bit maps of valid and long term DPBs.
++	 * NOTE: The bits are reversed, i.e. MSb is DPB 0.
++	 */
++	if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || (slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
++		for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
++			// check for correct reference use
++			u32 flag = (i & 0x1) ? V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM : V4L2_H264_DPB_ENTRY_FLAG_REF_TOP;
++			if (dpb[i / 2].flags & flag)
++				dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
++
++			if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
++				dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
++		}
++
++		ctx->h264_dec.dpb_valid = dpb_valid;
++		ctx->h264_dec.dpb_longterm = dpb_longterm;
++	} else {
++		for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
++			if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
++				dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
++
++			if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
++				dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
++		}
++
++		ctx->h264_dec.dpb_valid = dpb_valid << 16;
++		ctx->h264_dec.dpb_longterm = dpb_longterm << 16;
++	}
++
+ 	for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
+-		tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
+-		tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
++		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
++			tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
++			tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
++		} else {
++			tbl->poc[i * 2] = 0;
++			tbl->poc[i * 2 + 1] = 0;
++		}
+ 	}
+ 
+-	tbl->poc[32] = dec_param->top_field_order_cnt;
+-	tbl->poc[33] = dec_param->bottom_field_order_cnt;
++	if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || !(slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
++		if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
++			tbl->poc[32] = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
++					dec_param->bottom_field_order_cnt :
++					dec_param->top_field_order_cnt;
++		else
++			tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt);
++		tbl->poc[33] = 0;
++	} else {
++		tbl->poc[32] = dec_param->top_field_order_cnt;
++		tbl->poc[33] = dec_param->bottom_field_order_cnt;
++	}
+ 
+ 	reorder_scaling_list(ctx);
+ }
+@@ -249,21 +297,6 @@ struct hantro_h264_reflist_builder {
+ 	u8 num_valid;
+ };
+ 
+-static s32 get_poc(enum v4l2_field field, s32 top_field_order_cnt,
+-		   s32 bottom_field_order_cnt)
+-{
+-	switch (field) {
+-	case V4L2_FIELD_TOP:
+-		return top_field_order_cnt;
+-	case V4L2_FIELD_BOTTOM:
+-		return bottom_field_order_cnt;
+-	default:
+-		break;
+-	}
+-
+-	return min(top_field_order_cnt, bottom_field_order_cnt);
+-}
+-
+ static void
+ init_reflist_builder(struct hantro_ctx *ctx,
+ 		     struct hantro_h264_reflist_builder *b)
+@@ -271,9 +304,7 @@ init_reflist_builder(struct hantro_ctx *ctx,
+ 	const struct v4l2_ctrl_h264_slice_params *slice_params;
+ 	const struct v4l2_ctrl_h264_decode_params *dec_param;
+ 	const struct v4l2_ctrl_h264_sps *sps;
+-	struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx);
+ 	const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+-	struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
+ 	int cur_frame_num, max_frame_num;
+ 	unsigned int i;
+ 
+@@ -285,21 +316,15 @@ init_reflist_builder(struct hantro_ctx *ctx,
+ 
+ 	memset(b, 0, sizeof(*b));
+ 	b->dpb = dpb;
+-	b->curpoc = get_poc(buf->field, dec_param->top_field_order_cnt,
+-			    dec_param->bottom_field_order_cnt);
++	b->curpoc = (slice_params->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
++		    dec_param->bottom_field_order_cnt :
++		    dec_param->top_field_order_cnt;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) {
+-		int buf_idx;
+-
+-		if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
++		u32 ref_flag = dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME;
++		if (!ref_flag)
+ 			continue;
+ 
+-		buf_idx = vb2_find_timestamp(cap_q, dpb[i].reference_ts, 0);
+-		if (buf_idx < 0)
+-			continue;
+-
+-		buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx));
+-
+ 		/*
+ 		 * Handle frame_num wraparound as described in section
+ 		 * '8.2.4.1 Decoding process for picture numbers' of the spec.
+@@ -311,8 +336,13 @@ init_reflist_builder(struct hantro_ctx *ctx,
+ 		else
+ 			b->frame_nums[i] = dpb[i].frame_num;
+ 
+-		b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt,
+-				     dpb[i].bottom_field_order_cnt);
++		if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME)
++			b->pocs[i] = min(dpb[i].bottom_field_order_cnt, dpb[i].top_field_order_cnt);
++		else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM)
++			b->pocs[i] = dpb[i].bottom_field_order_cnt;
++		else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_TOP)
++			b->pocs[i] = dpb[i].top_field_order_cnt;
++
+ 		b->unordered_reflist[b->num_valid] = i;
+ 		b->num_valid++;
+ 	}
+@@ -466,8 +496,7 @@ build_b_ref_lists(const struct hantro_h264_reflist_builder *builder,
+ static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a,
+ 			    const struct v4l2_h264_dpb_entry *b)
+ {
+-	return a->top_field_order_cnt == b->top_field_order_cnt &&
+-	       a->bottom_field_order_cnt == b->bottom_field_order_cnt;
++	return a->reference_ts == b->reference_ts;
+ }
+ 
+ static void update_dpb(struct hantro_ctx *ctx)
+@@ -481,13 +510,13 @@ static void update_dpb(struct hantro_ctx *ctx)
+ 
+ 	/* Disable all entries by default. */
+ 	for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++)
+-		ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE;
++		ctx->h264_dec.dpb[i].flags = 0;
+ 
+ 	/* Try to match new DPB entries with existing ones by their POCs. */
+ 	for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) {
+ 		const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i];
+ 
+-		if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
++		if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))
+ 			continue;
+ 
+ 		/*
+@@ -498,8 +527,7 @@ static void update_dpb(struct hantro_ctx *ctx)
+ 			struct v4l2_h264_dpb_entry *cdpb;
+ 
+ 			cdpb = &ctx->h264_dec.dpb[j];
+-			if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ||
+-			    !dpb_entry_match(cdpb, ndpb))
++			if (!dpb_entry_match(cdpb, ndpb))
+ 				continue;
+ 
+ 			*cdpb = *ndpb;
+@@ -535,7 +563,11 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
+ 				   unsigned int dpb_idx)
+ {
+ 	struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
++	const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode;
++	const struct v4l2_ctrl_h264_slice_params *slices = ctx->h264_dec.ctrls.slices;
+ 	dma_addr_t dma_addr = 0;
++	s32 cur_poc;
++	u32 flags;
+ 
+ 	if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+ 		dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts);
+@@ -553,7 +585,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
+ 		dma_addr = vb2_dma_contig_plane_dma_addr(buf, 0);
+ 	}
+ 
+-	return dma_addr;
++	cur_poc = slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD ?
++		  dec_param->bottom_field_order_cnt :
++		  dec_param->top_field_order_cnt;
++	flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE ? 0x2 : 0;
++	flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) <
++		 abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ?
++		 0x1 : 0;
++
++	return dma_addr | flags;
+ }
+ 
+ int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx)
+diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
+index 2398d4c1f207..3dc7b8f27c32 100644
+--- a/drivers/staging/media/hantro/hantro_hw.h
++++ b/drivers/staging/media/hantro/hantro_hw.h
+@@ -88,6 +88,8 @@ struct hantro_h264_dec_hw_ctx {
+ 	struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
+ 	struct hantro_h264_dec_reflists reflists;
+ 	struct hantro_h264_dec_ctrls ctrls;
++	u32 dpb_longterm;
++	u32 dpb_valid;
+ };
+ 
+ /**
+-- 
+2.17.1
+

patch/kernel/rk322x-current/01-linux-0015-fromlist-rga-for-rk322x.patch

@@ -0,0 +1,334 @@
+diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.txt b/Documentation/devicetree/bindings/media/rockchip-rga.txt
+index fd5276abf..c53a8e513 100644
+--- a/Documentation/devicetree/bindings/media/rockchip-rga.txt
++++ b/Documentation/devicetree/bindings/media/rockchip-rga.txt
+@@ -6,8 +6,9 @@ BitBLT, alpha blending and image blur/sharpness.
+ 
+ Required properties:
+ - compatible: value should be one of the following
+-		"rockchip,rk3288-rga";
+-		"rockchip,rk3399-rga";
++  "rockchip,rk3228-rga", "rockchip,rk3288-rga": for Rockchip RK3228
++  "rockchip,rk3288-rga": for Rockchip RK3288
++  "rockchip,rk3399-rga": for Rockchip RK3399
+ 
+ - interrupts: RGA interrupt specifier.
+ 
+
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+Subject: [PATCH v4 2/3] ARM: dts: rockchip: add rga node for rk322x
+Date: Mon,  3 Feb 2020 22:40:16 +0000
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+
+Add a node to define the presence of RGA, a 2D raster
+graphic acceleration unit.
+
+Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
+---
+ arch/arm/boot/dts/rk322x.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index 340ed6ccb..29d50bebc 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -621,6 +621,17 @@
+ 		status = "disabled";
+ 	};
+ 
++	rga: rga@20060000 {
++		compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
++		reg = <0x20060000 0x1000>;
++		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
++		clock-names = "aclk", "hclk", "sclk";
++		resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
++		reset-names = "core", "axi", "ahb";
++		status = "disabled";
++	};
++
+ 	iep_mmu: iommu@20070800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x20070800 0x100>;
+
+From patchwork Mon Feb  3 22:40:17 2020
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+Subject: [PATCH v4 3/3] ARM: dts: rockchip: enable rga for rk3229-xms6
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+ 3jR5NeVaJQBh0uawl0Cg8j+knAzOA9mmoJvkuhKHiekUuskYaI6ERCKp8gXWqnT9kLHhStr5fiGK
+ 7KncpWELuTEvuGslKTrRIXcXpFg5ivY=
+X-Report-Abuse-To: spam@antispammaster.host-h.net
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+ pts rule name              description
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+ --------------------------------------------------
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+ -0.0 SPF_PASS               SPF: sender matches SPF record
+X-BeenThere: linux-rockchip@lists.infradead.org
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+Precedence: list
+List-Id: Upstream kernel work for Rockchip platforms
+ <linux-rockchip.lists.infradead.org>
+List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>,
+ <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe>
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+List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-rockchip>,
+ <mailto:linux-rockchip-request@lists.infradead.org?subject=subscribe>
+Cc: linux-rockchip@lists.infradead.org,
+ Justin Swartz <justin.swartz@risingedge.co.za>, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
+MIME-Version: 1.0
+Sender: "Linux-rockchip" <linux-rockchip-bounces@lists.infradead.org>
+Errors-To: 
+ linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org
+
+Enable RGA for Mecer Xtreme Mini S6.
+
+Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
+---
+ arch/arm/boot/dts/rk3229-xms6.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts
+index 679fc2b00..894f64a4a 100644
+--- a/arch/arm/boot/dts/rk3229-xms6.dts
++++ b/arch/arm/boot/dts/rk3229-xms6.dts
+@@ -202,6 +202,10 @@
+ 	status = "okay";
+ };
+ 
++&rga {
++	status = "okay";
++};
++
+ &sdmmc {
+ 	cap-mmc-highspeed;
+ 	disable-wp;

patch/kernel/rk322x-current/01-linux-0015-hantro-set-of-small-cleanups-and-fixes.patch

@@ -0,0 +1,732 @@
+diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c
+index cc34c5ab7009..3070672e6b4f 100644
+--- a/drivers/media/v4l2-core/v4l2-mem2mem.c
++++ b/drivers/media/v4l2-core/v4l2-mem2mem.c
+@@ -499,12 +499,21 @@ void v4l2_m2m_buf_done_and_job_finish(struct v4l2_m2m_dev *m2m_dev,
+ 
+ 	if (WARN_ON(!src_buf || !dst_buf))
+ 		goto unlock;
+-	v4l2_m2m_buf_done(src_buf, state);
+ 	dst_buf->is_held = src_buf->flags & V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF;
+ 	if (!dst_buf->is_held) {
+ 		v4l2_m2m_dst_buf_remove(m2m_ctx);
+ 		v4l2_m2m_buf_done(dst_buf, state);
+ 	}
++	/*
++	 * If the request API is being used, returning the OUTPUT
++	 * (src) buffer will wake-up any process waiting on the
++	 * request file descriptor.
++	 *
++	 * Therefore, return the CAPTURE (dst) buffer first,
++	 * to avoid signalling the request file descriptor
++	 * before the CAPTURE buffer is done.
++	 */
++	v4l2_m2m_buf_done(src_buf, state);
+ 	schedule_next = _v4l2_m2m_job_finish(m2m_dev, m2m_ctx);
+ unlock:
+ 	spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags);
+-- 
+2.17.1
+
+
+From 46fef6ecbc765dedaeef46339474529645f09404 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:02 -0300
+Subject: [PATCH] hantro: Set buffers' zeroth plane payload in .buf_prepare
+
+Buffers' zeroth plane payload size is calculated at format
+negotiation time, and so it can be set in .buf_prepare.
+
+Keep in mind that, to make this change easier, hantro_buf_prepare
+is refactored, using the cedrus driver as reference. This results
+in cleaner code as byproduct.
+
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ drivers/staging/media/hantro/hantro_v4l2.c | 16 +++++++++++-----
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
+index f4ae2cee0f18..3142ab6697d5 100644
+--- a/drivers/staging/media/hantro/hantro_v4l2.c
++++ b/drivers/staging/media/hantro/hantro_v4l2.c
+@@ -608,7 +608,7 @@ hantro_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
+ }
+ 
+ static int
+-hantro_buf_plane_check(struct vb2_buffer *vb, const struct hantro_fmt *vpu_fmt,
++hantro_buf_plane_check(struct vb2_buffer *vb,
+ 		       struct v4l2_pix_format_mplane *pixfmt)
+ {
+ 	unsigned int sz;
+@@ -630,12 +630,18 @@ static int hantro_buf_prepare(struct vb2_buffer *vb)
+ {
+ 	struct vb2_queue *vq = vb->vb2_queue;
+ 	struct hantro_ctx *ctx = vb2_get_drv_priv(vq);
++	struct v4l2_pix_format_mplane *pix_fmt;
++	int ret;
+ 
+ 	if (V4L2_TYPE_IS_OUTPUT(vq->type))
+-		return hantro_buf_plane_check(vb, ctx->vpu_src_fmt,
+-						  &ctx->src_fmt);
+-
+-	return hantro_buf_plane_check(vb, ctx->vpu_dst_fmt, &ctx->dst_fmt);
++		pix_fmt = &ctx->src_fmt;
++	else
++		pix_fmt = &ctx->dst_fmt;
++	ret = hantro_buf_plane_check(vb, pix_fmt);
++	if (ret)
++		return ret;
++	vb2_set_plane_payload(vb, 0, pix_fmt->plane_fmt[0].sizeimage);
++	return 0;
+ }
+ 
+ static void hantro_buf_queue(struct vb2_buffer *vb)
+-- 
+2.17.1
+
+
+From 49b98070ac9cbd4e731a84f0a3c10e6dd803d37c Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:03 -0300
+Subject: [PATCH] hantro: Use v4l2_m2m_buf_done_and_job_finish
+
+Let the core sort out the nuances of returning buffers
+to userspace, by using the v4l2_m2m_buf_done_and_job_finish
+helper.
+
+This change also removes usage of buffer sequence fields,
+which shouldn't have any meaning for stateless decoders.
+
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+Nacked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
+---
+ drivers/staging/media/hantro/hantro_drv.c | 27 ++++++++---------------
+ 1 file changed, 9 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
+index c98835326135..dd503918a017 100644
+--- a/drivers/staging/media/hantro/hantro_drv.c
++++ b/drivers/staging/media/hantro/hantro_drv.c
+@@ -94,32 +94,23 @@ static void hantro_job_finish(struct hantro_dev *vpu,
+ 			      unsigned int bytesused,
+ 			      enum vb2_buffer_state result)
+ {
+-	struct vb2_v4l2_buffer *src, *dst;
+ 	int ret;
+ 
+ 	pm_runtime_mark_last_busy(vpu->dev);
+ 	pm_runtime_put_autosuspend(vpu->dev);
+ 	clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
+ 
+-	src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+-	dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+-
+-	if (WARN_ON(!src))
+-		return;
+-	if (WARN_ON(!dst))
+-		return;
+-
+-	src->sequence = ctx->sequence_out++;
+-	dst->sequence = ctx->sequence_cap++;
+-
+-	ret = ctx->buf_finish(ctx, &dst->vb2_buf, bytesused);
+-	if (ret)
+-		result = VB2_BUF_STATE_ERROR;
++	if (ctx->buf_finish) {
++		struct vb2_v4l2_buffer *dst;
+ 
+-	v4l2_m2m_buf_done(src, result);
+-	v4l2_m2m_buf_done(dst, result);
++		dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
++		ret = ctx->buf_finish(ctx, &dst->vb2_buf, bytesused);
++		if (ret)
++			result = VB2_BUF_STATE_ERROR;
++	}
+ 
+-	v4l2_m2m_job_finish(vpu->m2m_dev, ctx->fh.m2m_ctx);
++	v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
++					 result);
+ }
+ 
+ void hantro_irq_done(struct hantro_dev *vpu, unsigned int bytesused,
+-- 
+2.17.1
+
+
+From ee3c913094e5776a0b1270b78ecce8a5e9803a42 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:04 -0300
+Subject: [PATCH] hantro: Remove unneeded hantro_dec_buf_finish
+
+Since now .buf_prepare takes care of setting the
+buffer payload size, we can get rid of this,
+at least for decoders.
+
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ drivers/staging/media/hantro/hantro_drv.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
+index dd503918a017..a732beeb3bb6 100644
+--- a/drivers/staging/media/hantro/hantro_drv.c
++++ b/drivers/staging/media/hantro/hantro_drv.c
+@@ -80,15 +80,6 @@ hantro_enc_buf_finish(struct hantro_ctx *ctx, struct vb2_buffer *buf,
+ 	return 0;
+ }
+ 
+-static int
+-hantro_dec_buf_finish(struct hantro_ctx *ctx, struct vb2_buffer *buf,
+-		      unsigned int bytesused)
+-{
+-	/* For decoders set bytesused as per the output picture. */
+-	buf->planes[0].bytesused = ctx->dst_fmt.plane_fmt[0].sizeimage;
+-	return 0;
+-}
+-
+ static void hantro_job_finish(struct hantro_dev *vpu,
+ 			      struct hantro_ctx *ctx,
+ 			      unsigned int bytesused,
+@@ -412,7 +403,6 @@ static int hantro_open(struct file *filp)
+ 		ctx->buf_finish = hantro_enc_buf_finish;
+ 	} else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
+ 		allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
+-		ctx->buf_finish = hantro_dec_buf_finish;
+ 	} else {
+ 		ret = -ENODEV;
+ 		goto err_ctx_free;
+-- 
+2.17.1
+
+
+From 403b36c2db7e39b46f8e0f6a363af6763373933d Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:05 -0300
+Subject: [PATCH] hantro: Move H264 motion vector calculation to a helper
+
+Move the extra bytes calculation that are needed for H264
+motion vector to a helper. This is just a cosmetic cleanup.
+
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ drivers/staging/media/hantro/hantro.h      |  4 ---
+ drivers/staging/media/hantro/hantro_hw.h   | 31 ++++++++++++++++++++++
+ drivers/staging/media/hantro/hantro_v4l2.c | 25 ++---------------
+ 3 files changed, 33 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
+index b0faa43b3f79..1a010d438ac2 100644
+--- a/drivers/staging/media/hantro/hantro.h
++++ b/drivers/staging/media/hantro/hantro.h
+@@ -26,10 +26,6 @@
+ 
+ #include "hantro_hw.h"
+ 
+-#define MB_DIM			16
+-#define MB_WIDTH(w)		DIV_ROUND_UP(w, MB_DIM)
+-#define MB_HEIGHT(h)		DIV_ROUND_UP(h, MB_DIM)
+-
+ struct hantro_ctx;
+ struct hantro_codec_ops;
+ 
+diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
+index 4a64873bf332..33c1ce169203 100644
+--- a/drivers/staging/media/hantro/hantro_hw.h
++++ b/drivers/staging/media/hantro/hantro_hw.h
+@@ -18,6 +18,10 @@
+ 
+ #define DEC_8190_ALIGN_MASK	0x07U
+ 
++#define MB_DIM			16
++#define MB_WIDTH(w)		DIV_ROUND_UP(w, MB_DIM)
++#define MB_HEIGHT(h)		DIV_ROUND_UP(h, MB_DIM)
++
+ struct hantro_dev;
+ struct hantro_ctx;
+ struct hantro_buf;
+@@ -180,6 +184,33 @@ void rk3399_vpu_h264_dec_run(struct hantro_ctx *ctx);
+ int hantro_h264_dec_init(struct hantro_ctx *ctx);
+ void hantro_h264_dec_exit(struct hantro_ctx *ctx);
+ 
++static inline size_t
++hantro_h264_mv_size(unsigned int width, unsigned int height)
++{
++	/*
++	* A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
++	* 448 bytes per macroblock with additional 32 bytes on
++	* multi-core variants.
++	*
++	* The H264 decoder needs extra space on the output buffers
++	* to store motion vectors. This is needed for reference
++	* frames and only if the format is non-post-processed NV12.
++	*
++	* Memory layout is as follow:
++	*
++	* +---------------------------+
++	* | Y-plane   256 bytes x MBs |
++	* +---------------------------+
++	* | UV-plane  128 bytes x MBs |
++	* +---------------------------+
++	* | MV buffer  64 bytes x MBs |
++	* +---------------------------+
++	* | MC sync          32 bytes |
++	* +---------------------------+
++	*/
++	return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
++}
++
+ void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
+ void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx);
+ void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
+diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
+index 3142ab6697d5..458b502ff01b 100644
+--- a/drivers/staging/media/hantro/hantro_v4l2.c
++++ b/drivers/staging/media/hantro/hantro_v4l2.c
+@@ -273,32 +273,11 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
+ 		/* Fill remaining fields */
+ 		v4l2_fill_pixfmt_mp(pix_mp, fmt->fourcc, pix_mp->width,
+ 				    pix_mp->height);
+-		/*
+-		 * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
+-		 * 448 bytes per macroblock with additional 32 bytes on
+-		 * multi-core variants.
+-		 *
+-		 * The H264 decoder needs extra space on the output buffers
+-		 * to store motion vectors. This is needed for reference
+-		 * frames and only if the format is non-post-processed NV12.
+-		 *
+-		 * Memory layout is as follow:
+-		 *
+-		 * +---------------------------+
+-		 * | Y-plane   256 bytes x MBs |
+-		 * +---------------------------+
+-		 * | UV-plane  128 bytes x MBs |
+-		 * +---------------------------+
+-		 * | MV buffer  64 bytes x MBs |
+-		 * +---------------------------+
+-		 * | MC sync          32 bytes |
+-		 * +---------------------------+
+-		 */
+ 		if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE &&
+ 		    !hantro_needs_postproc(ctx, fmt))
+ 			pix_mp->plane_fmt[0].sizeimage +=
+-				64 * MB_WIDTH(pix_mp->width) *
+-				     MB_WIDTH(pix_mp->height) + 32;
++				hantro_h264_mv_size(pix_mp->width,
++						    pix_mp->height);
+ 	} else if (!pix_mp->plane_fmt[0].sizeimage) {
+ 		/*
+ 		 * For coded formats the application can specify
+-- 
+2.17.1
+
+
+From 220559bea572812494ac528eb4bb3af770748641 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:06 -0300
+Subject: [PATCH] hantro: Refactor for V4L2 API spec compliancy
+
+Refactor how S_FMT and TRY_FMT are handled, and also make sure
+internal initial format and format reset are done properly.
+
+The latter is achieved by making sure the same hantro_{set,try}_fmt
+helpers are called on all paths that set the format (which is
+part of the driver state).
+
+This commit removes the following v4l2-compliance warnings:
+
+test VIDIOC_G_FMT: OK
+	fail: v4l2-test-formats.cpp(711): Video Capture Multiplanar: TRY_FMT(G_FMT) != G_FMT
+test VIDIOC_TRY_FMT: FAIL
+	fail: v4l2-test-formats.cpp(1116): Video Capture Multiplanar: S_FMT(G_FMT) != G_FMT
+test VIDIOC_S_FMT: FAIL
+
+Reported-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ drivers/staging/media/hantro/hantro.h      |  3 +-
+ drivers/staging/media/hantro/hantro_v4l2.c | 70 ++++++++++++++--------
+ 2 files changed, 47 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
+index 1a010d438ac2..f0aca46969f9 100644
+--- a/drivers/staging/media/hantro/hantro.h
++++ b/drivers/staging/media/hantro/hantro.h
+@@ -417,7 +417,8 @@ hantro_get_dst_buf(struct hantro_ctx *ctx)
+ }
+ 
+ static inline bool
+-hantro_needs_postproc(struct hantro_ctx *ctx, const struct hantro_fmt *fmt)
++hantro_needs_postproc(const struct hantro_ctx *ctx,
++		      const struct hantro_fmt *fmt)
+ {
+ 	return fmt->fourcc != V4L2_PIX_FMT_NV12;
+ }
+diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
+index 458b502ff01b..f28a94e2fa93 100644
+--- a/drivers/staging/media/hantro/hantro_v4l2.c
++++ b/drivers/staging/media/hantro/hantro_v4l2.c
+@@ -30,6 +30,11 @@
+ #include "hantro_hw.h"
+ #include "hantro_v4l2.h"
+ 
++static int hantro_set_fmt_out(struct hantro_ctx *ctx,
++			      struct v4l2_pix_format_mplane *pix_mp);
++static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
++			      struct v4l2_pix_format_mplane *pix_mp);
++
+ static const struct hantro_fmt *
+ hantro_get_formats(const struct hantro_ctx *ctx, unsigned int *num_fmts)
+ {
+@@ -227,12 +232,12 @@ static int vidioc_g_fmt_cap_mplane(struct file *file, void *priv,
+ 	return 0;
+ }
+ 
+-static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
+-			  bool capture)
++static int hantro_try_fmt(const struct hantro_ctx *ctx,
++			  struct v4l2_pix_format_mplane *pix_mp,
++			  enum v4l2_buf_type type)
+ {
+-	struct hantro_ctx *ctx = fh_to_ctx(priv);
+-	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+ 	const struct hantro_fmt *fmt, *vpu_fmt;
++	bool capture = !V4L2_TYPE_IS_OUTPUT(type);
+ 	bool coded;
+ 
+ 	coded = capture == hantro_is_encoder_ctx(ctx);
+@@ -246,7 +251,7 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
+ 	fmt = hantro_find_format(ctx, pix_mp->pixelformat);
+ 	if (!fmt) {
+ 		fmt = hantro_get_default_fmt(ctx, coded);
+-		f->fmt.pix_mp.pixelformat = fmt->fourcc;
++		pix_mp->pixelformat = fmt->fourcc;
+ 	}
+ 
+ 	if (coded) {
+@@ -294,13 +299,13 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f,
+ static int vidioc_try_fmt_cap_mplane(struct file *file, void *priv,
+ 				     struct v4l2_format *f)
+ {
+-	return vidioc_try_fmt(file, priv, f, true);
++	return hantro_try_fmt(fh_to_ctx(priv), &f->fmt.pix_mp, f->type);
+ }
+ 
+ static int vidioc_try_fmt_out_mplane(struct file *file, void *priv,
+ 				     struct v4l2_format *f)
+ {
+-	return vidioc_try_fmt(file, priv, f, false);
++	return hantro_try_fmt(fh_to_ctx(priv), &f->fmt.pix_mp, f->type);
+ }
+ 
+ static void
+@@ -334,11 +339,12 @@ hantro_reset_encoded_fmt(struct hantro_ctx *ctx)
+ 	}
+ 
+ 	hantro_reset_fmt(fmt, vpu_fmt);
+-	fmt->num_planes = 1;
+ 	fmt->width = vpu_fmt->frmsize.min_width;
+ 	fmt->height = vpu_fmt->frmsize.min_height;
+-	fmt->plane_fmt[0].sizeimage = vpu_fmt->header_size +
+-				fmt->width * fmt->height * vpu_fmt->max_depth;
++	if (hantro_is_encoder_ctx(ctx))
++		hantro_set_fmt_cap(ctx, fmt);
++	else
++		hantro_set_fmt_out(ctx, fmt);
+ }
+ 
+ static void
+@@ -360,9 +366,12 @@ hantro_reset_raw_fmt(struct hantro_ctx *ctx)
+ 	}
+ 
+ 	hantro_reset_fmt(raw_fmt, raw_vpu_fmt);
+-	v4l2_fill_pixfmt_mp(raw_fmt, raw_vpu_fmt->fourcc,
+-			    encoded_fmt->width,
+-			    encoded_fmt->height);
++	raw_fmt->width = encoded_fmt->width;
++	raw_fmt->width = encoded_fmt->width;
++	if (hantro_is_encoder_ctx(ctx))
++		hantro_set_fmt_out(ctx, raw_fmt);
++	else
++		hantro_set_fmt_cap(ctx, raw_fmt);
+ }
+ 
+ void hantro_reset_fmts(struct hantro_ctx *ctx)
+@@ -388,15 +397,15 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc)
+ 	}
+ }
+ 
+-static int
+-vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f)
++static int hantro_set_fmt_out(struct hantro_ctx *ctx,
++			      struct v4l2_pix_format_mplane *pix_mp)
+ {
+-	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+-	struct hantro_ctx *ctx = fh_to_ctx(priv);
+-	struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
++	struct vb2_queue *vq;
+ 	int ret;
+ 
+-	ret = vidioc_try_fmt_out_mplane(file, priv, f);
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
++			     V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
++	ret = hantro_try_fmt(ctx, pix_mp, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -458,16 +467,15 @@ vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f)
+ 	return 0;
+ }
+ 
+-static int vidioc_s_fmt_cap_mplane(struct file *file, void *priv,
+-				   struct v4l2_format *f)
++static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
++			      struct v4l2_pix_format_mplane *pix_mp)
+ {
+-	struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
+-	struct hantro_ctx *ctx = fh_to_ctx(priv);
+ 	struct vb2_queue *vq;
+ 	int ret;
+ 
+ 	/* Change not allowed if queue is busy. */
+-	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
++	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
++			     V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ 	if (vb2_is_busy(vq))
+ 		return -EBUSY;
+ 
+@@ -488,7 +496,7 @@ static int vidioc_s_fmt_cap_mplane(struct file *file, void *priv,
+ 			return -EBUSY;
+ 	}
+ 
+-	ret = vidioc_try_fmt_cap_mplane(file, priv, f);
++	ret = hantro_try_fmt(ctx, pix_mp, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -522,6 +530,18 @@ static int vidioc_s_fmt_cap_mplane(struct file *file, void *priv,
+ 	return 0;
+ }
+ 
++static int
++vidioc_s_fmt_out_mplane(struct file *file, void *priv, struct v4l2_format *f)
++{
++	return hantro_set_fmt_out(fh_to_ctx(priv), &f->fmt.pix_mp);
++}
++
++static int
++vidioc_s_fmt_cap_mplane(struct file *file, void *priv, struct v4l2_format *f)
++{
++	return hantro_set_fmt_cap(fh_to_ctx(priv), &f->fmt.pix_mp);
++}
++
+ const struct v4l2_ioctl_ops hantro_ioctl_ops = {
+ 	.vidioc_querycap = vidioc_querycap,
+ 	.vidioc_enum_framesizes = vidioc_enum_framesizes,
+-- 
+2.17.1
+
+
+From 03a4222379d16c8a5f4a9c74f78c977b6a0e16a0 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:07 -0300
+Subject: [PATCH] dt-bindings: rockchip-vpu: Convert bindings to json-schema
+
+Convert Rockchip VPU (Hantro IP block) codec driver documentation to
+json-schema.
+
+Cc: Rob Herring <robh@kernel.org>
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ .../bindings/media/rockchip-vpu.txt           | 43 ----------
+ .../bindings/media/rockchip-vpu.yaml          | 82 +++++++++++++++++++
+ MAINTAINERS                                   |  2 +-
+ 3 files changed, 83 insertions(+), 44 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/media/rockchip-vpu.txt
+ create mode 100644 Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.txt b/Documentation/devicetree/bindings/media/rockchip-vpu.txt
+deleted file mode 100644
+index 339252d9c515..000000000000
+--- a/Documentation/devicetree/bindings/media/rockchip-vpu.txt
++++ /dev/null
+@@ -1,43 +0,0 @@
+-device-tree bindings for rockchip VPU codec
+-
+-Rockchip (Video Processing Unit) present in various Rockchip platforms,
+-such as RK3288, RK3328 and RK3399.
+-
+-Required properties:
+-- compatible: value should be one of the following
+-		"rockchip,rk3288-vpu";
+-		"rockchip,rk3328-vpu";
+-		"rockchip,rk3399-vpu";
+-- interrupts: encoding and decoding interrupt specifiers
+-- interrupt-names: should be
+-		"vepu", "vdpu" on RK3288 and RK3399,
+-		"vdpu" on RK3328.
+-- clocks: phandle to VPU aclk, hclk clocks
+-- clock-names: should be "aclk" and "hclk"
+-- power-domains: phandle to power domain node
+-- iommus: phandle to a iommu node
+-
+-Example:
+-SoC-specific DT entry:
+-	vpu: video-codec@ff9a0000 {
+-		compatible = "rockchip,rk3288-vpu";
+-		reg = <0x0 0xff9a0000 0x0 0x800>;
+-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+-			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "vepu", "vdpu";
+-		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+-		clock-names = "aclk", "hclk";
+-		power-domains = <&power RK3288_PD_VIDEO>;
+-		iommus = <&vpu_mmu>;
+-	};
+-
+-	vpu: video-codec@ff350000 {
+-		compatible = "rockchip,rk3328-vpu";
+-		reg = <0x0 0xff350000 0x0 0x800>;
+-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-names = "vdpu";
+-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+-		clock-names = "aclk", "hclk";
+-		power-domains = <&power RK3328_PD_VPU>;
+-		iommus = <&vpu_mmu>;
+-	};
+diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+new file mode 100644
+index 000000000000..a0c45e05cf03
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+@@ -0,0 +1,82 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++
++%YAML 1.2
++---
++$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
++$schema: "http://devicetree.org/meta-schemas/core.yaml#"
++
++title: Hantro G1 VPU codecs implemented on Rockchip SoCs
++
++maintainers:
++  - Ezequiel Garcia <ezequiel@collabora.com>
++
++description:
++  Hantro G1 video encode and decode accelerators present on Rockchip SoCs.
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3288-vpu
++      - rockchip,rk3328-vpu
++      - rockchip,rk3399-vpu
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 2
++
++  interrupt-names:
++    items:
++      - const: vepu
++      - const: vdpu
++
++  clocks:
++    maxItems: 2
++
++  clock-names:
++    items:
++      - const: aclk
++      - const: hclk
++
++  power-domains:
++    maxItems: 1
++
++  iommus:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - interrupts
++  - interrupt-names
++  - clocks
++  - clock-names
++
++examples:
++  - |
++        #include <dt-bindings/clock/rk3288-cru.h>
++        #include <dt-bindings/interrupt-controller/arm-gic.h>
++
++        vpu: video-codec@ff9a0000 {
++                compatible = "rockchip,rk3288-vpu";
++                reg = <0x0 0xff9a0000 0x0 0x800>;
++                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++                interrupt-names = "vepu", "vdpu";
++                clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
++                clock-names = "aclk", "hclk";
++                power-domains = <&power RK3288_PD_VIDEO>;
++                iommus = <&vpu_mmu>;
++        };
++
++        vpu: video-codec@ff350000 {
++                compatible = "rockchip,rk3328-vpu";
++                reg = <0x0 0xff350000 0x0 0x800>;
++                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++                interrupt-names = "vdpu";
++                clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++                clock-names = "aclk", "hclk";
++                power-domains = <&power RK3328_PD_VPU>;
++                iommus = <&vpu_mmu>;
++        };
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 0bff05c4c96d..ca95e804aae0 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -14319,7 +14319,7 @@ M:	Ezequiel Garcia <ezequiel@collabora.com>
+ L:	linux-media@vger.kernel.org
+ S:	Maintained
+ F:	drivers/staging/media/hantro/
+-F:	Documentation/devicetree/bindings/media/rockchip-vpu.txt
++F:	Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+ 
+ ROCKER DRIVER
+ M:	Jiri Pirko <jiri@resnulli.us>
+-- 
+2.17.1
+
+
+From 1eba04297572f566a06ab9fe50f901640c77b091 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel@collabora.com>
+Date: Wed, 18 Mar 2020 10:21:08 -0300
+Subject: [PATCH] hantro: Add linux-rockchip mailing list to MAINTAINERS
+
+The linux-rockchip mailing list is relevant for the
+Hantro driver, given this support the VPU present
+in Rockchip SoCs.
+
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+---
+ MAINTAINERS | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index ca95e804aae0..47876afb9e26 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -14317,6 +14317,7 @@ F:	Documentation/devicetree/bindings/media/rockchip-rga.txt
+ HANTRO VPU CODEC DRIVER
+ M:	Ezequiel Garcia <ezequiel@collabora.com>
+ L:	linux-media@vger.kernel.org
++L:	linux-rockchip@lists.infradead.org
+ S:	Maintained
+ F:	drivers/staging/media/hantro/
+ F:	Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+-- 
+2.17.1
+

patch/kernel/rk322x-current/01-linux-1000-clk-rockchip-rk3228-fixup.patch

@@ -0,0 +1,98 @@
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 0127d702720c..6ef71ec239ae 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -353,7 +353,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 			RK2928_CLKGATE_CON(10), 12, GFLAGS),
+ 
+ 	COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
+-			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
++			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ 			RK2928_CLKGATE_CON(2), 15, GFLAGS),
+ 
+ 	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
+-- 
+2.17.1
+
+
+From 3acbbe5eb438e8b1061a803881579030d3c2b424 Mon Sep 17 00:00:00 2001
+From: Chen Lei <lei.chen@rock-chips.com>
+Date: Tue, 25 Dec 2018 18:29:04 +0800
+Subject: [PATCH] clk: rockchip: rk322x: fix wrong mmc phase shift for rk3228
+
+mmc sample shift should be 1 for rk3228, or it will fail
+if we enable mmc tuning for rk3228.
+
+Change-Id: I301c2a7d33de8d519d7c288aef03a82531016373
+Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 6ef71ec239ae..27adfca1a095 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -610,13 +610,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 
+ 	/* PD_MMC */
+ 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
+-	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
++	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
+ 
+ 	MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3228_SDIO_CON0,  1),
+-	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  0),
++	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  1),
+ 
+ 	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),
+-	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),
++	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  1),
+ };
+ 
+ static const char *const rk3228_critical_clocks[] __initconst = {
+-- 
+2.17.1
+
+
+From a692001c1249473bdfe975ef53d2bdb8a4df736d Mon Sep 17 00:00:00 2001
+From: Finley Xiao <finley.xiao@rock-chips.com>
+Date: Mon, 5 Feb 2018 10:04:15 +0800
+Subject: [PATCH] clk: rockchip: rk3228: Fix armclk parent
+
+Change-Id: I09830d96b37cca600f1782b9013b25e043467f97
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 58292f80ad66..fba513de94eb 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -170,7 +170,7 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
+ 	[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
+ 		     RK2928_MODE_CON, 8, 8, 0, NULL),
+ 	[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
+-		     RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
++		     RK2928_MODE_CON, 12, 9, 0, rk3228_pll_rates),
+ };
+ 
+ #define MFLAGS CLK_MUX_HIWORD_MASK
+-- 
+2.17.1
+
+
+From f57d5061e7357a8f7a181517530658a223ba415b Mon Sep 17 00:00:00 2001
+From: Finley Xiao <finley.xiao@rock-chips.com>
+Date: Thu, 22 Jun 2017 19:53:46 +0800
+Subject: [PATCH] clk: rockchip: rk3228: fix gpu gate-register
+
+Fix a typo making the aclk_gpu and aclk_gpu_noc access a wrong register to
+handle its gate.
+
+Change-Id: Ie0bac8014363af7c0409b8a56eacf2e858818843
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+---
+ drivers/clk/rockchip/clk-rk3228.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+

patch/kernel/rk322x-current/01-linux-1001-clk-rockchip-rk3228-more-fixes.patch

@@ -0,0 +1,219 @@
+diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
+index 448b202bf4f3..828d0003a18e 100644
+--- a/drivers/clk/rockchip/clk-rk3228.c
++++ b/drivers/clk/rockchip/clk-rk3228.c
+@@ -510,12 +510,12 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 
+ 	/* PD_VOP */
+ 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
+-	GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
++	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),
+ 	GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
+-	GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
++	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),
+ 
+ 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
+-	GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
++	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),
+ 
+ 	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
+ 	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
+@@ -523,13 +523,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
+ 	GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
+ 	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
+-	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
+-	GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
+-	GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
+-	GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
++	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),
++	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),
++	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),
++	GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 7, GFLAGS),
+ 	GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
+ 	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
+-	GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
++	GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 8, GFLAGS),
+ 	GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
+ 
+ 	/* PD_PERI */
+@@ -541,13 +541,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
+ 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
+ 	GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
+-	GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
++	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),
+ 	GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
+-	GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
++	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),
+ 	GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
+ 	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
+-	GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
+-	GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
++	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),
++	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),
+ 	GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
+ 
+ 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
+@@ -555,15 +555,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 
+ 	/* PD_GPU */
+ 	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
+-	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
++	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 15, GFLAGS),
+ 
+ 	/* PD_BUS */
+-	GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
+-	GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
++	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),
++	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),
+ 	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
+ 	GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
+ 
+-	GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
++	GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),
+ 	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
+ 	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
+ 	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
+@@ -572,9 +572,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+ 	GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
+ 
+-	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
+-	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
+-	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
++	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),
++	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),
++	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
+ 
+ 	GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+ 	GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
+@@ -583,7 +583,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
+ 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
+ 	GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
+-	GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
++	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),
+ 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
+ 	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
+ 	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
+@@ -597,22 +597,22 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
+ 	GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
+ 	GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
+ 	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
+-	GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
++	GATE(0, "pclk_sim", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+ 
+-	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
+-	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
++	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
++	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),
+ 	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
+-	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
+-	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
++	GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 8, GFLAGS),
++	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),
+ 
+ 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
+-	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
++	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),
+ 	GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
+-	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
++	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),
+ 	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
+-	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
++	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),
+ 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
+-	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
++	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),
+ 
+ 	/* PD_MMC */
+ 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
+@@ -656,25 +656,34 @@ static const char *const rk3228_critical_clocks[] __initconst = {
+ 	"pclk_phy_noc",
+ 	"aclk_vpu_noc",
+ 	"aclk_rkvdec_noc",
++	"aclk_rkvdec",
+ 	"hclk_vpu_noc",
+ 	"hclk_rkvdec_noc",
++	"hclk_rkvdec",
+ };
+ 
++static void __iomem *rk3228_cru_base;
++
++static void rk3228_clk_shutdown(void)
++{
++	writel_relaxed(0x11010000, rk3228_cru_base + RK3228_MODE_CON);
++}
++
+ static void __init rk3228_clk_init(struct device_node *np)
+ {
+ 	struct rockchip_clk_provider *ctx;
+-	void __iomem *reg_base;
+ 
+-	reg_base = of_iomap(np, 0);
+-	if (!reg_base) {
++	rk3228_cru_base = of_iomap(np, 0);
++
++	if (!rk3228_cru_base) {
+ 		pr_err("%s: could not map cru region\n", __func__);
+ 		return;
+ 	}
+ 
+-	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
++	ctx = rockchip_clk_init(np, rk3228_cru_base, CLK_NR_CLKS);
+ 	if (IS_ERR(ctx)) {
+ 		pr_err("%s: rockchip clk init failed\n", __func__);
+-		iounmap(reg_base);
++		iounmap(rk3228_cru_base);
+ 		return;
+ 	}
+ 
+@@ -691,10 +700,10 @@ static void __init rk3228_clk_init(struct device_node *np)
+ 			&rk3228_cpuclk_data, rk3228_cpuclk_rates,
+ 			ARRAY_SIZE(rk3228_cpuclk_rates));
+ 
+-	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
++	rockchip_register_softrst(np, 9, rk3228_cru_base + RK2928_SOFTRST_CON(0),
+ 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
+ 
+-	rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
++	rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, rk3228_clk_shutdown);
+ 
+ 	rockchip_clk_of_add_provider(np, ctx);
+ }
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index 2271a84124b0..f2f80f224f30 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -134,6 +134,7 @@ struct clk;
+ #define RK3308_EMMC_CON0		0x490
+ #define RK3308_EMMC_CON1		0x494
+ 
++#define RK3228_MODE_CON		0x40
+ #define RK3328_PLL_CON(x)		RK2928_PLL_CON(x)
+ #define RK3328_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
+ #define RK3328_CLKGATE_CON(x)		((x) * 0x4 + 0x200)
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index de550ea56eeb..16e1feae5ce4 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
++++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -65,6 +65,7 @@
+ #define SCLK_OTGPHY0		142
+ #define SCLK_OTGPHY1		143
+ #define SCLK_HDMI_PHY		144
++#define SCLK_DDRC		145
+ 
+ /* dclk gates */
+ #define DCLK_VOP		190
+@@ -115,6 +116,7 @@
+ #define PCLK_HDMI_CTRL		364
+ #define PCLK_HDMI_PHY		365
+ #define PCLK_GMAC		367
++#define PCLK_ACODECPHY		368
+ 
+ /* hclk gates */
+ #define HCLK_I2S0_8CH		442
+-- 
+2.17.1
+

patch/kernel/rk322x-current/01-linux-1003-rk322x-hantro.patch

@@ -0,0 +1,97 @@
+diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+index a0c45e05cf03..a20cfaa8973e 100644
+--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+@@ -16,6 +16,7 @@ description:
+ properties:
+   compatible:
+     enum:
++      - rockchip,rk322x-vpu
+       - rockchip,rk3288-vpu
+       - rockchip,rk3328-vpu
+       - rockchip,rk3399-vpu
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index f7a50b903a7d..2ed8aa7ae520 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -676,6 +676,18 @@
+ 		};
+ 	};
+ 
++	vpu: video-codec@20020000 {
++		compatible = "rockchip,rk322x-vpu";
++		reg = <0x20020000 0x800>;
++		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "vepu", "vdpu";
++		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++		clock-names = "aclk", "hclk";
++		iommus = <&vpu_mmu>;
++		power-domains = <&power RK3228_PD_VPU>;
++	};
++
+ 	vpu_mmu: iommu@20020800 {
+ 		compatible = "rockchip,iommu";
+ 		reg = <0x20020800 0x100>;
+diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
+index de77fe6554e7..9f99d1c9f453 100644
+--- a/drivers/staging/media/hantro/Kconfig
++++ b/drivers/staging/media/hantro/Kconfig
+@@ -20,4 +20,4 @@ config VIDEO_HANTRO_ROCKCHIP
+ 	depends on ARCH_ROCKCHIP || COMPILE_TEST
+ 	default y
+ 	help
+-	  Enable support for RK3288, RK3328, and RK3399 SoCs.
++	  Enable support for RK322x, RK3288, RK3328, and RK3399 SoCs.
+diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
+index a732beeb3bb6..fae9555a349b 100644
+--- a/drivers/staging/media/hantro/hantro_drv.c
++++ b/drivers/staging/media/hantro/hantro_drv.c
+@@ -469,6 +469,7 @@ static const struct of_device_id of_hantro_match[] = {
+ 	{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
+ 	{ .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
++	{ .compatible = "rockchip,rk322x-vpu", .data = &rk322x_vpu_variant, },
+ #endif
+ 	{ /* sentinel */ }
+ };
+diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
+index 33c1ce169203..e64369e01a21 100644
+--- a/drivers/staging/media/hantro/hantro_hw.h
++++ b/drivers/staging/media/hantro/hantro_hw.h
+@@ -157,6 +157,7 @@ enum hantro_enc_fmt {
+ extern const struct hantro_variant rk3399_vpu_variant;
+ extern const struct hantro_variant rk3328_vpu_variant;
+ extern const struct hantro_variant rk3288_vpu_variant;
++extern const struct hantro_variant rk322x_vpu_variant;
+ 
+ extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
+ 
+diff --git a/drivers/staging/media/hantro/rk3399_vpu_hw.c b/drivers/staging/media/hantro/rk3399_vpu_hw.c
+index 78f878ca01ff..0a6c021c2332 100644
+--- a/drivers/staging/media/hantro/rk3399_vpu_hw.c
++++ b/drivers/staging/media/hantro/rk3399_vpu_hw.c
+@@ -241,3 +241,20 @@ const struct hantro_variant rk3328_vpu_variant = {
+ 	.clk_names = rk3399_clk_names,
+ 	.num_clocks = ARRAY_SIZE(rk3399_clk_names),
+ };
++
++const struct hantro_variant rk322x_vpu_variant = {
++	.enc_offset = 0x0,
++	.enc_fmts = rk3399_vpu_enc_fmts,
++	.num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
++	.dec_offset = 0x400,
++	.dec_fmts = rk3399_vpu_dec_fmts,
++	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
++	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
++		 HANTRO_H264_DECODER,
++	.codec_ops = rk3399_vpu_codec_ops,
++	.irqs = rk3399_irqs,
++	.num_irqs = ARRAY_SIZE(rk3399_irqs),
++	.init = rk3399_vpu_hw_init,
++	.clk_names = rk3399_clk_names,
++	.num_clocks = ARRAY_SIZE(rk3399_clk_names)
++};
+-- 
+2.17.1
+

patch/kernel/rk322x-current/01-linux-1004-rockchip-rk322x-enhancements-and-fixes.patch

@@ -0,0 +1,439 @@
+diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
+index 54eb6cfc5d5b..c6b33f7c43df 100644
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -71,6 +71,7 @@ struct rockchip_pm_domain {
+ 	struct regmap **qos_regmap;
+ 	u32 *qos_save_regs[MAX_QOS_REGS_NUM];
+ 	int num_clks;
++	bool is_ignore_pwr;
+ 	struct clk_bulk_data *clks;
+ };
+ 
+@@ -330,6 +331,9 @@ static int rockchip_pd_power_on(struct generic_pm_domain *domain)
+ {
+ 	struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+ 
++	if (pd->is_ignore_pwr)
++		return 0;
++
+ 	return rockchip_pd_power(pd, true);
+ }
+ 
+@@ -337,6 +341,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain)
+ {
+ 	struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
+ 
++	if (pd->is_ignore_pwr)
++		return 0;
++
+ 	return rockchip_pd_power(pd, false);
+ }
+ 
+@@ -416,6 +423,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
+ 	pd->info = pd_info;
+ 	pd->pmu = pmu;
+ 
++	if (!pd_info->pwr_mask)
++		pd->is_ignore_pwr = true;
++
+ 	pd->num_clks = of_clk_get_parent_count(node);
+ 	if (pd->num_clks > 0) {
+ 		pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
+@@ -566,6 +576,7 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
+ {
+ 	struct device_node *np;
+ 	struct generic_pm_domain *child_domain, *parent_domain;
++	struct rockchip_pm_domain *child_pd, *parent_pd;
+ 	int error;
+ 
+ 	for_each_child_of_node(parent, np) {
+@@ -606,6 +617,18 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
+ 				parent_domain->name, child_domain->name);
+ 		}
+ 
++		/*
++		 * If child_pd doesn't do idle request or power on/off,
++		 * parent_pd may fail to do power on/off, so if parent_pd
++		 * need to power on/off, child_pd can't ignore to do idle
++		 * request and power on/off.
++		 */
++		child_pd = to_rockchip_pd(child_domain);
++		parent_pd = to_rockchip_pd(parent_domain);
++		if (!parent_pd->is_ignore_pwr)
++			child_pd->is_ignore_pwr = false;
++
++
+ 		rockchip_pm_add_subdomain(pmu, np);
+ 	}
+ 
+-- 
+2.17.1
+
+From c94b1272290bafced10d79b7da1525466e8c843b Mon Sep 17 00:00:00 2001
+From: "Huang, Tao" <huangtao@rock-chips.com>
+Date: Thu, 28 Jul 2016 10:59:22 +0800
+Subject: [PATCH] power: reset: reboot-mode: fix normal mode setup
+
+If cmd is empty in get_reboot_mode_magic, we should return normal magic.
+
+Change-Id: I10931adc49e33f72ae73d9471159f82cc02ff0c0
+Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
+---
+ drivers/power/reset/reboot-mode.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c
+index b4076b10b893..47f9a162807d 100644
+--- a/drivers/power/reset/reboot-mode.c
++++ b/drivers/power/reset/reboot-mode.c
+@@ -26,7 +26,7 @@ static unsigned int get_reboot_mode_magic(struct reboot_mode_driver *reboot,
+ 	int magic = 0;
+ 	struct mode_info *info;
+ 
+-	if (!cmd)
++	if (!cmd || !cmd[0])
+ 		cmd = normal;
+ 
+ 	list_for_each_entry(info, &reboot->head, list) {
+-- 
+2.17.1
+
+
+From be9674f270c97399f9f6b1facb11e93eced6ec34 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Thu, 8 Dec 2016 16:58:07 +0800
+Subject: [PATCH] power: reset: reboot-mode: treat unrecognized reboot mode as
+ normal mode
+
+Some bootloader will check the reboot mode to take different action, so
+we treat unrecognized reboot mode as normal mode to prevent the system
+run into abnormal case.
+
+Change-Id: I88063a5b41e4e645443229fa490b2b55db5ccf27
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+---
+ drivers/power/reset/reboot-mode.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/power/reset/reboot-mode.c b/drivers/power/reset/reboot-mode.c
+index 47f9a162807d..99bf938404e3 100644
+--- a/drivers/power/reset/reboot-mode.c
++++ b/drivers/power/reset/reboot-mode.c
+@@ -47,6 +47,8 @@ static int reboot_mode_notify(struct notifier_block *this,
+ 
+ 	reboot = container_of(this, struct reboot_mode_driver, reboot_notifier);
+ 	magic = get_reboot_mode_magic(reboot, cmd);
++	if (!magic)
++		magic = get_reboot_mode_magic(reboot, NULL);
+ 	if (magic)
+ 		reboot->write(reboot, magic);
+ 
+-- 
+2.17.1
+
+From 7c097120eb21a9bd15ab63c0ac60ffd5cba902b2 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 13:01:07 +0200
+Subject: [PATCH] sound: soc: rockchip: use rouned rate for i2s
+
+---
+ sound/soc/rockchip/rockchip_i2s.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
+index 61c984f10d8e..efca853eba6b 100644
+--- a/sound/soc/rockchip/rockchip_i2s.c
++++ b/sound/soc/rockchip/rockchip_i2s.c
+@@ -279,10 +279,13 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
+ 	if (i2s->is_master_mode) {
+ 		mclk_rate = clk_get_rate(i2s->mclk);
+ 		bclk_rate = 2 * 32 * params_rate(params);
+-		if (bclk_rate && mclk_rate % bclk_rate)
++		if (!bclk_rate) {
++			dev_err(i2s->dev, "invalid bclk_rate: %d\n",
++				bclk_rate);
+ 			return -EINVAL;
++		}
+ 
+-		div_bclk = mclk_rate / bclk_rate;
++		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
+ 		div_lrck = bclk_rate / params_rate(params);
+ 		regmap_update_bits(i2s->regmap, I2S_CKR,
+ 				   I2S_CKR_MDIV_MASK,
+@@ -312,6 +315,8 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
+ 		val |= I2S_TXCR_VDW(32);
+ 		break;
+ 	default:
++		dev_err(i2s->dev, "invalid format: %d\n",
++			params_format(params));
+ 		return -EINVAL;
+ 	}
+ 
+-- 
+2.17.1
+
+From ed1bc72e4842eddebd2ee06e984d32990ea54e55 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 08:05:27 +0200
+Subject: [PATCH] drm: rockchip: vop: interlaced modes are not supported by
+ current driver - reject them
+
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index b8c0d2fcc52a..d50345bdcadc 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1063,6 +1063,8 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
+ enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc,
+ 					 const struct drm_display_mode *mode)
+ {
++	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
++		return MODE_NO_INTERLACE;
+ 	if (mode->hdisplay > 3840)
+ 		return MODE_BAD_HVALUE;
+ 
+-- 
+2.17.1
+
+From 4102c5b07d8610c729d577612c1df52737fb9a0f Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 09:08:44 +0200
+Subject: [PATCH] phy: rockchip: hdmi: readout hdmi phy flag for RK3228 HDMI
+ phys
+
+Some RK3228 HDMI phys only get a stable pll on frequencies higher 337,5 MHz.
+This is defined in a flag in efuse of those devices.
+---
+ arch/arm/boot/dts/rk322x.dtsi                 |  7 ++++
+ drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 38 ++++++++++++++++++-
+ 2 files changed, 43 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index 2ed8aa7ae520..8c50dcb0e9f1 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -402,6 +402,11 @@
+ 		cpu_leakage: cpu_leakage@17 {
+ 			reg = <0x17 0x1>;
+ 		};
++
++		hdmi_phy_flag: hdmi-phy-flag@1d {
++			reg = <0x1d 0x1>;
++			bits = <1 1>;
++		};
+ 	};
+ 
+ 	i2c0: i2c@11050000 {
+@@ -628,6 +633,8 @@
+ 		clock-names = "sysclk", "refoclk", "refpclk";
+ 		#clock-cells = <0>;
+ 		clock-output-names = "hdmiphy_phy";
++		nvmem-cells = <&hdmi_phy_flag>;
++		nvmem-cell-names = "hdmi-phy-flag";
+ 		#phy-cells = <0>;
+ 		status = "disabled";
+ 	};
+diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+index bb8bdf5e3301..0c7a97352714 100644
+--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+@@ -237,6 +237,9 @@ struct inno_hdmi_phy {
+ 	struct clk *refoclk;
+ 	struct clk *refpclk;
+ 
++	/* phy_flag flag */
++	bool phy_flag;
++
+ 	/* platform data */
+ 	const struct inno_hdmi_phy_drv_data *plat_data;
+ 	int chip_version;
+@@ -347,6 +350,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
+ static const struct post_pll_config post_pll_cfg_table[] = {
+ 	{33750000,  1, 40, 8, 1},
+ 	{33750000,  1, 80, 8, 2},
++	{33750000,  1, 10, 2, 4},
+ 	{74250000,  1, 40, 8, 1},
+ 	{74250000, 18, 80, 8, 2},
+ 	{148500000, 2, 40, 4, 3},
+@@ -497,8 +501,11 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
+ 		return -EINVAL;
+ 
+ 	for (; cfg->tmdsclock != 0; cfg++)
+-		if (tmdsclock <= cfg->tmdsclock &&
+-		    cfg->version & inno->chip_version)
++		if (((!inno->phy_flag || tmdsclock > 33750000)
++		     && tmdsclock <= cfg->tmdsclock
++		     && cfg->version & inno->chip_version) ||
++		    (inno->phy_flag && tmdsclock <= 33750000
++		     && cfg->version & 4))
+ 			break;
+ 
+ 	for (; phy_cfg->tmdsclock != 0; phy_cfg++)
+@@ -909,6 +916,10 @@ static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
+ 
+ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
+ {
++	struct nvmem_cell *cell;
++	unsigned char *efuse_buf;
++	size_t len;
++
+ 	/*
+ 	 * Use phy internal register control
+ 	 * rxsense/poweron/pllpd/pdataen signal.
+@@ -923,7 +934,28 @@ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
+ 	inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
+ 			 RK3228_POST_PLL_CTRL_MANUAL);
+ 
++
+ 	inno->chip_version = 1;
++	inno->phy_flag = false;
++
++	cell = nvmem_cell_get(inno->dev, "hdmi-phy-flag");
++	if (IS_ERR(cell)) {
++		if (PTR_ERR(cell) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++
++		return 0;
++	}
++
++	efuse_buf = nvmem_cell_read(cell, &len);
++	nvmem_cell_put(cell);
++
++	if (IS_ERR(efuse_buf))
++		return 0;
++	if (len == 1)
++		inno->phy_flag = (efuse_buf[0] & BIT(1)) ? true : false;
++	kfree(efuse_buf);
++
++	dev_info(inno->dev, "phy_flag is: %d\n", inno->phy_flag);
+ 
+ 	return 0;
+ }
+@@ -1023,6 +1055,8 @@ static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
+ 
+ 	/* try to read the chip-version */
+ 	inno->chip_version = 1;
++	inno->phy_flag = false;
++
+ 	cell = nvmem_cell_get(inno->dev, "cpu-version");
+ 	if (IS_ERR(cell)) {
+ 		if (PTR_ERR(cell) == -EPROBE_DEFER)
+-- 
+2.17.1
+
+From 80891e83d78781a8dddf8a5e50d89ad944d9c55b Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 14:15:08 +0200
+Subject: [PATCH] drm: rockchip: allow ycbcr420 and yuv444 for RK3228 HDMI
+
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index eb405cb3d1f6..cb2d3d6bab95 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -552,6 +552,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
+ 
+ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
+ 	.lcdsel_grf_reg = -1,
++	.ycbcr_444_allowed = false,
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+@@ -560,6 +561,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+ 	.phy_ops = &rk3228_hdmi_phy_ops,
+ 	.phy_name = "inno_dw_hdmi_phy2",
+ 	.phy_force_vendor = true,
++	.ycbcr_420_allowed = false,
+ };
+ 
+ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
+-- 
+2.17.1
+
+From fe30b024a7a7d6261dff0b87c2aec270ad530c39 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Fri, 24 Apr 2020 14:23:38 +0200
+Subject: [PATCH] drm: rockchip: Use 2nd RK3228 plane as an overlay
+
+As per datasheet the second plane of RK3228 vop is an overlay window. For
+the missing implementation of hardware cursor it is missued as such (as
+already pointed in comment for RK3288). Furthermore the overlay window
+does not support YUV modes with the current implementation - so it
+supports only RGB modes for now.
+---
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 44 +++++++++++++++++++--
+ 1 file changed, 41 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 73d24c6bbf05..d4ac6e161ef2 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -614,6 +614,44 @@ static const struct vop_common rk3288_common = {
+ 	.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
+ };
+ 
++static const struct vop_win_phy rk3228_win0_data = {
++	.scl = &rk3288_win_full_scl,
++	.data_formats = formats_win_full,
++	.nformats = ARRAY_SIZE(formats_win_full),
++	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
++	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
++	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
++	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
++	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
++	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
++	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
++	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
++	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
++	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
++	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
++	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
++	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
++};
++
++static const struct vop_win_phy rk3228_win1_data = {
++	.scl = &rk3288_win_full_scl,
++	.data_formats = formats_win_lite,
++	.nformats = ARRAY_SIZE(formats_win_lite),
++	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
++	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
++	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
++	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
++	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
++	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
++	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
++	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
++	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
++	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
++	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
++	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
++	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
++};
++
+ /*
+  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
+  * special support to get alpha blending working.  For now, just use overlay
+@@ -864,10 +902,10 @@ static const struct vop_data rk3399_vop_lit = {
+ };
+ 
+ static const struct vop_win_data rk3228_vop_win_data[] = {
+-	{ .base = 0x00, .phy = &rk3288_win01_data,
++	{ .base = 0x00, .phy = &rk3228_win0_data,
+ 	  .type = DRM_PLANE_TYPE_PRIMARY },
+-	{ .base = 0x40, .phy = &rk3288_win01_data,
+-	  .type = DRM_PLANE_TYPE_CURSOR },
++	{ .base = 0x40, .phy = &rk3228_win1_data,
++	  .type = DRM_PLANE_TYPE_OVERLAY },
+ };
+ 
+ static const struct vop_data rk3228_vop = {
+-- 
+2.17.1
+

patch/kernel/rk322x-current/02-linux-0001-add-board-makefile.patch

@@ -0,0 +1,12 @@
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 08011dc8c..4bee5c4cd 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -923,6 +923,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3228-evb.dtb \
+ 	rk3229-evb.dtb \
+ 	rk3229-xms6.dtb \
++	rk322x-box.dtb \
+ 	rk3288-evb-act8846.dtb \
+ 	rk3288-evb-rk808.dtb \
+ 	rk3288-firefly-beta.dtb \

patch/kernel/rk322x-current/02-linux-0003-dtsi-integrate-rk322x-box.patch

@@ -0,0 +1,15 @@
+diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi
+index 44fb2f4ea..15d07a736 100644
+--- a/arch/arm/boot/dts/rk322x-box.dtsi
++++ b/arch/arm/boot/dts/rk322x-box.dtsi
+@@ -89,6 +89,10 @@
+ 	cap-mmc-highspeed;
+ 	keep-power-in-suspend;
+ 	non-removable;
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	/delete-property/ default-sample-phase;
++	rockchip,default-sample-phase = <180>;
+ };
+ 
+ &gmac {

patch/kernel/rk322x-current/02-linux-0004-dtsi-adjust-nand-pinctrls.patch

@@ -0,0 +1,92 @@
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index b2fcf0e75..25051c03f 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -1149,51 +1149,71 @@
+ 
+ 			flash_cs0: flash-cs0 {
+ 				rockchip,pins =
+-					<2 RK_PA6 1 &pcfg_pull_none>;
++					<2 RK_PA6 RK_FUNC_1 &pcfg_pull_up>;
+ 			};
+ 
+ 			flash_cs1: flash-cs1 {
+ 				rockchip,pins =
+-					<0 RK_PC7 1 &pcfg_pull_none>;
++					<0 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_cs2: flash-cs2 {
++				rockchip,pins =
++					<1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_cs3: flash-cs3 {
++				rockchip,pins =
++					<1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
+ 			};
+ 
+ 			flash_rdy: flash-rdy {
+ 				rockchip,pins =
+-					<2 RK_PA4 1 &pcfg_pull_none>;
++					<2 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
+ 			};
+ 
+ 			flash_ale: flash-ale {
+ 				rockchip,pins =
+-					<2 RK_PA0 1 &pcfg_pull_none>;
++					<2 RK_PA0 RK_FUNC_1 &pcfg_pull_down>;
+ 			};
+ 
+ 			flash_cle: flash-cle {
+ 				rockchip,pins =
+-					<2 RK_PA1 1 &pcfg_pull_none>;
++					<2 RK_PA1 RK_FUNC_1 &pcfg_pull_down>;
+ 			};
+ 
+ 			flash_wrn: flash-wrn {
+-				rockchip,pins =
+-					<2 RK_PA2 1 &pcfg_pull_none>;
++			rockchip,pins =
++					<2 RK_PA2 RK_FUNC_1 &pcfg_pull_up>;
+ 			};
+ 
+ 			flash_rdn: flash-rdn {
+ 				rockchip,pins =
+-					<2 RK_PA3 1 &pcfg_pull_none>;
++					<2 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
+ 			};
+ 
+ 			flash_bus8: flash-bus8 {
+-				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
+-						<1 RK_PD1 1 &pcfg_pull_none>,
+-						<1 RK_PD2 1 &pcfg_pull_none>,
+-						<1 RK_PD3 1 &pcfg_pull_none>,
+-						<1 RK_PD4 1 &pcfg_pull_none>,
+-						<1 RK_PD5 1 &pcfg_pull_none>,
+-						<1 RK_PD6 1 &pcfg_pull_none>,
+-						<1 RK_PD7 1 &pcfg_pull_none>;
++				rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD4 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD5 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD6 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD7 RK_FUNC_1 &pcfg_pull_up>;
+ 			};
++
++			flash_dqs: flash-dqs {
++				rockchip,pins = <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_wp: flash-wp {
++				rockchip,pins = <2 RK_PA5 RK_FUNC_1 &pcfg_pull_down>;
++			};
++
+ 		};
+ 
++
+ 		gmac {
+ 			rgmii_pins: rgmii-pins {
+ 				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,

patch/kernel/rk322x-current/board-rk322x-box.patch

@@ -0,0 +1,219 @@
+diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
+new file mode 100644
+index 000000000..6f2833a50
+--- /dev/null
++++ b/arch/arm/boot/dts/rk322x-box.dts
+@@ -0,0 +1,213 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3228a-box.dtsi"
++
++/ {
++
++	model = "Generic RK322x Tv Box board";
++
++	/delete-node/ leds;
++
++	gpio_leds: gpio-leds {
++
++		compatible = "gpio-leds";
++
++		/*
++		 * Working led, available on all boards
++		 */
++		working {
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			label = "working";
++			default-state = "on";
++			linux,default-trigger = "timer";
++			pinctrl-names = "default";
++			pinctrl-0 = <&gpio_led_working>;
++		};
++
++	};
++
++};
++
++&emmc {
++	status = "okay";
++	/delete-property/ mmc-ddr-1_8v;
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	rockchip,default-sample-phase = <180>;
++};
++
++&nfc {
++	status = "okay";
++};
++
++&gmac {
++	tx_delay = <0x26>;
++	rx_delay = <0x11>;
++};
++
++&ir_receiver {
++	status = "okay";
++};
++
++&power_key {
++	status = "okay";
++};
++
++&usb_otg {
++        dr_mode = "host";
++};
++
++&sdio {
++	mmc-pwrseq = <&sdio_pwrseq>;
++	status = "okay";
++};
++
++&sdmmc {
++	status = "okay";
++};
++
++/** Integration to pin controller */
++&pinctrl {
++
++	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
++        	drive-strength = <12>;
++                bias-pull-up;
++        };
++
++        pcfg_pull_down_12ma: pcfg-pull-down-12ma {
++        	drive-strength = <12>;
++                bias-pull-down;
++        };
++
++        pcfg_pull_none_12ma: pcfg-pull-none-12ma {
++        	drive-strength = <12>;
++                bias-disable;
++        };
++
++	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
++        	drive-strength = <2>;
++                bias-pull-up;
++        };
++
++        pcfg_pull_down_2ma: pcfg-pull-down-2ma {
++        	drive-strength = <2>;
++                bias-pull-down;
++        };
++
++        pcfg_pull_none_2ma: pcfg-pull-none-2ma {
++        	drive-strength = <2>;
++                bias-disable;
++        };
++
++	/*
++	 * Some rk322x electrical schemes report this kind of pull-up/down
++	 * pin configurations. We set them here, but we don't use it in this
++	 * device tree. These instead are useful for overlays, because they seem
++	 * to increase stability on at least one board I got here
++	 */
++	sdmmc {
++		sdmmc_clk: sdmmc-clk {
++			rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_down>;
++		};
++
++		sdmmc_cmd: sdmmc-cmd {
++			rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_up>;
++		};
++
++		sdmmc_bus4: sdmmc-bus4 {
++			rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_up>,
++					<1 19 RK_FUNC_1 &pcfg_pull_up>,
++					<1 20 RK_FUNC_1 &pcfg_pull_up>,
++					<1 21 RK_FUNC_1 &pcfg_pull_up>;
++		};
++	};
++
++	/*
++	 * Same as above, decreasing strength of SDIO pins seems to be benefical
++	 * to stability
++	 */
++	sdio {
++		sdio_clk: sdio-clk {
++			rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_down_2ma>;
++		};
++
++		sdio_cmd: sdio-cmd {
++			rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_up_2ma>;
++		};
++
++		sdio_bus4: sdio-bus4 {
++			rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up_2ma>,
++					<3 3 RK_FUNC_1 &pcfg_pull_up_2ma>,
++					<3 4 RK_FUNC_1 &pcfg_pull_up_2ma>,
++					<3 5 RK_FUNC_1 &pcfg_pull_up_2ma>;
++		};
++	};
++
++	/*
++	 * Same drill as above, electrical schemes also report this pull-up/down
++	 * configurations.
++	 */
++	emmc {
++		emmc_clk: emmc-clk {
++			rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++		emmc_cmd: emmc-cmd {
++			rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++		emmc_bus8: emmc-bus8 {
++			rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_up>,
++					<1 25 RK_FUNC_2 &pcfg_pull_up>,
++					<1 26 RK_FUNC_2 &pcfg_pull_up>,
++					<1 27 RK_FUNC_2 &pcfg_pull_up>,
++					<1 28 RK_FUNC_2 &pcfg_pull_up>,
++					<1 29 RK_FUNC_2 &pcfg_pull_up>,
++					<1 30 RK_FUNC_2 &pcfg_pull_up>,
++					<1 31 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++		emmc_pwr: emmc-pwr {
++			rockchip,pins = <2 RK_PA5 RK_FUNC_2 &pcfg_pull_down>;
++		};
++
++		emmc_rst: emmc-rst {
++			rockchip,pins = <1 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++	};
++
++
++	gpio {
++		gpio_led_working: gpio-led-working {
++			rockchip,pins =  <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	keys {
++		pwr_key: pwr-key {
++			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	gpio {
++		gpio_led_working: gpio-led-working {
++			rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++};

patch/kernel/rk322x-current/general-add-overlay-compilation-support.patch

@@ -0,0 +1,96 @@
+diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
+index 3c79f859..4e5c1d59 100644
+--- a/arch/arm/boot/.gitignore
++++ b/arch/arm/boot/.gitignore
+@@ -3,3 +3,5 @@ zImage
+ xipImage
+ bootpImage
+ uImage
++*.dtb*
++*.scr
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 34614a48..8a8313d6 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -20,6 +20,9 @@ include scripts/Kbuild.include
+ include $(src)/Makefile
+
+ dtbinst-files	:= $(sort $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS), $(dtb-)))
++dtboinst-files	:= $(dtbo-y)
++script-files	:= $(scr-y)
++readme-files	:= $(dtbotxt-y)
+ dtbinst-dirs	:= $(subdir-y) $(subdir-m)
+
+ # Helper targets for Installing DTBs into the boot directory
+@@ -32,10 +35,19 @@ install-dir = $(patsubst $(dtbinst-root)%,$(INSTALL_DTBS_PATH)%,$(obj))
+ $(dtbinst-files): %.dtb: $(obj)/%.dtb
+ 	$(call cmd,dtb_install,$(install-dir))
+
++$(dtboinst-files): %.dtbo: $(obj)/%.dtbo
++	$(call cmd,dtb_install,$(install-dir))
++
++$(script-files): %.scr: $(obj)/%.scr
++	$(call cmd,dtb_install,$(install-dir))
++
++$(readme-files): %: $(src)/%
++	$(call cmd,dtb_install,$(install-dir))
++
+ $(dtbinst-dirs):
+ 	$(Q)$(MAKE) $(dtbinst)=$(obj)/$@
+
+-PHONY += $(dtbinst-files) $(dtbinst-dirs)
+-__dtbs_install: $(dtbinst-files) $(dtbinst-dirs)
++PHONY += $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs)
++__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs)
+
+ .PHONY: $(PHONY)
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 58c05e5d..2b95dda9 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -278,6 +278,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
+ # ---------------------------------------------------------------------------
+ DTC ?= $(objtree)/scripts/dtc/dtc
+
++# Overlay support
++DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg
++
+ # Disable noisy checks by default
+ ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),)
+ DTC_FLAGS += -Wno-unit_address_vs_reg \
+@@ -324,6 +327,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
+ $(obj)/%.dtb: $(src)/%.dts FORCE
+ 	$(call if_changed_dep,dtc)
+
++quiet_cmd_dtco = DTCO    $@
++cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
++	$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
++	$(DTC) -O dtb -o $@ -b 0 \
++		-i $(dir $<) $(DTC_FLAGS) \
++		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
++	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
++
++$(obj)/%.dtbo: $(src)/%.dts FORCE
++	$(call if_changed_dep,dtco)
++
++quiet_cmd_scr = MKIMAGE $@
++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+
+ # Bzip2
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 1bd2c74f5..560cf1c7f 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -977,6 +977,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3288-veyron-speedy.dtb \
+ 	rk3288-veyron-tiger.dtb \
+ 	rk3288-vyasa.dtb
++subdir-y       := overlay
+ dtb-$(CONFIG_ARCH_S3C24XX) += \
+ 	s3c2416-smdk2416.dtb
+ dtb-$(CONFIG_ARCH_S3C64XX) += \

patch/kernel/rk322x-current/general-add-overlay-configfs.patch

@@ -0,0 +1,358 @@
+--- /dev/null
++++ b/Documentation/devicetree/configfs-overlays.txt
+@@ -0,0 +1,31 @@
++Howto use the configfs overlay interface.
++
++A device-tree configfs entry is created in /config/device-tree/overlays
++and and it is manipulated using standard file system I/O.
++Note that this is a debug level interface, for use by developers and
++not necessarily something accessed by normal users due to the
++security implications of having direct access to the kernel's device tree.
++
++* To create an overlay you mkdir the directory:
++
++	# mkdir /config/device-tree/overlays/foo
++
++* Either you echo the overlay firmware file to the path property file.
++
++	# echo foo.dtbo >/config/device-tree/overlays/foo/path
++
++* Or you cat the contents of the overlay to the dtbo file
++
++	# cat foo.dtbo >/config/device-tree/overlays/foo/dtbo
++
++The overlay file will be applied, and devices will be created/destroyed
++as required.
++
++To remove it simply rmdir the directory.
++
++	# rmdir /config/device-tree/overlays/foo
++
++The rationalle of the dual interface (firmware & direct copy) is that each is
++better suited to different use patterns. The firmware interface is what's
++intended to be used by hardware managers in the kernel, while the copy interface
++make sense for developers (since it avoids problems with namespaces).
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index 37c2ccbefecdc..d3fc81a40c0e7 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -103,4 +103,11 @@ config OF_OVERLAY
+ config OF_NUMA
+ 	bool
+ 
++config OF_CONFIGFS
++	bool "Device Tree Overlay ConfigFS interface"
++	select CONFIGFS_FS
++	select OF_OVERLAY
++	help
++	  Enable a simple user-space driven DT overlay interface.
++
+ endif # OF
+diff --git a/drivers/of/Makefile b/drivers/of/Makefile
+index 663a4af0cccd5..b00a95adf5199 100644
+--- a/drivers/of/Makefile
++++ b/drivers/of/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-y = base.o device.o platform.o property.o
+ obj-$(CONFIG_OF_KOBJ) += kobj.o
++obj-$(CONFIG_OF_CONFIGFS) += configfs.o
+ obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
+ obj-$(CONFIG_OF_FLATTREE) += fdt.o
+ obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
+diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
+new file mode 100644
+index 000000000..5dd509e8f
+--- /dev/null
++++ b/drivers/of/configfs.c
+@@ -0,0 +1,290 @@
++/*
++ * Configfs entries for device-tree
++ *
++ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++#include <linux/ctype.h>
++#include <linux/cpu.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/configfs.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/limits.h>
++#include <linux/file.h>
++#include <linux/vmalloc.h>
++#include <linux/firmware.h>
++#include <linux/sizes.h>
++
++#include "of_private.h"
++
++struct cfs_overlay_item {
++	struct config_item	item;
++
++	char			path[PATH_MAX];
++
++	const struct firmware	*fw;
++	struct device_node	*overlay;
++	int			ov_id;
++
++	void			*dtbo;
++	int			dtbo_size;
++};
++
++static int create_overlay(struct cfs_overlay_item *overlay, void *blob, u32 blob_size)
++{
++	int err;
++
++	err = of_overlay_fdt_apply(blob, blob_size, &overlay->ov_id);
++	if (err < 0) {
++		pr_err("%s: Failed to create overlay (err=%d)\n",
++				__func__, err);
++		goto out_err;
++	}
++
++out_err:
++	return err;
++}
++
++static inline struct cfs_overlay_item *to_cfs_overlay_item(
++		struct config_item *item)
++{
++	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
++}
++
++static ssize_t cfs_overlay_item_path_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	return sprintf(page, "%s\n", overlay->path);
++}
++
++static ssize_t cfs_overlay_item_path_store(struct config_item *item,
++		const char *page, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	const char *p = page;
++	char *s;
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy to path buffer (and make sure it's always zero terminated */
++	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
++	overlay->path[sizeof(overlay->path) - 1] = '\0';
++
++	/* strip trailing newlines */
++	s = overlay->path + strlen(overlay->path);
++	while (s > overlay->path && *--s == '\n')
++		*s = '\0';
++
++	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
++
++	err = request_firmware(&overlay->fw, overlay->path, NULL);
++	if (err != 0)
++		goto out_err;
++
++	err = create_overlay(overlay, (void *)overlay->fw->data, overlay->fw->size);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++
++	release_firmware(overlay->fw);
++	overlay->fw = NULL;
++
++	overlay->path[0] = '\0';
++	return err;
++}
++
++static ssize_t cfs_overlay_item_status_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	return sprintf(page, "%s\n",
++			overlay->ov_id >= 0 ? "applied" : "unapplied");
++}
++
++CONFIGFS_ATTR(cfs_overlay_item_, path);
++CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
++
++static struct configfs_attribute *cfs_overlay_attrs[] = {
++	&cfs_overlay_item_attr_path,
++	&cfs_overlay_item_attr_status,
++	NULL,
++};
++
++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
++		void *buf, size_t max_count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
++			buf, max_count);
++
++	if (overlay->dtbo == NULL)
++		return 0;
++
++	/* copy if buffer provided */
++	if (buf != NULL) {
++		/* the buffer must be large enough */
++		if (overlay->dtbo_size > max_count)
++			return -ENOSPC;
++
++		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
++	}
++
++	return overlay->dtbo_size;
++}
++
++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
++		const void *buf, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy the contents */
++	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
++	if (overlay->dtbo == NULL)
++		return -ENOMEM;
++
++	overlay->dtbo_size = count;
++
++	err = create_overlay(overlay, overlay->dtbo, overlay->dtbo_size);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++	kfree(overlay->dtbo);
++	overlay->dtbo = NULL;
++	overlay->dtbo_size = 0;
++
++	return err;
++}
++
++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
++
++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
++	&cfs_overlay_item_attr_dtbo,
++	NULL,
++};
++
++static void cfs_overlay_release(struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	if (overlay->ov_id >= 0)
++		of_overlay_remove(&overlay->ov_id);
++	if (overlay->fw)
++		release_firmware(overlay->fw);
++	/* kfree with NULL is safe */
++	kfree(overlay->dtbo);
++	kfree(overlay);
++}
++
++static struct configfs_item_operations cfs_overlay_item_ops = {
++	.release	= cfs_overlay_release,
++};
++
++static struct config_item_type cfs_overlay_type = {
++	.ct_item_ops	= &cfs_overlay_item_ops,
++	.ct_attrs	= cfs_overlay_attrs,
++	.ct_bin_attrs	= cfs_overlay_bin_attrs,
++	.ct_owner	= THIS_MODULE,
++};
++
++static struct config_item *cfs_overlay_group_make_item(
++		struct config_group *group, const char *name)
++{
++	struct cfs_overlay_item *overlay;
++
++	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
++	if (!overlay)
++		return ERR_PTR(-ENOMEM);
++	overlay->ov_id = -1;
++
++	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
++	return &overlay->item;
++}
++
++static void cfs_overlay_group_drop_item(struct config_group *group,
++		struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	config_item_put(&overlay->item);
++}
++
++static struct configfs_group_operations overlays_ops = {
++	.make_item	= cfs_overlay_group_make_item,
++	.drop_item	= cfs_overlay_group_drop_item,
++};
++
++static struct config_item_type overlays_type = {
++	.ct_group_ops   = &overlays_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++static struct configfs_group_operations of_cfs_ops = {
++	/* empty - we don't allow anything to be created */
++};
++
++static struct config_item_type of_cfs_type = {
++	.ct_group_ops   = &of_cfs_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++struct config_group of_cfs_overlay_group;
++
++static struct configfs_subsystem of_cfs_subsys = {
++	.su_group = {
++		.cg_item = {
++			.ci_namebuf = "device-tree",
++			.ci_type = &of_cfs_type,
++		},
++	},
++	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
++};
++
++static int __init of_cfs_init(void)
++{
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	config_group_init(&of_cfs_subsys.su_group);
++	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
++			&overlays_type);
++	configfs_add_default_group(&of_cfs_overlay_group,
++			&of_cfs_subsys.su_group);
++
++	ret = configfs_register_subsystem(&of_cfs_subsys);
++	if (ret != 0) {
++		pr_err("%s: failed to register subsys\n", __func__);
++		goto out;
++	}
++	pr_info("%s: OK\n", __func__);
++out:
++	return ret;
++}
++late_initcall(of_cfs_init);

patch/kernel/rk322x-current/general-add-overlays.patch

@@ -0,0 +1,308 @@
+diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
+new file mode 100644
+index 000000000..f024e8db0
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/Makefile
+@@ -0,0 +1,20 @@
++# SPDX-License-Identifier: GPL-2.0
++dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
++	rk322x-emmc.dtbo	\
++	rk322x-nand.dtbo	\
++	rk322x-emmc-nand.dtbo	\
++	rk322x-led-conf1.dtbo	\
++	rk322x-led-conf2.dtbo	\
++	rk322x-cpu-hs.dtbo
++
++scr-$(CONFIG_ARCH_ROCKCHIP) += \
++       rk322x-fixup.scr
++
++dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \
++       README.rk322x-overlays
++
++targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
++
++always         := $(dtbo-y) $(scr-y) $(dtbotxt-y)
++clean-files    := *.dtbo *.scr
++
+diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays
+new file mode 100644
+index 000000000..d5bc7f3d5
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays
+@@ -0,0 +1,51 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++rk322x (Rockchip)
++
++### Provided overlays:
++
++- rk322x-cpu-hs
++- rk322x-emmc
++- rk322x-nand
++- rk322x-emmc-nand
++- rk322x-led1-low
++- rk322x-led1-high
++- rk322x-led2-low
++- rk322x-led2-high
++
++### Overlay details:
++
++### rk322x-cpu-hs
++
++Activates higher CPU speed (up to 1.4ghz) for rk3228b/rk3229 boxes
++
++### emmc
++
++Activates onboard emmc device node and deactivates the nand controller.
++Also sets up the pin controller default pull up/down configuration
++
++### nand
++
++Activates onboard nand device node and deactivates the emmc controller.
++Also sets up the pin controller default pull up/down configuration
++
++### emmc-nand
++
++Activates onboard nand and emmc devices. Usually they are alternative
++because manufacturers share the same pads so emmc and nand cannot be
++mixed together. Usually this works because the emmc and nand drivers
++can automatically guess what's in the pads, but may bring instabilities
++or misdetections. Also does not set up the pin controller default
++configuration, which in turn can be detrimental of stability and
++performance
++
++### rk322x-led-conf*
++
++Each device tree of this kind provides a different known wiring configuration
++(ie: gpio and active low/high) of the onboard leds. Each board manufacturer
++usually choose a different GPIO for the auxiliary led, but the main "working"
++led is always wired to the same gpio (although it may be active high or low)
+diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
+new file mode 100644
+index 000000000..1c2fc79e1
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++		__overlay__ {
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1325000 1325000 1400000>;
++			};
++			opp-1392000000 {
++				opp-hz = /bits/ 64 <1392000000>;
++				opp-microvolt = <1350000 1350000 1400000>;
++			};
++			/*
++			opp-1464000000 {
++				opp-hz = /bits/ 64 <1464000000>;
++				opp-microvolt = <1400000 1400000 1400000>;
++			};
++			*/
++
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
+new file mode 100644
+index 000000000..9b273bf75
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&emmc>;
++		__overlay__ {
++			status = "okay";
++			mmc-ddr-1_8v;
++			rockchip,default-sample-phase = <180>;
++		};
++	};
++
++	fragment@1 {
++		target = <&nfc>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
+new file mode 100644
+index 000000000..10b2f0f0d
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
+@@ -0,0 +1,24 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&emmc>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
++			mmc-ddr-1_8v;
++			rockchip,default-sample-phase = <180>;
++		};
++	};
++
++	fragment@1 {
++		target = <&nfc>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd b/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd
+new file mode 100644
+index 000000000..d4c39e20a
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd
+@@ -0,0 +1,4 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
+diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
+new file mode 100644
+index 000000000..faaee4070
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++/ {
++
++	fragment@0 {
++		target-path = "/gpio-leds";
++		__overlay__ {
++
++			working {
++				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++				linux,default-trigger = "none";
++			};
++
++			auxiliary {
++				gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++				label = "auxiliary";
++				linux,default-trigger = "mmc2";
++				default-state = "off";
++				pinctrl-names = "default";
++				pinctrl-0 = <&gpio_led_aux>;
++			};
++
++		};
++	};
++
++	fragment@1 {
++		target-path = "/pinctrl/gpio";
++		__overlay__ {
++
++			gpio_led_aux: gpio-led-aux {
++				rockchip,pins =  <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
++
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts
+new file mode 100644
+index 000000000..bbf2b0ee0
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++/ {
++
++	fragment@0 {
++		target-path = "/gpio-leds";
++		__overlay__ {
++
++			working {
++				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++				linux,default-trigger = "none";
++			};
++
++			auxiliary {
++				gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
++				label = "auxiliary";
++				linux,default-trigger = "mmc2";
++				default-state = "off";
++				pinctrl-names = "default";
++				pinctrl-0 = <&gpio_led_aux>;
++			};
++
++		};
++	};
++
++	fragment@1 {
++		target-path = "/pinctrl/gpio";
++		__overlay__ {
++
++			gpio_led_aux: gpio-led-aux {
++				rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
++
++		};
++	};
++
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-nand.dts b/arch/arm/boot/dts/overlay/rk322x-nand.dts
+new file mode 100644
+index 000000000..2a939ab49
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-nand.dts
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&nfc>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-0 = <&flash_cs0 &flash_cs1 &flash_cs2 &flash_cs3 &flash_rdy &flash_ale &flash_cle &flash_wrn &flash_bus8 &flash_dqs &flash_wp>;
++			pinctrl-names = "default";
++		};
++	};
++
++	fragment@1 {
++		target = <&emmc>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++};

patch/kernel/rk322x-current/linux.999.03-arm-vdso-add-vdso_clock_gettime64-phys-timer-syscall.patch

@@ -0,0 +1,12 @@
+diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
+index e0330a25e1..28cfe7bad1 100644
+--- a/arch/arm/kernel/vdso.c
++++ b/arch/arm/kernel/vdso.c
+@@ -184,6 +184,7 @@ static void __init patch_vdso(void *ehdr)
+ 	if (!cntvct_ok) {
+ 		vdso_nullpatch_one(&einfo, "__vdso_gettimeofday");
+ 		vdso_nullpatch_one(&einfo, "__vdso_clock_gettime");
++		vdso_nullpatch_one(&einfo, "__vdso_clock_gettime64");
+ 	}
+ }
+ 

patch/kernel/rk322x-legacy/01-linux-0000-Revert-rk-add-gcc-wrapper.patch

@@ -0,0 +1,27 @@
+From a968000cae7b5d0c3c10b4e5a94fd187c891ee08 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 27 Dec 2017 22:01:06 +0100
+Subject: [PATCH] Revert "rk: add gcc-wrapper"
+
+This reverts part of commit 7a51384d24fe4da183fc15b2d17aa3c153b822e7.
+---
+ Makefile | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index a785aeed4674..d34c20a89fb7 100644
+--- a/Makefile
++++ b/Makefile
+@@ -372,12 +372,6 @@ PERL		= perl
+ PYTHON		= python
+ CHECK		= sparse
+ 
+-# Use the wrapper for the compiler. This wrapper scans for new
+-# warnings and causes the build to stop upon encountering them.
+-ifneq ($(wildcard $(srctree)/scripts/gcc-wrapper.py),)
+-CC		= $(srctree)/scripts/gcc-wrapper.py $(CROSS_COMPILE)gcc
+-endif
+-
+ CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
+ 		  -Wbitwise -Wno-return-void $(CF)
+ CFLAGS_MODULE   =

patch/kernel/rk322x-legacy/01-linux-0002-ir.patch

@@ -0,0 +1,831 @@
+From 2031709371a600b1b803ec928cc1adb2e9b5a4c1 Mon Sep 17 00:00:00 2001
+From: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
+Date: Thu, 19 Nov 2015 11:41:36 -0200
+Subject: [PATCH] UPSTREAM: smsir.h: remove a now duplicated definition
+ (IR_DEFAULT_TIMEOUT)
+
+This macro is now part of the core. Remove from Siano driver.
+
+Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
+(cherry picked from commit 850c8a7d68a761b5f11d5b443b5ece185e8068f4)
+---
+ drivers/media/common/siano/smsir.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/media/common/siano/smsir.h b/drivers/media/common/siano/smsir.h
+index fc8b7925c532..d9abd96ef48b 100644
+--- a/drivers/media/common/siano/smsir.h
++++ b/drivers/media/common/siano/smsir.h
+@@ -30,8 +30,6 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ #include <linux/input.h>
+ #include <media/rc-core.h>
+ 
+-#define IR_DEFAULT_TIMEOUT		100
+-
+ struct smscore_device_t;
+ 
+ struct ir_t {
+
+From 3b533a5c5f7880759fcad51e9400851a80295764 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 6 Sep 2017 18:39:09 +0200
+Subject: [PATCH] [media] rc/keymaps: add keytable for Pine64 IR Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile    |  1 +
+ drivers/media/rc/keymaps/rc-pine64.c | 65 ++++++++++++++++++++++++++++++++++++
+ include/media/rc-map.h               |  1 +
+ 3 files changed, 67 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-pine64.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index fbbd3bbcd252..8816520600f7 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -66,6 +66,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-norwood.o \
+ 			rc-npgtech.o \
+ 			rc-pctv-sedna.o \
++			rc-pine64.o \
+ 			rc-pinnacle-color.o \
+ 			rc-pinnacle-grey.o \
+ 			rc-pinnacle-pctv-hd.o \
+diff --git a/drivers/media/rc/keymaps/rc-pine64.c b/drivers/media/rc/keymaps/rc-pine64.c
+new file mode 100644
+index 000000000000..bdf3975e7445
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-pine64.c
+@@ -0,0 +1,65 @@
++/* Keytable for Pine64 IR Remote Controller
++ *
++ * Copyright (c) 2017 PINE64
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table pine64[] = {
++	{ 0x404000, KEY_NUMERIC_0 },
++	{ 0x404001, KEY_NUMERIC_1 },
++	{ 0x404002, KEY_NUMERIC_2 },
++	{ 0x404003, KEY_NUMERIC_3 },
++	{ 0x404004, KEY_NUMERIC_4 },
++	{ 0x404005, KEY_NUMERIC_5 },
++	{ 0x404006, KEY_NUMERIC_6 },
++	{ 0x404007, KEY_NUMERIC_7 },
++	{ 0x404008, KEY_NUMERIC_8 },
++	{ 0x404009, KEY_NUMERIC_9 },
++	{ 0x40400a, KEY_MUTE },
++	{ 0x40400b, KEY_UP },
++	{ 0x40400c, KEY_BACKSPACE },
++	{ 0x40400d, KEY_OK },
++	{ 0x40400e, KEY_DOWN },
++	{ 0x404010, KEY_LEFT },
++	{ 0x404011, KEY_RIGHT },
++	{ 0x404017, KEY_VOLUMEDOWN },
++	{ 0x404018, KEY_VOLUMEUP },
++	{ 0x40401a, KEY_HOME },
++	{ 0x40401d, KEY_MENU },
++	{ 0x40401f, KEY_WWW },
++	{ 0x404045, KEY_BACK },
++	{ 0x404047, KEY_INFO },
++	{ 0x40404d, KEY_POWER },
++};
++
++static struct rc_map_list pine64_map = {
++	.map = {
++		.scan    = pine64,
++		.size    = ARRAY_SIZE(pine64),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_PINE64,
++	}
++};
++
++static int __init init_rc_map_pine64(void)
++{
++	return rc_map_register(&pine64_map);
++}
++
++static void __exit exit_rc_map_pine64(void)
++{
++	rc_map_unregister(&pine64_map);
++}
++
++module_init(init_rc_map_pine64)
++module_exit(exit_rc_map_pine64)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("PINE64");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 7c4bbc4dfab4..3a34a9631dd1 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -173,6 +173,7 @@ void rc_map_init(void);
+ #define RC_MAP_NORWOOD                   "rc-norwood"
+ #define RC_MAP_NPGTECH                   "rc-npgtech"
+ #define RC_MAP_PCTV_SEDNA                "rc-pctv-sedna"
++#define RC_MAP_PINE64                    "rc-pine64"
+ #define RC_MAP_PINNACLE_COLOR            "rc-pinnacle-color"
+ #define RC_MAP_PINNACLE_GREY             "rc-pinnacle-grey"
+ #define RC_MAP_PINNACLE_PCTV_HD          "rc-pinnacle-pctv-hd"
+
+From 21e2e6f847c6e1d0f98ce3770e6d380b20af3064 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 6 Sep 2017 18:39:09 +0200
+Subject: [PATCH] [media] rc/keymaps: add keytable for ODROID IR Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile    |  1 +
+ drivers/media/rc/keymaps/rc-odroid.c | 52 ++++++++++++++++++++++++++++++++++++
+ include/media/rc-map.h               |  1 +
+ 3 files changed, 54 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-odroid.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index 8816520600f7..f4321cfbbc79 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -65,6 +65,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-nec-terratec-cinergy-xs.o \
+ 			rc-norwood.o \
+ 			rc-npgtech.o \
++			rc-odroid.o \
+ 			rc-pctv-sedna.o \
+ 			rc-pine64.o \
+ 			rc-pinnacle-color.o \
+diff --git a/drivers/media/rc/keymaps/rc-odroid.c b/drivers/media/rc/keymaps/rc-odroid.c
+new file mode 100644
+index 000000000000..52089f0b7c1d
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-odroid.c
+@@ -0,0 +1,52 @@
++/* Keytable for ODROID IR Remote Controller
++ *
++ * Copyright (c) 2017 Hardkernel co., Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table odroid[] = {
++	{ 0xb2dc, KEY_POWER },
++	{ 0xb288, KEY_MUTE },
++	{ 0xb282, KEY_HOME },
++	{ 0xb2ce, KEY_OK },
++	{ 0xb2ca, KEY_UP },
++	{ 0xb299, KEY_LEFT },
++	{ 0xb2c1, KEY_RIGHT },
++	{ 0xb2d2, KEY_DOWN },
++	{ 0xb2c5, KEY_MENU },
++	{ 0xb29a, KEY_BACK },
++	{ 0xb281, KEY_VOLUMEDOWN },
++	{ 0xb280, KEY_VOLUMEUP },
++};
++
++static struct rc_map_list odroid_map = {
++	.map = {
++		.scan    = odroid,
++		.size    = ARRAY_SIZE(odroid),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_ODROID,
++	}
++};
++
++static int __init init_rc_map_odroid(void)
++{
++	return rc_map_register(&odroid_map);
++}
++
++static void __exit exit_rc_map_odroid(void)
++{
++	rc_map_unregister(&odroid_map);
++}
++
++module_init(init_rc_map_odroid)
++module_exit(exit_rc_map_odroid)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Hardkernel co., Ltd.");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 3a34a9631dd1..f1badbfbca90 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -172,6 +172,7 @@ void rc_map_init(void);
+ #define RC_MAP_NEC_TERRATEC_CINERGY_XS   "rc-nec-terratec-cinergy-xs"
+ #define RC_MAP_NORWOOD                   "rc-norwood"
+ #define RC_MAP_NPGTECH                   "rc-npgtech"
++#define RC_MAP_ODROID                    "rc-odroid"
+ #define RC_MAP_PCTV_SEDNA                "rc-pctv-sedna"
+ #define RC_MAP_PINE64                    "rc-pine64"
+ #define RC_MAP_PINNACLE_COLOR            "rc-pinnacle-color"
+
+From 0cb159b68f91fb352861a23241a24611201e0d05 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 6 Sep 2017 18:39:09 +0200
+Subject: [PATCH] [media] rc/keymaps: add keytable for WeTek Hub Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile       |  1 +
+ drivers/media/rc/keymaps/rc-wetek-hub.c | 52 +++++++++++++++++++++++++++++++++
+ include/media/rc-map.h                  |  1 +
+ 3 files changed, 54 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-wetek-hub.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index f4321cfbbc79..e8e6434cbc13 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -101,6 +101,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-tt-1500.o \
+ 			rc-twinhan-dtv-cab-ci.o \
+ 			rc-twinhan1027.o \
++			rc-wetek-hub.o \
+ 			rc-videomate-m1f.o \
+ 			rc-videomate-s350.o \
+ 			rc-videomate-tv-pvr.o \
+diff --git a/drivers/media/rc/keymaps/rc-wetek-hub.c b/drivers/media/rc/keymaps/rc-wetek-hub.c
+new file mode 100644
+index 000000000000..0955ecfcb77c
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-wetek-hub.c
+@@ -0,0 +1,52 @@
++/* Keytable for WeTek Hub Remote Controller
++ *
++ * Copyright (c) 2017 WeTek
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table wetek_hub[] = {
++	{ 0x77f1, KEY_POWER },
++	{ 0x77f2, KEY_HOME },
++	{ 0x77f3, KEY_MUTE },
++	{ 0x77f4, KEY_UP },
++	{ 0x77f5, KEY_DOWN },
++	{ 0x77f6, KEY_LEFT },
++	{ 0x77f7, KEY_RIGHT },
++	{ 0x77f8, KEY_OK },
++	{ 0x77f9, KEY_BACK },
++	{ 0x77fa, KEY_MENU },
++	{ 0x77fb, KEY_VOLUMEUP },
++	{ 0x77fc, KEY_VOLUMEDOWN },
++};
++
++static struct rc_map_list wetek_hub_map = {
++	.map = {
++		.scan    = wetek_hub,
++		.size    = ARRAY_SIZE(wetek_hub),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_WETEK_HUB,
++	}
++};
++
++static int __init init_rc_map_wetek_hub(void)
++{
++	return rc_map_register(&wetek_hub_map);
++}
++
++static void __exit exit_rc_map_wetek_hub(void)
++{
++	rc_map_unregister(&wetek_hub_map);
++}
++
++module_init(init_rc_map_wetek_hub)
++module_exit(exit_rc_map_wetek_hub)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("WeTek");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index f1badbfbca90..cd8590c99e22 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -209,6 +209,7 @@ void rc_map_init(void);
+ #define RC_MAP_TT_1500                   "rc-tt-1500"
+ #define RC_MAP_TWINHAN_DTV_CAB_CI        "rc-twinhan-dtv-cab-ci"
+ #define RC_MAP_TWINHAN_VP1027_DVBS       "rc-twinhan1027"
++#define RC_MAP_WETEK_HUB                 "rc-wetek-hub"
+ #define RC_MAP_VIDEOMATE_K100            "rc-videomate-k100"
+ #define RC_MAP_VIDEOMATE_S350            "rc-videomate-s350"
+ #define RC_MAP_VIDEOMATE_TV_PVR          "rc-videomate-tv-pvr"
+
+From d81bc903c323311f09eb3f8a298c10d99c62f601 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 6 Sep 2017 18:39:09 +0200
+Subject: [PATCH] [media] rc/keymaps: add keytable for WeTek Play 2 Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile          |  1 +
+ drivers/media/rc/keymaps/rc-wetek-play-2.c | 83 ++++++++++++++++++++++++++++++
+ include/media/rc-map.h                     |  1 +
+ 3 files changed, 85 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-wetek-play-2.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index e8e6434cbc13..650481039f00 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -102,6 +102,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-twinhan-dtv-cab-ci.o \
+ 			rc-twinhan1027.o \
+ 			rc-wetek-hub.o \
++			rc-wetek-play-2.o \
+ 			rc-videomate-m1f.o \
+ 			rc-videomate-s350.o \
+ 			rc-videomate-tv-pvr.o \
+diff --git a/drivers/media/rc/keymaps/rc-wetek-play-2.c b/drivers/media/rc/keymaps/rc-wetek-play-2.c
+new file mode 100644
+index 000000000000..37586cedbb8a
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-wetek-play-2.c
+@@ -0,0 +1,83 @@
++/* Keytable for WeTek Play 2 Remote Controller
++ *
++ * Copyright (c) 2017 WeTek
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table wetek_play_2[] = {
++	{ 0x5e5f02, KEY_POWER },
++	{ 0x5e5f46, KEY_POWER2 },
++	{ 0x5e5f10, KEY_MUTE },
++	{ 0x5e5f22, KEY_NUMERIC_1 },
++	{ 0x5e5f23, KEY_NUMERIC_2 },
++	{ 0x5e5f24, KEY_NUMERIC_3 },
++	{ 0x5e5f25, KEY_NUMERIC_4 },
++	{ 0x5e5f26, KEY_NUMERIC_5 },
++	{ 0x5e5f27, KEY_NUMERIC_6 },
++	{ 0x5e5f28, KEY_NUMERIC_7 },
++	{ 0x5e5f29, KEY_NUMERIC_8 },
++	{ 0x5e5f30, KEY_NUMERIC_9 },
++	{ 0x5e5f71, KEY_BACKSPACE },
++	{ 0x5e5f21, KEY_NUMERIC_0 },
++	{ 0x5e5f72, KEY_CAPSLOCK },
++	{ 0x5e5f03, KEY_HOME },
++	{ 0x5e5f48, KEY_MENU },
++	{ 0x5e5f61, KEY_BACK },
++	{ 0x5e5f83, KEY_INFO },
++	{ 0x5e5f84, KEY_COMPOSE },
++	{ 0x5e5f77, KEY_HELP },
++	{ 0x5e5f50, KEY_UP },
++	{ 0x5e5f4b, KEY_DOWN },
++	{ 0x5e5f4c, KEY_LEFT },
++	{ 0x5e5f4d, KEY_RIGHT },
++	{ 0x5e5f47, KEY_OK },
++	{ 0x5e5f44, KEY_VOLUMEUP },
++	{ 0x5e5f43, KEY_VOLUMEDOWN },
++	{ 0x5e5f41, KEY_CHANNELUP },
++	{ 0x5e5f42, KEY_CHANNELDOWN },
++	{ 0x5e5f4f, KEY_ZENKAKUHANKAKU },
++	{ 0x5e5f82, KEY_TEXT },
++	{ 0x5e5f73, KEY_RED },
++	{ 0x5e5f74, KEY_GREEN },
++	{ 0x5e5f75, KEY_YELLOW },
++	{ 0x5e5f76, KEY_BLUE },
++	{ 0x5e5f67, KEY_PREVIOUS },
++	{ 0x5e5f79, KEY_REWIND },
++	{ 0x5e5f80, KEY_FASTFORWARD },
++	{ 0x5e5f81, KEY_NEXT },
++	{ 0x5e5f04, KEY_RECORD },
++	{ 0x5e5f2c, KEY_PLAYPAUSE },
++	{ 0x5e5f2b, KEY_STOP },
++};
++
++static struct rc_map_list wetek_play_2_map = {
++	.map = {
++		.scan    = wetek_play_2,
++		.size    = ARRAY_SIZE(wetek_play_2),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_WETEK_PLAY_2,
++	}
++};
++
++static int __init init_rc_map_wetek_play_2(void)
++{
++	return rc_map_register(&wetek_play_2_map);
++}
++
++static void __exit exit_rc_map_wetek_play_2(void)
++{
++	rc_map_unregister(&wetek_play_2_map);
++}
++
++module_init(init_rc_map_wetek_play_2)
++module_exit(exit_rc_map_wetek_play_2)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("WeTek");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index cd8590c99e22..93cac05a5170 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -210,6 +210,7 @@ void rc_map_init(void);
+ #define RC_MAP_TWINHAN_DTV_CAB_CI        "rc-twinhan-dtv-cab-ci"
+ #define RC_MAP_TWINHAN_VP1027_DVBS       "rc-twinhan1027"
+ #define RC_MAP_WETEK_HUB                 "rc-wetek-hub"
++#define RC_MAP_WETEK_PLAY_2              "rc-wetek-play-2"
+ #define RC_MAP_VIDEOMATE_K100            "rc-videomate-k100"
+ #define RC_MAP_VIDEOMATE_S350            "rc-videomate-s350"
+ #define RC_MAP_VIDEOMATE_TV_PVR          "rc-videomate-tv-pvr"
+
+From 6518b8acbe53a153740bad1e93c9d361fed136fd Mon Sep 17 00:00:00 2001
+From: hzq <hzq@t-firefly.com>
+Date: Mon, 19 Mar 2018 16:47:24 +0800
+Subject: [PATCH] [media] rc/keymaps: add keytable for ROC-RK3328-CC Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile    |  1 +
+ drivers/media/rc/keymaps/rc-roc-cc.c | 52 ++++++++++++++++++++++++++++++++++++
+ include/media/rc-map.h               |  1 +
+ 3 files changed, 54 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-roc-cc.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index 650481039f00..b743914487a5 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -83,6 +83,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-rc6-mce.o \
+ 			rc-real-audio-220-32-keys.o \
+ 			rc-reddo.o \
++			rc-roc-cc.o \
+ 			rc-snapstream-firefly.o \
+ 			rc-streamzap.o \
+ 			rc-tbs-nec.o \
+diff --git a/drivers/media/rc/keymaps/rc-roc-cc.c b/drivers/media/rc/keymaps/rc-roc-cc.c
+new file mode 100644
+index 000000000000..3a2a255d5723
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-roc-cc.c
+@@ -0,0 +1,52 @@
++/* Keytable for ROC-RK3328-CC IR Remote Controller
++ *
++ * Copyright (c) 2017 ROC-RK3328-CC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table roc_cc[] = {
++	{ 0x28d7, KEY_POWER },
++	{ 0xc837, KEY_MUTE },
++	{ 0xe01f, KEY_ENTER},
++	{ 0xc03f, KEY_UP },
++	{ 0x40bf, KEY_DOWN },
++	{ 0x708f, KEY_LEFT },
++	{ 0x58a7, KEY_RIGHT },
++	{ 0x1ae5, KEY_VOLUMEDOWN },
++	{ 0xd02f, KEY_VOLUMEUP },
++	{ 0x3ac5, KEY_WWW },
++	{ 0x807f, KEY_BACK },
++	{ 0x12ed, KEY_HOME },
++};
++
++static struct rc_map_list roc_cc_map = {
++	.map = {
++		.scan    = roc_cc,
++		.size    = ARRAY_SIZE(roc_cc),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_ROC_CC,
++	}
++};
++
++static int __init init_rc_map_roc_cc(void)
++{
++	return rc_map_register(&roc_cc_map);
++}
++
++static void __exit exit_rc_map_roc_cc(void)
++{
++	rc_map_unregister(&roc_cc_map);
++}
++
++module_init(init_rc_map_roc_cc)
++module_exit(exit_rc_map_roc_cc)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("ROC-RK3328-CC");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 93cac05a5170..8bbe335e650c 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -191,6 +191,7 @@ void rc_map_init(void);
+ #define RC_MAP_RC6_MCE                   "rc-rc6-mce"
+ #define RC_MAP_REAL_AUDIO_220_32_KEYS    "rc-real-audio-220-32-keys"
+ #define RC_MAP_REDDO                     "rc-reddo"
++#define RC_MAP_ROC_CC                    "rc-roc-cc"
+ #define RC_MAP_SNAPSTREAM_FIREFLY        "rc-snapstream-firefly"
+ #define RC_MAP_STREAMZAP                 "rc-streamzap"
+ #define RC_MAP_TBS_NEC                   "rc-tbs-nec"
+
+From c0220800efec28f6a59eae563f4f083ceedff6cc Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 3 Jul 2018 21:55:56 +0200
+Subject: [PATCH] [media] rc/keymaps: add keytable for T-Chip TRN9 IR Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile  |  1 +
+ drivers/media/rc/keymaps/rc-trn9.c | 52 ++++++++++++++++++++++++++++++++++++++
+ include/media/rc-map.h             |  1 +
+ 3 files changed, 54 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-trn9.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index b743914487a5..2aaa1b33ddca 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -102,6 +102,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-tt-1500.o \
+ 			rc-twinhan-dtv-cab-ci.o \
+ 			rc-twinhan1027.o \
++			rc-trn9.o \
+ 			rc-wetek-hub.o \
+ 			rc-wetek-play-2.o \
+ 			rc-videomate-m1f.o \
+diff --git a/drivers/media/rc/keymaps/rc-trn9.c b/drivers/media/rc/keymaps/rc-trn9.c
+new file mode 100644
+index 000000000000..f81bc3a419b3
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-trn9.c
+@@ -0,0 +1,52 @@
++/* Keytable for T-Chip TRN9 IR Remote Controller
++ *
++ * Copyright (c) 2018 Omegamoon
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table trn9[] = {
++	{ 0x0014, KEY_POWER },
++	{ 0x0013, KEY_MENU },
++	{ 0x0003, KEY_UP },
++	{ 0x0002, KEY_DOWN },
++	{ 0x000e, KEY_LEFT },
++	{ 0x001a, KEY_RIGHT },
++	{ 0x0007, KEY_OK },
++	{ 0x0058, KEY_VOLUMEDOWN },
++	{ 0x005c, KEY_MUTE },
++	{ 0x000b, KEY_VOLUMEUP },
++	{ 0x0001, KEY_BACK },
++	{ 0x0048, KEY_HOME },
++};
++
++static struct rc_map_list trn9_map = {
++	.map = {
++		.scan    = trn9,
++		.size    = ARRAY_SIZE(trn9),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_TRN9,
++	}
++};
++
++static int __init init_rc_map_trn9(void)
++{
++	return rc_map_register(&trn9_map);
++}
++
++static void __exit exit_rc_map_trn9(void)
++{
++	rc_map_unregister(&trn9_map);
++}
++
++module_init(init_rc_map_trn9)
++module_exit(exit_rc_map_trn9)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Omegamoon");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 8bbe335e650c..66e1c50b38fc 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -210,6 +210,7 @@ void rc_map_init(void);
+ #define RC_MAP_TT_1500                   "rc-tt-1500"
+ #define RC_MAP_TWINHAN_DTV_CAB_CI        "rc-twinhan-dtv-cab-ci"
+ #define RC_MAP_TWINHAN_VP1027_DVBS       "rc-twinhan1027"
++#define RC_MAP_TRN9                 	  "rc-trn9"
+ #define RC_MAP_WETEK_HUB                 "rc-wetek-hub"
+ #define RC_MAP_WETEK_PLAY_2              "rc-wetek-play-2"
+ #define RC_MAP_VIDEOMATE_K100            "rc-videomate-k100"
+
+From 312b78202feca8f3966343b0362466e9c6ff2297 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Mon, 17 Dec 2018 07:41:16 +0100
+Subject: [PATCH] [media] rc/keymaps: add keytable for Khadas IR Remote
+ Controller
+
+---
+ drivers/media/rc/keymaps/Makefile    |  1 +
+ drivers/media/rc/keymaps/rc-khadas.c | 52 ++++++++++++++++++++++++++++++++++++
+ include/media/rc-map.h               |  1 +
+ 3 files changed, 54 insertions(+)
+ create mode 100644 drivers/media/rc/keymaps/rc-khadas.c
+
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index 2aaa1b33ddca..fc0207d322a0 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-it913x-v1.o \
+ 			rc-it913x-v2.o \
+ 			rc-kaiomy.o \
++			rc-khadas.o \
+ 			rc-kworld-315u.o \
+ 			rc-kworld-pc150u.o \
+ 			rc-kworld-plus-tv-analog.o \
+diff --git a/drivers/media/rc/keymaps/rc-khadas.c b/drivers/media/rc/keymaps/rc-khadas.c
+new file mode 100644
+index 000000000000..492368db75d9
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-khadas.c
+@@ -0,0 +1,52 @@
++/* Keytable for Khadas IR Remote Controller
++ *
++ * Copyright (c) 2018 Shenzhen Wesion Technology Co., Ltd
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table khadas[] = {
++	{ 0x14, KEY_POWER },
++	{ 0x07, KEY_OK },
++	{ 0x03, KEY_UP },
++	{ 0x02, KEY_DOWN },
++	{ 0x0e, KEY_LEFT },
++	{ 0x1a, KEY_RIGHT },
++	{ 0x13, KEY_MENU },
++	{ 0x01, KEY_BACK },
++	{ 0x0b, KEY_VOLUMEUP },
++	{ 0x58, KEY_VOLUMEDOWN },
++	{ 0x48, KEY_HOME },
++	{ 0x5b, KEY_CONTEXT_MENU },
++};
++
++static struct rc_map_list khadas_map = {
++	.map = {
++		.scan    = khadas,
++		.size    = ARRAY_SIZE(khadas),
++		.rc_type = RC_TYPE_NEC,
++		.name    = RC_MAP_KHADAS,
++	}
++};
++
++static int __init init_rc_map_khadas(void)
++{
++	return rc_map_register(&khadas_map);
++}
++
++static void __exit exit_rc_map_khadas(void)
++{
++	rc_map_unregister(&khadas_map);
++}
++
++module_init(init_rc_map_khadas)
++module_exit(exit_rc_map_khadas)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Khadas");
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index 66e1c50b38fc..6b2db526fac0 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -154,6 +154,7 @@ void rc_map_init(void);
+ #define RC_MAP_IT913X_V1                 "rc-it913x-v1"
+ #define RC_MAP_IT913X_V2                 "rc-it913x-v2"
+ #define RC_MAP_KAIOMY                    "rc-kaiomy"
++#define RC_MAP_KHADAS                    "rc-khadas"
+ #define RC_MAP_KWORLD_315U               "rc-kworld-315u"
+ #define RC_MAP_KWORLD_PC150U             "rc-kworld-pc150u"
+ #define RC_MAP_KWORLD_PLUS_TV_ANALOG     "rc-kworld-plus-tv-analog"
+--- a/drivers/media/rc/keymaps/rc-rktvbox.c
++++ b/drivers/media/rc/keymaps/rc-rktvbox.c
+@@ -0,0 +1,65 @@
++/* Keytable for Rockchip TV Box IR Remote Controller
++ *
++ * Copyright (c) 2018 knaerzche
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++static struct rc_map_table rktvbox[] = {
++	{ 0xcc1d49, KEY_NUMERIC_0 },
++	{ 0xcc1d41, KEY_NUMERIC_1 },
++	{ 0xcc1d45, KEY_NUMERIC_2 },
++	{ 0xcc1d4d, KEY_NUMERIC_3 },
++	{ 0xcc1d42, KEY_NUMERIC_4 },
++	{ 0xcc1d46, KEY_NUMERIC_5 },
++	{ 0xcc1d4e, KEY_NUMERIC_6 },
++	{ 0xcc1d43, KEY_NUMERIC_7 },
++	{ 0xcc1d47, KEY_NUMERIC_8 },
++	{ 0xcc1d4f, KEY_NUMERIC_9 },
++	{ 0xcc1d0c, KEY_MUTE },
++	{ 0xcc1d07, KEY_UP },
++	{ 0xcc1d4a, KEY_BACKSPACE },
++	{ 0xcc1d11, KEY_OK },
++	{ 0xcc1d44, KEY_DOWN },
++	{ 0xcc1d10, KEY_LEFT },
++	{ 0xcc1d12, KEY_RIGHT },
++	{ 0xcc1d02, KEY_VOLUMEDOWN },
++	{ 0xcc1d0e, KEY_VOLUMEUP },
++	{ 0xcc1d03, KEY_HOME },
++	{ 0xcc1d40, KEY_MENU },
++	{ 0xcc1d09, KEY_WWW },
++	{ 0xcc1d0f, KEY_BACK },
++	{ 0xcc1d4c, KEY_INFO },
++	{ 0xcc1d00, KEY_POWER },
++};
++
++static struct rc_map_list rktvbox_map = {
++	.map = {
++		.scan     = rktvbox,
++		.size     = ARRAY_SIZE(rktvbox),
++               .rc_proto = RC_PROTO_NEC,
++		.name     = RC_MAP_RKTVBOX,
++	}
++};
++
++static int __init init_rc_map_rktvbox(void)
++{
++	return rc_map_register(&rktvbox_map);
++}
++
++static void __exit exit_rc_map_rktvbox(void)
++{
++	rc_map_unregister(&rktvbox_map);
++}
++
++module_init(init_rc_map_rktvbox)
++module_exit(exit_rc_map_rktvbox)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("knaerzche");
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -69,6 +69,7 @@
+ 			rc-odroid.o \
+ 			rc-pctv-sedna.o \
+ 			rc-pine64.o \
++			rc-rktvbox.o \
+ 			rc-pinnacle-color.o \
+ 			rc-pinnacle-grey.o \
+ 			rc-pinnacle-pctv-hd.o \
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -178,6 +178,7 @@
+ #define RC_MAP_ODROID                    "rc-odroid"
+ #define RC_MAP_PCTV_SEDNA                "rc-pctv-sedna"
+ #define RC_MAP_PINE64                    "rc-pine64"
++#define RC_MAP_RKTVBOX                   "rc-rktvbox"
+ #define RC_MAP_PINNACLE_COLOR            "rc-pinnacle-color"
+ #define RC_MAP_PINNACLE_GREY             "rc-pinnacle-grey"
+ #define RC_MAP_PINNACLE_PCTV_HD          "rc-pinnacle-pctv-hd"

patch/kernel/rk322x-legacy/01-linux-0006-rtl8211f.patch

@@ -0,0 +1,870 @@
+From eec386c5e9f5067dc7fdd3c86adae7de835e090a Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 25 Nov 2016 14:12:01 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: fix enabling of the TX-delay for
+ RTL8211F
+
+The old logic always enabled the TX-delay when the phy-mode was set to
+PHY_INTERFACE_MODE_RGMII. There are dedicated phy-modes which tell the
+PHY driver to enable the RX and/or TX delays:
+- PHY_INTERFACE_MODE_RGMII should disable the RX and TX delay in the
+  PHY (if required, the MAC should add the delays in this case)
+- PHY_INTERFACE_MODE_RGMII_ID should enable RX and TX delay in the PHY
+- PHY_INTERFACE_MODE_RGMII_TXID should enable the TX delay in the PHY
+- PHY_INTERFACE_MODE_RGMII_RXID should enable the RX delay in the PHY
+  (currently not supported by RTL8211F)
+
+With this patch we enable the TX delay for PHY_INTERFACE_MODE_RGMII_ID
+and PHY_INTERFACE_MODE_RGMII_TXID.
+Additionally we now explicity disable the TX-delay, which seems to be
+enabled automatically after a hard-reset of the PHY (by triggering it's
+reset pin) to get a consistent state (as defined by the phy-mode).
+
+This fixes a compatibility problem with some SoCs where the TX-delay was
+also added by the MAC. With the TX-delay being applied twice the TX
+clock was off and TX traffic was broken or very slow (<10Mbit/s) on
+1000Mbit/s links.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit e3230494b57ece68750e3e32d3e53d6b00917058)
+---
+ drivers/net/phy/realtek.c | 20 ++++++++++++--------
+ 1 file changed, 12 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 43ab691362d4..686f3b259dc0 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -102,15 +102,19 @@ static int rtl8211f_config_init(struct phy_device *phydev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
+-		/* enable TXDLY */
+-		phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
+-		reg = phy_read(phydev, 0x11);
++	phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
++	reg = phy_read(phydev, 0x11);
++
++	/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
++	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ 		reg |= RTL8211F_TX_DELAY;
+-		phy_write(phydev, 0x11, reg);
+-		/* restore to default page 0 */
+-		phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
+-	}
++	else
++		reg &= ~RTL8211F_TX_DELAY;
++
++	phy_write(phydev, 0x11, reg);
++	/* restore to default page 0 */
++	phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
+ 
+ 	return 0;
+ }
+
+From e0a1654d1e79bea21f6397b6caa038c2dee25f97 Mon Sep 17 00:00:00 2001
+From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Date: Tue, 12 Sep 2017 18:54:35 +0900
+Subject: [PATCH] UPSTREAM: net: phy: realtek: rename RTL8211F_PAGE_SELECT to
+ RTL821x_PAGE_SELECT
+
+This renames the definition of page select register from
+RTL8211F_PAGE_SELECT to RTL821x_PAGE_SELECT to use it across models.
+
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 013955a6556766a76f9f2cc31e740fc6db6ecff4)
+---
+ drivers/net/phy/realtek.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 686f3b259dc0..d58cc8f518ac 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -22,11 +22,11 @@
+ #define RTL821x_INER		0x12
+ #define RTL821x_INER_INIT	0x6400
+ #define RTL821x_INSR		0x13
++#define RTL821x_PAGE_SELECT	0x1f
+ #define RTL8211E_INER_LINK_STATUS 0x400
+ 
+ #define RTL8211F_INER_LINK_STATUS 0x0010
+ #define RTL8211F_INSR		0x1d
+-#define RTL8211F_PAGE_SELECT	0x1f
+ #define RTL8211F_TX_DELAY	0x100
+ 
+ MODULE_DESCRIPTION("Realtek PHY driver");
+@@ -46,10 +46,10 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)
+ {
+ 	int err;
+ 
+-	phy_write(phydev, RTL8211F_PAGE_SELECT, 0xa43);
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa43);
+ 	err = phy_read(phydev, RTL8211F_INSR);
+ 	/* restore to default page 0 */
+-	phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
+ 
+ 	return (err < 0) ? err : 0;
+ }
+@@ -102,7 +102,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0xd08);
+ 	reg = phy_read(phydev, 0x11);
+ 
+ 	/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
+@@ -114,7 +114,7 @@ static int rtl8211f_config_init(struct phy_device *phydev)
+ 
+ 	phy_write(phydev, 0x11, reg);
+ 	/* restore to default page 0 */
+-	phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
+ 
+ 	return 0;
+ }
+
+From 4ec70bc0ea714cc0129a4631dbda493ba706f40f Mon Sep 17 00:00:00 2001
+From: Jassi Brar <jaswinder.singh@linaro.org>
+Date: Tue, 12 Sep 2017 18:54:36 +0900
+Subject: [PATCH] UPSTREAM: net: phy: realtek: add RTL8201F phy-id and
+ functions
+
+Add RTL8201F phy-id and the related functions to the driver.
+
+The original patch is as follows:
+https://patchwork.kernel.org/patch/2538341/
+
+Signed-off-by: Jongsung Kim <neidhard.kim@lge.com>
+Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
+Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 513588dd44b09bb5fdd5066a4fbc1e7443b86d1c)
+---
+ drivers/net/phy/realtek.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index d58cc8f518ac..422cf1f6a60c 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -29,10 +29,22 @@
+ #define RTL8211F_INSR		0x1d
+ #define RTL8211F_TX_DELAY	0x100
+ 
++#define RTL8201F_ISR		0x1e
++#define RTL8201F_IER		0x13
++
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+ MODULE_LICENSE("GPL");
+ 
++static int rtl8201_ack_interrupt(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_read(phydev, RTL8201F_ISR);
++
++	return (err < 0) ? err : 0;
++}
++
+ static int rtl821x_ack_interrupt(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -54,6 +66,25 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)
+ 	return (err < 0) ? err : 0;
+ }
+ 
++static int rtl8201_config_intr(struct phy_device *phydev)
++{
++	int err;
++
++	/* switch to page 7 */
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0x7);
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
++		err = phy_write(phydev, RTL8201F_IER,
++				BIT(13) | BIT(12) | BIT(11));
++	else
++		err = phy_write(phydev, RTL8201F_IER, 0);
++
++	/* restore to default page 0 */
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
++
++	return err;
++}
++
+ static int rtl8211b_config_intr(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -129,6 +160,18 @@ static struct phy_driver realtek_drvs[] = {
+ 		.config_aneg    = &genphy_config_aneg,
+ 		.read_status    = &genphy_read_status,
+ 		.driver         = { .owner = THIS_MODULE,},
++	}, {
++		.phy_id		= 0x001cc816,
++		.name		= "RTL8201F 10/100Mbps Ethernet",
++		.phy_id_mask	= 0x001fffff,
++		.features	= PHY_BASIC_FEATURES,
++		.flags		= PHY_HAS_INTERRUPT,
++		.config_aneg	= &genphy_config_aneg,
++		.read_status	= &genphy_read_status,
++		.ack_interrupt	= &rtl8201_ack_interrupt,
++		.config_intr	= &rtl8201_config_intr,
++		.suspend	= genphy_suspend,
++		.resume		= genphy_resume,
+ 	}, {
+ 		.phy_id		= 0x001cc912,
+ 		.name		= "RTL8211B Gigabit Ethernet",
+@@ -186,6 +229,7 @@ static struct phy_driver realtek_drvs[] = {
+ module_phy_driver(realtek_drvs);
+ 
+ static struct mdio_device_id __maybe_unused realtek_tbl[] = {
++	{ 0x001cc816, 0x001fffff },
+ 	{ 0x001cc912, 0x001fffff },
+ 	{ 0x001cc914, 0x001fffff },
+ 	{ 0x001cc915, 0x001fffff },
+
+From cd0c207d7747ac36c446099ff018682373999764 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Sun, 12 Nov 2017 16:16:04 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: fix RTL8211F interrupt mode
+
+After commit b94d22d94ad22 "ARM64: dts: meson-gx: add external PHY
+interrupt on some platforms" ethernet stopped working on my Odroid-C2
+which has a RTL8211F phy.
+
+It turned out that no interrupts were triggered. Further analysis
+showed the register INER can't be altered on page 0.
+Because register INSR needs to be accessed via page 0xa43 I assumed
+that register INER needs to be accessed via some page too.
+Some brute force check resulted in page 0xa42 being the right one.
+
+With this patch the phy is working properly in interrupt mode.
+
+Fixes: 3447cf2e9a11 ("net/phy: Add support for Realtek RTL8211F")
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Tested-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 3697d058b08d5b874f0253de173ef72e5d648f9a)
+---
+ drivers/net/phy/realtek.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 422cf1f6a60c..a30d0c08c63b 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -115,11 +115,13 @@ static int rtl8211f_config_intr(struct phy_device *phydev)
+ {
+ 	int err;
+ 
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa42);
+ 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ 		err = phy_write(phydev, RTL821x_INER,
+ 				RTL8211F_INER_LINK_STATUS);
+ 	else
+ 		err = phy_write(phydev, RTL821x_INER, 0);
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
+ 
+ 	return err;
+ }
+
+From df04368281177832f4dff078f0cc735ce651ded1 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 22:51:24 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: use the BIT and GENMASK macros
+
+This makes it easier to compare the #defines with the datasheets.
+No functional changes.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 8cc5baefbc0266b6d6c8e99cb8568f59be36a575)
+---
+ drivers/net/phy/realtek.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index a30d0c08c63b..f8dc29a75828 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -13,21 +13,22 @@
+  * option) any later version.
+  *
+  */
++#include <linux/bitops.h>
+ #include <linux/phy.h>
+ #include <linux/module.h>
+ 
+ #define RTL821x_PHYSR		0x11
+-#define RTL821x_PHYSR_DUPLEX	0x2000
+-#define RTL821x_PHYSR_SPEED	0xc000
++#define RTL821x_PHYSR_DUPLEX	BIT(13)
++#define RTL821x_PHYSR_SPEED	GENMASK(15, 14)
+ #define RTL821x_INER		0x12
+ #define RTL821x_INER_INIT	0x6400
+ #define RTL821x_INSR		0x13
+ #define RTL821x_PAGE_SELECT	0x1f
+-#define RTL8211E_INER_LINK_STATUS 0x400
++#define RTL8211E_INER_LINK_STATUS	BIT(10)
+ 
+-#define RTL8211F_INER_LINK_STATUS 0x0010
++#define RTL8211F_INER_LINK_STATUS	BIT(4)
+ #define RTL8211F_INSR		0x1d
+-#define RTL8211F_TX_DELAY	0x100
++#define RTL8211F_TX_DELAY	BIT(8)
+ 
+ #define RTL8201F_ISR		0x1e
+ #define RTL8201F_IER		0x13
+
+From c6479ba05b0013658491a86171df7e0110a0e85a Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 22:51:25 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: rename RTL821x_INER_INIT to
+ RTL8211B_INER_INIT
+
+This macro is only used by the RTL8211B code. RTL8211E and RTL8211F both
+use other bits to initialize the RTL821x_INER register.
+No functional changes.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 69021e32ec3ef02170482f6ed8130febaed27357)
+---
+ drivers/net/phy/realtek.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index f8dc29a75828..89308eac4088 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -21,7 +21,7 @@
+ #define RTL821x_PHYSR_DUPLEX	BIT(13)
+ #define RTL821x_PHYSR_SPEED	GENMASK(15, 14)
+ #define RTL821x_INER		0x12
+-#define RTL821x_INER_INIT	0x6400
++#define RTL8211B_INER_INIT	0x6400
+ #define RTL821x_INSR		0x13
+ #define RTL821x_PAGE_SELECT	0x1f
+ #define RTL8211E_INER_LINK_STATUS	BIT(10)
+@@ -92,7 +92,7 @@ static int rtl8211b_config_intr(struct phy_device *phydev)
+ 
+ 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+ 		err = phy_write(phydev, RTL821x_INER,
+-				RTL821x_INER_INIT);
++				RTL8211B_INER_INIT);
+ 	else
+ 		err = phy_write(phydev, RTL821x_INER, 0);
+ 
+
+From c49b1806174ac4140a3fe90c626ef694992f7db6 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 22:51:26 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: group all register bit #defines
+ for RTL821x_INER
+
+This simply moves all register bit #defines which describe the (PHY
+specific) bits in the RTL821x_INER right below the RTL821x_INER register
+definition. This makes it easier to spot which registers and bits belong
+together.
+No functional changes.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit a82f266d240d87e6111878bbfe287024fb6857c1)
+---
+ drivers/net/phy/realtek.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 89308eac4088..df97d903d2bf 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -20,13 +20,16 @@
+ #define RTL821x_PHYSR		0x11
+ #define RTL821x_PHYSR_DUPLEX	BIT(13)
+ #define RTL821x_PHYSR_SPEED	GENMASK(15, 14)
++
+ #define RTL821x_INER		0x12
+ #define RTL8211B_INER_INIT	0x6400
++#define RTL8211E_INER_LINK_STATUS	BIT(10)
++#define RTL8211F_INER_LINK_STATUS	BIT(4)
++
+ #define RTL821x_INSR		0x13
++
+ #define RTL821x_PAGE_SELECT	0x1f
+-#define RTL8211E_INER_LINK_STATUS	BIT(10)
+ 
+-#define RTL8211F_INER_LINK_STATUS	BIT(4)
+ #define RTL8211F_INSR		0x1d
+ #define RTL8211F_TX_DELAY	BIT(8)
+ 
+
+From 3cd6e2f5de15c4c071d9ca9f02efcbd23b8435ad Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 22:51:27 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: use the same indentation for all
+ #defines
+
+This simply makes the code easier to read. No functional changes.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit f609ab0ed8e7bef2cd61d230bf9e83e1ec5b9ddb)
+---
+ drivers/net/phy/realtek.c | 27 ++++++++++++++-------------
+ 1 file changed, 14 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index df97d903d2bf..701f34ad7d8d 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -17,24 +17,25 @@
+ #include <linux/phy.h>
+ #include <linux/module.h>
+ 
+-#define RTL821x_PHYSR		0x11
+-#define RTL821x_PHYSR_DUPLEX	BIT(13)
+-#define RTL821x_PHYSR_SPEED	GENMASK(15, 14)
++#define RTL821x_PHYSR				0x11
++#define RTL821x_PHYSR_DUPLEX			BIT(13)
++#define RTL821x_PHYSR_SPEED			GENMASK(15, 14)
+ 
+-#define RTL821x_INER		0x12
+-#define RTL8211B_INER_INIT	0x6400
+-#define RTL8211E_INER_LINK_STATUS	BIT(10)
+-#define RTL8211F_INER_LINK_STATUS	BIT(4)
++#define RTL821x_INER				0x12
++#define RTL8211B_INER_INIT			0x6400
++#define RTL8211E_INER_LINK_STATUS		BIT(10)
++#define RTL8211F_INER_LINK_STATUS		BIT(4)
+ 
+-#define RTL821x_INSR		0x13
++#define RTL821x_INSR				0x13
+ 
+-#define RTL821x_PAGE_SELECT	0x1f
++#define RTL821x_PAGE_SELECT			0x1f
+ 
+-#define RTL8211F_INSR		0x1d
+-#define RTL8211F_TX_DELAY	BIT(8)
++#define RTL8211F_INSR				0x1d
+ 
+-#define RTL8201F_ISR		0x1e
+-#define RTL8201F_IER		0x13
++#define RTL8211F_TX_DELAY			BIT(8)
++
++#define RTL8201F_ISR				0x1e
++#define RTL8201F_IER				0x13
+ 
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+
+From 47e40b66fdafc0ce940090626759fe8418034a0e Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 22:51:28 +0100
+Subject: [PATCH] UPSTREAM: net: phy: realtek: add utility functions to
+ read/write page addresses
+
+Realtek PHYs implement the concept of so-called "extension pages". The
+reason for this is probably because these PHYs expose more registers
+than available in the standard address range.
+After all read/write operations on such a page are done the driver
+should switch back to page 0 where the standard MII registers (such as
+MII_BMCR) are available.
+
+When referring to such a register the datasheets of RTL8211E and
+RTL8211F always specify:
+- the page / "ext. page" which has to be written to RTL821x_PAGE_SELECT
+- an address (sometimes also called reg)
+
+These new utility functions make the existing code easier to read since
+it removes some duplication (switching back to page 0 is done within the
+new helpers for example).
+
+No functional changes are intended.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 136819a6e8df374e6b9b424586ff11c9e241a1cb)
+---
+ drivers/net/phy/realtek.c | 83 ++++++++++++++++++++++++++++++-----------------
+ 1 file changed, 53 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 701f34ad7d8d..b1d52e61d91c 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -41,6 +41,39 @@ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+ MODULE_LICENSE("GPL");
+ 
++static int rtl8211x_page_read(struct phy_device *phydev, u16 page, u16 address)
++{
++	int ret;
++
++	ret = phy_write(phydev, RTL821x_PAGE_SELECT, page);
++	if (ret)
++		return ret;
++
++	ret = phy_read(phydev, address);
++
++	/* restore to default page 0 */
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
++
++	return ret;
++}
++
++static int rtl8211x_page_write(struct phy_device *phydev, u16 page,
++			       u16 address, u16 val)
++{
++	int ret;
++
++	ret = phy_write(phydev, RTL821x_PAGE_SELECT, page);
++	if (ret)
++		return ret;
++
++	ret = phy_write(phydev, address, val);
++
++	/* restore to default page 0 */
++	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
++
++	return ret;
++}
++
+ static int rtl8201_ack_interrupt(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -63,31 +96,21 @@ static int rtl8211f_ack_interrupt(struct phy_device *phydev)
+ {
+ 	int err;
+ 
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa43);
+-	err = phy_read(phydev, RTL8211F_INSR);
+-	/* restore to default page 0 */
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
++	err = rtl8211x_page_read(phydev, 0xa43, RTL8211F_INSR);
+ 
+ 	return (err < 0) ? err : 0;
+ }
+ 
+ static int rtl8201_config_intr(struct phy_device *phydev)
+ {
+-	int err;
+-
+-	/* switch to page 7 */
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0x7);
++	u16 val;
+ 
+ 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+-		err = phy_write(phydev, RTL8201F_IER,
+-				BIT(13) | BIT(12) | BIT(11));
++		val = BIT(13) | BIT(12) | BIT(11);
+ 	else
+-		err = phy_write(phydev, RTL8201F_IER, 0);
++		val = 0;
+ 
+-	/* restore to default page 0 */
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
+-
+-	return err;
++	return rtl8211x_page_write(phydev, 0x7, RTL8201F_IER, val);
+ }
+ 
+ static int rtl8211b_config_intr(struct phy_device *phydev)
+@@ -118,41 +141,41 @@ static int rtl8211e_config_intr(struct phy_device *phydev)
+ 
+ static int rtl8211f_config_intr(struct phy_device *phydev)
+ {
+-	int err;
++	u16 val;
+ 
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa42);
+ 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+-		err = phy_write(phydev, RTL821x_INER,
+-				RTL8211F_INER_LINK_STATUS);
++		val = RTL8211F_INER_LINK_STATUS;
+ 	else
+-		err = phy_write(phydev, RTL821x_INER, 0);
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
++		val = 0;
+ 
+-	return err;
++	return rtl8211x_page_write(phydev, 0xa42, RTL821x_INER, val);
+ }
+ 
+ static int rtl8211f_config_init(struct phy_device *phydev)
+ {
+ 	int ret;
+-	u16 reg;
++	u16 val;
+ 
+ 	ret = genphy_config_init(phydev);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0xd08);
+-	reg = phy_read(phydev, 0x11);
++	ret = rtl8211x_page_read(phydev, 0xd08, 0x11);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
+ 
+ 	/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
+ 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+-		reg |= RTL8211F_TX_DELAY;
++		val |= RTL8211F_TX_DELAY;
+ 	else
+-		reg &= ~RTL8211F_TX_DELAY;
++		val &= ~RTL8211F_TX_DELAY;
+ 
+-	phy_write(phydev, 0x11, reg);
+-	/* restore to default page 0 */
+-	phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
++	ret = rtl8211x_page_write(phydev, 0xd08, 0x11, val);
++	if (ret)
++		return ret;
+ 
+ 	return 0;
+ }
+
+From b747e5d48f83fd4d3b824578f666ac136bc6de49 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 23:06:48 +0100
+Subject: [PATCH] FROMLIST: net: phy: realtek: add support for configuring the
+ RX delay on RTL8211F
+
+On RTL8211F the RX delay can also be enabled/disabled.
+The overall behavior of the RX delay is similar to the behavior of the
+TX delay, which was already supported by the driver.
+
+The RX delay (similar to the TX delay) may be enabled using hardware pin
+strapping. If the MAC already configures the RX delay (if required) then
+the RX delay generated by the RTL8211F PHY has to be turned off.
+
+While here, update the comment regarding the TX delay why it has to be
+enabled or disabled within the driver.
+Also avoid code-duplication by extracting the code to mask/unmask bits
+in a paged register into a new rtl8211x_page_mask_bits helper function.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/phy/realtek.c | 55 ++++++++++++++++++++++++++++++++++++++---------
+ 1 file changed, 45 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index b1d52e61d91c..890ea9d18d27 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -32,7 +32,10 @@
+ 
+ #define RTL8211F_INSR				0x1d
+ 
+-#define RTL8211F_TX_DELAY			BIT(8)
++#define RTL8211F_RX_DELAY_REG			0x15
++#define RTL8211F_RX_DELAY_EN			BIT(3)
++#define RTL8211F_TX_DELAY_REG			0x11
++#define RTL8211F_TX_DELAY_EN			BIT(8)
+ 
+ #define RTL8201F_ISR				0x1e
+ #define RTL8201F_IER				0x13
+@@ -74,6 +77,23 @@ static int rtl8211x_page_write(struct phy_device *phydev, u16 page,
+ 	return ret;
+ }
+ 
++static int rtl8211x_page_mask_bits(struct phy_device *phydev, u16 page,
++				   u16 address, u16 mask, u16 set)
++{
++	int ret;
++	u16 val;
++
++	ret = rtl8211x_page_read(phydev, page, address);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
++	val &= ~mask;
++	val |= (set & mask);
++
++	return rtl8211x_page_write(phydev, page, address, val);
++}
++
+ static int rtl8201_ack_interrupt(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -160,20 +180,35 @@ static int rtl8211f_config_init(struct phy_device *phydev)
+ 	if (ret < 0)
+ 		return ret;
+ 
+-	ret = rtl8211x_page_read(phydev, 0xd08, 0x11);
+-	if (ret < 0)
+-		return ret;
++	/*
++	 * enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it.
++	 * this is needed because it can be enabled by pin strapping and
++	 * conflict with the TX-delay configured by the MAC.
++	 */
++	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
++		val = RTL8211F_TX_DELAY_EN;
++	else
++		val = 0;
+ 
+-	val = ret & 0xffff;
++	ret = rtl8211x_page_mask_bits(phydev, 0xd08, RTL8211F_TX_DELAY_REG,
++				      RTL8211F_TX_DELAY_EN, val);
++	if (ret)
++		return ret;
+ 
+-	/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
++	/*
++	 * enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it.
++	 * this is needed because it can be enabled by pin strapping and
++	 * conflict with the RX-delay configured by the MAC.
++	 */
+ 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+-		val |= RTL8211F_TX_DELAY;
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
++		val = RTL8211F_RX_DELAY_EN;
+ 	else
+-		val &= ~RTL8211F_TX_DELAY;
++		val = 0;
+ 
+-	ret = rtl8211x_page_write(phydev, 0xd08, 0x11, val);
++	ret = rtl8211x_page_mask_bits(phydev, 0xd08, RTL8211F_RX_DELAY_REG,
++				      RTL8211F_RX_DELAY_EN, val);
+ 	if (ret)
+ 		return ret;
+ 
+
+From 4264d7cd3670514648b2ef632097c80e210e5690 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 23:06:49 +0100
+Subject: [PATCH] FROMLIST: net: phy: realtek: configure the INTB pin on
+ RTL8211F
+
+The interrupt pin on the RTL8211F PHY can be used in two different
+modes:
+INTB
+- the default mode of the PHY
+- interrupts can be configured through page 0xa42 register RTL821x_INER
+- interrupts can be ACK'ed through RTL8211F_INSR
+- it acts as a level-interrupt which is active low
+- Wake-on-LAN "wakeup" status is available in RTL8211F_INSR bit 7
+
+PMEB:
+- special mode for Wake-on-LAN
+- interrupts configured through page 0xa42 register RTL821x_INER are
+  disabled
+- it supports a "pulse low" waveform for the interrupt
+
+For now we simply force the pin into INTB mode since the PHY driver does
+not support Wake-on-LAN yet.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/phy/realtek.c | 27 +++++++++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index 890ea9d18d27..f307d220b49a 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -40,6 +40,9 @@
+ #define RTL8201F_ISR				0x1e
+ #define RTL8201F_IER				0x13
+ 
++#define RTL8211F_INTBCR				0x16
++#define RTL8211F_INTBCR_INTB_PMEB		BIT(5)
++
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+ MODULE_LICENSE("GPL");
+@@ -161,12 +164,32 @@ static int rtl8211e_config_intr(struct phy_device *phydev)
+ 
+ static int rtl8211f_config_intr(struct phy_device *phydev)
+ {
++	int err;
+ 	u16 val;
+ 
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
++		/*
++		 * The interrupt pin has two functions:
++		 * 0: INTB: it acts as interrupt pin which can be configured
++		 *    through RTL821x_INER and the status can be read through
++		 *    RTL8211F_INSR
++		 * 1: PMEB: a special "Power Management Event" mode for
++		 *    Wake-on-LAN operation (with support for a "pulse low"
++		 *    wave format). Interrupts configured through RTL821x_INER
++		 *    will not work in this mode
++		 *
++		 * select INTB mode in the "INTB pin control" register to
++		 * ensure that the interrupt pin is in the correct mode.
++		 */
++		err = rtl8211x_page_mask_bits(phydev, 0xd40, RTL8211F_INTBCR,
++					      RTL8211F_INTBCR_INTB_PMEB, 0);
++		if (err)
++			return err;
++
+ 		val = RTL8211F_INER_LINK_STATUS;
+-	else
++	} else {
+ 		val = 0;
++	}
+ 
+ 	return rtl8211x_page_write(phydev, 0xa42, RTL821x_INER, val);
+ }
+
+From 5f21ae02ffa16fafd12f635e7a5965842d7d492a Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 2 Dec 2017 23:06:50 +0100
+Subject: [PATCH] FROMLIST: net: phy: realtek: add more interrupt bits for
+ RTL8211E and RTL8211F
+
+This documents a few more bits in the RTL821x_INER register for RTL8211E
+and RTL8211F. These are added only to document them (as no public
+datasheets are available for these PHYs), they are currently not used.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/phy/realtek.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
+index f307d220b49a..15d342eefd6d 100644
+--- a/drivers/net/phy/realtek.c
++++ b/drivers/net/phy/realtek.c
+@@ -24,7 +24,14 @@
+ #define RTL821x_INER				0x12
+ #define RTL8211B_INER_INIT			0x6400
+ #define RTL8211E_INER_LINK_STATUS		BIT(10)
++#define RTL8211E_INER_ANEG_COMPLETED		BIT(11)
++#define RTL8211E_INER_PAGE_RECEIVED		BIT(12)
++#define RTL8211E_INER_ANEG_ERROR		BIT(15)
+ #define RTL8211F_INER_LINK_STATUS		BIT(4)
++#define RTL8211F_INER_PHY_REGISTER_ACCESSIBLE	BIT(5)
++#define RTL8211F_INER_WOL_PME			BIT(7)
++#define RTL8211F_INER_ALDPS_STATE_CHANGE	BIT(9)
++#define RTL8211F_INER_JABBER			BIT(10)
+ 
+ #define RTL821x_INSR				0x13
+ 

patch/kernel/rk322x-legacy/01-linux-0008-mmc-pwrseq.patch

@@ -0,0 +1,877 @@
+From 625c86fa85aa4d18f7711d0314f2ef78a71b79c0 Mon Sep 17 00:00:00 2001
+From: Julia Lawall <Julia.Lawall@lip6.fr>
+Date: Sat, 14 Nov 2015 18:05:20 +0100
+Subject: [PATCH] UPSTREAM: mmc: pwrseq: constify mmc_pwrseq_ops structures
+
+The mmc_pwrseq_ops structures are never modified, so declare them as const.
+
+Done with the help of Coccinelle.
+
+Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit ffedbd2210f2f4cba490a9205adc11fd1b89a852)
+---
+ drivers/mmc/core/pwrseq.h        | 2 +-
+ drivers/mmc/core/pwrseq_emmc.c   | 2 +-
+ drivers/mmc/core/pwrseq_simple.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/mmc/core/pwrseq.h b/drivers/mmc/core/pwrseq.h
+index 096da48c6a7e..133de0426687 100644
+--- a/drivers/mmc/core/pwrseq.h
++++ b/drivers/mmc/core/pwrseq.h
+@@ -16,7 +16,7 @@ struct mmc_pwrseq_ops {
+ };
+ 
+ struct mmc_pwrseq {
+-	struct mmc_pwrseq_ops *ops;
++	const struct mmc_pwrseq_ops *ops;
+ };
+ 
+ #ifdef CONFIG_OF
+diff --git a/drivers/mmc/core/pwrseq_emmc.c b/drivers/mmc/core/pwrseq_emmc.c
+index ad4f94ec7e8d..4a82bc77fe49 100644
+--- a/drivers/mmc/core/pwrseq_emmc.c
++++ b/drivers/mmc/core/pwrseq_emmc.c
+@@ -51,7 +51,7 @@ static void mmc_pwrseq_emmc_free(struct mmc_host *host)
+ 	kfree(pwrseq);
+ }
+ 
+-static struct mmc_pwrseq_ops mmc_pwrseq_emmc_ops = {
++static const struct mmc_pwrseq_ops mmc_pwrseq_emmc_ops = {
+ 	.post_power_on = mmc_pwrseq_emmc_reset,
+ 	.free = mmc_pwrseq_emmc_free,
+ };
+diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
+index d10538bb5e07..2b16263458af 100644
+--- a/drivers/mmc/core/pwrseq_simple.c
++++ b/drivers/mmc/core/pwrseq_simple.c
+@@ -87,7 +87,7 @@ static void mmc_pwrseq_simple_free(struct mmc_host *host)
+ 	kfree(pwrseq);
+ }
+ 
+-static struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = {
++static const struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = {
+ 	.pre_power_on = mmc_pwrseq_simple_pre_power_on,
+ 	.post_power_on = mmc_pwrseq_simple_post_power_on,
+ 	.power_off = mmc_pwrseq_simple_power_off,
+
+From 58975b7a58defa92efd5533cc731fb9a0c1cb780 Mon Sep 17 00:00:00 2001
+From: Peter Chen <peter.chen@freescale.com>
+Date: Wed, 6 Jan 2016 11:34:10 +0800
+Subject: [PATCH] UPSTREAM: mmc: core: pwrseq_simple: remove unused header file
+
+Signed-off-by: Peter Chen <peter.chen@freescale.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 62c03ca3ffa1ddf55a66411be02f7e4678771fce)
+---
+ drivers/mmc/core/pwrseq_simple.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
+index aba786daebca..bc173e18b71c 100644
+--- a/drivers/mmc/core/pwrseq_simple.c
++++ b/drivers/mmc/core/pwrseq_simple.c
+@@ -12,7 +12,6 @@
+ #include <linux/slab.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
+-#include <linux/of_gpio.h>
+ #include <linux/gpio/consumer.h>
+ 
+ #include <linux/mmc/host.h>
+
+From 01946788b015b9d3f7d18f5b4a43e09e6bf66623 Mon Sep 17 00:00:00 2001
+From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Date: Thu, 14 Apr 2016 14:02:14 +0100
+Subject: [PATCH] UPSTREAM: mmc: pwrseq_simple: add to_pwrseq_simple() macro
+
+This patch adds to_pwrseq_simple() macro to make the code more readable.
+
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 5b96fea730ab79bdf6f8071cadf8208296bf5e8d)
+---
+ drivers/mmc/core/pwrseq_simple.c | 14 ++++++--------
+ 1 file changed, 6 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
+index bc173e18b71c..f94271bb1f6b 100644
+--- a/drivers/mmc/core/pwrseq_simple.c
++++ b/drivers/mmc/core/pwrseq_simple.c
+@@ -25,6 +25,8 @@ struct mmc_pwrseq_simple {
+ 	struct gpio_descs *reset_gpios;
+ };
+ 
++#define to_pwrseq_simple(p) container_of(p, struct mmc_pwrseq_simple, pwrseq)
++
+ static void mmc_pwrseq_simple_set_gpios_value(struct mmc_pwrseq_simple *pwrseq,
+ 					      int value)
+ {
+@@ -44,8 +46,7 @@ static void mmc_pwrseq_simple_set_gpios_value(struct mmc_pwrseq_simple *pwrseq,
+ 
+ static void mmc_pwrseq_simple_pre_power_on(struct mmc_host *host)
+ {
+-	struct mmc_pwrseq_simple *pwrseq = container_of(host->pwrseq,
+-					struct mmc_pwrseq_simple, pwrseq);
++	struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
+ 
+ 	if (!IS_ERR(pwrseq->ext_clk) && !pwrseq->clk_enabled) {
+ 		clk_prepare_enable(pwrseq->ext_clk);
+@@ -57,16 +58,14 @@ static void mmc_pwrseq_simple_pre_power_on(struct mmc_host *host)
+ 
+ static void mmc_pwrseq_simple_post_power_on(struct mmc_host *host)
+ {
+-	struct mmc_pwrseq_simple *pwrseq = container_of(host->pwrseq,
+-					struct mmc_pwrseq_simple, pwrseq);
++	struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
+ 
+ 	mmc_pwrseq_simple_set_gpios_value(pwrseq, 0);
+ }
+ 
+ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
+ {
+-	struct mmc_pwrseq_simple *pwrseq = container_of(host->pwrseq,
+-					struct mmc_pwrseq_simple, pwrseq);
++	struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
+ 
+ 	mmc_pwrseq_simple_set_gpios_value(pwrseq, 1);
+ 
+@@ -78,8 +77,7 @@ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
+ 
+ static void mmc_pwrseq_simple_free(struct mmc_host *host)
+ {
+-	struct mmc_pwrseq_simple *pwrseq = container_of(host->pwrseq,
+-					struct mmc_pwrseq_simple, pwrseq);
++	struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
+ 
+ 	if (!IS_ERR(pwrseq->reset_gpios))
+ 		gpiod_put_array(pwrseq->reset_gpios);
+
+From b76637491013b2298cf46729767ba76544d4023b Mon Sep 17 00:00:00 2001
+From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Date: Thu, 14 Apr 2016 14:02:15 +0100
+Subject: [PATCH] UPSTREAM: mmc: pwrseq_emmc: add to_pwrseq_emmc() macro
+
+This patch adds to_pwrseq_emmc() macro to make the code more readable.
+
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit f01b72d0fd53b61cafd25b16d15e18b1ef8ae065)
+---
+ drivers/mmc/core/pwrseq_emmc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/core/pwrseq_emmc.c b/drivers/mmc/core/pwrseq_emmc.c
+index 4a82bc77fe49..c2d732aa464c 100644
+--- a/drivers/mmc/core/pwrseq_emmc.c
++++ b/drivers/mmc/core/pwrseq_emmc.c
+@@ -25,6 +25,8 @@ struct mmc_pwrseq_emmc {
+ 	struct gpio_desc *reset_gpio;
+ };
+ 
++#define to_pwrseq_emmc(p) container_of(p, struct mmc_pwrseq_emmc, pwrseq)
++
+ static void __mmc_pwrseq_emmc_reset(struct mmc_pwrseq_emmc *pwrseq)
+ {
+ 	gpiod_set_value(pwrseq->reset_gpio, 1);
+@@ -35,16 +37,14 @@ static void __mmc_pwrseq_emmc_reset(struct mmc_pwrseq_emmc *pwrseq)
+ 
+ static void mmc_pwrseq_emmc_reset(struct mmc_host *host)
+ {
+-	struct mmc_pwrseq_emmc *pwrseq = container_of(host->pwrseq,
+-					struct mmc_pwrseq_emmc, pwrseq);
++	struct mmc_pwrseq_emmc *pwrseq =  to_pwrseq_emmc(host->pwrseq);
+ 
+ 	__mmc_pwrseq_emmc_reset(pwrseq);
+ }
+ 
+ static void mmc_pwrseq_emmc_free(struct mmc_host *host)
+ {
+-	struct mmc_pwrseq_emmc *pwrseq = container_of(host->pwrseq,
+-					struct mmc_pwrseq_emmc, pwrseq);
++	struct mmc_pwrseq_emmc *pwrseq =  to_pwrseq_emmc(host->pwrseq);
+ 
+ 	unregister_restart_handler(&pwrseq->reset_nb);
+ 	gpiod_put(pwrseq->reset_gpio);
+
+From c1631d2cea4e5956e368c4652859a9090a509af2 Mon Sep 17 00:00:00 2001
+From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Date: Thu, 14 Apr 2016 14:02:16 +0100
+Subject: [PATCH] UPSTREAM: mmc: pwrseq: convert to proper platform device
+
+simple-pwrseq and emmc-pwrseq drivers rely on platform_device
+structure from of_find_device_by_node(), this works mostly. But, as there
+is no driver associated with this devices, cases like default/init pinctrl
+setup would never be performed by pwrseq. This becomes problem when the
+gpios used in pwrseq require pinctrl setup.
+
+Currently most of the common pinctrl setup is done in
+drivers/base/pinctrl.c by pinctrl_bind_pins().
+
+There are two ways to solve this issue on either convert pwrseq drivers
+to a proper platform drivers or copy the exact code from
+pcintrl_bind_pins(). I prefer converting pwrseq to proper drivers so that
+other cases like setting up clks/parents from dt would also be possible.
+
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit d97a1e5d7cd2b5b0edc02a40fe6897b710c9e10f)
+---
+ drivers/mmc/core/Kconfig         |  22 ++++++++
+ drivers/mmc/core/Makefile        |   4 +-
+ drivers/mmc/core/pwrseq.c        | 108 ++++++++++++++++++---------------------
+ drivers/mmc/core/pwrseq.h        |  19 ++++---
+ drivers/mmc/core/pwrseq_emmc.c   |  75 +++++++++++++++++----------
+ drivers/mmc/core/pwrseq_simple.c |  79 +++++++++++++++-------------
+ 6 files changed, 178 insertions(+), 129 deletions(-)
+
+diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
+index 87cc07dedd9f..00dfaea06003 100644
+--- a/drivers/mmc/core/Kconfig
++++ b/drivers/mmc/core/Kconfig
+@@ -16,3 +16,25 @@ config MMC_PARANOID_SD_INIT
+ 	  about re-trying SD init requests. This can be a useful
+ 	  work-around for buggy controllers and hardware. Enable
+ 	  if you are experiencing issues with SD detection.
++
++config PWRSEQ_EMMC
++	tristate "HW reset support for eMMC"
++	default y
++	depends on OF
++	help
++	  This selects Hardware reset support aka pwrseq-emmc for eMMC
++	  devices. By default this option is set to y.
++
++	  This driver can also be built as a module. If so, the module
++	  will be called pwrseq_emmc.
++
++config PWRSEQ_SIMPLE
++	tristate "Simple HW reset support for MMC"
++	default y
++	depends on OF
++	help
++	  This selects simple hardware reset support aka pwrseq-simple for MMC
++	  devices. By default this option is set to y.
++
++	  This driver can also be built as a module. If so, the module
++	  will be called pwrseq_simple.
+diff --git a/drivers/mmc/core/Makefile b/drivers/mmc/core/Makefile
+index 2c25138f28b7..f007151dfdc6 100644
+--- a/drivers/mmc/core/Makefile
++++ b/drivers/mmc/core/Makefile
+@@ -8,5 +8,7 @@ mmc_core-y			:= core.o bus.o host.o \
+ 				   sdio.o sdio_ops.o sdio_bus.o \
+ 				   sdio_cis.o sdio_io.o sdio_irq.o \
+ 				   quirks.o slot-gpio.o
+-mmc_core-$(CONFIG_OF)		+= pwrseq.o pwrseq_simple.o pwrseq_emmc.o
++mmc_core-$(CONFIG_OF)		+= pwrseq.o
++obj-$(CONFIG_PWRSEQ_SIMPLE)	+= pwrseq_simple.o
++obj-$(CONFIG_PWRSEQ_EMMC)	+= pwrseq_emmc.o
+ mmc_core-$(CONFIG_DEBUG_FS)	+= debugfs.o
+diff --git a/drivers/mmc/core/pwrseq.c b/drivers/mmc/core/pwrseq.c
+index 4c1d1757dbf9..9386c4771814 100644
+--- a/drivers/mmc/core/pwrseq.c
++++ b/drivers/mmc/core/pwrseq.c
+@@ -8,88 +8,55 @@
+  *  MMC power sequence management
+  */
+ #include <linux/kernel.h>
+-#include <linux/platform_device.h>
+ #include <linux/err.h>
++#include <linux/module.h>
+ #include <linux/of.h>
+-#include <linux/of_platform.h>
+ 
+ #include <linux/mmc/host.h>
+ 
+ #include "pwrseq.h"
+ 
+-struct mmc_pwrseq_match {
+-	const char *compatible;
+-	struct mmc_pwrseq *(*alloc)(struct mmc_host *host, struct device *dev);
+-};
+-
+-static struct mmc_pwrseq_match pwrseq_match[] = {
+-	{
+-		.compatible = "mmc-pwrseq-simple",
+-		.alloc = mmc_pwrseq_simple_alloc,
+-	}, {
+-		.compatible = "mmc-pwrseq-emmc",
+-		.alloc = mmc_pwrseq_emmc_alloc,
+-	},
+-};
+-
+-static struct mmc_pwrseq_match *mmc_pwrseq_find(struct device_node *np)
+-{
+-	struct mmc_pwrseq_match *match = ERR_PTR(-ENODEV);
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(pwrseq_match); i++) {
+-		if (of_device_is_compatible(np,	pwrseq_match[i].compatible)) {
+-			match = &pwrseq_match[i];
+-			break;
+-		}
+-	}
+-
+-	return match;
+-}
++static DEFINE_MUTEX(pwrseq_list_mutex);
++static LIST_HEAD(pwrseq_list);
+ 
+ int mmc_pwrseq_alloc(struct mmc_host *host)
+ {
+-	struct platform_device *pdev;
+ 	struct device_node *np;
+-	struct mmc_pwrseq_match *match;
+-	struct mmc_pwrseq *pwrseq;
+-	int ret = 0;
++	struct mmc_pwrseq *p;
+ 
+ 	np = of_parse_phandle(host->parent->of_node, "mmc-pwrseq", 0);
+ 	if (!np)
+ 		return 0;
+ 
+-	pdev = of_find_device_by_node(np);
+-	if (!pdev) {
+-		ret = -ENODEV;
+-		goto err;
+-	}
++	mutex_lock(&pwrseq_list_mutex);
++	list_for_each_entry(p, &pwrseq_list, pwrseq_node) {
++		if (p->dev->of_node == np) {
++			if (!try_module_get(p->owner))
++				dev_err(host->parent,
++					"increasing module refcount failed\n");
++			else
++				host->pwrseq = p;
+ 
+-	match = mmc_pwrseq_find(np);
+-	if (IS_ERR(match)) {
+-		ret = PTR_ERR(match);
+-		goto err;
++			break;
++		}
+ 	}
+ 
+-	pwrseq = match->alloc(host, &pdev->dev);
+-	if (IS_ERR(pwrseq)) {
+-		ret = PTR_ERR(pwrseq);
+-		goto err;
+-	}
++	of_node_put(np);
++	mutex_unlock(&pwrseq_list_mutex);
++
++	if (!host->pwrseq)
++		return -EPROBE_DEFER;
+ 
+-	host->pwrseq = pwrseq;
+ 	dev_info(host->parent, "allocated mmc-pwrseq\n");
+ 
+-err:
+-	of_node_put(np);
+-	return ret;
++	return 0;
+ }
+ 
+ void mmc_pwrseq_pre_power_on(struct mmc_host *host)
+ {
+ 	struct mmc_pwrseq *pwrseq = host->pwrseq;
+ 
+-	if (pwrseq && pwrseq->ops && pwrseq->ops->pre_power_on)
++	if (pwrseq && pwrseq->ops->pre_power_on)
+ 		pwrseq->ops->pre_power_on(host);
+ }
+ 
+@@ -97,7 +64,7 @@ void mmc_pwrseq_post_power_on(struct mmc_host *host)
+ {
+ 	struct mmc_pwrseq *pwrseq = host->pwrseq;
+ 
+-	if (pwrseq && pwrseq->ops && pwrseq->ops->post_power_on)
++	if (pwrseq && pwrseq->ops->post_power_on)
+ 		pwrseq->ops->post_power_on(host);
+ }
+ 
+@@ -105,7 +72,7 @@ void mmc_pwrseq_power_off(struct mmc_host *host)
+ {
+ 	struct mmc_pwrseq *pwrseq = host->pwrseq;
+ 
+-	if (pwrseq && pwrseq->ops && pwrseq->ops->power_off)
++	if (pwrseq && pwrseq->ops->power_off)
+ 		pwrseq->ops->power_off(host);
+ }
+ 
+@@ -113,8 +80,31 @@ void mmc_pwrseq_free(struct mmc_host *host)
+ {
+ 	struct mmc_pwrseq *pwrseq = host->pwrseq;
+ 
+-	if (pwrseq && pwrseq->ops && pwrseq->ops->free)
+-		pwrseq->ops->free(host);
++	if (pwrseq) {
++		module_put(pwrseq->owner);
++		host->pwrseq = NULL;
++	}
++}
++
++int mmc_pwrseq_register(struct mmc_pwrseq *pwrseq)
++{
++	if (!pwrseq || !pwrseq->ops || !pwrseq->dev)
++		return -EINVAL;
+ 
+-	host->pwrseq = NULL;
++	mutex_lock(&pwrseq_list_mutex);
++	list_add(&pwrseq->pwrseq_node, &pwrseq_list);
++	mutex_unlock(&pwrseq_list_mutex);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(mmc_pwrseq_register);
++
++void mmc_pwrseq_unregister(struct mmc_pwrseq *pwrseq)
++{
++	if (pwrseq) {
++		mutex_lock(&pwrseq_list_mutex);
++		list_del(&pwrseq->pwrseq_node);
++		mutex_unlock(&pwrseq_list_mutex);
++	}
+ }
++EXPORT_SYMBOL_GPL(mmc_pwrseq_unregister);
+diff --git a/drivers/mmc/core/pwrseq.h b/drivers/mmc/core/pwrseq.h
+index 133de0426687..d69e751f148b 100644
+--- a/drivers/mmc/core/pwrseq.h
++++ b/drivers/mmc/core/pwrseq.h
+@@ -8,32 +8,39 @@
+ #ifndef _MMC_CORE_PWRSEQ_H
+ #define _MMC_CORE_PWRSEQ_H
+ 
++#include <linux/mmc/host.h>
++
+ struct mmc_pwrseq_ops {
+ 	void (*pre_power_on)(struct mmc_host *host);
+ 	void (*post_power_on)(struct mmc_host *host);
+ 	void (*power_off)(struct mmc_host *host);
+-	void (*free)(struct mmc_host *host);
+ };
+ 
+ struct mmc_pwrseq {
+ 	const struct mmc_pwrseq_ops *ops;
++	struct device *dev;
++	struct list_head pwrseq_node;
++	struct module *owner;
+ };
+ 
+ #ifdef CONFIG_OF
+ 
++int mmc_pwrseq_register(struct mmc_pwrseq *pwrseq);
++void mmc_pwrseq_unregister(struct mmc_pwrseq *pwrseq);
++
+ int mmc_pwrseq_alloc(struct mmc_host *host);
+ void mmc_pwrseq_pre_power_on(struct mmc_host *host);
+ void mmc_pwrseq_post_power_on(struct mmc_host *host);
+ void mmc_pwrseq_power_off(struct mmc_host *host);
+ void mmc_pwrseq_free(struct mmc_host *host);
+ 
+-struct mmc_pwrseq *mmc_pwrseq_simple_alloc(struct mmc_host *host,
+-					   struct device *dev);
+-struct mmc_pwrseq *mmc_pwrseq_emmc_alloc(struct mmc_host *host,
+-					 struct device *dev);
+-
+ #else
+ 
++static inline int mmc_pwrseq_register(struct mmc_pwrseq *pwrseq)
++{
++	return -ENOSYS;
++}
++static inline void mmc_pwrseq_unregister(struct mmc_pwrseq *pwrseq) {}
+ static inline int mmc_pwrseq_alloc(struct mmc_host *host) { return 0; }
+ static inline void mmc_pwrseq_pre_power_on(struct mmc_host *host) {}
+ static inline void mmc_pwrseq_post_power_on(struct mmc_host *host) {}
+diff --git a/drivers/mmc/core/pwrseq_emmc.c b/drivers/mmc/core/pwrseq_emmc.c
+index c2d732aa464c..adc9c0c614fb 100644
+--- a/drivers/mmc/core/pwrseq_emmc.c
++++ b/drivers/mmc/core/pwrseq_emmc.c
+@@ -9,6 +9,9 @@
+  */
+ #include <linux/delay.h>
+ #include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/module.h>
+ #include <linux/slab.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
+@@ -42,20 +45,6 @@ static void mmc_pwrseq_emmc_reset(struct mmc_host *host)
+ 	__mmc_pwrseq_emmc_reset(pwrseq);
+ }
+ 
+-static void mmc_pwrseq_emmc_free(struct mmc_host *host)
+-{
+-	struct mmc_pwrseq_emmc *pwrseq =  to_pwrseq_emmc(host->pwrseq);
+-
+-	unregister_restart_handler(&pwrseq->reset_nb);
+-	gpiod_put(pwrseq->reset_gpio);
+-	kfree(pwrseq);
+-}
+-
+-static const struct mmc_pwrseq_ops mmc_pwrseq_emmc_ops = {
+-	.post_power_on = mmc_pwrseq_emmc_reset,
+-	.free = mmc_pwrseq_emmc_free,
+-};
+-
+ static int mmc_pwrseq_emmc_reset_nb(struct notifier_block *this,
+ 				    unsigned long mode, void *cmd)
+ {
+@@ -66,21 +55,22 @@ static int mmc_pwrseq_emmc_reset_nb(struct notifier_block *this,
+ 	return NOTIFY_DONE;
+ }
+ 
+-struct mmc_pwrseq *mmc_pwrseq_emmc_alloc(struct mmc_host *host,
+-					 struct device *dev)
++static const struct mmc_pwrseq_ops mmc_pwrseq_emmc_ops = {
++	.post_power_on = mmc_pwrseq_emmc_reset,
++};
++
++static int mmc_pwrseq_emmc_probe(struct platform_device *pdev)
+ {
+ 	struct mmc_pwrseq_emmc *pwrseq;
+-	int ret = 0;
++	struct device *dev = &pdev->dev;
+ 
+-	pwrseq = kzalloc(sizeof(struct mmc_pwrseq_emmc), GFP_KERNEL);
++	pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL);
+ 	if (!pwrseq)
+-		return ERR_PTR(-ENOMEM);
++		return -ENOMEM;
+ 
+-	pwrseq->reset_gpio = gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+-	if (IS_ERR(pwrseq->reset_gpio)) {
+-		ret = PTR_ERR(pwrseq->reset_gpio);
+-		goto free;
+-	}
++	pwrseq->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
++	if (IS_ERR(pwrseq->reset_gpio))
++		return PTR_ERR(pwrseq->reset_gpio);
+ 
+ 	/*
+ 	 * register reset handler to ensure emmc reset also from
+@@ -92,9 +82,38 @@ struct mmc_pwrseq *mmc_pwrseq_emmc_alloc(struct mmc_host *host,
+ 	register_restart_handler(&pwrseq->reset_nb);
+ 
+ 	pwrseq->pwrseq.ops = &mmc_pwrseq_emmc_ops;
++	pwrseq->pwrseq.dev = dev;
++	pwrseq->pwrseq.owner = THIS_MODULE;
++	platform_set_drvdata(pdev, pwrseq);
++
++	return mmc_pwrseq_register(&pwrseq->pwrseq);
++}
++
++static int mmc_pwrseq_emmc_remove(struct platform_device *pdev)
++{
++	struct mmc_pwrseq_emmc *pwrseq = platform_get_drvdata(pdev);
++
++	unregister_restart_handler(&pwrseq->reset_nb);
++	mmc_pwrseq_unregister(&pwrseq->pwrseq);
+ 
+-	return &pwrseq->pwrseq;
+-free:
+-	kfree(pwrseq);
+-	return ERR_PTR(ret);
++	return 0;
+ }
++
++static const struct of_device_id mmc_pwrseq_emmc_of_match[] = {
++	{ .compatible = "mmc-pwrseq-emmc",},
++	{/* sentinel */},
++};
++
++MODULE_DEVICE_TABLE(of, mmc_pwrseq_emmc_of_match);
++
++static struct platform_driver mmc_pwrseq_emmc_driver = {
++	.probe = mmc_pwrseq_emmc_probe,
++	.remove = mmc_pwrseq_emmc_remove,
++	.driver = {
++		.name = "pwrseq_emmc",
++		.of_match_table = mmc_pwrseq_emmc_of_match,
++	},
++};
++
++module_platform_driver(mmc_pwrseq_emmc_driver);
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
+index f94271bb1f6b..450d907c6e6c 100644
+--- a/drivers/mmc/core/pwrseq_simple.c
++++ b/drivers/mmc/core/pwrseq_simple.c
+@@ -8,7 +8,10 @@
+  *  Simple MMC power sequence management
+  */
+ #include <linux/clk.h>
++#include <linux/init.h>
+ #include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/module.h>
+ #include <linux/slab.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
+@@ -75,58 +78,64 @@ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
+ 	}
+ }
+ 
+-static void mmc_pwrseq_simple_free(struct mmc_host *host)
+-{
+-	struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
+-
+-	if (!IS_ERR(pwrseq->reset_gpios))
+-		gpiod_put_array(pwrseq->reset_gpios);
+-
+-	if (!IS_ERR(pwrseq->ext_clk))
+-		clk_put(pwrseq->ext_clk);
+-
+-	kfree(pwrseq);
+-}
+-
+ static const struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = {
+ 	.pre_power_on = mmc_pwrseq_simple_pre_power_on,
+ 	.post_power_on = mmc_pwrseq_simple_post_power_on,
+ 	.power_off = mmc_pwrseq_simple_power_off,
+-	.free = mmc_pwrseq_simple_free,
+ };
+ 
+-struct mmc_pwrseq *mmc_pwrseq_simple_alloc(struct mmc_host *host,
+-					   struct device *dev)
++static const struct of_device_id mmc_pwrseq_simple_of_match[] = {
++	{ .compatible = "mmc-pwrseq-simple",},
++	{/* sentinel */},
++};
++MODULE_DEVICE_TABLE(of, mmc_pwrseq_simple_of_match);
++
++static int mmc_pwrseq_simple_probe(struct platform_device *pdev)
+ {
+ 	struct mmc_pwrseq_simple *pwrseq;
+-	int ret = 0;
++	struct device *dev = &pdev->dev;
+ 
+-	pwrseq = kzalloc(sizeof(*pwrseq), GFP_KERNEL);
++	pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL);
+ 	if (!pwrseq)
+-		return ERR_PTR(-ENOMEM);
++		return -ENOMEM;
+ 
+-	pwrseq->ext_clk = clk_get(dev, "ext_clock");
+-	if (IS_ERR(pwrseq->ext_clk) &&
+-	    PTR_ERR(pwrseq->ext_clk) != -ENOENT) {
+-		ret = PTR_ERR(pwrseq->ext_clk);
+-		goto free;
+-	}
++	pwrseq->ext_clk = devm_clk_get(dev, "ext_clock");
++	if (IS_ERR(pwrseq->ext_clk) && PTR_ERR(pwrseq->ext_clk) != -ENOENT)
++		return PTR_ERR(pwrseq->ext_clk);
+ 
+-	pwrseq->reset_gpios = gpiod_get_array(dev, "reset", GPIOD_OUT_HIGH);
++	pwrseq->reset_gpios = devm_gpiod_get_array(dev, "reset",
++							GPIOD_OUT_HIGH);
+ 	if (IS_ERR(pwrseq->reset_gpios) &&
+ 	    PTR_ERR(pwrseq->reset_gpios) != -ENOENT &&
+ 	    PTR_ERR(pwrseq->reset_gpios) != -ENOSYS) {
+-		ret = PTR_ERR(pwrseq->reset_gpios);
+-		goto clk_put;
++		return PTR_ERR(pwrseq->reset_gpios);
+ 	}
+ 
++	pwrseq->pwrseq.dev = dev;
+ 	pwrseq->pwrseq.ops = &mmc_pwrseq_simple_ops;
++	pwrseq->pwrseq.owner = THIS_MODULE;
++	platform_set_drvdata(pdev, pwrseq);
+ 
+-	return &pwrseq->pwrseq;
+-clk_put:
+-	if (!IS_ERR(pwrseq->ext_clk))
+-		clk_put(pwrseq->ext_clk);
+-free:
+-	kfree(pwrseq);
+-	return ERR_PTR(ret);
++	return mmc_pwrseq_register(&pwrseq->pwrseq);
+ }
++
++static int mmc_pwrseq_simple_remove(struct platform_device *pdev)
++{
++	struct mmc_pwrseq_simple *pwrseq = platform_get_drvdata(pdev);
++
++	mmc_pwrseq_unregister(&pwrseq->pwrseq);
++
++	return 0;
++}
++
++static struct platform_driver mmc_pwrseq_simple_driver = {
++	.probe = mmc_pwrseq_simple_probe,
++	.remove = mmc_pwrseq_simple_remove,
++	.driver = {
++		.name = "pwrseq_simple",
++		.of_match_table = mmc_pwrseq_simple_of_match,
++	},
++};
++
++module_platform_driver(mmc_pwrseq_simple_driver);
++MODULE_LICENSE("GPL v2");
+
+From 2abada2ff3999a38dc87d5803f98141a0971c06c Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Sun, 7 Aug 2016 21:02:38 +0200
+Subject: [PATCH] UPSTREAM: mmc: pwrseq-simple: Add an optional
+ post-power-on-delay
+
+Some devices need a while to boot their firmware after providing clks /
+de-asserting resets before they are ready to receive sdio commands.
+
+This commits adds a post-power-on-delay-ms devicetree property to
+mmc-pwrseq-simple for use with such devices.
+
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+(cherry picked from commit 721e0497172f0fa661eed2d63367cddf479f35e8)
+---
+ Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 2 ++
+ drivers/mmc/core/pwrseq_simple.c                            | 9 +++++++++
+ 2 files changed, 11 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
+index ce0e76749671..e25436861867 100644
+--- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
++++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
+@@ -16,6 +16,8 @@ Optional properties:
+   See ../clocks/clock-bindings.txt for details.
+ - clock-names : Must include the following entry:
+   "ext_clock" (External clock provided to the card).
++- post-power-on-delay-ms : Delay in ms after powering the card and
++	de-asserting the reset-gpios (if any)
+ 
+ Example:
+ 
+diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
+index 450d907c6e6c..1304160de168 100644
+--- a/drivers/mmc/core/pwrseq_simple.c
++++ b/drivers/mmc/core/pwrseq_simple.c
+@@ -16,6 +16,8 @@
+ #include <linux/device.h>
+ #include <linux/err.h>
+ #include <linux/gpio/consumer.h>
++#include <linux/delay.h>
++#include <linux/property.h>
+ 
+ #include <linux/mmc/host.h>
+ 
+@@ -24,6 +26,7 @@
+ struct mmc_pwrseq_simple {
+ 	struct mmc_pwrseq pwrseq;
+ 	bool clk_enabled;
++	u32 post_power_on_delay_ms;
+ 	struct clk *ext_clk;
+ 	struct gpio_descs *reset_gpios;
+ };
+@@ -64,6 +67,9 @@ static void mmc_pwrseq_simple_post_power_on(struct mmc_host *host)
+ 	struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
+ 
+ 	mmc_pwrseq_simple_set_gpios_value(pwrseq, 0);
++
++	if (pwrseq->post_power_on_delay_ms)
++		msleep(pwrseq->post_power_on_delay_ms);
+ }
+ 
+ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
+@@ -111,6 +117,9 @@ static int mmc_pwrseq_simple_probe(struct platform_device *pdev)
+ 		return PTR_ERR(pwrseq->reset_gpios);
+ 	}
+ 
++	device_property_read_u32(dev, "post-power-on-delay-ms",
++				 &pwrseq->post_power_on_delay_ms);
++
+ 	pwrseq->pwrseq.dev = dev;
+ 	pwrseq->pwrseq.ops = &mmc_pwrseq_simple_ops;
+ 	pwrseq->pwrseq.owner = THIS_MODULE;
+
+From 4d0a703460821fc7541ae96916eca948e326b16c Mon Sep 17 00:00:00 2001
+From: Ulf Hansson <ulf.hansson@linaro.org>
+Date: Sat, 6 May 2017 11:41:30 +0200
+Subject: [PATCH] UPSTREAM: mmc: dt: pwrseq-simple: Invent power-off-delay-us
+
+During power off, after the GPIO pin has been asserted, some devices like
+the Wifi chip from TI, Wl18xx, needs a delay before the host continues with
+clock gating and turning off regulators as to follow a graceful shutdown
+sequence.
+
+Therefore invent an optional power-off-delay-us DT binding for
+mmc-pwrseq-simple, to allow us to support this constraint.
+
+Cc: devicetree@vger.kernel.org
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: linux-mmc@vger.kernel.org
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+---
+ Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
+index e25436861867..9029b45b8a22 100644
+--- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
++++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
+@@ -18,6 +18,8 @@ Optional properties:
+   "ext_clock" (External clock provided to the card).
+ - post-power-on-delay-ms : Delay in ms after powering the card and
+ 	de-asserting the reset-gpios (if any)
++- power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
++	during power off of the card.
+ 
+ Example:
+ 
+
+From e85294cdf12c6a6e6fb3c24cae1ad0994ae6aca2 Mon Sep 17 00:00:00 2001
+From: Ulf Hansson <ulf.hansson@linaro.org>
+Date: Sat, 6 May 2017 11:43:05 +0200
+Subject: [PATCH] UPSTREAM: mmc: pwrseq_simple: Parse DTS for the
+ power-off-delay-us property
+
+If the optional power-off-delay-us property is found, insert the
+corresponding delay after asserting the GPIO during power off. This enables
+a graceful shutdown sequence for some devices.
+
+Cc: linux-mmc@vger.kernel.org
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit e9256e142f597edf90c68cec22db4c4aebaa27de)
+---
+ drivers/mmc/core/pwrseq_simple.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
+index 1304160de168..13ef162cf066 100644
+--- a/drivers/mmc/core/pwrseq_simple.c
++++ b/drivers/mmc/core/pwrseq_simple.c
+@@ -27,6 +27,7 @@ struct mmc_pwrseq_simple {
+ 	struct mmc_pwrseq pwrseq;
+ 	bool clk_enabled;
+ 	u32 post_power_on_delay_ms;
++	u32 power_off_delay_us;
+ 	struct clk *ext_clk;
+ 	struct gpio_descs *reset_gpios;
+ };
+@@ -78,6 +79,10 @@ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
+ 
+ 	mmc_pwrseq_simple_set_gpios_value(pwrseq, 1);
+ 
++	if (pwrseq->power_off_delay_us)
++		usleep_range(pwrseq->power_off_delay_us,
++			2 * pwrseq->power_off_delay_us);
++
+ 	if (!IS_ERR(pwrseq->ext_clk) && pwrseq->clk_enabled) {
+ 		clk_disable_unprepare(pwrseq->ext_clk);
+ 		pwrseq->clk_enabled = false;
+@@ -119,6 +124,8 @@ static int mmc_pwrseq_simple_probe(struct platform_device *pdev)
+ 
+ 	device_property_read_u32(dev, "post-power-on-delay-ms",
+ 				 &pwrseq->post_power_on_delay_ms);
++	device_property_read_u32(dev, "power-off-delay-us",
++				 &pwrseq->power_off_delay_us);
+ 
+ 	pwrseq->pwrseq.dev = dev;
+ 	pwrseq->pwrseq.ops = &mmc_pwrseq_simple_ops;

patch/kernel/rk322x-legacy/01-linux-0009-mmc.patch

@@ -0,0 +1,267 @@
+diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
+index f82b1eb..d2c59b5 100644
+--- a/drivers/mmc/core/core.c
++++ b/drivers/mmc/core/core.c
+@@ -1574,7 +1574,34 @@ u32 mmc_select_voltage(struct mmc_host *host, u32 ocr)
+ 	return ocr;
+ }
+ 
+-int mmc_host_set_uhs_voltage(struct mmc_host *host, int signal_voltage)
++int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage)
++{
++	int err = 0;
++	int old_signal_voltage = host->ios.signal_voltage;
++
++	host->ios.signal_voltage = signal_voltage;
++	if (host->ops->start_signal_voltage_switch)
++		err = host->ops->start_signal_voltage_switch(host, &host->ios);
++
++	if (err)
++		host->ios.signal_voltage = old_signal_voltage;
++
++	return err;
++
++}
++
++void mmc_set_initial_signal_voltage(struct mmc_host *host)
++{
++	/* Try to set signal voltage to 3.3V but fall back to 1.8v or 1.2v */
++	if (!mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330))
++		dev_dbg(mmc_dev(host), "Initial signal voltage of 3.3v\n");
++	else if (!mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180))
++		dev_dbg(mmc_dev(host), "Initial signal voltage of 1.8v\n");
++	else if (!mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120))
++		dev_dbg(mmc_dev(host), "Initial signal voltage of 1.2v\n");
++}
++
++int mmc_host_set_uhs_voltage(struct mmc_host *host)
+ {
+ 	u32 clock;
+ 
+@@ -1586,7 +1613,7 @@ int mmc_host_set_uhs_voltage(struct mmc_host *host, int signal_voltage)
+ 	host->ios.clock = 0;
+ 	mmc_set_ios(host);
+ 
+-	if (__mmc_set_signal_voltage(host, signal_voltage))
++	if (mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180))
+ 		return -EAGAIN;
+ 
+ 	/* Keep clock gated for at least 10 ms, though spec only says 5 ms */
+@@ -1597,23 +1624,7 @@ int mmc_host_set_uhs_voltage(struct mmc_host *host, int signal_voltage)
+ 	return 0;
+ }
+ 
+-int __mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage)
+-{
+-	int err = 0;
+-	int old_signal_voltage = host->ios.signal_voltage;
+-
+-	host->ios.signal_voltage = signal_voltage;
+-	if (host->ops->start_signal_voltage_switch)
+-		err = host->ops->start_signal_voltage_switch(host, &host->ios);
+-
+-	if (err)
+-		host->ios.signal_voltage = old_signal_voltage;
+-
+-	return err;
+-
+-}
+-
+-int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr)
++int mmc_set_uhs_voltage(struct mmc_host *host, u32 ocr)
+ {
+ 	struct mmc_command cmd = {0};
+ 	int err = 0;
+@@ -1621,13 +1632,6 @@ int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr)
+ 	BUG_ON(!host);
+ 
+ 	/*
+-	 * Send CMD11 only if the request is to switch the card to
+-	 * 1.8V signalling.
+-	 */
+-	if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+-		return __mmc_set_signal_voltage(host, signal_voltage);
+-
+-	/*
+ 	 * If we cannot switch voltages, return failure so the caller
+ 	 * can continue without UHS mode
+ 	 */
+@@ -1658,7 +1662,7 @@ int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr)
+ 		goto power_cycle;
+ 	}
+ 
+-	if (mmc_host_set_uhs_voltage(host, signal_voltage)) {
++	if (mmc_host_set_uhs_voltage(host)) {
+ 		/*
+ 		 * Voltages may not have been switched, but we've already
+ 		 * sent CMD11, so a power cycle is required anyway
+@@ -1761,13 +1765,7 @@ void mmc_power_up(struct mmc_host *host, u32 ocr)
+ 	/* Set initial state and call mmc_set_ios */
+ 	mmc_set_initial_state(host);
+ 
+-	/* Try to set signal voltage to 3.3V but fall back to 1.8v or 1.2v */
+-	if (__mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330) == 0)
+-		dev_dbg(mmc_dev(host), "Initial signal voltage of 3.3v\n");
+-	else if (__mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180) == 0)
+-		dev_dbg(mmc_dev(host), "Initial signal voltage of 1.8v\n");
+-	else if (__mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120) == 0)
+-		dev_dbg(mmc_dev(host), "Initial signal voltage of 1.2v\n");
++	mmc_set_initial_signal_voltage(host);
+ 
+ 	/*
+ 	 * This delay should be sufficient to allow the power supply
+@@ -1794,6 +1792,14 @@ void mmc_power_off(struct mmc_host *host)
+ 	if (host->ios.power_mode == MMC_POWER_OFF)
+ 		return;
+ 
++	mmc_set_initial_signal_voltage(host);
++
++	/*
++	 * This delay should be sufficient to allow the power supply
++	 * to reach the minimum voltage.
++	 */
++	mmc_delay(10);
++
+ 	mmc_pwrseq_power_off(host);
+ 
+ 	host->ios.clock = 0;
+diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
+index 2cd32dc..2634722 100644
+--- a/drivers/mmc/core/core.h
++++ b/drivers/mmc/core/core.h
+@@ -43,9 +43,10 @@ void mmc_set_clock(struct mmc_host *host, unsigned int hz);
+ void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode);
+ void mmc_set_bus_width(struct mmc_host *host, unsigned int width);
+ u32 mmc_select_voltage(struct mmc_host *host, u32 ocr);
+-int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, u32 ocr);
+-int mmc_host_set_uhs_voltage(struct mmc_host *host, int signal_voltage);
+-int __mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage);
++int mmc_set_uhs_voltage(struct mmc_host *host, u32 ocr);
++int mmc_host_set_uhs_voltage(struct mmc_host *host);
++int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage);
++void mmc_set_initial_signal_voltage(struct mmc_host *host);
+ void mmc_set_timing(struct mmc_host *host, unsigned int timing);
+ void mmc_set_driver_type(struct mmc_host *host, unsigned int drv_type);
+ int mmc_select_drive_strength(struct mmc_card *card, unsigned int max_dtr,
+diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
+index a814eb6..dd0040a 100644
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1088,14 +1088,14 @@ static int mmc_select_hs_ddr(struct mmc_card *card)
+ 	 */
+ 	err = -EINVAL;
+ 	if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_2V)
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
+ 
+ 	if (err && (card->mmc_avail_type & EXT_CSD_CARD_TYPE_DDR_1_8V))
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
+ 
+ 	/* make sure vccq is 3.3v after switching disaster */
+ 	if (err)
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330);
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330);
+ 
+ 	if (!err)
+ 		mmc_set_timing(host, MMC_TIMING_MMC_DDR52);
+@@ -1251,7 +1251,7 @@ out_err:
+ static int mmc_select_hs400es(struct mmc_card *card)
+ {
+ 	struct mmc_host *host = card->host;
+-	int err = 0;
++	int err = -EINVAL;
+ 	u8 val;
+ 
+ 	if (!(host->caps & MMC_CAP_8_BIT_DATA)) {
+@@ -1259,11 +1259,11 @@ static int mmc_select_hs400es(struct mmc_card *card)
+ 		goto out_err;
+ 	}
+ 
+-	if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_2V)
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
++	if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400_1_2V)
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
+ 
+-	if (err && card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_8V)
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
++	if (err && card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400_1_8V)
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
+ 
+ 	/* If fails try again during next card power cycle */
+ 	if (err)
+@@ -1362,10 +1362,10 @@ static int mmc_select_hs200(struct mmc_card *card)
+ 
+ 	old_signal_voltage = host->ios.signal_voltage;
+ 	if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_2V)
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_120);
+ 
+ 	if (err && card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200_1_8V)
+-		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
++		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
+ 
+ 	/* If fails try again during next card power cycle */
+ 	if (err)
+@@ -1393,7 +1393,7 @@ static int mmc_select_hs200(struct mmc_card *card)
+ err:
+ 	if (err) {
+ 		/* fall back to the old signal voltage, if fails report error */
+-		if (__mmc_set_signal_voltage(host, old_signal_voltage))
++		if (mmc_set_signal_voltage(host, old_signal_voltage))
+ 			err = -EIO;
+ 
+ 		pr_err("%s: %s failed, error %d\n", mmc_hostname(card->host),
+diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
+index 78638ee..17919cb 100644
+--- a/drivers/mmc/core/sd.c
++++ b/drivers/mmc/core/sd.c
+@@ -742,8 +742,7 @@ try_again:
+ 	 */
+ 	if (!mmc_host_is_spi(host) && rocr &&
+ 	   ((*rocr & 0x41000000) == 0x41000000)) {
+-		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180,
+-					pocr);
++		err = mmc_set_uhs_voltage(host, pocr);
+ 		if (err == -EAGAIN) {
+ 			retries--;
+ 			goto try_again;
+@@ -928,7 +927,6 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr,
+ 
+ 	BUG_ON(!host);
+ 	WARN_ON(!host->claimed);
+-
+ retry:
+ 	err = mmc_sd_get_cid(host, ocr, cid, &rocr);
+ 	if (err)
+@@ -1013,7 +1011,7 @@ retry:
+ 				goto free_card;
+ 		}
+ 		if (mmc_sd_card_using_v18(card)) {
+-			if (mmc_host_set_uhs_voltage(host, MMC_SIGNAL_VOLTAGE_180) ||
++			if (mmc_host_set_uhs_voltage(host) ||
+ 			    mmc_sd_init_uhs_card(card)) {
+ 				v18_fixup_failed = true;
+ 				mmc_power_cycle(host, ocr);
+@@ -1057,7 +1055,6 @@ retry:
+ 			mmc_set_bus_width(host, MMC_BUS_WIDTH_4);
+ 		}
+ 	}
+-
+ done:
+ 	host->card = card;
+ 	return 0;
+diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
+index c586b11..f221418 100644
+--- a/drivers/mmc/core/sdio.c
++++ b/drivers/mmc/core/sdio.c
+@@ -648,8 +648,7 @@ try_again:
+ 	 * to make sure which speed mode should work.
+ 	 */
+ 	if (!powered_resume && (rocr & ocr & R4_18V_PRESENT)) {
+-		err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180,
+-					ocr_card);
++		err = mmc_set_uhs_voltage(host, ocr_card);
+ 		if (err == -EAGAIN) {
+ 			mmc_sdio_resend_if_cond(host, card);
+ 			retries--;

patch/kernel/rk322x-legacy/01-linux-0010-dvb.patch

@@ -0,0 +1,376 @@
+From 77d2716cf5579c4ad74df978ad58d983419cc44b Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <jakub.kicinski@netronome.com>
+Date: Wed, 31 Aug 2016 12:46:44 +0100
+Subject: [PATCH] UPSTREAM: add basic register-field manipulation macros
+
+Common approach to accessing register fields is to define
+structures or sets of macros containing mask and shift pair.
+Operations on the register are then performed as follows:
+
+ field = (reg >> shift) & mask;
+
+ reg &= ~(mask << shift);
+ reg |= (field & mask) << shift;
+
+Defining shift and mask separately is tedious.  Ivo van Doorn
+came up with an idea of computing them at compilation time
+based on a single shifted mask (later refined by Felix) which
+can be used like this:
+
+ #define REG_FIELD 0x000ff000
+
+ field = FIELD_GET(REG_FIELD, reg);
+
+ reg &= ~REG_FIELD;
+ reg |= FIELD_PREP(REG_FIELD, field);
+
+FIELD_{GET,PREP} macros take care of finding out what the
+appropriate shift is based on compilation time ffs operation.
+
+GENMASK can be used to define registers (which is usually
+less error-prone and easier to match with datasheets).
+
+This approach is the most convenient I've seen so to limit code
+multiplication let's move the macros to a global header file.
+Attempts to use static inlines instead of macros failed due
+to false positive triggering of BUILD_BUG_ON()s, especially with
+GCC < 6.0.
+
+Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
+Reviewed-by: Dinan Gunawardena <dinan.gunawardena@netronome.com>
+Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
+(cherry picked from commit 3e9b3112ec74f192eaab976c3889e34255cae940)
+---
+ include/linux/bitfield.h | 93 ++++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/bug.h      |  3 ++
+ 2 files changed, 96 insertions(+)
+ create mode 100644 include/linux/bitfield.h
+
+diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
+new file mode 100644
+index 000000000000..f6505d83069d
+--- /dev/null
++++ b/include/linux/bitfield.h
+@@ -0,0 +1,93 @@
++/*
++ * Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>
++ * Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2
++ * as published by the Free Software Foundation
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _LINUX_BITFIELD_H
++#define _LINUX_BITFIELD_H
++
++#include <linux/bug.h>
++
++/*
++ * Bitfield access macros
++ *
++ * FIELD_{GET,PREP} macros take as first parameter shifted mask
++ * from which they extract the base mask and shift amount.
++ * Mask must be a compilation time constant.
++ *
++ * Example:
++ *
++ *  #define REG_FIELD_A  GENMASK(6, 0)
++ *  #define REG_FIELD_B  BIT(7)
++ *  #define REG_FIELD_C  GENMASK(15, 8)
++ *  #define REG_FIELD_D  GENMASK(31, 16)
++ *
++ * Get:
++ *  a = FIELD_GET(REG_FIELD_A, reg);
++ *  b = FIELD_GET(REG_FIELD_B, reg);
++ *
++ * Set:
++ *  reg = FIELD_PREP(REG_FIELD_A, 1) |
++ *	  FIELD_PREP(REG_FIELD_B, 0) |
++ *	  FIELD_PREP(REG_FIELD_C, c) |
++ *	  FIELD_PREP(REG_FIELD_D, 0x40);
++ *
++ * Modify:
++ *  reg &= ~REG_FIELD_C;
++ *  reg |= FIELD_PREP(REG_FIELD_C, c);
++ */
++
++#define __bf_shf(x) (__builtin_ffsll(x) - 1)
++
++#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx)			\
++	({								\
++		BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),		\
++				 _pfx "mask is not constant");		\
++		BUILD_BUG_ON_MSG(!(_mask), _pfx "mask is zero");	\
++		BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
++				 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
++				 _pfx "value too large for the field"); \
++		BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull,		\
++				 _pfx "type of reg too small for mask"); \
++		__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +			\
++					      (1ULL << __bf_shf(_mask))); \
++	})
++
++/**
++ * FIELD_PREP() - prepare a bitfield element
++ * @_mask: shifted mask defining the field's length and position
++ * @_val:  value to put in the field
++ *
++ * FIELD_PREP() masks and shifts up the value.  The result should
++ * be combined with other fields of the bitfield using logical OR.
++ */
++#define FIELD_PREP(_mask, _val)						\
++	({								\
++		__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");	\
++		((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask);	\
++	})
++
++/**
++ * FIELD_GET() - extract a bitfield element
++ * @_mask: shifted mask defining the field's length and position
++ * @_reg:  32bit value of entire bitfield
++ *
++ * FIELD_GET() extracts the field specified by @_mask from the
++ * bitfield passed in as @_reg by masking and shifting it down.
++ */
++#define FIELD_GET(_mask, _reg)						\
++	({								\
++		__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: ");	\
++		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));	\
++	})
++
++#endif
+diff --git a/include/linux/bug.h b/include/linux/bug.h
+index 7f4818673c41..edd3d8d3cd90 100644
+--- a/include/linux/bug.h
++++ b/include/linux/bug.h
+@@ -13,6 +13,7 @@ enum bug_trap_type {
+ struct pt_regs;
+ 
+ #ifdef __CHECKER__
++#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
+ #define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
+ #define BUILD_BUG_ON_ZERO(e) (0)
+ #define BUILD_BUG_ON_NULL(e) ((void*)0)
+@@ -23,6 +24,8 @@ struct pt_regs;
+ #else /* __CHECKER__ */
+ 
+ /* Force a compilation error if a constant expression is not a power of 2 */
++#define __BUILD_BUG_ON_NOT_POWER_OF_2(n)	\
++	BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
+ #define BUILD_BUG_ON_NOT_POWER_OF_2(n)			\
+ 	BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
+ 
+
+From 3841d053b087e87d8d3d77738452c3b14d724049 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <jakub.kicinski@netronome.com>
+Date: Thu, 9 Feb 2017 09:17:27 -0800
+Subject: [PATCH] UPSTREAM: bitfield.h: add FIELD_FIT() helper
+
+Add a helper for checking at runtime that a value will fit inside
+a specified field/mask.
+
+Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+(cherry picked from commit 1697599ee301a52cded6499a09bd609f7f63fd06)
+---
+ include/linux/bitfield.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
+index f6505d83069d..8b9d6fff002d 100644
+--- a/include/linux/bitfield.h
++++ b/include/linux/bitfield.h
+@@ -62,6 +62,19 @@
+ 					      (1ULL << __bf_shf(_mask))); \
+ 	})
+ 
++/**
++ * FIELD_FIT() - check if value fits in the field
++ * @_mask: shifted mask defining the field's length and position
++ * @_val:  value to test against the field
++ *
++ * Return: true if @_val can fit inside @_mask, false if @_val is too big.
++ */
++#define FIELD_FIT(_mask, _val)						\
++	({								\
++		__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: ");	\
++		!((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \
++	})
++
+ /**
+  * FIELD_PREP() - prepare a bitfield element
+  * @_mask: shifted mask defining the field's length and position
+
+From b0dcc7c8cc60ef7877baf3639a46344d8b184fc7 Mon Sep 17 00:00:00 2001
+From: Laurent Defert <laurent.defert@smartjog.com>
+Date: Wed, 11 Oct 2017 08:46:52 +0200
+Subject: [PATCH] FROMLIST: compat_ioctl: add compat handler for
+ FE_SET_PROPERTY and FE_GET_PROPERTY
+
+https://patchwork.linuxtv.org/patch/8209/
+---
+ fs/compat_ioctl.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 138 insertions(+)
+
+diff --git a/fs/compat_ioctl.c b/fs/compat_ioctl.c
+index a52ca5cba015..438ce0c6851e 100644
+--- a/fs/compat_ioctl.c
++++ b/fs/compat_ioctl.c
+@@ -223,6 +223,140 @@ static int do_video_set_spu_palette(unsigned int fd, unsigned int cmd,
+ 	return err;
+ }
+ 
++struct compat_dtv_property {
++	__u32 cmd;
++	__u32 reserved[3];
++	union {
++		__u32 data;
++		struct {
++			__u8 data[32];
++			__u32 len;
++			__u32 reserved1[3];
++			compat_uptr_t reserved2;
++		} buffer;
++	} u;
++	int result;
++};
++
++struct compat_dtv_properties {
++	__u32 num;
++	compat_uptr_t props;
++};
++
++#define FE_SET_PROPERTY32    _IOW('o', 82, struct compat_dtv_properties)
++#define FE_GET_PROPERTY32    _IOR('o', 83, struct compat_dtv_properties)
++
++static int do_fe_set_property(unsigned int fd, unsigned int cmd,
++		struct compat_dtv_properties __user *dtv32)
++{
++	struct dtv_properties __user *dtv;
++	struct dtv_property __user *properties;
++	struct compat_dtv_property __user *properties32;
++	compat_uptr_t data;
++
++	int err;
++	int i;
++	__u32 num;
++
++	err = get_user(num, &dtv32->num);
++	err |= get_user(data, &dtv32->props);
++
++	if(err)
++		return -EFAULT;
++
++	dtv = compat_alloc_user_space(sizeof(struct dtv_properties) +
++			sizeof(struct dtv_property) * num);
++	properties = (struct dtv_property*)((char*)dtv +
++			sizeof(struct dtv_properties));
++
++	err = put_user(properties, &dtv->props);
++	err |= put_user(num, &dtv->num);
++
++	properties32 = compat_ptr(data);
++
++	if(err)
++		return -EFAULT;
++
++	for(i = 0; i < num; i++) {
++		compat_uptr_t reserved2;
++
++		err |= copy_in_user(&properties[i], &properties32[i],
++				(8 * sizeof(__u32)) + (32 * sizeof(__u8)));
++		err |= get_user(reserved2, &properties32[i].u.buffer.reserved2);
++		err |= put_user(compat_ptr(reserved2),
++				&properties[i].u.buffer.reserved2);
++	}
++
++	if(err)
++		return -EFAULT;
++
++	err = sys_ioctl(fd, FE_SET_PROPERTY, (unsigned long) dtv);
++
++	for(i = 0; i < num; i++) {
++		if(copy_in_user(&properties32[i].result, &properties[i].result,
++					sizeof(int)))
++			return -EFAULT;
++	}
++
++	return err;
++}
++
++static int do_fe_get_property(unsigned int fd, unsigned int cmd,
++		struct compat_dtv_properties __user *dtv32)
++{
++	struct dtv_properties __user *dtv;
++	struct dtv_property __user *properties;
++	struct compat_dtv_property __user *properties32;
++	compat_uptr_t data;
++
++	int err;
++	int i;
++	__u32 num;
++
++	err = get_user(num, &dtv32->num);
++	err |= get_user(data, &dtv32->props);
++
++	if(err)
++		return -EFAULT;
++
++	dtv = compat_alloc_user_space(sizeof(struct dtv_properties) +
++			sizeof(struct dtv_property) * num);
++	properties = (struct dtv_property*)((char*)dtv +
++			sizeof(struct dtv_properties));
++
++	err = put_user(properties, &dtv->props);
++	err |= put_user(num, &dtv->num);
++
++	properties32 = compat_ptr(data);
++
++	if(err)
++		return -EFAULT;
++
++	for(i = 0; i < num; i++) {
++		compat_uptr_t reserved2;
++
++		err |= copy_in_user(&properties[i], &properties32[i],
++				(8 * sizeof(__u32)) + (32 * sizeof(__u8)));
++		err |= get_user(reserved2, &properties32[i].u.buffer.reserved2);
++		err |= put_user(compat_ptr(reserved2),
++				&properties[i].u.buffer.reserved2);
++	}
++
++	if(err)
++		return -EFAULT;
++
++	err = sys_ioctl(fd, FE_GET_PROPERTY, (unsigned long) dtv);
++
++	for(i = 0; i < num; i++) {
++
++		if(copy_in_user(&properties32[i], &properties[i],
++					sizeof(properties32[i])))
++			return -EFAULT;
++	}
++
++	return err;
++}
++
+ #ifdef CONFIG_BLOCK
+ typedef struct sg_io_hdr32 {
+ 	compat_int_t interface_id;	/* [i] 'S' for SCSI generic (required) */
+@@ -1483,6 +1617,10 @@ static long do_ioctl_trans(int fd, unsigned int cmd,
+ 		return do_video_stillpicture(fd, cmd, argp);
+ 	case VIDEO_SET_SPU_PALETTE:
+ 		return do_video_set_spu_palette(fd, cmd, argp);
++	case FE_SET_PROPERTY32:
++		return do_fe_set_property(fd, cmd, argp);
++	case FE_GET_PROPERTY32:
++		return do_fe_get_property(fd, cmd, argp);
+ 	}
+ 
+ 	/*

patch/kernel/rk322x-legacy/01-linux-1000-vcodec.patch

@@ -0,0 +1,945 @@
+From e222e9913d3c70967bae92f1aed46de726974dc7 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 5 Jul 2018 00:14:14 +0200
+Subject: [PATCH] Revert "drm/drm-prime: cache dma_buf import context"
+
+This reverts commit 5a90381e5acc2cf32be03099a14d05d4362b3348.
+---
+ drivers/gpu/drm/drm_prime.c                 | 46 ++---------------------------
+ drivers/gpu/drm/rockchip/rockchip_drm_gem.c |  1 +
+ 2 files changed, 3 insertions(+), 44 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index 6f207d5946dc..6b7417a194a3 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -71,11 +71,6 @@ struct drm_prime_attachment {
+ 	enum dma_data_direction dir;
+ };
+ 
+-struct drm_prime_callback_data {
+-	struct drm_gem_object *obj;
+-	struct sg_table *sgt;
+-};
+-
+ static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
+ 				    struct dma_buf *dma_buf, uint32_t handle)
+ {
+@@ -524,23 +519,6 @@ out_unlock:
+ }
+ EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
+ 
+-static void drm_gem_prime_dmabuf_release_callback(void *data)
+-{
+-	struct drm_prime_callback_data *cb_data = data;
+-
+-	if (cb_data && cb_data->obj && cb_data->obj->import_attach) {
+-		struct dma_buf_attachment *attach = cb_data->obj->import_attach;
+-		struct sg_table *sgt = cb_data->sgt;
+-
+-		if (sgt)
+-			dma_buf_unmap_attachment(attach, sgt,
+-						 DMA_BIDIRECTIONAL);
+-		dma_buf_detach(attach->dmabuf, attach);
+-		drm_gem_object_unreference_unlocked(cb_data->obj);
+-		kfree(cb_data);
+-	}
+-}
+-
+ /**
+  * drm_gem_prime_import - helper library implementation of the import callback
+  * @dev: drm_device to import into
+@@ -555,7 +533,6 @@ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
+ 	struct dma_buf_attachment *attach;
+ 	struct sg_table *sgt;
+ 	struct drm_gem_object *obj;
+-	struct drm_prime_callback_data *cb_data;
+ 	int ret;
+ 
+ 	if (dma_buf->ops == &drm_gem_prime_dmabuf_ops) {
+@@ -570,13 +547,6 @@ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
+ 		}
+ 	}
+ 
+-	cb_data = dma_buf_get_release_callback_data(dma_buf,
+-					drm_gem_prime_dmabuf_release_callback);
+-	if (cb_data && cb_data->obj && cb_data->obj->dev == dev) {
+-		drm_gem_object_reference(cb_data->obj);
+-		return cb_data->obj;
+-	}
+-
+ 	if (!dev->driver->gem_prime_import_sg_table)
+ 		return ERR_PTR(-EINVAL);
+ 
+@@ -585,16 +555,11 @@ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
+ 		return ERR_CAST(attach);
+ 
+ 	get_dma_buf(dma_buf);
+-	cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
+-	if (!cb_data) {
+-		ret = -ENOMEM;
+-		goto fail_detach;
+-	}
+ 
+ 	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
+ 	if (IS_ERR(sgt)) {
+ 		ret = PTR_ERR(sgt);
+-		goto fail_free;
++		goto fail_detach;
+ 	}
+ 
+ 	obj = dev->driver->gem_prime_import_sg_table(dev, attach, sgt);
+@@ -602,20 +567,13 @@ struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
+ 		ret = PTR_ERR(obj);
+ 		goto fail_unmap;
+ 	}
++
+ 	obj->import_attach = attach;
+-	cb_data->obj = obj;
+-	cb_data->sgt = sgt;
+-	dma_buf_set_release_callback(dma_buf,
+-			drm_gem_prime_dmabuf_release_callback, cb_data);
+-	dma_buf_put(dma_buf);
+-	drm_gem_object_reference(obj);
+ 
+ 	return obj;
+ 
+ fail_unmap:
+ 	dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
+-fail_free:
+-	kfree(cb_data);
+ fail_detach:
+ 	dma_buf_detach(dma_buf, attach);
+ 	dma_buf_put(dma_buf);
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+index 273a52b5eb66..85bbd19c87b0 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+@@ -649,6 +649,7 @@ void rockchip_gem_free_object(struct drm_gem_object *obj)
+ 			dma_unmap_sg(drm->dev, rk_obj->sgt->sgl,
+ 				     rk_obj->sgt->nents, DMA_BIDIRECTIONAL);
+ 		}
++		drm_prime_gem_destroy(obj, rk_obj->sgt);
+ 	} else {
+ 		rockchip_gem_free_buf(rk_obj);
+ 	}
+
+From 0868438e92b0e9a44d6c6e711ef3be0a429ab4af Mon Sep 17 00:00:00 2001
+From: Rob Clark <robdclark@gmail.com>
+Date: Thu, 9 Jun 2016 15:29:19 -0400
+Subject: [PATCH] UPSTREAM: drm/prime: fix error path deadlock fail
+
+There were a couple messed up things about this fail path.
+(1) it would drop object_name_lock twice
+(2) drm_gem_handle_delete() (in drm_gem_remove_prime_handles())
+    needs to grab prime_lock
+
+Reported-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Rob Clark <robdclark@gmail.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/1465500559-17873-1-git-send-email-robdclark@gmail.com
+(cherry picked from commit bd6e2732f0e2894ce792f344c41fc32591436fe3)
+---
+ drivers/gpu/drm/drm_prime.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index 6b7417a194a3..d8d85286764d 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -628,7 +628,7 @@ int drm_gem_prime_fd_to_handle(struct drm_device *dev,
+ 		get_dma_buf(dma_buf);
+ 	}
+ 
+-	/* drm_gem_handle_create_tail unlocks dev->object_name_lock. */
++	/* _handle_create_tail unconditionally unlocks dev->object_name_lock. */
+ 	ret = drm_gem_handle_create_tail(file_priv, obj, handle);
+ 	drm_gem_object_unreference_unlocked(obj);
+ 	if (ret)
+@@ -636,11 +636,10 @@ int drm_gem_prime_fd_to_handle(struct drm_device *dev,
+ 
+ 	ret = drm_prime_add_buf_handle(&file_priv->prime,
+ 			dma_buf, *handle);
++	mutex_unlock(&file_priv->prime.lock);
+ 	if (ret)
+ 		goto fail;
+ 
+-	mutex_unlock(&file_priv->prime.lock);
+-
+ 	dma_buf_put(dma_buf);
+ 
+ 	return 0;
+@@ -650,11 +649,14 @@ fail:
+ 	 * to detach.. which seems ok..
+ 	 */
+ 	drm_gem_handle_delete(file_priv, *handle);
++	dma_buf_put(dma_buf);
++	return ret;
++
+ out_unlock:
+ 	mutex_unlock(&dev->object_name_lock);
+ out_put:
+-	dma_buf_put(dma_buf);
+ 	mutex_unlock(&file_priv->prime.lock);
++	dma_buf_put(dma_buf);
+ 	return ret;
+ }
+ EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);
+
+From 8e4ac090d0a814f73d719887f96f7dc44112e03e Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Mon, 26 Sep 2016 21:44:14 +0100
+Subject: [PATCH] UPSTREAM: drm: Convert prime dma-buf <-> handle to rbtree
+
+Currently we use a linear walk to lookup a handle and return a dma-buf,
+and vice versa. A long overdue TODO task is to convert that to a
+hashtable. Since the initial implementation of dma-buf/prime, we now
+have resizeable hashtables we can use (and now a future task is to RCU
+enable the lookup!). However, this patch opts to use an rbtree instead
+to provide O(lgN) lookups (and insertion, deletion). rbtrees were chosen
+over using the RCU backed resizable hashtable to firstly avoid the
+reallocations (rbtrees can be embedded entirely within the parent
+struct) and to favour simpler code with predictable worst case
+behaviour. In simple testing, the difference between using the constant
+lookup and insertion of the rhashtable and the rbtree was less than 10%
+of the wall time (igt/benchmarks/prime_lookup) - both are dramatic
+improvements over the existing linear lists.
+
+v2: Favour rbtree over rhashtable
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94631
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Sean Paul <seanpaul@chromium.org>
+Cc: David Herrmann <dh.herrmann@gmail.com>
+Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
+Reviewed-by: Sean Paul <seanpaul@chromium.org>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/20160926204414.23222-1-chris@chris-wilson.co.uk
+(cherry picked from commit 077675c1e8a193a6355d4a7c8c7bf63be310b472)
+---
+ drivers/gpu/drm/drm_prime.c | 85 +++++++++++++++++++++++++++++++++++++++------
+ include/drm/drmP.h          |  5 +--
+ 2 files changed, 77 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index d8d85286764d..4c49e736bc9c 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -28,6 +28,7 @@
+ 
+ #include <linux/export.h>
+ #include <linux/dma-buf.h>
++#include <linux/rbtree.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_gem.h>
+ 
+@@ -61,9 +62,11 @@
+  */
+ 
+ struct drm_prime_member {
+-	struct list_head entry;
+ 	struct dma_buf *dma_buf;
+ 	uint32_t handle;
++
++	struct rb_node dmabuf_rb;
++	struct rb_node handle_rb;
+ };
+ 
+ struct drm_prime_attachment {
+@@ -75,6 +78,7 @@ static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
+ 				    struct dma_buf *dma_buf, uint32_t handle)
+ {
+ 	struct drm_prime_member *member;
++	struct rb_node **p, *rb;
+ 
+ 	member = kmalloc(sizeof(*member), GFP_KERNEL);
+ 	if (!member)
+@@ -83,18 +87,56 @@ static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv,
+ 	get_dma_buf(dma_buf);
+ 	member->dma_buf = dma_buf;
+ 	member->handle = handle;
+-	list_add(&member->entry, &prime_fpriv->head);
++
++	rb = NULL;
++	p = &prime_fpriv->dmabufs.rb_node;
++	while (*p) {
++		struct drm_prime_member *pos;
++
++		rb = *p;
++		pos = rb_entry(rb, struct drm_prime_member, dmabuf_rb);
++		if (dma_buf > pos->dma_buf)
++			p = &rb->rb_right;
++		else
++			p = &rb->rb_left;
++	}
++	rb_link_node(&member->dmabuf_rb, rb, p);
++	rb_insert_color(&member->dmabuf_rb, &prime_fpriv->dmabufs);
++
++	rb = NULL;
++	p = &prime_fpriv->handles.rb_node;
++	while (*p) {
++		struct drm_prime_member *pos;
++
++		rb = *p;
++		pos = rb_entry(rb, struct drm_prime_member, handle_rb);
++		if (handle > pos->handle)
++			p = &rb->rb_right;
++		else
++			p = &rb->rb_left;
++	}
++	rb_link_node(&member->handle_rb, rb, p);
++	rb_insert_color(&member->handle_rb, &prime_fpriv->handles);
++
+ 	return 0;
+ }
+ 
+ static struct dma_buf *drm_prime_lookup_buf_by_handle(struct drm_prime_file_private *prime_fpriv,
+ 						      uint32_t handle)
+ {
+-	struct drm_prime_member *member;
++	struct rb_node *rb;
++
++	rb = prime_fpriv->handles.rb_node;
++	while (rb) {
++		struct drm_prime_member *member;
+ 
+-	list_for_each_entry(member, &prime_fpriv->head, entry) {
++		member = rb_entry(rb, struct drm_prime_member, handle_rb);
+ 		if (member->handle == handle)
+ 			return member->dma_buf;
++		else if (member->handle < handle)
++			rb = rb->rb_right;
++		else
++			rb = rb->rb_left;
+ 	}
+ 
+ 	return NULL;
+@@ -104,14 +146,23 @@ static int drm_prime_lookup_buf_handle(struct drm_prime_file_private *prime_fpri
+ 				       struct dma_buf *dma_buf,
+ 				       uint32_t *handle)
+ {
+-	struct drm_prime_member *member;
++	struct rb_node *rb;
++
++	rb = prime_fpriv->dmabufs.rb_node;
++	while (rb) {
++		struct drm_prime_member *member;
+ 
+-	list_for_each_entry(member, &prime_fpriv->head, entry) {
++		member = rb_entry(rb, struct drm_prime_member, dmabuf_rb);
+ 		if (member->dma_buf == dma_buf) {
+ 			*handle = member->handle;
+ 			return 0;
++		} else if (member->dma_buf < dma_buf) {
++			rb = rb->rb_right;
++		} else {
++			rb = rb->rb_left;
+ 		}
+ 	}
++
+ 	return -ENOENT;
+ }
+ 
+@@ -166,13 +217,24 @@ static void drm_gem_map_detach(struct dma_buf *dma_buf,
+ void drm_prime_remove_buf_handle_locked(struct drm_prime_file_private *prime_fpriv,
+ 					struct dma_buf *dma_buf)
+ {
+-	struct drm_prime_member *member, *safe;
++	struct rb_node *rb;
+ 
+-	list_for_each_entry_safe(member, safe, &prime_fpriv->head, entry) {
++	rb = prime_fpriv->dmabufs.rb_node;
++	while (rb) {
++		struct drm_prime_member *member;
++
++		member = rb_entry(rb, struct drm_prime_member, dmabuf_rb);
+ 		if (member->dma_buf == dma_buf) {
++			rb_erase(&member->handle_rb, &prime_fpriv->handles);
++			rb_erase(&member->dmabuf_rb, &prime_fpriv->dmabufs);
++
+ 			dma_buf_put(dma_buf);
+-			list_del(&member->entry);
+ 			kfree(member);
++			return;
++		} else if (member->dma_buf < dma_buf) {
++			rb = rb->rb_right;
++		} else {
++			rb = rb->rb_left;
+ 		}
+ 	}
+ }
+@@ -794,12 +856,13 @@ EXPORT_SYMBOL(drm_prime_gem_destroy);
+ 
+ void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv)
+ {
+-	INIT_LIST_HEAD(&prime_fpriv->head);
+ 	mutex_init(&prime_fpriv->lock);
++	prime_fpriv->dmabufs = RB_ROOT;
++	prime_fpriv->handles = RB_ROOT;
+ }
+ 
+ void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv)
+ {
+ 	/* by now drm_gem_release should've made sure the list is empty */
+-	WARN_ON(!list_empty(&prime_fpriv->head));
++	WARN_ON(!RB_EMPTY_ROOT(&prime_fpriv->dmabufs));
+ }
+diff --git a/include/drm/drmP.h b/include/drm/drmP.h
+index 04edcd32b409..93da65df2e7e 100644
+--- a/include/drm/drmP.h
++++ b/include/drm/drmP.h
+@@ -51,6 +51,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/poll.h>
+ #include <linux/ratelimit.h>
++#include <linux/rbtree.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
+ #include <linux/types.h>
+@@ -365,10 +366,10 @@ struct drm_pending_event {
+ 	void (*destroy)(struct drm_pending_event *event);
+ };
+ 
+-/* initial implementaton using a linked list - todo hashtab */
+ struct drm_prime_file_private {
+-	struct list_head head;
+ 	struct mutex lock;
++	struct rb_root dmabufs;
++	struct rb_root handles;
+ };
+ 
+ /** File private data */
+
+From fcb8af30f524cd437434ec6ddea0231cc37529bc Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed, 5 Oct 2016 13:21:44 +0100
+Subject: [PATCH] UPSTREAM: drm/prime: Take a ref on the drm_dev when exporting
+ a dma_buf
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+dma_buf may live a long time, longer than the last direct user of the
+driver. We already hold a reference to the owner module (that prevents
+the object code from disappearing), but there is no reference to the
+drm_dev - so the pointers to the driver backend themselves may vanish.
+
+v2: Resist temptation to fix the bug in armada_gem.c not setting the
+correct flags on the exported dma-buf (it should pass the flags through
+and not be arbitrarily setting O_RDWR).
+
+Use a common wrapper for exporting the dmabuf and acquiring the
+reference to the drm_device.
+
+Testcase: igt/vgem_basic/unload
+Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Petri Latvala <petri.latvala@intel.com>
+Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
+Cc: stable@vger.kernel.org
+Tested-by: Petri Latvala <petri.latvala@intel.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/20161005122145.1507-2-chris@chris-wilson.co.uk
+(cherry picked from commit a4fce9cb782ad340ee5576a38e934e5e75832dc6)
+---
+ drivers/gpu/drm/armada/armada_gem.c    |  2 +-
+ drivers/gpu/drm/drm_prime.c            | 30 +++++++++++++++++++++++++++++-
+ drivers/gpu/drm/i915/i915_gem_dmabuf.c |  2 +-
+ drivers/gpu/drm/tegra/gem.c            |  2 +-
+ drivers/gpu/drm/udl/udl_dmabuf.c       |  2 +-
+ include/drm/drmP.h                     |  4 ++++
+ 6 files changed, 37 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/armada/armada_gem.c b/drivers/gpu/drm/armada/armada_gem.c
+index 60a688ef81c7..cd5bb991f49a 100644
+--- a/drivers/gpu/drm/armada/armada_gem.c
++++ b/drivers/gpu/drm/armada/armada_gem.c
+@@ -546,7 +546,7 @@ armada_gem_prime_export(struct drm_device *dev, struct drm_gem_object *obj,
+ 	exp_info.flags = O_RDWR;
+ 	exp_info.priv = obj;
+ 
+-	return dma_buf_export(&exp_info);
++	return drm_gem_dmabuf_export(dev, &exp_info);
+ }
+ 
+ struct drm_gem_object *
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index 4c49e736bc9c..94b4872255c8 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -283,19 +283,47 @@ static void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
+ 	/* nothing to be done here */
+ }
+ 
++/**
++ * drm_gem_dmabuf_export - dma_buf export implementation for GEM
++ * @dma_buf: buffer to be exported
++ *
++ * This wraps dma_buf_export() for use by generic GEM drivers that are using
++ * drm_gem_dmabuf_release(). In addition to calling dma_buf_export(), we take
++ * a reference to the drm_device which is released by drm_gem_dmabuf_release().
++ *
++ * Returns the new dmabuf.
++ */
++struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
++				      struct dma_buf_export_info *exp_info)
++{
++	struct dma_buf *dma_buf;
++
++	dma_buf = dma_buf_export(exp_info);
++	if (!IS_ERR(dma_buf))
++		drm_dev_ref(dev);
++
++	return dma_buf;
++}
++EXPORT_SYMBOL(drm_gem_dmabuf_export);
++
+ /**
+  * drm_gem_dmabuf_release - dma_buf release implementation for GEM
+  * @dma_buf: buffer to be released
+  *
+  * Generic release function for dma_bufs exported as PRIME buffers. GEM drivers
+  * must use this in their dma_buf ops structure as the release callback.
++ * drm_gem_dmabuf_release() should be used in conjunction with
++ * drm_gem_dmabuf_export().
+  */
+ void drm_gem_dmabuf_release(struct dma_buf *dma_buf)
+ {
+ 	struct drm_gem_object *obj = dma_buf->priv;
++	struct drm_device *dev = obj->dev;
+ 
+ 	/* drop the reference on the export fd holds */
+ 	drm_gem_object_unreference_unlocked(obj);
++
++	drm_dev_unref(dev);
+ }
+ EXPORT_SYMBOL(drm_gem_dmabuf_release);
+ 
+@@ -444,7 +472,7 @@ struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
+ 	if (dev->driver->gem_prime_res_obj)
+ 		exp_info.resv = dev->driver->gem_prime_res_obj(obj);
+ 
+-	return dma_buf_export(&exp_info);
++	return drm_gem_dmabuf_export(dev, &exp_info);
+ }
+ EXPORT_SYMBOL(drm_gem_prime_export);
+ 
+diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+index e9c2bfd85b52..d4a021629bd6 100644
+--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
++++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+@@ -244,7 +244,7 @@ struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
+ 			return ERR_PTR(ret);
+ 	}
+ 
+-	return dma_buf_export(&exp_info);
++	return drm_gem_dmabuf_export(dev, &exp_info);
+ }
+ 
+ static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
+diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
+index 01e16e146bfe..da06f1c1ee0f 100644
+--- a/drivers/gpu/drm/tegra/gem.c
++++ b/drivers/gpu/drm/tegra/gem.c
+@@ -625,7 +625,7 @@ struct dma_buf *tegra_gem_prime_export(struct drm_device *drm,
+ 	exp_info.flags = flags;
+ 	exp_info.priv = gem;
+ 
+-	return dma_buf_export(&exp_info);
++	return drm_gem_dmabuf_export(drm, &exp_info);
+ }
+ 
+ struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm,
+diff --git a/drivers/gpu/drm/udl/udl_dmabuf.c b/drivers/gpu/drm/udl/udl_dmabuf.c
+index e2243edd1ce3..ac90ffdb5912 100644
+--- a/drivers/gpu/drm/udl/udl_dmabuf.c
++++ b/drivers/gpu/drm/udl/udl_dmabuf.c
+@@ -209,7 +209,7 @@ struct dma_buf *udl_gem_prime_export(struct drm_device *dev,
+ 	exp_info.flags = flags;
+ 	exp_info.priv = obj;
+ 
+-	return dma_buf_export(&exp_info);
++	return drm_gem_dmabuf_export(dev, &exp_info);
+ }
+ 
+ static int udl_prime_create(struct drm_device *dev,
+diff --git a/include/drm/drmP.h b/include/drm/drmP.h
+index 93da65df2e7e..4aba6478d718 100644
+--- a/include/drm/drmP.h
++++ b/include/drm/drmP.h
+@@ -1124,6 +1124,8 @@ static inline int drm_debugfs_remove_files(const struct drm_info_list *files,
+ }
+ #endif
+ 
++struct dma_buf_export_info;
++
+ extern struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
+ 					    struct drm_gem_object *obj,
+ 					    int flags);
+@@ -1134,6 +1136,8 @@ extern struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
+ 		struct dma_buf *dma_buf);
+ extern int drm_gem_prime_fd_to_handle(struct drm_device *dev,
+ 		struct drm_file *file_priv, int prime_fd, uint32_t *handle);
++struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
++				      struct dma_buf_export_info *exp_info);
+ extern void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
+ 
+ extern int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
+
+From 2c0a8737dd35ba259d3bbbf1b956fb43da32f117 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed, 7 Dec 2016 21:45:27 +0000
+Subject: [PATCH] UPSTREAM: drm: Take ownership of the dmabuf->obj when
+ exporting
+
+Currently the reference for the dmabuf->obj is incremented for the
+dmabuf in drm_gem_prime_handle_to_fd() (at the high level userspace
+interface), but is released in drm_gem_dmabuf_release() (the lowlevel
+handler). Improve the symmetry of the dmabuf->obj ownership by acquiring
+the reference in drm_gem_dmabuf_export(). This makes it easier to use
+the prime functions directly.
+
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+[danvet: Update kerneldoc.]
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: http://patchwork.freedesktop.org/patch/msgid/20161207214527.22533-1-chris@chris-wilson.co.uk
+(cherry picked from commit 72a93e8dd52c9feea42f1258d555e6070680a347)
+---
+ drivers/gpu/drm/drm_prime.c | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index 94b4872255c8..dbd34fa7f71c 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -289,7 +289,8 @@ static void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
+  *
+  * This wraps dma_buf_export() for use by generic GEM drivers that are using
+  * drm_gem_dmabuf_release(). In addition to calling dma_buf_export(), we take
+- * a reference to the drm_device which is released by drm_gem_dmabuf_release().
++ * a reference to the &drm_device and the exported &drm_gem_object (stored in
++ * exp_info->priv) which is released by drm_gem_dmabuf_release().
+  *
+  * Returns the new dmabuf.
+  */
+@@ -299,8 +300,11 @@ struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
+ 	struct dma_buf *dma_buf;
+ 
+ 	dma_buf = dma_buf_export(exp_info);
+-	if (!IS_ERR(dma_buf))
+-		drm_dev_ref(dev);
++	if (IS_ERR(dma_buf))
++		return dma_buf;
++
++	drm_dev_ref(dev);
++	drm_gem_object_reference(exp_info->priv);
+ 
+ 	return dma_buf;
+ }
+@@ -503,8 +507,6 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev,
+ 	 */
+ 	obj->dma_buf = dmabuf;
+ 	get_dma_buf(obj->dma_buf);
+-	/* Grab a new ref since the callers is now used by the dma-buf */
+-	drm_gem_object_reference(obj);
+ 
+ 	return dmabuf;
+ }
+
+From 595e921b1e908458bd1ee022c9a7ee08cf203ad9 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Thu, 30 Nov 2017 18:34:28 +0100
+Subject: [PATCH] UPSTREAM: drm/prime: skip CPU sync in map/unmap dma_buf
+
+Dma-bufs should already be device coherent, as they are only pulled in the
+CPU domain via the begin/end cpu_access calls. As we cache the mapping set
+up by dma_map_sg a CPU sync at this point will not actually guarantee proper
+coherency on non-coherent architectures, so we can as well stop pretending.
+
+This is an important performance fix for architectures which need explicit
+cache synchronization and userspace doing lots of dma-buf imports.
+Improves Weston on Etnaviv performance 5x, where before this patch > 90%
+of Weston CPU time was spent synchronizing caches for buffers which are
+already device coherent.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Link: https://patchwork.freedesktop.org/patch/msgid/20171130173428.8666-1-l.stach@pengutronix.de
+(cherry picked from commit ca0e68e21aae10220eff71a297e7d794425add77)
+---
+ drivers/gpu/drm/drm_prime.c | 11 ++++++++---
+ 1 file changed, 8 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index dbd34fa7f71c..133362279591 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -203,9 +203,12 @@ static void drm_gem_map_detach(struct dma_buf *dma_buf,
+ 
+ 	sgt = prime_attach->sgt;
+ 	if (sgt) {
++		DEFINE_DMA_ATTRS(attrs);
++		dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
+ 		if (prime_attach->dir != DMA_NONE)
+-			dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents,
+-					prime_attach->dir);
++			dma_unmap_sg_attrs(attach->dev, sgt->sgl, sgt->nents,
++					   prime_attach->dir,
++					   &attrs);
+ 		sg_free_table(sgt);
+ 	}
+ 
+@@ -263,7 +266,9 @@ static struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment *attach,
+ 	sgt = obj->dev->driver->gem_prime_get_sg_table(obj);
+ 
+ 	if (!IS_ERR(sgt)) {
+-		if (!dma_map_sg(attach->dev, sgt->sgl, sgt->nents, dir)) {
++		DEFINE_DMA_ATTRS(attrs);
++		dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
++		if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir, &attrs)) {
+ 			sg_free_table(sgt);
+ 			kfree(sgt);
+ 			sgt = ERR_PTR(-ENOMEM);
+
+From d314fd1a48e930d034eccd49342a23340c3f1c27 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com>
+Date: Tue, 27 Feb 2018 12:49:56 +0100
+Subject: [PATCH] UPSTREAM: drm/prime: fix potential race in drm_gem_map_detach
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unpin the GEM object only after freeing the sg table.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Acked-by: Roger He <Hongbo.He@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180227115000.4105-1-christian.koenig@amd.com
+(cherry picked from commit 681066ec1d41e4b299146bada52cef846b323c04)
+---
+ drivers/gpu/drm/drm_prime.c | 36 ++++++++++++++++++------------------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index 133362279591..95ecc69d03a0 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -193,28 +193,28 @@ static void drm_gem_map_detach(struct dma_buf *dma_buf,
+ 	struct drm_prime_attachment *prime_attach = attach->priv;
+ 	struct drm_gem_object *obj = dma_buf->priv;
+ 	struct drm_device *dev = obj->dev;
+-	struct sg_table *sgt;
+-
+-	if (dev->driver->gem_prime_unpin)
+-		dev->driver->gem_prime_unpin(obj);
+ 
+-	if (!prime_attach)
+-		return;
++	if (prime_attach) {
++		struct sg_table *sgt = prime_attach->sgt;
++
++		if (sgt) {
++			DEFINE_DMA_ATTRS(attrs);
++			dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
++			if (prime_attach->dir != DMA_NONE)
++				dma_unmap_sg_attrs(attach->dev, sgt->sgl,
++						   sgt->nents,
++						   prime_attach->dir,
++						   &attrs);
++			sg_free_table(sgt);
++		}
+ 
+-	sgt = prime_attach->sgt;
+-	if (sgt) {
+-		DEFINE_DMA_ATTRS(attrs);
+-		dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &attrs);
+-		if (prime_attach->dir != DMA_NONE)
+-			dma_unmap_sg_attrs(attach->dev, sgt->sgl, sgt->nents,
+-					   prime_attach->dir,
+-					   &attrs);
+-		sg_free_table(sgt);
++		kfree(sgt);
++		kfree(prime_attach);
++		attach->priv = NULL;
+ 	}
+ 
+-	kfree(sgt);
+-	kfree(prime_attach);
+-	attach->priv = NULL;
++	if (dev->driver->gem_prime_unpin)
++		dev->driver->gem_prime_unpin(obj);
+ }
+ 
+ void drm_prime_remove_buf_handle_locked(struct drm_prime_file_private *prime_fpriv,
+
+From c74449bbd7e3ee3f3195ac9da48271c83c56f101 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com>
+Date: Tue, 27 Feb 2018 12:49:57 +0100
+Subject: [PATCH] UPSTREAM: drm/prime: make the pages array optional for
+ drm_prime_sg_to_page_addr_arrays
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Most of the time we only need the dma addresses.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Roger He <Hongbo.He@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20180227115000.4105-2-christian.koenig@amd.com
+Link: https://patchwork.freedesktop.org/patch/msgid/20180227115000.4105-3-christian.koenig@amd.com
+Link: https://patchwork.freedesktop.org/patch/msgid/20180227115000.4105-4-christian.koenig@amd.com
+Link: https://patchwork.freedesktop.org/patch/msgid/20180227115000.4105-5-christian.koenig@amd.com
+Link: https://patchwork.freedesktop.org/patch/msgid/BN6PR12MB18262C0DE9B5F07B9A42EAE7F2C60@BN6PR12MB1826.namprd12.prod.outlook.com
+(cherry picked from commit 186ca446aea19e49d2e1433dd170c6e1c211a52a)
+---
+ drivers/gpu/drm/drm_prime.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
+index 95ecc69d03a0..7ea65c4105c1 100644
+--- a/drivers/gpu/drm/drm_prime.c
++++ b/drivers/gpu/drm/drm_prime.c
+@@ -827,40 +827,40 @@ EXPORT_SYMBOL(drm_prime_pages_to_sg);
+ /**
+  * drm_prime_sg_to_page_addr_arrays - convert an sg table into a page array
+  * @sgt: scatter-gather table to convert
+- * @pages: array of page pointers to store the page array in
++ * @pages: optional array of page pointers to store the page array in
+  * @addrs: optional array to store the dma bus address of each page
+- * @max_pages: size of both the passed-in arrays
++ * @max_entries: size of both the passed-in arrays
+  *
+  * Exports an sg table into an array of pages and addresses. This is currently
+  * required by the TTM driver in order to do correct fault handling.
+  */
+ int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
+-				     dma_addr_t *addrs, int max_pages)
++				     dma_addr_t *addrs, int max_entries)
+ {
+ 	unsigned count;
+ 	struct scatterlist *sg;
+ 	struct page *page;
+-	u32 len;
+-	int pg_index;
++	u32 len, index;
+ 	dma_addr_t addr;
+ 
+-	pg_index = 0;
++	index = 0;
+ 	for_each_sg(sgt->sgl, sg, sgt->nents, count) {
+ 		len = sg->length;
+ 		page = sg_page(sg);
+ 		addr = sg_dma_address(sg);
+ 
+ 		while (len > 0) {
+-			if (WARN_ON(pg_index >= max_pages))
++			if (WARN_ON(index >= max_entries))
+ 				return -1;
+-			pages[pg_index] = page;
++			if (pages)
++				pages[index] = page;
+ 			if (addrs)
+-				addrs[pg_index] = addr;
++				addrs[index] = addr;
+ 
+ 			page++;
+ 			addr += PAGE_SIZE;
+ 			len -= PAGE_SIZE;
+-			pg_index++;
++			index++;
+ 		}
+ 	}
+ 	return 0;
+
+From 2fc969d64eb928db78c9fd99fb68d9d2442a8919 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Sat, 19 Aug 2017 13:05:58 +0100
+Subject: [PATCH] UPSTREAM: drm: Release driver tracking before making the
+ object available again
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is the same bug as we fixed in commit f6cd7daecff5 ("drm: Release
+driver references to handle before making it available again"), but now
+the exposure is via the PRIME lookup tables. If we remove the
+object/handle from the PRIME lut, then a new request for the same
+object/fd will generate a new handle, thus for a short window that
+object is known to userspace by two different handles. Fix this by
+releasing the driver tracking before PRIME.
+
+Fixes: 0ff926c7d4f0 ("drm/prime: add exported buffers to current fprivs
+imported buffer list (v2)")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: David Airlie <airlied@linux.ie>
+Cc: Daniel Vetter <daniel.vetter@intel.com>
+Cc: Rob Clark <robdclark@gmail.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Cc: Thierry Reding <treding@nvidia.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20170819120558.6465-1-chris@chris-wilson.co.uk
+(cherry picked from commit d0a133f7f5bc3583e460ba6bb54474a50ada5201)
+---
+ drivers/gpu/drm/drm_gem.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
+index d7f39a03c2c9..966ea63581b1 100644
+--- a/drivers/gpu/drm/drm_gem.c
++++ b/drivers/gpu/drm/drm_gem.c
+@@ -255,13 +255,13 @@ drm_gem_object_release_handle(int id, void *ptr, void *data)
+ 	struct drm_gem_object *obj = ptr;
+ 	struct drm_device *dev = obj->dev;
+ 
++	if (dev->driver->gem_close_object)
++		dev->driver->gem_close_object(obj, file_priv);
++
+ 	if (drm_core_check_feature(dev, DRIVER_PRIME))
+ 		drm_gem_remove_prime_handles(obj, file_priv);
+ 	drm_vma_node_revoke(&obj->vma_node, file_priv->filp);
+ 
+-	if (dev->driver->gem_close_object)
+-		dev->driver->gem_close_object(obj, file_priv);
+-
+ 	drm_gem_object_handle_unreference_unlocked(obj);
+ 
+ 	return 0;
+
+From 1d9b65acb4e776f43408afed2b0fd7b86fdb95ce Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 17 Feb 2018 05:30:36 +0100
+Subject: [PATCH] vcodec: skip reduce freq
+
+---
+ drivers/video/rockchip/vcodec/vcodec_service.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/video/rockchip/vcodec/vcodec_service.c b/drivers/video/rockchip/vcodec/vcodec_service.c
+index c4ee73be92d3..9d5ee5c8b1f9 100644
+--- a/drivers/video/rockchip/vcodec/vcodec_service.c
++++ b/drivers/video/rockchip/vcodec/vcodec_service.c
+@@ -1630,9 +1630,6 @@ static void try_set_reg(struct vpu_subdev_data *data)
+ 			reg_from_wait_to_run(pservice, reg);
+ 			reg_copy_to_hw(reg->data, reg);
+ 		}
+-	} else {
+-		if (pservice->hw_ops->reduce_freq)
+-			pservice->hw_ops->reduce_freq(pservice);
+ 	}
+ 
+ 	mutex_unlock(&pservice->shutdown_lock);
+@@ -2385,6 +2382,7 @@ static void vcodec_set_freq_rk3328(struct vpu_service_info *pservice,
+ 	if (curr == reg->freq)
+ 		return;
+ 
++	atomic_set(&pservice->freq_status, reg->freq);
+ 	if (pservice->dev_id == VCODEC_DEVICE_ID_RKVDEC) {
+ 		if (reg->reg[1] & 0x00800000) {
+ 			if (rkv_dec_get_fmt(reg->reg) == FMT_H264D)

patch/kernel/rk322x-legacy/01-linux-1001-ssv6051.patch

@@ -0,0 +1,174 @@
+--- a/drivers/net/wireless/rockchip_wlan/ssv6xxx/ssvdevice/ssvdevice.c
++++ b/drivers/net/wireless/rockchip_wlan/ssv6xxx/ssvdevice/ssvdevice.c
+@@ -58,7 +58,7 @@
+ char *ssv6xxx_result_buf;
+ extern struct ssv6xxx_cfg_cmd_table cfg_cmds[];
+ extern struct ssv6xxx_cfg ssv_cfg;
+-char DEFAULT_CFG_PATH[] = "/vendor/etc/firmware/ssv6051-wifi.cfg";
++char DEFAULT_CFG_PATH[] = "/etc/firmware/ssv6051/ssv6051-wifi.cfg";
+ static int ssv6xxx_dbg_open(struct inode *inode, struct file *filp)
+ {
+     filp->private_data = inode->i_private;
+
+--- a/drivers/net/wireless/rockchip_wlan/ssv6xxx/ssvdevice/ssv_cmd.c
++++ b/drivers/net/wireless/rockchip_wlan/ssv6xxx/ssvdevice/ssv_cmd.c
+@@ -1541,7 +1541,7 @@
+  size_per_frame = simple_strtoul(argv[2], &endp, 10);
+  loop_times = simple_strtoul(argv[3], &endp, 10);
+  sprintf(tmpbf, "type&size&frames:%d&%d&%d\n", pkt_type, size_per_frame, loop_times);
+- strncat(ssv6xxx_result_buf, tmpbf, sizeof(tmpbf));
++ strcat(ssv6xxx_result_buf, tmpbf);
+  if (ssv6xxx_txtput->txtput_tsk) {
+   sprintf(tmpbf, "txtput already in progress\n");
+   strcat(ssv6xxx_result_buf, tmpbf);
+--- a/drivers/net/wireless/rockchip_wlan/ssv6xxx/smac/dev.c
++++ b/drivers/net/wireless/rockchip_wlan/ssv6xxx/smac/dev.c
+@@ -92,8 +92,6 @@
+  unsigned int timeout;
+  SKB_info *mpdu_skb_info = (SKB_info *)mpdu_skb->head;
+  timeout = (unsigned int)ktime_to_ms(ktime_sub(ktime_get(), mpdu_skb_info->timestamp));
+- if (timeout > SKB_DURATION_TIMEOUT_MS)
+-  printk("*mpdu_duration: %ums\n", timeout);
+  return timeout;
+ }
+ #endif
+@@ -179,7 +177,7 @@
+                 size, type);
+     else
+     {
+-        dev_info(sc->dev, "Allocated %d type packet buffer of size %d (%d) at address %x.\n",
++        dev_dbg(sc->dev, "Allocated %d type packet buffer of size %d (%d) at address %x.\n",
+                  type, size, page_cnt, regval);
+     }
+     return regval;
+@@ -197,7 +195,6 @@
+     }
+     mutex_lock(&sc->mem_mutex);
+     regval = ((M_ENG_TRASH_CAN << HW_ID_OFFSET) |(pbuf_addr >> ADDRESS_OFFSET));
+-    printk("[A] ssv6xxx_pbuf_free addr[%08x][%x]\n", pbuf_addr, regval);
+     SMAC_REG_WRITE(sc->sh, ADR_CH0_TRIG_1, regval);
+     if (*p_tx_page_cnt)
+     {
+@@ -1136,7 +1133,7 @@
+     address = sec_key_tbl
+               + ((index-1) * sizeof(struct ssv6xxx_hw_key));
+     if (vif_info->vif_priv != NULL)
+-        dev_info(sc->dev, "Write group key %d to VIF %d to %08X\n",
++        dev_dbg(sc->dev, "Write group key %d to VIF %d to %08X\n",
+                  index, vif_info->vif_priv->vif_idx, address);
+     else
+         dev_err(sc->dev, "NULL VIF.\n");
+@@ -1189,7 +1186,7 @@
+     #if 0
+     sta_info->s_flags |= STA_FLAG_ENCRYPT;
+     #endif
+-    dev_info(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid, key_len);
++    dev_dbg(sc->dev, "Set STA %d's pair-wise key of %d bytes.\n", wsid, key_len);
+     sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+     sramKey->sta_key[wsid].pair_key_idx = 0;
+     sramKey->sta_key[wsid].group_key_idx = vif_priv->group_key_idx;
+@@ -1234,7 +1231,7 @@
+         dev_err(sc->dev, "Setting group key to NULL VIF\n");
+         return -EOPNOTSUPP;
+     }
+-    dev_info(sc->dev, "Setting VIF %d group key %d of length %d to WSID %d.\n",
++    dev_dbg(sc->dev, "Setting VIF %d group key %d of length %d to WSID %d.\n",
+              vif_priv->vif_idx, index, key_len, wsid);
+     sramKey = &(sc->vif_info[vif_priv->vif_idx].sramKey);
+     vif_priv->group_key_idx = index;
+@@ -1384,7 +1381,7 @@
+         else
+         {
+             dev_err(sc->dev, "[Local Crypto]: Failed to initialize driver's crypto!\n");
+-            dev_info(sc->dev, "[Local Crypto]: Use MAC80211's encrypter.\n");
++            dev_dbg(sc->dev, "[Local Crypto]: Use MAC80211's encrypter.\n");
+             vif_priv->need_sw_decrypt = false;
+             vif_priv->need_sw_encrypt = false;
+             vif_priv->use_mac80211_decrypt = true;
+@@ -1457,7 +1454,7 @@
+         if (((val >>4) & 0xF) != M_ENG_CPU){
+             SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, ((val & 0xf) | (M_ENG_CPU<<4)
+                 | (val & 0xfffffff0) <<4));
+-            dev_info(sc->dev, "orginal Rx_Flow %x , modified flow %x \n", val,
++            dev_dbg(sc->dev, "orginal Rx_Flow %x , modified flow %x \n", val,
+             ((val & 0xf) | (M_ENG_CPU<<4) | (val & 0xfffffff0) <<4));
+         }
+     }
+@@ -1476,7 +1473,7 @@
+                 (sta_priv->sta_info->sta->ht_cap.ht_supported == false))
+                 && (vif_priv->force_sw_encrypt == false)))
+         {
+-            dev_info(sc->dev, "STA %d uses HW encrypter for pairwise.\n", sta_priv->sta_idx);
++            dev_dbg(sc->dev, "STA %d uses HW encrypter for pairwise.\n", sta_priv->sta_idx);
+             sta_priv->has_hw_encrypt = true;
+             sta_priv->need_sw_encrypt = false;
+             sta_priv->use_mac80211_decrypt = false;
+@@ -1601,7 +1598,7 @@
+     if (((vif_priv->vif_idx == 0) && (tkip_use_sw_cipher == false))
+         || ((cipher == SSV_CIPHER_CCMP) && (sc->sh->cfg.use_wpa2_only == 1)))
+     {
+-        dev_info(sc->dev, "VIF %d uses HW %s cipher for group.\n", vif_priv->vif_idx, cipher_name);
++        dev_dbg(sc->dev, "VIF %d uses HW %s cipher for group.\n", vif_priv->vif_idx, cipher_name);
+         #ifdef USE_MAC80211_DECRYPT_BROADCAST
+         vif_priv->has_hw_decrypt = false;
+         ret = -EOPNOTSUPP;
+@@ -1700,7 +1697,7 @@
+                 if (((val >>4) & 0xF) != M_ENG_CPU){
+                     SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA, ((val & 0xf) | (M_ENG_CPU<<4)
+                         | (val & 0xfffffff0) <<4));
+-                    dev_info(sc->dev, "orginal Rx_Flow %x , modified flow %x \n", val,
++                    dev_dbg(sc->dev, "orginal Rx_Flow %x , modified flow %x \n", val,
+                     ((val & 0xf) | (M_ENG_CPU<<4) | (val & 0xfffffff0) <<4));
+                 } else {
+                     printk(" doesn't need to change rx flow\n");
+@@ -1913,7 +1910,7 @@
+                                     SMAC_REG_WRITE(sc->sh, ADR_RX_FLOW_DATA,
+                                         ((val & 0xf) | (M_ENG_CPU<<4)
+                                          | (val & 0xfffffff0) <<4));
+-                                    dev_info(sc->dev, "orginal Rx_Flow %x , modified flow %x \n",
++                                    dev_dbg(sc->dev, "orginal Rx_Flow %x , modified flow %x \n",
+                                         val, ((val & 0xf) | (M_ENG_CPU<<4) | (val & 0xfffffff0) <<4));
+                                 } else {
+                                     printk(" doesn't need to change rx flow\n");
+@@ -2997,15 +2994,15 @@
+     u32 sta_addr0_3 = *(u32 *)&sta->addr[0];
+     u32 sta_addr4_5 = (u32)*(u16 *)&sta->addr[4];
+     u32 removed_skb_num;
+-    dev_info(sc->dev, "Clean up skb for STA %pM.\n", sta->addr);
++    dev_dbg(sc->dev, "Clean up skb for STA %pM.\n", sta->addr);
+     _stop_crypto_task(sc);
+     spin_lock_irqsave(&sc->crypt_st_lock, flags);
+     removed_skb_num = _remove_sta_skb_from_q(sc, &sc->preprocess_q,
+                                              sta_addr0_3, sta_addr4_5);
+-    dev_info(sc->dev, "Removed %u MPDU from precess queue.\n", removed_skb_num);
++    dev_dbg(sc->dev, "Removed %u MPDU from precess queue.\n", removed_skb_num);
+     removed_skb_num = _remove_sta_skb_from_q(sc, &sc->crypted_q,
+                                              sta_addr0_3, sta_addr4_5);
+-    dev_info(sc->dev, "Removed %u MPDU from encrypted queue.\n", removed_skb_num);
++    dev_dbg(sc->dev, "Removed %u MPDU from encrypted queue.\n", removed_skb_num);
+     spin_unlock_irqrestore(&sc->crypt_st_lock, flags);
+     _resume_crypto_task(sc);
+ }
+@@ -4007,7 +4004,7 @@
+             && crypto_data->priv)
+         {
+             crypto_data->ops->deinit(crypto_data->priv);
+-            dev_info(sc->dev, "STA releases crypto OK!\n");
++            dev_dbg(sc->dev, "STA releases crypto OK!\n");
+         }
+         crypto_data->priv = NULL;
+         crypto_data->ops = NULL;
+
+diff --git a/drivers/net/wireless/rockchip_wlan/ssv6xxx/Makefile b/drivers/net/wireless/rockchip_wlan/ssv6xxx/Makefile
+index f86faef..e1df615 100644
+--- a/drivers/net/wireless/rockchip_wlan/ssv6xxx/Makefile
++++ b/drivers/net/wireless/rockchip_wlan/ssv6xxx/Makefile
+@@ -19,7 +19,7 @@ include $(KBUILD_TOP)/ssv6051.cfg
+ include $(KBUILD_TOP)/platform-config.mak
+ 
+ 
+-EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include
++EXTRA_CFLAGS := -I$(KBUILD_TOP) -I$(KBUILD_TOP)/include -Wno-error=missing-attributes
+ DEF_PARSER_H = $(KBUILD_TOP)/include/ssv_conf_parser.h
+ $(shell env ccflags="$(ccflags-y)" $(KBUILD_TOP)/parser-conf.sh $(DEF_PARSER_H))
+ 

patch/kernel/rk322x-legacy/02-000-remove-broken-dts.patch

@@ -0,0 +1,12 @@
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 4d9f7b32..1133f2ad 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -536,7 +536,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3229-echo-v10.dtb \
+ 	rk3229-evb.dtb \
+ 	rk3229-evb-android.dtb \
+-	rk3229-evb-android-avb.dts \
+ 	rk3229-gva-sdk.dtb \
+ 	rk3288-evb-act8846.dtb \
+ 	rk3288-evb-android-act8846-edp.dtb \

patch/kernel/rk322x-legacy/02-001-rk322x-box-dtsi-integrate.patch

@@ -0,0 +1,153 @@
+diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi
+index 04330d393..608d3f386 100644
+--- a/arch/arm/boot/dts/rk322x-box.dtsi
++++ b/arch/arm/boot/dts/rk322x-box.dtsi
+@@ -22,9 +22,39 @@
+ 
+ 
+ 	chosen {
++		stdout-path = &uart2;
+ 		bootargs = "earlycon=uart8250,mmio32,0x11030000";
+ 	};
+ 
++	bus_intmem@10080000 {
++                compatible = "mmio-sram";
++                reg = <0x10080000 0x9000>;
++                #address-cells = <1>;
++                #size-cells = <1>;
++                ranges = <0 0x10080000 0x9000>;
++                smp-sram@0 {
++                        compatible = "rockchip,rk3066-smp-sram";
++                        reg = <0x00 0x10>;
++                };
++                ddr_sram: ddr-sram@1000 {
++                        compatible = "rockchip,rk322x-ddr-sram";
++                        reg = <0x1000 0x8000>;
++                };
++        };
++
++	fiq-debugger {
++		compatible = "rockchip,fiq-debugger";
++		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
++		rockchip,serial-id = <2>;
++		rockchip,signal-irq = <159>;
++		rockchip,wake-irq = <0>;
++		rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
++		rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
++		pinctrl-names = "default";
++		pinctrl-0 = <&uart21_xfer>;
++		status = "disabled";
++	};
++
+ 	reserved-memory {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+@@ -59,7 +89,7 @@
+ 		compatible = "simple-audio-card";
+ 		simple-audio-card,format = "i2s";
+ 		simple-audio-card,mclk-fs = <256>;
+-		simple-audio-card,name = "ROCKCHIP,RK3229";
++		simple-audio-card,name = "ANALOG";
+ 		simple-audio-card,cpu {
+ 			sound-dai = <&i2s1>;
+ 		};
+@@ -73,7 +103,7 @@
+ 		compatible = "simple-audio-card";
+ 		simple-audio-card,format = "i2s";
+ 		simple-audio-card,mclk-fs = <128>;
+-		simple-audio-card,name = "HDMI";
++		simple-audio-card,name = "DW-I2S-HDMI";
+ 		simple-audio-card,cpu {
+ 			sound-dai = <&i2s0>;
+ 		};
+@@ -113,7 +143,7 @@
+ 	spdif-sound {
+ 		status = "okay";
+ 		compatible = "simple-audio-card";
+-		simple-audio-card,name = "ROCKCHIP,SPDIF";
++		simple-audio-card,name = "SPDIF";
+ 		simple-audio-card,cpu {
+ 			sound-dai = <&spdif>;
+ 		};
+@@ -219,14 +249,17 @@
+ 
+ &cpu1 {
+ 	enable-method = "psci";
++	cpu-supply = <&vdd_arm>;
+ };
+ 
+ &cpu2 {
+ 	enable-method = "psci";
++	cpu-supply = <&vdd_arm>;
+ };
+ 
+ &cpu3 {
+ 	enable-method = "psci";
++	cpu-supply = <&vdd_arm>;
+ };
+ 
+ 
+@@ -237,11 +270,23 @@
+ &gmac {
+ 	assigned-clocks = <&cru SCLK_MAC_SRC>;
+ 	assigned-clock-rates = <50000000>;
++
+ 	clock_in_out = "output";
+ 	phy-supply = <&vcc_phy>;
+ 	phy-mode = "rmii";
+ 	phy-is-integrated;
++
++	tx_delay = < 0x30 >;
++	rx_delay = < 0x10 >;
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&phy_pins>;
++
++	snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++
+ 	status = "okay";
++
+ };
+ 
+ &gpu {
+@@ -273,11 +318,13 @@
+ 	broken-cd;
+ 	bus-width = <8>;
+ 	cap-mmc-highspeed;
+-	mmc-hs200-1_8v;
+ 	supports-emmc;
+ 	disable-wp;
+ 	non-removable;
+ 	num-slots = <1>;
++	max-frequency = <150000000>;
++	clock-frequency = <50000000>;
++	/delete-property/ clock-freq-min-max;
+ 	/delete-property/ default-sample-phase;
+ 	/delete-property/ pinctrl-names;
+ 	/delete-property/ pinctrl-0;
+@@ -288,7 +335,7 @@
+ 	cap-sd-highspeed;
+ 	card-detect-delay = <200>;
+ 	disable-wp;
+-	max-frequency = <50000000>;
++	max-frequency = <150000000>;
+ 	num-slots = <1>;
+ 	supports-sd;
+ 	pinctrl-names = "default";
+@@ -433,6 +480,7 @@
+ 	status = "okay";
+ 
+ 	u2phy1_otg: otg-port {
++		phy-supply = <&vcc_host>;
+ 		status = "okay";
+ 	};
+ 
+@@ -443,6 +491,7 @@
+ };
+ 
+ &usb_otg {
++	dr_mode = "host";
+ 	status = "okay";
+ };
+ 

patch/kernel/rk322x-legacy/02-002-dtsi-fix-arch-sys-counter.patch

@@ -0,0 +1,12 @@
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index 1f1e4e69..ec37b4d9 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -262,6 +262,7 @@
+ 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 		clock-frequency = <24000000>;
++		arm,cpu-registers-not-fw-configured;
+ 	};
+ 
+ 	xin24m: oscillator {

patch/kernel/rk322x-legacy/02-003-dtsi-adjust-gpu-node-for-r7p0.patch.disabled

@@ -0,0 +1,62 @@
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index af417ae37..a4108dde0 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -774,23 +775,9 @@
+ 		status = "disabled";
+ 	};
+ 
+-	gpu: gpu@0x20001000 {
+-		compatible = "arm,mali400";
+-		reg = <0x20001000 0x200>,
+-		      <0x20000000 0x100>,
+-		      <0x20003000 0x100>,
+-		      <0x20008000 0x1100>,
+-		      <0x20004000 0x100>,
+-		      <0x2000A000 0x1100>,
+-		      <0x20005000 0x100>;
+-
+-		reg-names = "Mali_L2",
+-			    "Mali_GP",
+-			    "Mali_GP_MMU",
+-			    "Mali_PP0",
+-			    "Mali_PP0_MMU",
+-			    "Mali_PP1",
+-			    "Mali_PP1_MMU";
++	gpu: gpu@20000000 {
++		compatible = "arm,mali-400";
++		reg = <0x20000000 0x10000>;
+ 
+ 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+@@ -799,16 +786,21 @@
+ 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 
+-		interrupt-names = "Mali_GP_IRQ",
+-				  "Mali_GP_MMU_IRQ",
+-				  "Mali_PP0_IRQ",
+-				  "Mali_PP0_MMU_IRQ",
+-				  "Mali_PP1_IRQ",
+-				  "Mali_PP1_MMU_IRQ";
+-		clocks = <&cru ACLK_GPU>;
+-		#cooling-cells = <2>; /* min followed by max */
+-		clock-names = "clk_mali";
++		interrupt-names = "IRQGP",
++				  "IRQGPMMU",
++				  "IRQPP0",
++				  "IRQPPMMU0",
++				  "IRQPP1",
++				  "IRQPPMMU1";
++
++		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>, <&cru ACLK_GPU>;
++		clock-names = "clk_mali", "core", "bus";
++
++		resets = <&cru SRST_GPU_A>;
++
+ 		operating-points-v2 = <&gpu_opp_table>;
++
++		#cooling-cells = <2>; /* min followed by max */
+ 		status = "disabled";
+ 
+ 		gpu_power_model: power_model {

patch/kernel/rk322x-legacy/02-004-dts-makefile.patch

@@ -0,0 +1,12 @@
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 4d9f7b328..15d4a1da3 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -530,6 +530,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3128h-evb-linux.dtb \
+ 	rk3188-radxarock.dtb \
+ 	rk3228-evb.dtb \
++	rk322x-box.dtb \
+ 	rk3229-at-3nod.dtb \
+ 	rk3229-at-3nod-func.dtb \
+ 	rk3229-at-gva.dtb \

patch/kernel/rk322x-legacy/02-005-dtsi-add-nand-pinctrls.patch

@@ -0,0 +1,79 @@
+diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
+index af417ae37..80868dcda 100644
+--- a/arch/arm/boot/dts/rk322x.dtsi
++++ b/arch/arm/boot/dts/rk322x.dtsi
+@@ -1386,6 +1386,74 @@
+ 			};
+ 		};
+ 
++		flash {
++
++			flash_cs0: flash-cs0 {
++				rockchip,pins =
++					<2 RK_PA6 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_cs1: flash-cs1 {
++				rockchip,pins =
++					<0 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_cs2: flash-cs2 {
++				rockchip,pins =
++					<1 RK_PC6 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_cs3: flash-cs3 {
++				rockchip,pins =
++					<1 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_rdy: flash-rdy {
++				rockchip,pins =
++					<2 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_ale: flash-ale {
++				rockchip,pins =
++					<2 RK_PA0 RK_FUNC_1 &pcfg_pull_down>;
++			};
++
++			flash_cle: flash-cle {
++				rockchip,pins =
++					<2 RK_PA1 RK_FUNC_1 &pcfg_pull_down>;
++			};
++
++			flash_wrn: flash-wrn {
++				rockchip,pins =
++					<2 RK_PA2 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_rdn: flash-rdn {
++				rockchip,pins =
++					<2 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_bus8: flash-bus8 {
++				rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD1 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD4 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD5 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD6 RK_FUNC_1 &pcfg_pull_up>,
++						<1 RK_PD7 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_dqs: flash-dqs {
++				rockchip,pins = <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
++			};
++
++			flash_wp: flash-wp {
++				rockchip,pins = <2 RK_PA5 RK_FUNC_1 &pcfg_pull_down>;
++			};
++
++		};
++
+ 		emmc {
+ 			emmc_clk: emmc-clk {
+ 				rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;

patch/kernel/rk322x-legacy/arm64_makefile_fix_build_of_i-file_in_external_module_case.patch

@@ -0,0 +1,20 @@
+diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
+index 605f6cf4..08b797df 100644
+--- a/arch/arm64/Makefile
++++ b/arch/arm64/Makefile
+@@ -141,6 +141,7 @@ archclean:
+ 	$(Q)$(MAKE) $(clean)=$(boot)
+ 	$(Q)$(MAKE) $(clean)=$(boot)/dts
+ 
++ifeq ($(KBUILD_EXTMOD),)
+ # We need to generate vdso-offsets.h before compiling certain files in kernel/.
+ # In order to do that, we should use the archprepare target, but we can't since
+ # asm-offsets.h is included in some files used to generate vdso-offsets.h, and
+@@ -150,6 +151,7 @@ archclean:
+ prepare: vdso_prepare
+ vdso_prepare: prepare0
+ 	$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso include/generated/vdso-offsets.h
++endif
+ 
+ define archhelp
+   echo  '* Image.gz      - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'

patch/kernel/rk322x-legacy/board-rk322x-box.patch

@@ -0,0 +1,221 @@
+diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
+new file mode 100644
+index 000000000..e5f09873c
+--- /dev/null
++++ b/arch/arm/boot/dts/rk322x-box.dts
+@@ -0,0 +1,215 @@
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ *  Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "rk3228a-box.dtsi"
++
++/ {
++
++	model = "Generic RK322x TV Box board";
++
++	gpio_leds: gpio-leds {
++
++		compatible = "gpio-leds";
++
++		working {
++			pinctrl-names = "default";
++			pinctrl-0 = <&gpio_led_working>;
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++			label = "working";
++			default-state = "on";
++			linux,default-trigger = "timer";
++		};
++
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>;
++		reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; /* GPIO2_D2 */
++	};
++
++};
++
++/** Integration to pin controller */
++&pinctrl {
++
++	pcfg_pull_up_12ma: pcfg-pull-up-12ma {
++		drive-strength = <12>;
++		bias-pull-up;
++	};
++
++	pcfg_pull_down_12ma: pcfg-pull-down-12ma {
++		drive-strength = <12>;
++		bias-pull-down;
++	};
++
++	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
++		drive-strength = <12>;
++		bias-disable;
++	};
++
++	pcfg_pull_up_2ma: pcfg-pull-up-2ma {
++		drive-strength = <2>;
++		bias-pull-up;
++	};
++
++	pcfg_pull_down_2ma: pcfg-pull-down-2ma {
++		drive-strength = <2>;
++		bias-pull-down;
++	};
++
++	pcfg_pull_none_2ma: pcfg-pull-none-2ma {
++		drive-strength = <2>;
++		bias-disable;
++	};
++
++	/*
++	* Some rk322x electrical schemes report this kind of pull-up/down
++	* pin configurations. We set them here, but we don't use it in this
++	* device tree. These instead are useful for overlays, because they seem
++	* to increase stability on at least one board I got here
++	*/
++	sdmmc {
++		sdmmc_clk: sdmmc-clk {
++			rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_down>;
++		};
++
++		sdmmc_cmd: sdmmc-cmd {
++			rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_up>;
++		};
++
++		sdmmc_bus4: sdmmc-bus4 {
++			rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_up>,
++					<1 19 RK_FUNC_1 &pcfg_pull_up>,
++					<1 20 RK_FUNC_1 &pcfg_pull_up>,
++					<1 21 RK_FUNC_1 &pcfg_pull_up>;
++		};
++	};
++
++	/*
++	* Same as above, decreasing strength of SDIO pins seems to be benefical
++	* to stability
++	*/
++	sdio {
++		sdio_clk: sdio-clk {
++			rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_down_2ma>;
++		};
++
++		sdio_cmd: sdio-cmd {
++			rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_up_2ma>;
++		};
++
++		sdio_bus4: sdio-bus4 {
++			rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up_2ma>,
++					<3 3 RK_FUNC_1 &pcfg_pull_up_2ma>,
++					<3 4 RK_FUNC_1 &pcfg_pull_up_2ma>,
++					<3 5 RK_FUNC_1 &pcfg_pull_up_2ma>;
++		};
++	};
++
++	/*
++	* Same drill as above, electrical schemes also report this pull-up/down
++	* configurations.
++	*/
++	emmc {
++		emmc_clk: emmc-clk {
++			rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++		emmc_cmd: emmc-cmd {
++			rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++		emmc_bus8: emmc-bus8 {
++			rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_up>,
++					<1 25 RK_FUNC_2 &pcfg_pull_up>,
++					<1 26 RK_FUNC_2 &pcfg_pull_up>,
++					<1 27 RK_FUNC_2 &pcfg_pull_up>,
++					<1 28 RK_FUNC_2 &pcfg_pull_up>,
++					<1 29 RK_FUNC_2 &pcfg_pull_up>,
++					<1 30 RK_FUNC_2 &pcfg_pull_up>,
++					<1 31 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++		emmc_pwr: emmc-pwr {
++			rockchip,pins = <2 RK_PA5 RK_FUNC_2 &pcfg_pull_down>;
++		};
++
++		emmc_rst: emmc-rst {
++			rockchip,pins = <1 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
++		};
++
++	};
++
++	gpio {
++		gpio_led_working: gpio-led-working {
++			rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++};
++
++/** MMC and NAND controller and interfaces */
++
++&emmc {
++	status = "okay";
++};
++
++&sdio {
++	mmc-pwrseq = <&sdio_pwrseq>;
++	status = "okay";
++};
++
++&sdmmc {
++	status = "okay";
++};
++
++&nandc {
++	status = "okay";
++};
++
++&usb_otg {
++        dr_mode = "host";
++};

patch/kernel/rk322x-legacy/general-add-overlay-compilation-support.patch

@@ -0,0 +1,129 @@
+diff --git a/arch/arm/Makefile b/arch/arm/Makefile
+index 554985b52..c4629fc51 100644
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -338,6 +338,12 @@ $(INSTALL_TARGETS):
+ %.dtb: | scripts
+ 	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
+ 
++%.dtbo: | scripts
++	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
++
++%.scr: | scripts
++	$(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@
++
+ PHONY += dtbs dtbs_install
+ 
+ dtbs: prepare scripts
+diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
+index ad7a0253e..e064e5f27 100644
+--- a/arch/arm/boot/.gitignore
++++ b/arch/arm/boot/.gitignore
+@@ -3,5 +3,6 @@ zImage
+ xipImage
+ bootpImage
+ uImage
+-*.dtb
+-zImage-dtb
+\ No newline at end of file
++*.dtb*
++*.scr
++zImage-dtb
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 4d9f7b328..743b62522 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -850,7 +850,10 @@ DTB_LIST := $(dtb-y)
+ endif
+ 
+ targets += dtbs dtbs_install
+-targets += $(DTB_LIST)
++targets += $(dtb-y)
+ 
+-always		:= $(DTB_LIST)
++always		:= $(dtb-y)
++subdir-y	:= overlay
+ clean-files	:= *.dtb
++
++dts-dirs += overlay
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 1c15717e0..bcc0fc524 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -29,6 +29,9 @@ ifeq ("$(dtbinst-root)", "$(obj)")
+ endif
+ 
+ dtbinst-files	:= $(dtb-y)
++dtboinst-files	:= $(dtbo-y)
++script-files	:= $(scr-y)
++readme-files	:= $(dtbotxt-y)
+ dtbinst-dirs	:= $(dts-dirs)
+ 
+ # Helper targets for Installing DTBs into the boot directory
+@@ -37,15 +40,25 @@ quiet_cmd_dtb_install =	INSTALL $<
+ 
+ install-dir = $(patsubst $(dtbinst-root)%,$(INSTALL_DTBS_PATH)%,$(obj))
+ 
+-$(dtbinst-files) $(dtbinst-dirs): | __dtbs_install_prep
++$(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs): | __dtbs_install_prep
+ 
+ $(dtbinst-files): %.dtb: $(obj)/%.dtb
+ 	$(call cmd,dtb_install,$(install-dir))
+ 
++
++$(dtboinst-files): %.dtbo: $(obj)/%.dtbo
++	$(call cmd,dtb_install,$(install-dir))
++
++$(script-files): %.scr: $(obj)/%.scr
++	$(call cmd,dtb_install,$(install-dir))
++
++$(readme-files): %: $(src)/%
++	$(call cmd,dtb_install,$(install-dir))
++
+ $(dtbinst-dirs):
+ 	$(Q)$(MAKE) $(dtbinst)=$(obj)/$@
+ 
+-PHONY += $(dtbinst-files) $(dtbinst-dirs)
+-__dtbs_install: $(dtbinst-files) $(dtbinst-dirs)
++PHONY += $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs)
++__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs)
+ 
+ .PHONY: $(PHONY)
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index 3fb2aaa00..7956778c3 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -270,6 +270,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
+ # ---------------------------------------------------------------------------
+ DTC ?= $(objtree)/scripts/dtc/dtc
+ 
++# Overlay support
++DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg
++
+ # Generation of symbols for Android
+ ifeq ($(CONFIG_ANDROID),y)
+ DTC_FLAGS += -@
+@@ -319,6 +322,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
+ $(obj)/%.dtb: $(src)/%.dts FORCE
+ 	$(call if_changed_dep,dtc)
+ 
++quiet_cmd_dtco = DTCO    $@
++cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
++	$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
++	$(DTC) -O dtb -o $@ -b 0 \
++		-i $(dir $<) $(DTC_FLAGS) \
++		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
++	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
++
++$(obj)/%.dtbo: $(src)/%.dts FORCE
++	$(call if_changed_dep,dtco)
++
++quiet_cmd_scr = MKIMAGE $@
++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+ 
+ # cat

patch/kernel/rk322x-legacy/general-add-overlays.patch

@@ -0,0 +1,307 @@
+diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile
+new file mode 100644
+index 000000000..f024e8db0
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/Makefile
+@@ -0,0 +1,20 @@
++# SPDX-License-Identifier: GPL-2.0
++dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
++	rk322x-emmc.dtbo	\
++	rk322x-nand.dtbo	\
++	rk322x-emmc-nand.dtbo	\
++	rk322x-led-conf1.dtbo	\
++	rk322x-led-conf2.dtbo	\
++	rk322x-cpu-hs.dtbo
++
++scr-$(CONFIG_ARCH_ROCKCHIP) += \
++       rk322x-fixup.scr
++
++dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \
++       README.rk322x-overlays
++
++targets += $(dtbo-y) $(scr-y) $(dtbotxt-y)
++
++always         := $(dtbo-y) $(scr-y) $(dtbotxt-y)
++clean-files    := *.dtbo *.scr
++
+diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays
+new file mode 100644
+index 000000000..d5bc7f3d5
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays
+@@ -0,0 +1,51 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++rk322x (Rockchip)
++
++### Provided overlays:
++
++- rk322x-cpu-hs
++- rk322x-emmc
++- rk322x-nand
++- rk322x-emmc-nand
++- rk322x-led1-low
++- rk322x-led1-high
++- rk322x-led2-low
++- rk322x-led2-high
++
++### Overlay details:
++
++### rk322x-cpu-hs
++
++Activates higher CPU speed (up to 1.4ghz) for rk3228b/rk3229 boxes
++
++### emmc
++
++Activates onboard emmc device node and deactivates the nand controller.
++Also sets up the pin controller default pull up/down configuration
++
++### nand
++
++Activates onboard nand device node and deactivates the emmc controller.
++Also sets up the pin controller default pull up/down configuration
++
++### emmc-nand
++
++Activates onboard nand and emmc devices. Usually they are alternative
++because manufacturers share the same pads so emmc and nand cannot be
++mixed together. Usually this works because the emmc and nand drivers
++can automatically guess what's in the pads, but may bring instabilities
++or misdetections. Also does not set up the pin controller default
++configuration, which in turn can be detrimental of stability and
++performance
++
++### rk322x-led-conf*
++
++Each device tree of this kind provides a different known wiring configuration
++(ie: gpio and active low/high) of the onboard leds. Each board manufacturer
++usually choose a different GPIO for the auxiliary led, but the main "working"
++led is always wired to the same gpio (although it may be active high or low)
+diff --git a/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
+new file mode 100644
+index 000000000..1c2fc79e1
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-cpu-hs.dts
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++		__overlay__ {
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1325000 1325000 1400000>;
++			};
++			opp-1392000000 {
++				opp-hz = /bits/ 64 <1392000000>;
++				opp-microvolt = <1350000 1350000 1400000>;
++			};
++			/*
++			opp-1464000000 {
++				opp-hz = /bits/ 64 <1464000000>;
++				opp-microvolt = <1400000 1400000 1400000>;
++			};
++			*/
++
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
+new file mode 100644
+index 000000000..b451da657
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-emmc-nand.dts
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&emmc>;
++		__overlay__ {
++			status = "okay";
++			mmc-ddr-1_8v;
++			rockchip,default-sample-phase = <180>;
++		};
++	};
++
++	fragment@1 {
++		target = <&nandc>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc.dts b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
+new file mode 100644
+index 000000000..f3b262ef7
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-emmc.dts
+@@ -0,0 +1,24 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&emmc>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr &emmc_rst>;
++			mmc-ddr-1_8v;
++			rockchip,default-sample-phase = <180>;
++		};
++	};
++
++	fragment@1 {
++		target = <&nandc>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd b/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd
+new file mode 100644
+index 000000000..d4c39e20a
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-fixup.scr-cmd
+@@ -0,0 +1,4 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
+diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
+new file mode 100644
+index 000000000..053947ce8
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-led-conf1.dts
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++/ {
++
++	fragment@0 {
++		target-path = "/gpio-leds";
++		__overlay__ {
++
++			working {
++				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++				linux,default-trigger = "none";
++			};
++
++			auxiliary {
++				gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++				label = "auxiliary";
++				linux,default-trigger = "mmc2";
++				default-state = "off";
++				pinctrl-names = "default";
++				pinctrl-0 = <&gpio_led_aux>;
++			};
++
++		};
++	};
++
++	fragment@1 {
++		target-path = "/pinctrl/gpio";
++		__overlay__ {
++
++			gpio_led_aux: gpio-led-aux {
++				rockchip,pins =  <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
++
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts b/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts
+new file mode 100644
+index 000000000..a3b0bfcee
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-led-conf2.dts
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++/ {
++
++	fragment@0 {
++		target-path = "/gpio-leds";
++		__overlay__ {
++
++			working {
++				gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++				linux,default-trigger = "none";
++			};
++
++			auxiliary {
++				gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
++				label = "auxiliary";
++				linux,default-trigger = "mmc2";
++				default-state = "off";
++				pinctrl-names = "default";
++				pinctrl-0 = <&gpio_led_aux>;
++			};
++
++		};
++	};
++
++	fragment@1 {
++		target-path = "/pinctrl/gpio";
++		__overlay__ {
++
++			gpio_led_aux: gpio-led-aux {
++				rockchip,pins =  <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++			};
++
++		};
++	};
++
++};
+diff --git a/arch/arm/boot/dts/overlay/rk322x-nand.dts b/arch/arm/boot/dts/overlay/rk322x-nand.dts
+new file mode 100644
+index 000000000..5675f5b3d
+--- /dev/null
++++ b/arch/arm/boot/dts/overlay/rk322x-nand.dts
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++
++	fragment@0 {
++		target = <&nandc>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-0 = <&flash_cs0 &flash_cs1 &flash_cs2 &flash_cs3 &flash_rdy &flash_ale &flash_cle &flash_wrn &flash_bus8 &flash_dqs &flash_wp>;
++			pinctrl-names = "default";
++		};
++	};
++
++	fragment@1 {
++		target = <&emmc>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++};

patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-defconfig.patch

@@ -0,0 +1,117 @@
+diff --git a/configs/rk322x-box_defconfig b/configs/rk322x-box_defconfig
+new file mode 100644
+index 00000000..950f122f
+--- /dev/null
++++ b/configs/rk322x-box_defconfig
+@@ -0,0 +1,111 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x61000000
++CONFIG_SYS_MALLOC_F_LEN=0x2000
++CONFIG_ROCKCHIP_RK322X=y
++CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
++CONFIG_SPL_MMC_SUPPORT=y
++CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
++CONFIG_TARGET_RK322X_BOX=y
++CONFIG_SPL_STACK_R_ADDR=0x60600000
++CONFIG_NR_DRAM_BANKS=2
++CONFIG_DEBUG_UART_BASE=0x11030000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_DEBUG_UART=y
++CONFIG_SPL_TEXT_BASE=0x60000000
++CONFIG_LOCALVERSION="-armbian"
++# CONFIG_LOCALVERSION_AUTO is not set
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/fit_spl_optee.sh"
++CONFIG_SD_BOOT=y
++CONFIG_BOOTDELAY=0
++CONFIG_USE_PREBOOT=y
++CONFIG_PREBOOT="usb start; usb stop; usb start"
++# CONFIG_CONSOLE_MUX is not set
++CONFIG_DEFAULT_FDT_FILE="rk322x-box.dtb"
++CONFIG_MISC_INIT_R=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++CONFIG_BOARD_EARLY_INIT_R=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
++CONFIG_SPL_OPTEE=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_ROCKUSB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="rk322x-box"
++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_ENV_IS_IN_EXT4=y
++CONFIG_ENV_EXT4_INTERFACE="mmc"
++CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto"
++CONFIG_ENV_EXT4_FILE="/boot/boot.env"
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_TPL_CLK=y
++CONFIG_FASTBOOT_BUF_SIZE=0x04000000
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_LED=y
++CONFIG_LED_GPIO=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PHY=y
++CONFIG_PINCTRL=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_DEBUG_UART_SKIP_INIT=y
++CONFIG_SYSRESET=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_DWC2=y
++CONFIG_ROCKCHIP_USB2_PHY=y
++CONFIG_USB_KEYBOARD=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_USB_FUNCTION_MASS_STORAGE=y
++CONFIG_USB_FUNCTION_ROCKUSB=y
++CONFIG_DM_VIDEO=y
++# CONFIG_BACKLIGHT_PWM is not set
++# CONFIG_SYS_WHITE_ON_BLACK is not set
++CONFIG_VIDEO_ROCKCHIP=y
++CONFIG_DISPLAY_ROCKCHIP_HDMI=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OPTEE_LOAD_ADDR=0x68400000
++CONFIG_OPTEE_TZDRAM_SIZE=0x00200000
++CONFIG_OPTEE_TZDRAM_BASE=0x68400000
++CONFIG_BOOTM_OPTEE=y

patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-device-tree-makefile.patch

@@ -0,0 +1,220 @@
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 20dbc2ff..e6aa0b07 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -75,7 +75,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3188) += \
+ 	rk3188-radxarock.dtb
+
+ dtb-$(CONFIG_ROCKCHIP_RK322X) += \
+-	rk3229-evb.dtb
++	rk3229-evb.dtb \
++	rk322x-box.dtb
+
+ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
+ 	rk3288-evb.dtb \
+diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig
+index 8a1f95f7..249add9b 100644
+--- a/arch/arm/mach-rockchip/rk322x/Kconfig
++++ b/arch/arm/mach-rockchip/rk322x/Kconfig
+@@ -4,6 +4,10 @@ config TARGET_EVB_RK3229
+ 	bool "EVB_RK3229"
+ 	select BOARD_LATE_INIT
+
++config TARGET_RK322X_BOX
++	bool "RK322X-BOX"
++	select BOARD_LATE_INIT
++
+ config SYS_SOC
+ 	default "rk322x"
+
+@@ -14,5 +18,6 @@ config SPL_SERIAL_SUPPORT
+ 	default y
+
+ source "board/rockchip/evb_rk3229/Kconfig"
++source "board/rockchip/rk322x-box/Kconfig"
+
+ endif
+diff --git a/board/rockchip/rk322x-box/Kconfig b/board/rockchip/rk322x-box/Kconfig
+new file mode 100644
+index 00000000..9ec0227e
+--- /dev/null
++++ b/board/rockchip/rk322x-box/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_RK322X_BOX
++
++config SYS_BOARD
++	default "rk322x-box"
++
++config SYS_VENDOR
++	default "rockchip"
++
++config SYS_CONFIG_NAME
++	default "rk322x-box"
++
++config BOARD_SPECIFIC_OPTIONS # dummy
++	def_bool y
++
++endif
+diff --git a/board/rockchip/rk322x-box/MAINTAINERS b/board/rockchip/rk322x-box/MAINTAINERS
+new file mode 100644
+index 00000000..dddc7865
+--- /dev/null
++++ b/board/rockchip/rk322x-box/MAINTAINERS
+@@ -0,0 +1,6 @@
++XT-MX4VR-V10
++M:      Paolo Sabatino <paolo.sabatino@gmail.com>
++S:      Out of tree
++F:      board/rockchip/rk322x-box
++F:      include/configs/rk322x-box.h
++F:      configs/rk322x-box_defconfig
+diff --git a/board/rockchip/rk322x-box/Makefile b/board/rockchip/rk322x-box/Makefile
+new file mode 100644
+index 00000000..965ff42c
+--- /dev/null
++++ b/board/rockchip/rk322x-box/Makefile
+@@ -0,0 +1,7 @@
++#
++# (C) Copyright 2015 Google, Inc
++#
++# SPDX-License-Identifier:     GPL-2.0+
++#
++
++obj-y	+= rk322x-box.o
+diff --git a/board/rockchip/rk322x-box/README b/board/rockchip/rk322x-box/README
+new file mode 100644
+index 00000000..9c047470
+--- /dev/null
++++ b/board/rockchip/rk322x-box/README
+@@ -0,0 +1,72 @@
++Get the Source and prebuild binary
++==================================
++
++  > mkdir ~/rk322x-box
++  > cd ~/rk322x-box
++  > git clone git://git.denx.de/u-boot.git
++  > git clone https://github.com/OP-TEE/optee_os.git
++  > git clone https://github.com/rockchip-linux/rkbin.git
++  > git clone https://github.com/rockchip-linux/rkdeveloptool.git
++
++Compile the OP-TEE
++===============
++
++  > cd optee_os
++  > make clean
++  > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x
++  Get tee.bin in this step, copy it to U-Boot root dir:
++  > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin
++
++Compile the U-Boot
++==================
++
++  > cd ../u-boot
++  > export CROSS_COMPILE=arm-linux-gnueabihf-
++  > export ARCH=arm
++  > make rk322x-box_defconfig
++  > make
++  > make u-boot.itb
++
++  Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step.
++
++Compile the rkdeveloptool
++=======================
++  Follow instructions in latest README
++  > cd ../rkflashtool
++  > autoreconf -i
++  > ./configure
++  > make
++  > sudo make install
++
++  Get rkdeveloptool in you Host in this step.
++
++Both origin binaries and Tool are ready now, choose either option 1 or
++option 2 to deploy U-Boot.
++
++Package the image
++=================
++
++  > cd ../u-boot
++  > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img
++  > cat spl/u-boot-spl.bin >> idbloader.img
++
++  Get idbloader.img in this step.
++
++Flash the image to eMMC
++=======================
++Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
++  > cd ..
++  > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin
++  > rkdeveloptool wl 64 u-boot/idbloader.img
++  > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
++  > rkdeveloptool rd
++
++Flash the image to SD card
++==========================
++  > dd if=u-boot/idbloader.img of=/dev/sdb seek=64
++  > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384
++
++You should be able to get U-Boot log message with OP-TEE boot info.
++
++For more detail, please reference to:
++http://opensource.rock-chips.com/wiki_Boot_option
+diff --git a/include/configs/rk322x-box.h b/include/configs/rk322x-box.h
+new file mode 100644
+index 00000000..a909aa19
+--- /dev/null
++++ b/include/configs/rk322x-box.h
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define ROCKCHIP_DEVICE_SETTINGS \
++		"stdin=serial,usbkbd\0" \
++		"stdout=serial,vidconsole\0" \
++		"stderr=serial,vidconsole\0" 
++
++#include <configs/rk322x_common.h>
++
++#undef BOOT_TARGET_DEVICES
++
++#define BOOT_TARGET_DEVICES(func) \
++        func(MMC, mmc, 1) \
++        func(USB, usb, 0) \
++	func(MMC, mmc, 0) \
++        func(PXE, pxe, na) \
++        func(DHCP, dchp, na)
++
++#define CONFIG_SYS_MMC_ENV_DEV 0
++
++#endif
+diff --git a/board/rockchip/rk322x-box/rk322x-box.c b/board/rockchip/rk322x-box/rk322x-box.c
+new file mode 100644
+index 00000000..ff7d8c98
+--- /dev/null
++++ b/board/rockchip/rk322x-box/rk322x-box.c
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
++ */
++
++#include <common.h>
++#include <dm.h>
++#include <asm/io.h>
++#include <asm/arch-rockchip/uart.h>
++#include <led.h>
++
++int board_early_init_r(void) {
++
++        /* LED setup */
++	if (IS_ENABLED(CONFIG_LED))
++		led_default_state();
++
++	return 0;
++
++}
++

patch/u-boot/u-boot-rk322x/board_rk322x-box/rk322x-box-add-device-tree.patch

@@ -0,0 +1,72 @@
+diff --git a/arch/arm/dts/rk322x-box.dts b/arch/arm/dts/rk322x-box.dts
+new file mode 100755
+index 00000000..eb47f976
+--- /dev/null
++++ b/arch/arm/dts/rk322x-box.dts
+@@ -0,0 +1,66 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include "rk322x-generic-tvbox.dtsi"
++
++/ {
++	model = "Generic Rockchip rk322x TV Box board";
++	compatible = "rockchip,rk322x-box";
++
++};
++
++&leds {
++
++	/*
++		Alternative led: some boards which have main led wired
++		as ACTIVE_LOW will not show anything during boot, thus
++		we put this gpio led as ACTIVE_HIGH, so at least one
++		may give some hint during boot.
++		Schematics say that this pin is connected to I2C0 data
++		bus, which is usually unused on rk322x boards
++	*/
++		
++	alt {
++		label = "alternative";
++		gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++		default-state = "on";
++        };
++
++};
++
++&gmac {
++
++	tx_delay = < 0x26 >; // Default is 0x30, but original dts proposes 0x26
++	rx_delay = < 0x11 >; // Default is 0x10, but original dts proposes 0x11
++	status = "okay";
++
++};
++
++&emmc {
++
++	status = "okay";
++
++};
++
++&sdmmc {
++
++	status = "okay";
++
++};
++
++&pinctrl {
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&gpio_leds>;
++
++	gpio {
++		gpio_leds: gpio-leds {
++			rockchip,pins = <3 21 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++};

patch/u-boot/u-boot-rk322x/dtsi-add-generic-tvbox.patch

@@ -0,0 +1,157 @@
+diff --git a/arch/arm/dts/rk322x-generic-tvbox.dtsi b/arch/arm/dts/rk322x-generic-tvbox.dtsi
+new file mode 100644
+index 00000000..a9733ebd
+--- /dev/null
++++ b/arch/arm/dts/rk322x-generic-tvbox.dtsi
+@@ -0,0 +1,151 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * (C) Copyright 2019 Paolo Sabatino
++ *
++ * Generic rk322x tv box device tree include file.
++ *
++ * This dtsi covers most of the common hardware included in generic tv boxes around the market.
++ * Include this dtsi in your configuration and make the necessary adjustments there for base support.
++ *
++ */
++
++/dts-v1/;
++
++#include "rk322x.dtsi"
++
++/ {
++
++	chosen {
++		u-boot,dm-pre-reloc;
++		stdout-path = &uart2;
++		u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc;
++	};
++
++	memory@60000000 {
++		device_type = "memory";
++		reg = <0x60000000 0x40000000>;
++	};
++
++        leds: leds {
++                compatible = "gpio-leds";
++
++		/*
++			Main led is available on all boards.
++			Default state is honoured only if led_default_state() is called inside
++			an early init hook function.
++		*/
++                main {
++			label = "heartbeat";
++                        gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
++                        default-state = "on";
++			linux,default-trigger = "heartbeat";
++                };
++
++        };
++
++	vcc_sys: vcc-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc_phy: vcc-phy-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		regulator-name = "vcc_phy";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_otg_vbus: otg-vbus-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
++		regulator-name = "vcc_otg_vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-boot-on;
++		regulator-always-on;
++		enable-active-high;
++		vin-supply = <&vcc_sys>;
++	};
++
++};
++
++&gmac {
++
++	assigned-clocks = <&cru SCLK_MAC_SRC>;
++	assigned-clock-rates = <50000000>;
++
++	clock_in_out = "output";
++	phy-supply = <&vcc_phy>;
++	phy-mode = "rmii";
++	phy-is-integrated;
++
++	tx_delay = < 0x30 >; // Default is 0x30, but original dts proposes 0x26
++	rx_delay = < 0x10 >; // Default is 0x10, but original dts proposes 0x11
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&phy_pins>;
++
++	status = "okay";
++
++};
++
++&emmc {
++
++	u-boot,dm-spl;
++	clock-frequency = <50000000>;
++	clock-freq-min-max = <400000 50000000>;
++	broken-cd;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	supports-emmc;
++	disable-wp;
++	non-removable;
++	/delete-property/ pinctrl-names;
++	/delete-property/ pinctrl-0;
++	status = "okay";
++
++};
++
++&sdmmc {
++
++	u-boot,dm-spl;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	card-detect-delay = <200>;
++	disable-wp;
++	num-slots = <1>;
++	supports-sd;
++
++	status = "okay";
++
++};
++
++&uart2 {
++	u-boot,dm-pre-reloc;
++	status = "okay";
++};
++
++&usb20_otg {
++	vbus-supply = <&vcc_otg_vbus>;
++	status = "okay";
++};
++
++&pinctrl {
++
++	usb {
++		otg_vbus_drv: otg-vbus-drv {
++			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++};

patch/u-boot/u-boot-rk322x/fix-tee-path.patch

@@ -0,0 +1,13 @@
+diff --git a/arch/arm/mach-rockchip/fit_spl_optee.sh b/arch/arm/mach-rockchip/fit_spl_optee.sh
+index 4118472d..b7cbf958 100755
+--- a/arch/arm/mach-rockchip/fit_spl_optee.sh
++++ b/arch/arm/mach-rockchip/fit_spl_optee.sh
+@@ -8,6 +8,8 @@
+ #
+ # usage: $0 <dt_name>
+ 
++TEE="../../../../packages/blobs/rockchip/rk322x_tee.bin"
++
+ [ -z "$TEE" ] && TEE="tee.bin"
+ 
+ if [ ! -f $TEE ]; then

patch/u-boot/u-boot-rk322x/rockchip-device-settings.patch

@@ -0,0 +1,12 @@
+diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
+index 15bb8d63..093db403 100644
+--- a/include/configs/rk322x_common.h
++++ b/include/configs/rk322x_common.h
+@@ -51,6 +51,7 @@
+ 	"fdt_high=0x7fffffff\0" \
+ 	"partitions=" PARTS_DEFAULT \
+ 	ENV_MEM_LAYOUT_SETTINGS \
++	ROCKCHIP_DEVICE_SETTINGS \
+ 	BOOTENV
+ #endif
+ 

patch/u-boot/u-boot-rk322x/u-boot-1000-rockchip.patch

@@ -0,0 +1,452 @@
+From e54b3dfd77c4f72064fd62dd69f8bcc010ed0ef0 Mon Sep 17 00:00:00 2001
+From: Francis Fan <francis.fan@rock-chips.com>
+Date: Tue, 7 Nov 2017 17:50:11 +0800
+Subject: [PATCH 1/3] rockchip: efuse: Support rk322x non-secure efuse.
+
+Change-Id: Ia25df975d21d7c97cf090f0d374074c2c5cd1a58
+Signed-off-by: Francis Fan <francis.fan@rock-chips.com>
+Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
+---
+ drivers/misc/rockchip-efuse.c | 75 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 71 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
+index 2520c6a38e..36edf8d53d 100644
+--- a/drivers/misc/rockchip-efuse.c
++++ b/drivers/misc/rockchip-efuse.c
+@@ -27,6 +27,17 @@
+ #define RK3399_STROBE           BIT(1)
+ #define RK3399_CSB              BIT(0)
+ 
++#define RK3288_A_SHIFT          6
++#define RK3288_A_MASK           0x3ff
++#define RK3288_NFUSES           32
++#define RK3288_BYTES_PER_FUSE   1
++#define RK3288_PGENB            BIT(3)
++#define RK3288_LOAD             BIT(2)
++#define RK3288_STROBE           BIT(1)
++#define RK3288_CSB              BIT(0)
++
++typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
++
+ struct rockchip_efuse_regs {
+ 	u32 ctrl;      /* 0x00  efuse control register */
+ 	u32 dout;      /* 0x04  efuse data out register */
+@@ -53,7 +64,7 @@ static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
+ 	 */
+ 
+ 	struct udevice *dev;
+-	u8 fuses[128];
++	u8 fuses[128] = {0};
+ 	int ret;
+ 
+ 	/* retrieve the device */
+@@ -77,7 +88,7 @@ static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
+ }
+ 
+ U_BOOT_CMD(
+-	rk3399_dump_efuses, 1, 1, dump_efuses,
++	rockchip_dump_efuses, 1, 1, dump_efuses,
+ 	"Dump the content of the efuses",
+ 	""
+ );
+@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
+ 	return 0;
+ }
+ 
++static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
++				      void *buf, int size)
++{
++	struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
++	struct rockchip_efuse_regs *efuse =
++		(struct rockchip_efuse_regs *)plat->base;
++	u8 *buffer = buf;
++	int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
++
++	if (size > (max_size - offset))
++		size = max_size - offset;
++
++	/* Switch to read mode */
++	writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl);
++	udelay(1);
++
++	while (size--) {
++		writel(readl(&efuse->ctrl) &
++				(~(RK3288_A_MASK << RK3288_A_SHIFT)),
++				&efuse->ctrl);
++		/* set addr */
++		writel(readl(&efuse->ctrl) |
++				((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
++				&efuse->ctrl);
++		udelay(1);
++		/* strobe low to high */
++		writel(readl(&efuse->ctrl) |
++				RK3288_STROBE, &efuse->ctrl);
++		ndelay(60);
++		/* read data */
++		*buffer++ = readl(&efuse->dout);
++		/* reset strobe to low */
++		writel(readl(&efuse->ctrl) &
++				(~RK3288_STROBE), &efuse->ctrl);
++		udelay(1);
++	}
++
++	/* Switch to standby mode */
++	writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl);
++
++	return 0;
++}
++
+ static int rockchip_efuse_read(struct udevice *dev, int offset,
+ 			       void *buf, int size)
+ {
+-	return rockchip_rk3399_efuse_read(dev, offset, buf, size);
++	EFUSE_READ efuse_read = NULL;
++
++	efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
++	if (!efuse_read)
++		return -ENOSYS;
++
++	return (*efuse_read)(dev, offset, buf, size);
+ }
+ 
+ static const struct misc_ops rockchip_efuse_ops = {
+@@ -146,7 +206,14 @@ static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev)
+ }
+ 
+ static const struct udevice_id rockchip_efuse_ids[] = {
+-	{ .compatible = "rockchip,rk3399-efuse" },
++	{
++		.compatible = "rockchip,rk3288-efuse",
++		.data = (ulong)&rockchip_rk3288_efuse_read,
++	},
++	{
++		.compatible = "rockchip,rk3399-efuse",
++		.data = (ulong)&rockchip_rk3399_efuse_read,
++	},
+ 	{}
+ };
+ 
+
+From d2794118b9ddbe8e76da4249d2de393476337e5b Mon Sep 17 00:00:00 2001
+From: Joseph Chen <chenjh@rock-chips.com>
+Date: Thu, 2 Aug 2018 20:33:16 +0800
+Subject: [PATCH 2/3] rockchip: efuse: support rk3328 non-secure efuse
+
+Change-Id: Ie74764ef946b79c2e9f73e9082c1cb8bbc288abb
+Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
+---
+ drivers/misc/rockchip-efuse.c | 66 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 66 insertions(+)
+
+diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
+index 36edf8d53d..f2d362cef8 100644
+--- a/drivers/misc/rockchip-efuse.c
++++ b/drivers/misc/rockchip-efuse.c
+@@ -36,6 +36,13 @@
+ #define RK3288_STROBE           BIT(1)
+ #define RK3288_CSB              BIT(0)
+ 
++#define RK3328_INT_STATUS	0x0018
++#define RK3328_DOUT		0x0020
++#define RK3328_AUTO_CTRL	0x0024
++#define RK3328_INT_FINISH	BIT(0)
++#define RK3328_AUTO_ENB		BIT(0)
++#define RK3328_AUTO_RD		BIT(1)
++
+ typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
+ 
+ struct rockchip_efuse_regs {
+@@ -46,6 +53,10 @@ struct rockchip_efuse_regs {
+ 	u32 jtag_pass; /* 0x10  JTAG password */
+ 	u32 strobe_finish_ctrl;
+ 		       /* 0x14	efuse strobe finish control register */
++	u32 int_status;/* 0x18 */
++	u32 reserved;  /* 0x1c */
++	u32 dout2;     /* 0x20 */
++	u32 auto_ctrl; /* 0x24 */
+ };
+ 
+ struct rockchip_efuse_platdata {
+@@ -181,6 +192,57 @@ static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
+ 	return 0;
+ }
+ 
++static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
++				      void *buf, int size)
++{
++	struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
++	struct rockchip_efuse_regs *efuse =
++		(struct rockchip_efuse_regs *)plat->base;
++	unsigned int addr_start, addr_end, addr_offset, addr_len;
++	u32 out_value, status;
++	u8 *buffer;
++	int ret = 0, i = 0, j = 0;
++
++	/* Max non-secure Byte */
++	if (size > 32)
++		size = 32;
++
++	/* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
++	offset += 96;
++	addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) /
++						RK3399_BYTES_PER_FUSE;
++	addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) /
++						RK3399_BYTES_PER_FUSE;
++	addr_offset = offset % RK3399_BYTES_PER_FUSE;
++	addr_len = addr_end - addr_start;
++
++	buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE);
++	if (!buffer)
++		return -ENOMEM;
++
++	for (j = 0; j < addr_len; j++) {
++		writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
++		       ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
++		         &efuse->auto_ctrl);
++		udelay(5);
++		status = readl(&efuse->int_status);
++		if (!(status & RK3328_INT_FINISH)) {
++			ret = -EIO;
++			goto err;
++		}
++		out_value = readl(&efuse->dout2);
++		writel(RK3328_INT_FINISH, &efuse->int_status);
++
++		memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE);
++		i += RK3399_BYTES_PER_FUSE;
++	}
++	memcpy(buf, buffer + addr_offset, size);
++err:
++	free(buffer);
++
++	return ret;
++}
++
+ static int rockchip_efuse_read(struct udevice *dev, int offset,
+ 			       void *buf, int size)
+ {
+@@ -210,6 +272,10 @@ static const struct udevice_id rockchip_efuse_ids[] = {
+ 		.compatible = "rockchip,rk3288-efuse",
+ 		.data = (ulong)&rockchip_rk3288_efuse_read,
+ 	},
++	{
++		.compatible = "rockchip,rk3328-efuse",
++		.data = (ulong)&rockchip_rk3328_efuse_read,
++	},
+ 	{
+ 		.compatible = "rockchip,rk3399-efuse",
+ 		.data = (ulong)&rockchip_rk3399_efuse_read,
+
+From 81fd1a75139801213cd29af46df7b282648f4559 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 23 Jan 2020 21:09:38 +0000
+Subject: [PATCH 3/3] WIP: rockchip: get serial and ethaddr from efuse
+
+---
+ arch/arm/dts/rk3288.dtsi          |  3 +--
+ arch/arm/dts/rk3328.dtsi          | 14 ++++++++++++++
+ configs/evb-rk3328_defconfig      |  3 +++
+ configs/evb-rk3399_defconfig      |  2 ++
+ configs/miqi-rk3288_defconfig     |  2 ++
+ configs/rock64-rk3328_defconfig   |  2 ++
+ configs/tinker-rk3288_defconfig   |  1 +
+ configs/tinker-s-rk3288_defconfig |  1 +
+ 8 files changed, 26 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
+index 866fc08215..b0d1b2f90a 100644
+--- a/arch/arm/dts/rk3288.dtsi
++++ b/arch/arm/dts/rk3288.dtsi
+@@ -910,8 +910,7 @@
+ 
+ 	efuse: efuse@ffb40000 {
+ 		compatible = "rockchip,rk3288-efuse";
+-		reg = <0xffb40000 0x10000>;
+-		status = "disabled";
++		reg = <0xffb40000 0x20>;
+ 	};
+ 
+ 	gic: interrupt-controller@ffc01000 {
+diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
+index 060c84e6c0..34c0b7de41 100644
+--- a/arch/arm/dts/rk3328.dtsi
++++ b/arch/arm/dts/rk3328.dtsi
+@@ -337,6 +337,20 @@
+ 		};
+ 	};
+ 
++	efuse: efuse@ff260000 {
++		compatible = "rockchip,rk3328-efuse";
++		reg = <0x0 0xff260000 0x0 0x80>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		clocks = <&cru SCLK_EFUSE>;
++		clock-names = "pclk_efuse";
++
++		/* Data cells */
++		cpu_id: cpu-id@7 {
++			reg = <0x07 0x10>;
++		};
++	};
++
+ 	saradc: saradc@ff280000 {
+ 		compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
+ 		reg = <0x0 0xff280000 0x0 0x100>;
+diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
+index 3db40a9a1a..edd1c41f09 100644
+--- a/configs/evb-rk3328_defconfig
++++ b/configs/evb-rk3328_defconfig
+@@ -19,6 +19,7 @@ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_SPL_LOAD_FIT=y
+ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
++CONFIG_MISC_INIT_R=y
+ # CONFIG_DISPLAY_CPUINFO is not set
+ CONFIG_DISPLAY_BOARDINFO_LATE=y
+ # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+@@ -55,6 +56,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_SF_DEFAULT_SPEED=20000000
+diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
+index 8b8cdc5109..71c2daf8f5 100644
+--- a/configs/evb-rk3399_defconfig
++++ b/configs/evb-rk3399_defconfig
+@@ -28,6 +28,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+ CONFIG_NET_RANDOM_ETHADDR=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_ROCKCHIP=y
+diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
+index cec8e42c5e..ac05d35392 100644
+--- a/configs/miqi-rk3288_defconfig
++++ b/configs/miqi-rk3288_defconfig
+@@ -50,6 +50,8 @@ CONFIG_SPL_CLK=y
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_MTD=y
+diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
+index 720b5e0424..c849bc4939 100644
+--- a/configs/rock64-rk3328_defconfig
++++ b/configs/rock64-rk3328_defconfig
+@@ -54,6 +54,8 @@ CONFIG_FASTBOOT_BUF_ADDR=0x800800
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_SF_DEFAULT_SPEED=20000000
+diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
+index 83c3450839..d586b509f6 100644
+--- a/configs/tinker-rk3288_defconfig
++++ b/configs/tinker-rk3288_defconfig
+@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_I2C_EEPROM=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
+index 4925b14821..91dcc76564 100644
+--- a/configs/tinker-s-rk3288_defconfig
++++ b/configs/tinker-s-rk3288_defconfig
+@@ -53,6 +53,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
+ CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_I2C_EEPROM=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
+index 1217d5239f..2904303034 100644
+--- a/include/dt-bindings/clock/rk3228-cru.h
++++ b/include/dt-bindings/clock/rk3228-cru.h
+@@ -67,6 +67,10 @@
+ #define PCLK_GPIO1		321
+ #define PCLK_GPIO2		322
+ #define PCLK_GPIO3		323
++#define PCLK_VIO_H2P		324
++#define PCLK_HDCP		325
++#define PCLK_EFUSE_1024	326
++#define PCLK_EFUSE_256 	327
+ #define PCLK_GRF		329
+ #define PCLK_I2C0		332
+ #define PCLK_I2C1		333
+diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
+index 4a8be5dabb..255e3a7a28 100644
+--- a/arch/arm/dts/rk322x.dtsi
++++ b/arch/arm/dts/rk322x.dtsi
+@@ -212,6 +212,20 @@
+ 		status = "disabled";
+ 	};
+ 
++	efuse: efuse@11040000 {
++		compatible = "rockchip,rk3228-efuse", "rockchip,rk3288-efuse";
++		reg = <0x11040000 0x20>;
++		clocks = <&cru PCLK_EFUSE_256>;
++		clock-names = "pclk_efuse";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		/* Data cells */
++		cpu_id: cpu_id@7 {
++			reg = <0x7 0x10>;
++		};
++	};
++
+ 	i2c0: i2c@11050000 {
+ 		compatible = "rockchip,rk3228-i2c";
+ 		reg = <0x11050000 0x1000>;
+diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
+index 6b302e987c..3c0b82df1c 100644
+--- a/configs/evb-rk3229_defconfig
++++ b/configs/evb-rk3229_defconfig
+@@ -32,6 +32,7 @@ CONFIG_CMD_TIME=y
+ CONFIG_SPL_OF_CONTROL=y
+ CONFIG_TPL_OF_CONTROL=y
+ CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
++CONFIG_MISC_INIT_R=y
+ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+ CONFIG_ENV_IS_IN_MMC=y
+ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+@@ -49,6 +50,8 @@ CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+ CONFIG_ROCKCHIP_GPIO=y
+ CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MISC=y
++CONFIG_ROCKCHIP_EFUSE=y
+ CONFIG_MMC_DW=y
+ CONFIG_MMC_DW_ROCKCHIP=y
+ CONFIG_MTD=y
+diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
+index f2d362ce..2aa9373f 100644
+--- a/drivers/misc/rockchip-efuse.c
++++ b/drivers/misc/rockchip-efuse.c
+@@ -14,6 +14,7 @@
+ #include <linux/bitops.h>
+ #include <linux/delay.h>
+ #include <misc.h>
++#include <stdlib.h>
+ 
+ #define RK3399_A_SHIFT          16
+ #define RK3399_A_MASK           0x3ff

patch/u-boot/u-boot-rk322x/u-boot-1001-rockchip-rmii-integrated-phy.patch

@@ -0,0 +1,902 @@
+diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
+index 632cdc9bc3..f868524ae1 100644
+--- a/arch/arm/dts/rk3229-evb.dts
++++ b/arch/arm/dts/rk3229-evb.dts
+@@ -50,19 +50,25 @@
+ };
+ 
+ &gmac {
+-	assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+-	assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+-	clock_in_out = "input";
+-	phy-supply = <&vcc_phy>;
+-	phy-mode = "rgmii";
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&rgmii_pins>;
+-	snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
+-	snps,reset-active-low;
+-	snps,reset-delays-us = <0 10000 1000000>;
+-	tx_delay = <0x30>;
+-	rx_delay = <0x10>;
+-	status = "okay";
++        assigned-clocks = <&cru SCLK_MAC_SRC>;
++        assigned-clock-rates = <50000000>;
++        clock_in_out = "output";
++        phy-supply = <&vcc_phy>;
++        phy-mode = "rmii";
++        phy-handle = <&phy>;
++        status = "okay";
++
++        mdio {
++                compatible = "snps,dwmac-mdio";
++                #address-cells = <1>;
++                #size-cells = <0>;
++
++                phy: phy@0 {
++                        compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
++                        reg = <0>;
++                        phy-is-integrated;
++                };
++        };
+ };
+ 
+ &emmc {
+diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
+index 4a8be5dabb..3c2861f271 100644
+--- a/arch/arm/dts/rk322x.dtsi
++++ b/arch/arm/dts/rk322x.dtsi
+@@ -448,13 +448,13 @@
+ 		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ 			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
+ 			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+-			<&cru PCLK_GMAC>;
++			<&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>;
+ 		clock-names = "stmmaceth", "mac_clk_rx",
+ 			"mac_clk_tx", "clk_mac_ref",
+ 			"clk_mac_refout", "aclk_mac",
+-			"pclk_mac";
+-		resets = <&cru SRST_GMAC>;
+-		reset-names = "stmmaceth";
++			"pclk_mac", "clk_macphy";
++		resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>;
++		reset-names = "stmmaceth", "mac-phy";
+ 		rockchip,grf = <&grf>;
+ 		status = "disabled";
+ 	};
+diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
+index a2ee838fcd..704712a05e 100644
+--- a/arch/arm/dts/rk3328-evb.dts
++++ b/arch/arm/dts/rk3328-evb.dts
+@@ -100,6 +100,16 @@
+ 	pinctrl-0 = <&rgmiim1_pins>;
+ 	tx_delay = <0x26>;
+ 	rx_delay = <0x11>;
++	status = "disabled";
++};
++
++&gmac2phy {
++	phy-supply = <&vcc_phy>;
++	clock_in_out = "output";
++	assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
++	assigned-clock-rate = <50000000>;
++	assigned-clocks = <&cru SCLK_MAC2PHY>;
++	assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ 	status = "okay";
+ };
+ 
+diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
+index 060c84e6c0..c9419db07f 100644
+--- a/arch/arm/dts/rk3328.dtsi
++++ b/arch/arm/dts/rk3328.dtsi
+@@ -464,6 +464,41 @@
+ 		status = "disabled";
+ 	};
+ 
++	gmac2phy: ethernet@ff550000 {
++		compatible = "rockchip,rk3328-gmac";
++		reg = <0x0 0xff550000 0x0 0x10000>;
++		rockchip,grf = <&grf>;
++		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "macirq";
++		clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
++			 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
++			 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
++			 <&cru SCLK_MAC2PHY_OUT>;
++		clock-names = "stmmaceth", "mac_clk_rx",
++			      "mac_clk_tx", "clk_mac_ref",
++			      "aclk_mac", "pclk_mac",
++			      "clk_macphy";
++		resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
++		reset-names = "stmmaceth", "mac-phy";
++		phy-mode = "rmii";
++		phy-handle = <&phy>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
++		status = "disabled";
++
++		mdio {
++			compatible = "snps,dwmac-mdio";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			phy: phy@0 {
++				compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
++				reg = <0>;
++				phy-is-integrated;
++			};
++		};
++	};
++
+ 	usb_host0_ehci: usb@ff5c0000 {
+ 		compatible = "generic-ehci";
+ 		reg = <0x0 0xff5c0000 0x0 0x10000>;
+diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
+index c87c830716..15039c87be 100644
+--- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
++++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
+@@ -12,6 +12,7 @@
+ 
+ #define APLL_HZ		(600 * MHz)
+ #define GPLL_HZ		(594 * MHz)
++#define CPLL_HZ		(500 * MHz)
+ 
+ #define CORE_PERI_HZ	150000000
+ #define CORE_ACLK_HZ	300000000
+diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
+index f8e648bbb4..5fd2bd3ba2 100644
+--- a/configs/evb-rk3229_defconfig
++++ b/configs/evb-rk3229_defconfig
+@@ -58,6 +58,8 @@ CONFIG_GMAC_ROCKCHIP=y
+ CONFIG_PHY=y
+ CONFIG_PINCTRL=y
+ CONFIG_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_RESET_ROCKCHIP=y
+ CONFIG_SPL_RAM=y
+ CONFIG_TPL_RAM=y
+ CONFIG_BAUDRATE=1500000
+diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
+index 5bbdc00214..19c09e4503 100644
+--- a/configs/evb-rk3328_defconfig
++++ b/configs/evb-rk3328_defconfig
+@@ -71,6 +71,8 @@ CONFIG_DM_REGULATOR_FIXED=y
+ CONFIG_REGULATOR_RK8XX=y
+ CONFIG_PWM_ROCKCHIP=y
+ CONFIG_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_RESET_ROCKCHIP=y
+ CONFIG_SPL_RAM=y
+ CONFIG_TPL_RAM=y
+ CONFIG_BAUDRATE=1500000
+diff --git a/doc/device-tree-bindings/net/phy.txt b/doc/device-tree-bindings/net/phy.txt
+index 6599c667b5..ca1a4a8526 100644
+--- a/doc/device-tree-bindings/net/phy.txt
++++ b/doc/device-tree-bindings/net/phy.txt
+@@ -8,6 +8,19 @@ Required properties:
+ 
+  - reg : The ID number for the phy, usually a small integer
+ 
++Optional Properties:
++
++- compatible: Compatible list, may contain
++  "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
++  PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
++  specifications. If neither of these are specified, the default is to
++  assume clause 22.
++
++- phy-is-integrated: If set, indicates that the PHY is integrated into the same
++  physical package as the Ethernet MAC. If needed, muxers should be configured
++  to ensure the integrated PHY is used. The absence of this property indicates
++  the muxers should be configured so that the external PHY is used.
++
+ Example:
+ 
+ ethernet-phy@0 {
+diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
+index ef33adbf29..c427e0438b 100644
+--- a/drivers/clk/rockchip/clk_rk322x.c
++++ b/drivers/clk/rockchip/clk_rk322x.c
+@@ -38,6 +38,7 @@ enum {
+ /* use integer mode*/
+ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
++static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 3, 1);
+ 
+ static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
+ 			 const struct pll_div *div)
+@@ -87,11 +88,13 @@ static void rkclk_init(struct rk322x_cru *cru)
+ 	rk_clrsetreg(&cru->cru_mode_con,
+ 		     GPLL_MODE_MASK | APLL_MODE_MASK,
+ 		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+-		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
++		     APLL_MODE_SLOW << APLL_MODE_SHIFT |
++		     CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
+ 
+ 	/* init pll */
+ 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
+ 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
++	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
+ 
+ 	/*
+ 	 * select apll as cpu/core clock pll source and
+@@ -164,7 +167,8 @@ static void rkclk_init(struct rk322x_cru *cru)
+ 	rk_clrsetreg(&cru->cru_mode_con,
+ 		     GPLL_MODE_MASK | APLL_MODE_MASK,
+ 		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
+-		     APLL_MODE_NORM << APLL_MODE_SHIFT);
++		     APLL_MODE_NORM << APLL_MODE_SHIFT |
++		     CPLL_MODE_NORM << CPLL_MODE_SHIFT);
+ }
+ 
+ /* Get pll rate by id */
+@@ -254,11 +258,10 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
+ 		ulong pll_rate;
+ 		u8 div;
+ 
+-		if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
++		if (con & MAC_PLL_SEL_MASK)
+ 			pll_rate = GPLL_HZ;
+ 		else
+-			/* CPLL is not set */
+-			return -EPERM;
++			pll_rate = CPLL_HZ;
+ 
+ 		div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ 		if (div <= 0x1f)
+@@ -387,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
+ 	case CLK_DDR:
+ 		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
+ 		break;
++	case SCLK_MAC_SRC:
+ 	case SCLK_MAC:
+ 		new_rate = rk322x_mac_set_clk(priv->cru, rate);
+ 		break;
+diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
+index 8e867c58df..ba2b34c626 100644
+--- a/drivers/clk/rockchip/clk_rk3328.c
++++ b/drivers/clk/rockchip/clk_rk3328.c
+@@ -93,6 +93,14 @@ enum {
+ 	PCLK_DBG_DIV_SHIFT		= 0,
+ 	PCLK_DBG_DIV_MASK		= 0xF << PCLK_DBG_DIV_SHIFT,
+ 
++	/* CLKSEL_CON26 */
++	GMAC2PHY_PLL_SEL_SHIFT          = 7,
++	GMAC2PHY_PLL_SEL_MASK           = 1 << GMAC2PHY_PLL_SEL_SHIFT,
++	GMAC2PHY_PLL_SEL_CPLL           = 0,
++	GMAC2PHY_PLL_SEL_GPLL           = 1,
++	GMAC2PHY_CLK_DIV_MASK           = 0x1f,
++	GMAC2PHY_CLK_DIV_SHIFT          = 0,
++
+ 	/* CLKSEL_CON27 */
+ 	GMAC2IO_PLL_SEL_SHIFT		= 7,
+ 	GMAC2IO_PLL_SEL_MASK		= 1 << GMAC2IO_PLL_SEL_SHIFT,
+@@ -440,6 +448,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
+ 	return ret;
+ }
+ 
++static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate)
++{
++	u32 con = readl(&cru->clksel_con[26]);
++	ulong pll_rate;
++	u8 div;
++
++	if ((con >> GMAC2PHY_PLL_SEL_SHIFT) & GMAC2PHY_PLL_SEL_GPLL)
++		pll_rate = GPLL_HZ;
++	else
++		pll_rate = CPLL_HZ;
++
++	div = DIV_ROUND_UP(pll_rate, rate) - 1;
++	if (div <= 0x1f)
++		rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK,
++			     div << GMAC2PHY_CLK_DIV_SHIFT);
++	else
++		debug("Unsupported div for gmac:%d\n", div);
++
++	return DIV_TO_RATE(pll_rate, div);
++}
++
++static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate)
++{
++	struct rk3328_grf_regs *grf;
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	if (readl(&grf->mac_con[2]) & BIT(10))
++		/* An external clock will always generate the right rate... */
++		return rate;
++	else
++		return rk3328_gmac2phy_src_set_clk(cru, rate);
++}
++
+ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
+ {
+ 	u32 div, con, con_id;
+@@ -608,6 +649,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
+ 	case SCLK_MAC2IO:
+ 		ret = rk3328_gmac2io_set_clk(priv->cru, rate);
+ 		break;
++	case SCLK_MAC2PHY:
++		ret = rk3328_gmac2phy_set_clk(priv->cru, rate);
++		break;
++	case SCLK_MAC2PHY_SRC:
++		ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate);
++		break;
+ 	case SCLK_PWM:
+ 		ret = rk3328_pwm_set_clk(priv->cru, rate);
+ 		break;
+@@ -728,6 +775,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
+ 	return -EINVAL;
+ }
+ 
++static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent)
++{
++	struct rk3328_grf_regs *grf;
++	const char *clock_output_name;
++	int ret;
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++
++	/*
++	 * If the requested parent is in the same clock-controller and the id
++	 * is SCLK_MAC2PHY_SRC ("clk_mac2phy_src"), switch to the internal clock.
++	 */
++	if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) {
++		debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__);
++		rk_clrreg(&grf->mac_con[2], BIT(10));
++		return 0;
++	}
++
++	/*
++	 * Otherwise, we need to check the clock-output-names of the
++	 * requested parent to see if the requested id is "phy_50m_out".
++	 */
++	ret = dev_read_string_index(parent->dev, "clock-output-names",
++				    parent->id, &clock_output_name);
++	if (ret < 0)
++		return -ENODATA;
++
++	/* If this is "phy_50m_out", switch to the external clock input */
++	if (!strcmp(clock_output_name, "phy_50m_out")) {
++		debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__);
++		rk_setreg(&grf->mac_con[2], BIT(10));
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
+ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
+ {
+ 	switch (clk->id) {
+@@ -735,6 +819,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
+ 		return rk3328_gmac2io_set_parent(clk, parent);
+ 	case SCLK_MAC2IO_EXT:
+ 		return rk3328_gmac2io_ext_set_parent(clk, parent);
++	case SCLK_MAC2PHY:
++		return rk3328_gmac2phy_set_parent(clk, parent);
+ 	case DCLK_LCDC:
+ 	case SCLK_PDM:
+ 	case SCLK_RTC32K:
+diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
+index e152faf083..d3f6973043 100644
+--- a/drivers/net/gmac_rockchip.c
++++ b/drivers/net/gmac_rockchip.c
+@@ -9,6 +9,7 @@
+ #include <dm.h>
+ #include <clk.h>
+ #include <phy.h>
++#include <reset.h>
+ #include <syscon.h>
+ #include <asm/io.h>
+ #include <asm/arch-rockchip/periph.h>
+@@ -23,6 +24,7 @@
+ #include <asm/arch-rockchip/grf_rk3399.h>
+ #include <asm/arch-rockchip/grf_rv1108.h>
+ #include <dm/pinctrl.h>
++#include <dm/of_access.h>
+ #include <dt-bindings/clock/rk3288-cru.h>
+ #include "designware.h"
+ 
+@@ -39,21 +41,29 @@ DECLARE_GLOBAL_DATA_PTR;
+ struct gmac_rockchip_platdata {
+ 	struct dw_eth_pdata dw_eth_pdata;
+ 	bool clock_input;
++	bool integrated_phy;
++	struct reset_ctl phy_reset;
+ 	int tx_delay;
+ 	int rx_delay;
+ };
+ 
+ struct rk_gmac_ops {
+-	int (*fix_mac_speed)(struct dw_eth_dev *priv);
++	int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
++			      struct dw_eth_dev *priv);
++	int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
++			       struct dw_eth_dev *priv);
+ 	void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
+ 	void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
++	void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata);
+ };
+ 
+ 
+ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+ {
+ 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
++	struct ofnode_phandle_args args;
+ 	const char *string;
++	int ret;
+ 
+ 	string = dev_read_string(dev, "clock_in_out");
+ 	if (!strcmp(string, "input"))
+@@ -61,6 +71,25 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+ 	else
+ 		pdata->clock_input = false;
+ 
++	/* If phy-handle property is passed from DT, use it as the PHY */
++	ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args);
++	if (ret) {
++		debug("Cannot get phy phandle: ret=%d\n", ret);
++		pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated");
++	} else {
++		debug("Found phy-handle subnode\n");
++		pdata->integrated_phy = ofnode_read_bool(args.node,
++							 "phy-is-integrated");
++	}
++
++	if (pdata->integrated_phy) {
++		ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset);
++		if (ret) {
++			debug("No PHY reset control found: ret=%d\n", ret);
++			return ret;
++		}
++	}
++
+ 	/* Check the new naming-style first... */
+ 	pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
+ 	pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
+@@ -74,7 +103,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
+ 	return designware_eth_ofdata_to_platdata(dev);
+ }
+ 
+-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
++				      struct dw_eth_dev *priv)
+ {
+ 	struct px30_grf *grf;
+ 	struct clk clk_speed;
+@@ -115,7 +145,43 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
++				      struct dw_eth_dev *priv)
++{
++	struct rk322x_grf *grf;
++	int clk;
++	enum {
++		RK3228_GMAC_RMII_CLK_MASK   = BIT(7),
++		RK3228_GMAC_RMII_CLK_2_5M   = 0,
++		RK3228_GMAC_RMII_CLK_25M    = BIT(7),
++
++		RK3228_GMAC_RMII_SPEED_MASK = BIT(2),
++		RK3228_GMAC_RMII_SPEED_10   = 0,
++		RK3228_GMAC_RMII_SPEED_100  = BIT(2),
++	};
++
++	switch (priv->phydev->speed) {
++	case 10:
++		clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10;
++		break;
++	case 100:
++		clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100;
++		break;
++	default:
++		debug("Unknown phy speed: %d\n", priv->phydev->speed);
++		return -EINVAL;
++	}
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	rk_clrsetreg(&grf->mac_con[1],
++		     RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK,
++		     clk);
++
++	return 0;
++}
++
++static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rk322x_grf *grf;
+ 	int clk;
+@@ -148,7 +214,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rk3288_grf *grf;
+ 	int clk;
+@@ -174,7 +241,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rk3308_grf *grf;
+ 	struct clk clk_speed;
+@@ -215,7 +283,43 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
++				      struct dw_eth_dev *priv)
++{
++	struct rk3328_grf_regs *grf;
++	int clk;
++	enum {
++		RK3328_GMAC_RMII_CLK_MASK   = BIT(7),
++		RK3328_GMAC_RMII_CLK_2_5M   = 0,
++		RK3328_GMAC_RMII_CLK_25M    = BIT(7),
++
++		RK3328_GMAC_RMII_SPEED_MASK = BIT(2),
++		RK3328_GMAC_RMII_SPEED_10   = 0,
++		RK3328_GMAC_RMII_SPEED_100  = BIT(2),
++	};
++
++	switch (priv->phydev->speed) {
++	case 10:
++		clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10;
++		break;
++	case 100:
++		clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100;
++		break;
++	default:
++		debug("Unknown phy speed: %d\n", priv->phydev->speed);
++		return -EINVAL;
++	}
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1],
++		     RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK,
++		     clk);
++
++	return 0;
++}
++
++static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rk3328_grf_regs *grf;
+ 	int clk;
+@@ -248,7 +352,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rk3368_grf *grf;
+ 	int clk;
+@@ -280,7 +385,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
++static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rk3399_grf_regs *grf;
+ 	int clk;
+@@ -306,7 +412,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+ 	return 0;
+ }
+ 
+-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
++static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
++				       struct dw_eth_dev *priv)
+ {
+ 	struct rv1108_grf *grf;
+ 	int clk, speed;
+@@ -357,6 +464,28 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+ 		     PX30_GMAC_PHY_INTF_SEL_RMII);
+ }
+ 
++static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
++{
++	struct rk322x_grf *grf;
++	enum {
++		RK3228_GRF_CON_RMII_MODE_MASK = BIT(11),
++		RK3228_GRF_CON_RMII_MODE_SEL = BIT(11),
++		RK3228_RMII_MODE_MASK = BIT(10),
++		RK3228_RMII_MODE_SEL = BIT(10),
++		RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
++		RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6),
++	};
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	rk_clrsetreg(&grf->mac_con[1],
++		     RK3228_GRF_CON_RMII_MODE_MASK |
++		     RK3228_RMII_MODE_MASK |
++		     RK3228_GMAC_PHY_INTF_SEL_MASK,
++		     RK3228_GRF_CON_RMII_MODE_SEL |
++		     RK3228_RMII_MODE_SEL |
++		     RK3228_GMAC_PHY_INTF_SEL_RMII);
++}
++
+ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+ {
+ 	struct rk322x_grf *grf;
+@@ -435,6 +564,25 @@ static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+ 		     RK3308_GMAC_PHY_INTF_SEL_RMII);
+ }
+ 
++static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
++{
++	struct rk3328_grf_regs *grf;
++	enum {
++		RK3328_RMII_MODE_MASK  = BIT(9),
++		RK3328_RMII_MODE = BIT(9),
++
++		RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
++		RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6),
++	};
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1],
++		     RK3328_RMII_MODE_MASK |
++		     RK3328_GMAC_PHY_INTF_SEL_MASK,
++		     RK3328_GMAC_PHY_INTF_SEL_RMII |
++		     RK3328_RMII_MODE);
++}
++
+ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+ {
+ 	struct rk3328_grf_regs *grf;
+@@ -550,6 +698,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+ 		     RV1108_GMAC_PHY_INTF_SEL_RMII);
+ }
+ 
++static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
++{
++	struct rk322x_grf *grf;
++	enum {
++		RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15),
++		RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15),
++	};
++	enum {
++		RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14),
++		RK3228_MACPHY_CFG_CLK_50M = BIT(14),
++
++		RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6),
++		RK3228_MACPHY_RMII_MODE = BIT(6),
++
++		RK3228_MACPHY_ENABLE_MASK = BIT(0),
++		RK3228_MACPHY_DISENABLE = 0,
++		RK3228_MACPHY_ENABLE = BIT(0),
++	};
++	enum {
++		RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0),
++		RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234,
++	};
++	enum {
++		RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0),
++		RK3228_RK_GRF_CON3_MACPHY_ID = 0x35,
++	};
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	rk_clrsetreg(&grf->con_iomux,
++		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK,
++		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
++
++	rk_clrsetreg(&grf->macphy_con[2],
++		     RK3228_RK_GRF_CON2_MACPHY_ID_MASK,
++		     RK3228_RK_GRF_CON2_MACPHY_ID);
++
++	rk_clrsetreg(&grf->macphy_con[3],
++		     RK3228_RK_GRF_CON3_MACPHY_ID_MASK,
++		     RK3228_RK_GRF_CON3_MACPHY_ID);
++
++	/* disabled before trying to reset it */
++	rk_clrsetreg(&grf->macphy_con[0],
++		     RK3228_MACPHY_CFG_CLK_50M_MASK |
++		     RK3228_MACPHY_RMII_MODE_MASK |
++		     RK3228_MACPHY_ENABLE_MASK,
++		     RK3228_MACPHY_CFG_CLK_50M |
++		     RK3228_MACPHY_RMII_MODE |
++		     RK3228_MACPHY_DISENABLE);
++
++	reset_assert(&pdata->phy_reset);
++	udelay(10);
++	reset_deassert(&pdata->phy_reset);
++	udelay(10);
++
++	rk_clrsetreg(&grf->macphy_con[0],
++		     RK3228_MACPHY_ENABLE_MASK,
++		     RK3228_MACPHY_ENABLE);
++	udelay(30 * 1000);
++}
++
++static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
++{
++	struct rk3328_grf_regs *grf;
++	enum {
++		RK3328_GRF_CON_RMII_MODE_MASK = BIT(9),
++		RK3328_GRF_CON_RMII_MODE = BIT(9),
++	};
++	enum {
++		RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14),
++		RK3328_MACPHY_CFG_CLK_50M = BIT(14),
++
++		RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6),
++		RK3328_MACPHY_RMII_MODE = BIT(6),
++
++		RK3328_MACPHY_ENABLE_MASK = BIT(0),
++		RK3328_MACPHY_DISENABLE = 0,
++		RK3328_MACPHY_ENABLE = BIT(0),
++	};
++	enum {
++		RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0),
++		RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234,
++	};
++	enum {
++		RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0),
++		RK3328_RK_GRF_CON3_MACPHY_ID = 0x35,
++	};
++
++	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
++	rk_clrsetreg(&grf->macphy_con[1],
++		     RK3328_GRF_CON_RMII_MODE_MASK,
++		     RK3328_GRF_CON_RMII_MODE);
++
++	rk_clrsetreg(&grf->macphy_con[2],
++		     RK3328_RK_GRF_CON2_MACPHY_ID_MASK,
++		     RK3328_RK_GRF_CON2_MACPHY_ID);
++
++	rk_clrsetreg(&grf->macphy_con[3],
++		     RK3328_RK_GRF_CON3_MACPHY_ID_MASK,
++		     RK3328_RK_GRF_CON3_MACPHY_ID);
++
++	/* disabled before trying to reset it */
++	rk_clrsetreg(&grf->macphy_con[0],
++		     RK3328_MACPHY_CFG_CLK_50M_MASK |
++		     RK3328_MACPHY_RMII_MODE_MASK |
++		     RK3328_MACPHY_ENABLE_MASK,
++		     RK3328_MACPHY_CFG_CLK_50M |
++		     RK3328_MACPHY_RMII_MODE |
++		     RK3328_MACPHY_DISENABLE);
++
++	reset_assert(&pdata->phy_reset);
++	udelay(10);
++	reset_deassert(&pdata->phy_reset);
++	udelay(10);
++
++	rk_clrsetreg(&grf->macphy_con[0],
++		     RK3328_MACPHY_ENABLE_MASK,
++		     RK3328_MACPHY_ENABLE);
++	udelay(30 * 1000);
++}
++
+ static int gmac_rockchip_probe(struct udevice *dev)
+ {
+ 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+@@ -569,6 +837,9 @@ static int gmac_rockchip_probe(struct udevice *dev)
+ 	if (ret)
+ 		return ret;
+ 
++	if (pdata->integrated_phy && ops->integrated_phy_powerup)
++		ops->integrated_phy_powerup(pdata);
++
+ 	switch (eth_pdata->phy_interface) {
+ 	case PHY_INTERFACE_MODE_RGMII:
+ 		/* Set to RGMII mode */
+@@ -652,7 +923,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
+ 		break;
+ 
+ 	default:
+-		debug("NO interface defined!\n");
++		debug("%s: no interface defined!\n", __func__);
+ 		return -ENXIO;
+ 	}
+ 
+@@ -661,18 +932,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
+ 
+ static int gmac_rockchip_eth_start(struct udevice *dev)
+ {
+-	struct eth_pdata *pdata = dev_get_platdata(dev);
++	struct eth_pdata *eth_pdata = dev_get_platdata(dev);
+ 	struct dw_eth_dev *priv = dev_get_priv(dev);
+ 	struct rk_gmac_ops *ops =
+ 		(struct rk_gmac_ops *)dev_get_driver_data(dev);
++	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ 	int ret;
+ 
+-	ret = designware_eth_init(priv, pdata->enetaddr);
+-	if (ret)
+-		return ret;
+-	ret = ops->fix_mac_speed(priv);
++	ret = designware_eth_init(priv, eth_pdata->enetaddr);
+ 	if (ret)
+ 		return ret;
++
++	switch (eth_pdata->phy_interface) {
++	case PHY_INTERFACE_MODE_RGMII:
++		ret = ops->fix_rgmii_speed(pdata, priv);
++		if (ret)
++			return ret;
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		ret = ops->fix_rmii_speed(pdata, priv);
++		if (ret)
++			return ret;
++		break;
++	default:
++		debug("%s: no interface defined!\n", __func__);
++		return -ENXIO;
++	}
++
+ 	ret = designware_eth_enable(priv);
+ 	if (ret)
+ 		return ret;
+@@ -690,42 +976,48 @@ const struct eth_ops gmac_rockchip_eth_ops = {
+ };
+ 
+ const struct rk_gmac_ops px30_gmac_ops = {
+-	.fix_mac_speed = px30_gmac_fix_mac_speed,
++	.fix_rmii_speed = px30_gmac_fix_rmii_speed,
+ 	.set_to_rmii = px30_gmac_set_to_rmii,
+ };
+ 
+ const struct rk_gmac_ops rk3228_gmac_ops = {
+-	.fix_mac_speed = rk3228_gmac_fix_mac_speed,
++	.fix_rmii_speed = rk3228_gmac_fix_rmii_speed,
++	.fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed,
++	.set_to_rmii = rk3228_gmac_set_to_rmii,
+ 	.set_to_rgmii = rk3228_gmac_set_to_rgmii,
++	.integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup,
+ };
+ 
+ const struct rk_gmac_ops rk3288_gmac_ops = {
+-	.fix_mac_speed = rk3288_gmac_fix_mac_speed,
++	.fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed,
+ 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
+ };
+ 
+ const struct rk_gmac_ops rk3308_gmac_ops = {
+-	.fix_mac_speed = rk3308_gmac_fix_mac_speed,
++	.fix_rmii_speed = rk3308_gmac_fix_rmii_speed,
+ 	.set_to_rmii = rk3308_gmac_set_to_rmii,
+ };
+ 
+ const struct rk_gmac_ops rk3328_gmac_ops = {
+-	.fix_mac_speed = rk3328_gmac_fix_mac_speed,
++	.fix_rmii_speed = rk3328_gmac_fix_rmii_speed,
++	.fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed,
++	.set_to_rmii = rk3328_gmac_set_to_rmii,
+ 	.set_to_rgmii = rk3328_gmac_set_to_rgmii,
++	.integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup,
+ };
+ 
+ const struct rk_gmac_ops rk3368_gmac_ops = {
+-	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
++	.fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed,
+ 	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
+ };
+ 
+ const struct rk_gmac_ops rk3399_gmac_ops = {
+-	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
++	.fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed,
+ 	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
+ };
+ 
+ const struct rk_gmac_ops rv1108_gmac_ops = {
+-	.fix_mac_speed = rv1108_set_rmii_speed,
++	.fix_rmii_speed = rv1108_gmac_fix_rmii_speed,
+ 	.set_to_rmii = rv1108_gmac_set_to_rmii,
+ };
+ 

patch/u-boot/u-boot-rk322x/u-boot-1002-rockchip-sdram-rk322x-fix-dram-bank-size-calculation.patch

@@ -0,0 +1,42 @@
+From a05e0306d9793da2bb76a6c712ae20ecc3af6d98 Mon Sep 17 00:00:00 2001
+From: Alex Bee <knaerzche@gmail.com>
+Date: Thu, 27 Feb 2020 13:50:52 +0100
+Subject: [PATCH] rockchip: sdram: fix dram_init_banksize with CONFIG_SPL_OPTEE
+
+Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board when CONFIG_SPL_OPTEE is set.
+
+gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE) must not be taken into consideration
+for calculation of second bank size, since this offset is already included in calculation of "top".
+After applying this patch 992 MB (1024 MB -32 MB reserved for trustos) is calculated.
+
+Signed-off-by: Alex Bee <knaerzche@gmail.com>
+---
+ arch/arm/mach-rockchip/sdram.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
+index 530644c043..05bc0c14e5 100644
+--- a/arch/arm/mach-rockchip/sdram.c
++++ b/arch/arm/mach-rockchip/sdram.c
+@@ -55,16 +55,14 @@ int dram_init_banksize(void)
+ 					- CONFIG_SYS_SDRAM_BASE;
+ 		gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
+ 					tos_parameter->tee_mem.size;
+-		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+-					+ top - gd->bd->bi_dram[1].start;
++		gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
+ 	} else {
+ 		gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ 		gd->bd->bi_dram[0].size = 0x8400000;
+ 		/* Reserve 32M for OPTEE with TA */
+ 		gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ 					+ gd->bd->bi_dram[0].size + 0x2000000;
+-		gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+-					+ top - gd->bd->bi_dram[1].start;
++		gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
+ 	}
+ #else
+ 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+-- 
+2.17.1
+