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Added tinkerboard mainline wifi and rockchip DTS
updates
This commit is contained in:
Tonymac32
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parent
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commit
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2 changed files with 285 additions and 0 deletions
134
patch/kernel/rockchip-next/9200_DTS_tinkerboard_wifi.patch
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134
patch/kernel/rockchip-next/9200_DTS_tinkerboard_wifi.patch
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@ -0,0 +1,134 @@
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diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
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index 6bc4b39..79cdede 100644
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--- a/arch/arm/boot/dts/rk3288-miniarm.dts
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+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
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@@ -44,6 +44,7 @@
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#include "rk3288.dtsi"
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#include <dt-bindings/input/input.h>
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+#include <dt-bindings/clock/rockchip,rk808.h>
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/ {
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model = "Rockchip RK3288 Tinker Board";
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@@ -54,6 +55,15 @@
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device_type = "memory";
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};
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+ wireless-wlan {
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+ compatible = "wlan-platdata";
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+ rockchip,grf = <&grf>;
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+ wifi_chip_type = "8723bs";
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+ sdio_vref = <1800>;
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+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+ };
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+
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ext_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -133,6 +143,23 @@
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startup-delay-us = <100000>;
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vin-supply = <&vcc_io>;
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};
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&rk808 RK808_CLKOUT1>;
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+ clock-names = "ext_clock";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
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+
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+ /*
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+ * On the module itself this is one of these (depending
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+ * on the actual card populated):
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+ * - SDIO_RESET_L_WL_REG_ON
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+ * - PDN (power down when low)
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+ */
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+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
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+ };
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+
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};
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&cpu0 {
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@@ -396,9 +423,30 @@
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status = "okay";
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};
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-&io_domains {
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+&sdio0 {
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status = "okay";
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+ clock-frequency = <50000000>;
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+ clock-freq-min-max = <200000 50000000>;
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+ bus-width = <4>;
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+ cap-sd-highspeed;
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+ cap-sdio-irq;
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+ disable-wp;
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+ keep-power-in-suspend;
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+ mmc-pwrseq = <&sdio_pwrseq>;
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+ non-removable;
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+ num-slots = <1>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
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+ sd-uhs-sdr104;
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+ supports-sdio;
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+
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+};
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+
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+&io_domains {
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+ status = "okay";
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+ rockchip,grf = <&grf>;
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+ wifi-supply = <&vcc_18>;
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sdcard-supply = <&vccio_sd>;
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};
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@@ -447,6 +495,17 @@
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};
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};
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+ sdio-pwrseq {
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+ wifi_enable_h: wifienable-h {
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+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ chip_enable_h: chip-enable-h {
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+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+
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sdmmc {
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
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@@ -478,6 +537,13 @@
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rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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+
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+ wireless-bluetooth {
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+ uart0_gpios: uart0-gpios {
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+ rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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};
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&pwm0 {
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@@ -493,12 +559,17 @@
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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+ sd-uhs-sdr12;
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+ sd-uhs-sdr25;
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+ sd-uhs-sdr50;
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+ sd-uhs-sdr104;
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card-detect-delay = <200>;
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disable-wp; /* wp not hooked up */
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num-slots = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
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status = "okay";
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+ supports-sd;
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vmmc-supply = <&vcc33_sd>;
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vqmmc-supply = <&vccio_sd>;
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};
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151
patch/kernel/rockchip-next/9210_DTS_update.patch
Normal file
151
patch/kernel/rockchip-next/9210_DTS_update.patch
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@ -0,0 +1,151 @@
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diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
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index 79cdede..348e9be 100644
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--- a/arch/arm/boot/dts/rk3288-miniarm.dts
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+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
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@@ -50,11 +50,23 @@
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model = "Rockchip RK3288 Tinker Board";
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compatible = "asus,rk3288-tinker", "rockchip,rk3288";
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- memory {
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+ memory@0 {
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reg = <0x0 0x80000000>;
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device_type = "memory";
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};
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+ wireless-bluetooth {
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+ compatible = "bluetooth-platdata";
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+ uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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+ pinctrl-names = "default","rts_gpio";
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+ pinctrl-0 = <&uart0_rts>;
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+ pinctrl-1 = <&uart0_gpios>;
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+ BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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+ BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
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+ BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+ };
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+
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wireless-wlan {
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compatible = "wlan-platdata";
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rockchip,grf = <&grf>;
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@@ -314,6 +326,8 @@
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};
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vccio_sd: LDO_REG5 {
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+ regulator-always-on;
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+ regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vccio_sd";
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@@ -385,6 +399,11 @@
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&i2c2 {
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status = "okay";
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+
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+ eeprom:m24c08@50 {
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+ compatible = "at,24c08";
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+ reg = <0x50>;
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+ };
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};
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&i2c3 {
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@@ -581,6 +600,8 @@
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};
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&uart0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>;
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status = "okay";
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};
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index e1938d2..458d545 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -360,6 +360,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <0xff0c0000 0x4000>;
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resets = <&cru SRST_MMC0>;
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reset-names = "reset";
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@@ -374,6 +376,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <0xff0d0000 0x4000>;
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resets = <&cru SRST_SDIO0>;
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reset-names = "reset";
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@@ -388,6 +392,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <0xff0e0000 0x4000>;
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resets = <&cru SRST_SDIO1>;
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reset-names = "reset";
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@@ -402,6 +408,8 @@
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <0xff0f0000 0x4000>;
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resets = <&cru SRST_EMMC>;
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reset-names = "reset";
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@@ -1038,7 +1046,7 @@
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status = "disabled";
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};
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- spdif: sound@ff88b0000 {
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+ spdif: sound@ff8b0000 {
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compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
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reg = <0xff8b0000 0x10000>;
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#sound-dai-cells = <0>;
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@@ -1082,9 +1090,24 @@
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status = "okay";
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};
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+ rga: rga@ff920000 {
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+ compatible = "rockchip,rk3288-rga";
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+ reg = <0xff920000 0x180>;
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+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "rga";
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+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
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+ clock-names = "aclk", "hclk", "sclk";
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+ power-domains = <&power RK3288_PD_VIO>;
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+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
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+
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+ reset-names = "core", "axi", "ahb";
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+ status = "disabled";
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+ };
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+
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+
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vopb: vop@ff930000 {
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compatible = "rockchip,rk3288-vop";
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- reg = <0xff930000 0x19c>;
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+ reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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@@ -1127,7 +1150,7 @@
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vopl: vop@ff940000 {
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compatible = "rockchip,rk3288-vop";
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- reg = <0xff940000 0x19c>;
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+ reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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@@ -1202,6 +1225,7 @@
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
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clock-names = "dp", "pclk";
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+ power-domains = <&power RK3288_PD_VIO>;
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phys = <&edp_phy>;
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phy-names = "dp";
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resets = <&cru SRST_EDP>;
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