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170 lines
4.3 KiB
Diff
170 lines
4.3 KiB
Diff
From de9dcd5ecab0686022eee243464f35d2c7a34c97 Mon Sep 17 00:00:00 2001
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From: Myy <myy@miouyouyou.fr>
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Date: Mon, 16 Jan 2017 12:44:56 +0000
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Subject: [PATCH 08/28] Readapt: ARM: dts: rockchip: miqi: add turbo-mode
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operating points
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Readaptation of Willy Tarreau patch.
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Here's the original commit message:
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By switching to opp-v2 we can declare "turbo-mode" operating points
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which are only enabled when /sys/devices/system/cpu/cpufreq/boost is
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set. It is convenient because it allows to boot, set a safe powersave
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governor, enable boost, limit scaling_max_freq to a safe value, then
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change the governor to performance or ondemand, and the frequency can
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then be manually adjusted by only touching scaling_max_freq.
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New values are 1896, 1920, 1992, 2016, 2040 MHz, 2064, 2088, 2112,
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2136, 2160, 2184, 2208. MiQi boards work fine up to 2112 with a very
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good power supply (5.2V/3A real) and a strong heatsink. Higher
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frequencies may randomly work. At least 1992 is rock solid for hours
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using "openssl speed -multi 4". The other ones have only been tested
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for a few minutes. Frequencies of 1896 and 1920 MHz use 1.425V.
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1992 MHz uses 1.45V. 2016, 2040 and 2064 use 1.475V. 2088 and above
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use 1.500V. 2160, 2184 and 2208 cause the lowest frequency to be
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picked. It's obvious that it's a sign issue somewhere in the kernel
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but this one was not found yet.
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Signed-off-by: Myy <myy@miouyouyou.fr>
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---
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arch/arm/boot/dts/rk3288-miqi.dts | 120 +++++++++++++++++++++++++++++++++-----
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1 file changed, 107 insertions(+), 13 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
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index 80603a3d..d7fde483 100644
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--- a/arch/arm/boot/dts/rk3288-miqi.dts
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+++ b/arch/arm/boot/dts/rk3288-miqi.dts
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@@ -122,22 +122,116 @@
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regulator-always-on;
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regulator-boot-on;
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};
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-};
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+
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+ cpu0_opp_table: opp_table0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp@600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <900000>;
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+ };
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+ opp@816000000 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <1000000>;
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+ };
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+ opp@1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1050000>;
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+ };
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+ opp@1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1100000>;
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+ };
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+ opp@1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <1200000>;
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+ };
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+ opp@1512000000 {
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+ opp-hz = /bits/ 64 <1512000000>;
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+ opp-microvolt = <1250000>;
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+ };
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+ opp@1608000000 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <1300000>;
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+ };
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+ opp@1704000000 {
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+ opp-hz = /bits/ 64 <1704000000>;
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+ opp-microvolt = <1350000>;
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+ };
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+ opp@1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <1400000>;
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+ };
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+ /* boot-only frequencies below */
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+ opp@1896000000 {
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+ opp-hz = /bits/ 64 <1896000000>;
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+ opp-microvolt = <1425000>;
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+ turbo-mode;
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+ };
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+ opp@1920000000 {
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+ opp-hz = /bits/ 64 <1920000000>;
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+ opp-microvolt = <1425000>;
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+ turbo-mode;
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+ };
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+ opp@1992000000 {
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+ opp-hz = /bits/ 64 <1992000000>;
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+ opp-microvolt = <1450000>;
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+ turbo-mode;
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+ };
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+ opp@2016000000 {
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+ opp-hz = /bits/ 64 <2016000000>;
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+ opp-microvolt = <1475000>;
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+ turbo-mode;
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+ };
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+ opp@2040000000 {
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+ opp-hz = /bits/ 64 <2040000000>;
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+ opp-microvolt = <1475000>;
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+ turbo-mode;
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+ };
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+ opp@2064000000 {
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+ opp-hz = /bits/ 64 <2064000000>;
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+ opp-microvolt = <1475000>;
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+ turbo-mode;
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+ };
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+ opp@2088000000 {
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+ opp-hz = /bits/ 64 <2088000000>;
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+ opp-microvolt = <1500000>;
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+ turbo-mode;
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+ };
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+ opp@2112000000 {
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+ opp-hz = /bits/ 64 <2112000000>;
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+ opp-microvolt = <1500000>;
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+ turbo-mode;
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+ };
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+ opp@2136000000 {
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+ opp-hz = /bits/ 64 <2136000000>;
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+ opp-microvolt = <1500000>;
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+ turbo-mode;
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+ };
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+ opp@2160000000 {
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+ opp-hz = /bits/ 64 <2160000000>;
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+ opp-microvolt = <1500000>;
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+ turbo-mode;
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+ };
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+ opp@2184000000 {
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+ opp-hz = /bits/ 64 <2184000000>;
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+ opp-microvolt = <1500000>;
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+ turbo-mode;
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+ };
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+ opp@2208000000 {
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+ opp-hz = /bits/ 64 <2208000000>;
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+ opp-microvolt = <1500000>;
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+ turbo-mode;
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+ };
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+ };
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+};
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+
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&cpu0 {
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cpu0-supply = <&vdd_cpu>;
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- operating-points = <
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- /* KHz uV */
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- 1800000 1400000
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- 1704000 1350000
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- 1608000 1300000
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- 1512000 1250000
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- 1416000 1200000
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- 1200000 1100000
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- 1008000 1050000
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- 816000 1000000
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- 600000 900000
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- >;
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+
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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&emmc {
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--
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2.11.0
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