mirror of
https://github.com/Fishwaldo/build.git
synced 2025-03-27 01:02:19 +00:00
1748 lines
45 KiB
Diff
1748 lines
45 KiB
Diff
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
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index cbc7847..0f00abd 100644
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--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
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+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
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@@ -11,6 +11,7 @@ Required properties:
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* allwinner,sun8i-a33-usb-phy
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* allwinner,sun8i-a83t-usb-phy
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* allwinner,sun8i-h3-usb-phy
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+ * allwinner,sun8i-r40-usb-phy
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* allwinner,sun8i-v3s-usb-phy
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* allwinner,sun50i-a64-usb-phy
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- reg : a list of offset + length pairs
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diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
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index fc5da60..597dcd4 100644
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--- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
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+++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
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@@ -8,6 +8,7 @@ Required properties:
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- compatible: should be one of the following:
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- "allwinner,sun4i-a10-i2s"
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- "allwinner,sun6i-a31-i2s"
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+ - "allwinner,sun8i-a83t-i2s"
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- "allwinner,sun8i-h3-i2s"
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- reg: physical base address of the controller and length of memory mapped
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region.
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@@ -23,6 +24,7 @@ Required properties:
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Required properties for the following compatibles:
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- "allwinner,sun6i-a31-i2s"
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+ - "allwinner,sun8i-a83t-i2s"
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- "allwinner,sun8i-h3-i2s"
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- resets: phandle to the reset line for this codec
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 6817198..2fd4d80 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -936,6 +936,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
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sun8i-h3-orangepi-zeroplus2.dtb \
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sun8i-r16-bananapi-m2m.dtb \
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sun8i-r16-parrot.dtb \
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+ sun8i-r40-bananapi-m2-ultra.dtb \
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sun8i-v3s-licheepi-zero.dtb \
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sun8i-v3s-licheepi-zero-dock.dtb
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dtb-$(CONFIG_MACH_SUN9I) += \
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diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
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new file mode 100644
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index 0000000..73b761f
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--- /dev/null
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+++ b/arch/arm/boot/dts/axp81x.dtsi
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@@ -0,0 +1,139 @@
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+/*
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+ * Copyright 2017 Chen-Yu Tsai
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+ *
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+ * Chen-Yu Tsai <wens@csie.org>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPL or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This file is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This file is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/* AXP813/818 Integrated Power Management Chip */
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+
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+&axp81x {
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+
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+ regulators {
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+ /* Default work frequency for buck regulators */
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+ x-powers,dcdc-freq = <3000>;
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+
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+ reg_dcdc1: dcdc1 {
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+ };
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+
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+ reg_dcdc2: dcdc2 {
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+ };
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+
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+ reg_dcdc3: dcdc3 {
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+ };
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+
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+ reg_dcdc4: dcdc4 {
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+ };
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+
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+ reg_dcdc5: dcdc5 {
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+ };
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+
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+ reg_dcdc6: dcdc6 {
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+ };
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+
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+ reg_dcdc7: dcdc7 {
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+ };
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+
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+ reg_aldo1: aldo1 {
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+ };
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+
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+ reg_aldo2: aldo2 {
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+ };
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+
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+ reg_aldo3: aldo3 {
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+ };
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+
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+ reg_dldo1: dldo1 {
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+ };
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+
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+ reg_dldo2: dldo2 {
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+ };
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+
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+ reg_dldo3: dldo3 {
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+ };
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+
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+ reg_dldo4: dldo4 {
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+ };
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+
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+ reg_eldo1: eldo1 {
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+ };
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+
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+ reg_eldo2: eldo2 {
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+ };
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+
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+ reg_eldo3: eldo3 {
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+ };
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+
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+ reg_fldo1: fldo1 {
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+ };
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+
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+ reg_fldo2: fldo2 {
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+ };
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+
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+ reg_fldo3: fldo3 {
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+ };
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+
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+ reg_ldo_io0: ldo-io0 {
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+ /* Disable by default to avoid conflicts with GPIO */
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+ status = "disabled";
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+ };
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+
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+ reg_ldo_io1: ldo-io1 {
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+ /* Disable by default to avoid conflicts with GPIO */
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+ status = "disabled";
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+ };
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+
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+ reg_rtc_ldo: rtc-ldo {
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+ /* RTC_LDO is a fixed, always-on regulator */
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ };
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+
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+ reg_sw: sw {
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+ };
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+
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+ reg_drivevbus: drivevbus {
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+ status = "disabled";
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+ };
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+ };
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+};
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diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
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old mode 100644
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new mode 100755
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index 2bafd7e..01a1f29
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--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
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+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
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@@ -44,7 +44,6 @@
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/dts-v1/;
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#include "sun8i-a83t.dtsi"
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-#include "sunxi-common-regulators.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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@@ -53,12 +52,41 @@
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compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
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aliases {
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+ ethernet0 = &emac;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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+
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+ reg_vcc3v3: vcc3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ };
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+
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+ reg_usb1_vbus: reg-usb1-vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb1-vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ regulator-boot-on;
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+ enable-active-high;
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+ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
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+ };
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+
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+ wifi_pwrseq: wifi_pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ clocks = <&ac100_rtc 1>;
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+ clock-names = "ext_clock";
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+ /* The WiFi low power clock must be 32768 Hz */
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+ assigned-clocks = <&ac100_rtc 1>;
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+ assigned-clock-rates = <32768>;
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+ /* enables internal regulator and de-asserts reset */
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+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
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+ };
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};
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&ehci0 {
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@@ -68,6 +96,24 @@
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/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_sw>;
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+ phy-handle = <&rgmii_phy>;
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+ phy-mode = "rgmii";
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+ allwinner,rx-delay-ps = <700>;
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+ allwinner,tx-delay-ps = <700>;
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+ status = "okay";
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+};
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+
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+&mdio {
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+ rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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@@ -78,6 +124,23 @@
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status = "okay";
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};
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+&mmc1 {
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+ vmmc-supply = <®_dldo1>;
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+ vqmmc-supply = <®_dldo1>;
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+ mmc-pwrseq = <&wifi_pwrseq>;
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+ bus-width = <4>;
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+ non-removable;
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+ status = "okay";
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+
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+ brcmf: wifi@1 {
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+ reg = <1>;
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+ compatible = "brcm,bcm4329-fmac";
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+ interrupt-parent = <&r_pio>;
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+ interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "host-wake";
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+ };
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+};
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+
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_8bit_emmc_pins>;
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@@ -96,6 +159,10 @@
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reg = <0x3a3>;
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interrupt-parent = <&r_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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+ eldoin-supply = <®_dcdc1>;
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+ fldoin-supply = <®_dcdc5>;
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+ swin-supply = <®_dcdc1>;
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+ x-powers,drive-vbus-en;
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};
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ac100: codec@e89 {
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@@ -123,17 +190,126 @@
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};
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};
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-®_usb1_vbus {
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- gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
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+#include "axp81x.dtsi"
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+
|
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+®_aldo1 {
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+ regulator-always-on;
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+ regulator-min-microvolt = <1800000>;
|
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+ regulator-max-microvolt = <1800000>;
|
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+ regulator-name = "vcc-1v8";
|
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+};
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+
|
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+®_aldo2 {
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
|
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+ regulator-name = "dram-pll";
|
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+};
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+
|
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+®_aldo3 {
|
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <3000000>;
|
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+ regulator-max-microvolt = <3000000>;
|
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+ regulator-name = "avcc";
|
|
+};
|
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+
|
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+®_dcdc1 {
|
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+ /* schematics says 3.1V but FEX file says 3.3V */
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc-3v3";
|
|
+};
|
|
+
|
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+®_dcdc2 {
|
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+ regulator-always-on;
|
|
+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-cpua";
|
|
+};
|
|
+
|
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+®_dcdc3 {
|
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+ regulator-always-on;
|
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+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-cpub";
|
|
+};
|
|
+
|
|
+®_dcdc4 {
|
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+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-gpu";
|
|
+};
|
|
+
|
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+®_dcdc5 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-name = "vcc-dram";
|
|
+};
|
|
+
|
|
+®_dcdc6 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vdd-sys";
|
|
+};
|
|
+
|
|
+®_dldo1 {
|
|
+ /*
|
|
+ * This powers both the WiFi/BT module's main power, I/O supply,
|
|
+ * and external pull-ups on all the data lines. It should be set
|
|
+ * to the same voltage as the I/O supply (DCDC1 in this case) to
|
|
+ * avoid any leakage or mismatch.
|
|
+ */
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc-wifi";
|
|
+};
|
|
+
|
|
+®_dldo3 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <2500000>;
|
|
+ regulator-max-microvolt = <2500000>;
|
|
+ regulator-name = "vcc-pd";
|
|
+};
|
|
+
|
|
+®_drivevbus {
|
|
+ regulator-name = "usb0-vbus";
|
|
status = "okay";
|
|
};
|
|
|
|
-®_vcc3v0 {
|
|
- status = "disabled";
|
|
+®_fldo1 {
|
|
+ regulator-min-microvolt = <1080000>;
|
|
+ regulator-max-microvolt = <1320000>;
|
|
+ regulator-name = "vdd12-hsic";
|
|
+};
|
|
+
|
|
+®_fldo2 {
|
|
+ /*
|
|
+ * Despite the embedded CPUs core not being used in any way,
|
|
+ * this must remain on or the system will hang.
|
|
+ */
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-cpus";
|
|
+};
|
|
+
|
|
+®_rtc_ldo {
|
|
+ regulator-name = "vcc-rtc";
|
|
};
|
|
|
|
-®_vcc5v0 {
|
|
- status = "disabled";
|
|
+®_sw {
|
|
+ /*
|
|
+ * The PHY requires 20ms after all voltages
|
|
+ * are applied until core logic is ready and
|
|
+ * 30ms after the reset pin is de-asserted.
|
|
+ * Set a 100ms delay to account for PMIC
|
|
+ * ramp time and board traces.
|
|
+ */
|
|
+ regulator-enable-ramp-delay = <100000>;
|
|
+ regulator-name = "vcc-ephy";
|
|
};
|
|
|
|
&uart0 {
|
|
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
|
|
index 716a205..6da08cd 100644
|
|
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
|
|
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
|
|
@@ -44,7 +44,6 @@
|
|
|
|
/dts-v1/;
|
|
#include "sun8i-a83t.dtsi"
|
|
-#include "sunxi-common-regulators.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
@@ -53,6 +52,7 @@
|
|
compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
|
|
|
|
aliases {
|
|
+ ethernet0 = &emac;
|
|
serial0 = &uart0;
|
|
};
|
|
|
|
@@ -95,6 +95,26 @@
|
|
refclk-frequency = <19200000>;
|
|
};
|
|
|
|
+ reg_usb1_vbus: reg-usb1-vbus {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "usb1-vbus";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-boot-on;
|
|
+ enable-active-high;
|
|
+ gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
|
|
+ };
|
|
+
|
|
+ reg_usb2_vbus: reg-usb2-vbus {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "usb2-vbus";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-boot-on;
|
|
+ enable-active-high;
|
|
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
|
|
+ };
|
|
+
|
|
sound {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "On-board SPDIF";
|
|
@@ -112,6 +132,17 @@
|
|
#sound-dai-cells = <0>;
|
|
compatible = "linux,spdif-dit";
|
|
};
|
|
+
|
|
+ wifi_pwrseq: wifi_pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ clocks = <&ac100_rtc 1>;
|
|
+ clock-names = "ext_clock";
|
|
+ /* The WiFi low power clock must be 32768 Hz */
|
|
+ assigned-clocks = <&ac100_rtc 1>;
|
|
+ assigned-clock-rates = <32768>;
|
|
+ /* enables internal regulator and de-asserts reset */
|
|
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
|
|
+ };
|
|
};
|
|
|
|
&ehci0 {
|
|
@@ -124,20 +155,45 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&emac {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&emac_rgmii_pins>;
|
|
+ phy-supply = <®_dldo4>;
|
|
+ phy-handle = <&rgmii_phy>;
|
|
+ phy-mode = "rgmii";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mdio {
|
|
+ rgmii_phy: ethernet-phy@1 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
&mmc0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc0_pins>;
|
|
- vmmc-supply = <®_vcc3v3>;
|
|
+ vmmc-supply = <®_dcdc1>;
|
|
bus-width = <4>;
|
|
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
|
|
cd-inverted;
|
|
status = "okay";
|
|
};
|
|
|
|
+&mmc1 {
|
|
+ vmmc-supply = <®_dcdc1>;
|
|
+ vqmmc-supply = <®_sw>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ bus-width = <4>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
&mmc2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
|
|
- vmmc-supply = <®_vcc3v3>;
|
|
+ vmmc-supply = <®_dcdc1>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
cap-mmc-hw-reset;
|
|
@@ -152,6 +208,9 @@
|
|
reg = <0x3a3>;
|
|
interrupt-parent = <&r_intc>;
|
|
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
|
+ eldoin-supply = <®_dcdc1>;
|
|
+ swin-supply = <®_dcdc1>;
|
|
+ x-powers,drive-vbus-en;
|
|
};
|
|
|
|
ac100: codec@e89 {
|
|
@@ -179,22 +238,143 @@
|
|
};
|
|
};
|
|
|
|
-®_usb1_vbus {
|
|
- gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
|
|
- status = "okay";
|
|
+#include "axp81x.dtsi"
|
|
+
|
|
+®_aldo1 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc-1v8";
|
|
+};
|
|
+
|
|
+®_aldo2 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "dram-pll";
|
|
+};
|
|
+
|
|
+®_aldo3 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <3000000>;
|
|
+ regulator-max-microvolt = <3000000>;
|
|
+ regulator-name = "avcc";
|
|
+};
|
|
+
|
|
+®_dcdc1 {
|
|
+ /*
|
|
+ * The schematics say this should be 3.3V, but the FEX file says
|
|
+ * it should be 3V. The latter makes sense, as the WiFi module's
|
|
+ * I/O is indirectly powered from DCDC1, through SW. It is rated
|
|
+ * at 2.98V maximum.
|
|
+ */
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <3000000>;
|
|
+ regulator-max-microvolt = <3000000>;
|
|
+ regulator-name = "vcc-3v";
|
|
+};
|
|
+
|
|
+®_dcdc2 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-cpua";
|
|
+};
|
|
+
|
|
+®_dcdc3 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-cpub";
|
|
+};
|
|
+
|
|
+®_dcdc4 {
|
|
+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-gpu";
|
|
+};
|
|
+
|
|
+®_dcdc5 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1500000>;
|
|
+ regulator-max-microvolt = <1500000>;
|
|
+ regulator-name = "vcc-dram";
|
|
+};
|
|
+
|
|
+®_dcdc6 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <900000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-name = "vdd-sys";
|
|
+};
|
|
+
|
|
+®_dldo2 {
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "dp-pwr";
|
|
};
|
|
|
|
-®_usb2_vbus {
|
|
- gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
|
|
+®_dldo3 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <2500000>;
|
|
+ regulator-max-microvolt = <2500000>;
|
|
+ regulator-name = "ephy-io";
|
|
+};
|
|
+
|
|
+®_dldo4 {
|
|
+ /*
|
|
+ * The PHY requires 20ms after all voltages are applied until core
|
|
+ * logic is ready and 30ms after the reset pin is de-asserted.
|
|
+ * Set a 100ms delay to account for PMIC ramp time and board traces.
|
|
+ */
|
|
+ regulator-enable-ramp-delay = <100000>;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "ephy";
|
|
+};
|
|
+
|
|
+®_drivevbus {
|
|
+ regulator-name = "usb0-vbus";
|
|
status = "okay";
|
|
};
|
|
|
|
-®_vcc3v0 {
|
|
- status = "disabled";
|
|
+®_eldo1 {
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-name = "dp-bridge-1";
|
|
+};
|
|
+
|
|
+®_eldo2 {
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-name = "dp-bridge-2";
|
|
+};
|
|
+
|
|
+®_fldo1 {
|
|
+ /* TODO should be handled by USB PHY */
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1080000>;
|
|
+ regulator-max-microvolt = <1320000>;
|
|
+ regulator-name = "vdd12-hsic";
|
|
+};
|
|
+
|
|
+®_fldo2 {
|
|
+ /*
|
|
+ * Despite the embedded CPUs core not being used in any way,
|
|
+ * this must remain on or the system will hang.
|
|
+ */
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <700000>;
|
|
+ regulator-max-microvolt = <1100000>;
|
|
+ regulator-name = "vdd-cpus";
|
|
+};
|
|
+
|
|
+®_rtc_ldo {
|
|
+ regulator-name = "vcc-rtc";
|
|
};
|
|
|
|
-®_vcc5v0 {
|
|
- status = "disabled";
|
|
+®_sw {
|
|
+ regulator-name = "vcc-wifi-io";
|
|
};
|
|
|
|
&spdif {
|
|
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
|
|
index f996bd3..952923a 100644
|
|
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
|
|
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
|
|
@@ -54,12 +54,6 @@
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
- aliases {
|
|
- };
|
|
-
|
|
- chosen {
|
|
- };
|
|
-
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
@@ -218,6 +212,8 @@
|
|
resets = <&ccu RST_BUS_MMC1>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc1_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
@@ -242,7 +238,7 @@
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
- usb_otg: usb@01c19000 {
|
|
+ usb_otg: usb@1c19000 {
|
|
compatible = "allwinner,sun8i-a83t-musb",
|
|
"allwinner,sun8i-a33-musb";
|
|
reg = <0x01c19000 0x0400>;
|
|
@@ -340,6 +336,39 @@
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
+ emac_rgmii_pins: emac-rgmii-pins {
|
|
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
|
|
+ "PD11", "PD12", "PD13", "PD14", "PD18",
|
|
+ "PD19", "PD21", "PD22", "PD23";
|
|
+ function = "gmac";
|
|
+ /*
|
|
+ * data lines in RGMII mode use DDR mode
|
|
+ * and need a higher signal drive strength
|
|
+ */
|
|
+ drive-strength = <40>;
|
|
+ };
|
|
+
|
|
+ i2c0_pins: i2c0-pins {
|
|
+ pins = "PH0", "PH1";
|
|
+ function = "i2c0";
|
|
+ };
|
|
+
|
|
+ i2c1_pins: i2c1-pins {
|
|
+ pins = "PH2", "PH3";
|
|
+ function = "i2c1";
|
|
+ };
|
|
+
|
|
+ i2c2_ph_pins: i2c2-ph-pins {
|
|
+ pins = "PH4", "PH5";
|
|
+ function = "i2c2";
|
|
+ };
|
|
+
|
|
+ i2s1_pins: i2s1-pins {
|
|
+ /* I2S1 does not have external MCLK pin */
|
|
+ pins = "PG10", "PG11", "PG12", "PG13";
|
|
+ function = "i2s1";
|
|
+ };
|
|
+
|
|
mmc0_pins: mmc0-pins {
|
|
pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
@@ -348,6 +377,14 @@
|
|
bias-pull-up;
|
|
};
|
|
|
|
+ mmc1_pins: mmc1-pins {
|
|
+ pins = "PG0", "PG1", "PG2",
|
|
+ "PG3", "PG4", "PG5";
|
|
+ function = "mmc1";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
|
|
pins = "PC5", "PC6", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12", "PC13",
|
|
@@ -371,6 +408,16 @@
|
|
pins = "PF2", "PF4";
|
|
function = "uart0";
|
|
};
|
|
+
|
|
+ uart1_pins: uart1-pins {
|
|
+ pins = "PG6", "PG7";
|
|
+ function = "uart1";
|
|
+ };
|
|
+
|
|
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
|
|
+ pins = "PG8", "PG9";
|
|
+ function = "uart1";
|
|
+ };
|
|
};
|
|
|
|
timer@1c20c00 {
|
|
@@ -404,7 +451,48 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
- uart0: serial@01c28000 {
|
|
+ i2s0: i2s@1c22000 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "allwinner,sun8i-a83t-i2s";
|
|
+ reg = <0x01c22000 0x400>;
|
|
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
|
|
+ clock-names = "apb", "mod";
|
|
+ dmas = <&dma 3>, <&dma 3>;
|
|
+ resets = <&ccu RST_BUS_I2S0>;
|
|
+ dma-names = "rx", "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s1: i2s@1c22400 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "allwinner,sun8i-a83t-i2s";
|
|
+ reg = <0x01c22400 0x400>;
|
|
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
|
|
+ clock-names = "apb", "mod";
|
|
+ dmas = <&dma 4>, <&dma 4>;
|
|
+ resets = <&ccu RST_BUS_I2S1>;
|
|
+ dma-names = "rx", "tx";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2s1_pins>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2s2: i2s@1c22800 {
|
|
+ #sound-dai-cells = <0>;
|
|
+ compatible = "allwinner,sun8i-a83t-i2s";
|
|
+ reg = <0x01c22800 0x400>;
|
|
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
|
|
+ clock-names = "apb", "mod";
|
|
+ dmas = <&dma 27>;
|
|
+ resets = <&ccu RST_BUS_I2S2>;
|
|
+ dma-names = "tx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart0: serial@1c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -415,6 +503,78 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ i2c0: i2c@1c2ac00 {
|
|
+ compatible = "allwinner,sun8i-a83t-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2ac00 0x400>;
|
|
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C0>;
|
|
+ resets = <&ccu RST_BUS_I2C0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c0_pins>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@1c2b000 {
|
|
+ compatible = "allwinner,sun8i-a83t-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2b000 0x400>;
|
|
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C1>;
|
|
+ resets = <&ccu RST_BUS_I2C1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@1c2b400 {
|
|
+ compatible = "allwinner,sun8i-a83t-i2c",
|
|
+ "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2b400 0x400>;
|
|
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C2>;
|
|
+ resets = <&ccu RST_BUS_I2C2>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ emac: ethernet@1c30000 {
|
|
+ compatible = "allwinner,sun8i-a83t-emac";
|
|
+ syscon = <&syscon>;
|
|
+ reg = <0x01c30000 0x104>;
|
|
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+ resets = <&ccu 13>;
|
|
+ reset-names = "stmmaceth";
|
|
+ clocks = <&ccu 27>;
|
|
+ clock-names = "stmmaceth";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio: mdio {
|
|
+ compatible = "snps,dwmac-mdio";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1: serial@1c28400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28400 0x400>;
|
|
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART1>;
|
|
+ resets = <&ccu RST_BUS_UART1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
gic: interrupt-controller@1c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
|
new file mode 100644
|
|
index 0000000..5587d72
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
|
|
@@ -0,0 +1,228 @@
|
|
+/*
|
|
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
|
|
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
|
+ *
|
|
+ * This file is dual-licensed: you can use it either under the terms
|
|
+ * of the GPL or the X11 license, at your option. Note that this dual
|
|
+ * licensing only applies to this file, and not this project as a
|
|
+ * whole.
|
|
+ *
|
|
+ * a) This file is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of the
|
|
+ * License, or (at your option) any later version.
|
|
+ *
|
|
+ * This file is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * Or, alternatively,
|
|
+ *
|
|
+ * b) Permission is hereby granted, free of charge, to any person
|
|
+ * obtaining a copy of this software and associated documentation
|
|
+ * files (the "Software"), to deal in the Software without
|
|
+ * restriction, including without limitation the rights to use,
|
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
|
+ * sell copies of the Software, and to permit persons to whom the
|
|
+ * Software is furnished to do so, subject to the following
|
|
+ * conditions:
|
|
+ *
|
|
+ * The above copyright notice and this permission notice shall be
|
|
+ * included in all copies or substantial portions of the Software.
|
|
+ *
|
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "sun8i-r40.dtsi"
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ model = "Banana Pi BPI-M2-Ultra";
|
|
+ compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
|
|
+
|
|
+ aliases {
|
|
+ serial0 = &uart0;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+
|
|
+ pwr-led {
|
|
+ label = "bananapi:red:pwr";
|
|
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
|
|
+ default-state = "on";
|
|
+ };
|
|
+
|
|
+ user-led-green {
|
|
+ label = "bananapi:green:user";
|
|
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ user-led-blue {
|
|
+ label = "bananapi:blue:user";
|
|
+ gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reg_vcc5v0: vcc5v0 {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "vcc5v0";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
|
|
+ enable-active-high;
|
|
+ };
|
|
+
|
|
+ wifi_pwrseq: wifi_pwrseq {
|
|
+ compatible = "mmc-pwrseq-simple";
|
|
+ reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
|
|
+ };
|
|
+};
|
|
+
|
|
+&ehci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ehci2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c0 {
|
|
+ status = "okay";
|
|
+
|
|
+ axp22x: pmic@34 {
|
|
+ compatible = "x-powers,axp221";
|
|
+ reg = <0x34>;
|
|
+ interrupt-parent = <&nmi_intc>;
|
|
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
|
+ };
|
|
+};
|
|
+
|
|
+#include "axp22x.dtsi"
|
|
+
|
|
+&ahci {
|
|
+ vdd1v2-supply = <®_eldo3>;
|
|
+ vdd2v5-supply = <®_dldo4>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+®_aldo3 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <2700000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "avcc";
|
|
+};
|
|
+
|
|
+®_dldo4 {
|
|
+ regulator-min-microvolt = <2500000>;
|
|
+ regulator-max-microvolt = <2500000>;
|
|
+ regulator-name = "vdd-2v5-sata";
|
|
+};
|
|
+
|
|
+®_eldo3 {
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-name = "vdd-1v2-sata";
|
|
+};
|
|
+
|
|
+®_dcdc1 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <3000000>;
|
|
+ regulator-max-microvolt = <3000000>;
|
|
+ regulator-name = "vcc-3v0";
|
|
+};
|
|
+
|
|
+®_dcdc2 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1000000>;
|
|
+ regulator-max-microvolt = <1300000>;
|
|
+ regulator-name = "vdd-cpu";
|
|
+};
|
|
+
|
|
+®_dcdc3 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1000000>;
|
|
+ regulator-max-microvolt = <1300000>;
|
|
+ regulator-name = "vdd-sys";
|
|
+};
|
|
+
|
|
+®_dcdc5 {
|
|
+ regulator-always-on;
|
|
+ regulator-min-microvolt = <1500000>;
|
|
+ regulator-max-microvolt = <1500000>;
|
|
+ regulator-name = "vcc-dram";
|
|
+};
|
|
+
|
|
+®_dldo1 {
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc-wifi-io";
|
|
+};
|
|
+
|
|
+®_dldo2 {
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc-wifi";
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ vmmc-supply = <®_dcdc1>;
|
|
+ bus-width = <4>;
|
|
+ cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
|
|
+ cd-inverted;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc1_pg_pins>;
|
|
+ vmmc-supply = <®_dldo2>;
|
|
+ vqmmc-supply = <®_dldo1>;
|
|
+ mmc-pwrseq = <&wifi_pwrseq>;
|
|
+ bus-width = <4>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&mmc2 {
|
|
+ vmmc-supply = <®_dcdc1>;
|
|
+ vqmmc-supply = <®_dcdc1>;
|
|
+ bus-width = <8>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ohci1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ohci2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart0_pb_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbphy {
|
|
+ usb1_vbus-supply = <®_vcc5v0>;
|
|
+ usb2_vbus-supply = <®_vcc5v0>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
|
new file mode 100755
|
|
index 0000000..ef4df3b
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
|
|
@@ -0,0 +1,482 @@
|
|
+/*
|
|
+ * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
|
|
+ * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
|
|
+ *
|
|
+ * This file is dual-licensed: you can use it either under the terms
|
|
+ * of the GPL or the X11 license, at your option. Note that this dual
|
|
+ * licensing only applies to this file, and not this project as a
|
|
+ * whole.
|
|
+ *
|
|
+ * a) This file is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of the
|
|
+ * License, or (at your option) any later version.
|
|
+ *
|
|
+ * This file is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * Or, alternatively,
|
|
+ *
|
|
+ * b) Permission is hereby granted, free of charge, to any person
|
|
+ * obtaining a copy of this software and associated documentation
|
|
+ * files (the "Software"), to deal in the Software without
|
|
+ * restriction, including without limitation the rights to use,
|
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
|
+ * sell copies of the Software, and to permit persons to whom the
|
|
+ * Software is furnished to do so, subject to the following
|
|
+ * conditions:
|
|
+ *
|
|
+ * The above copyright notice and this permission notice shall be
|
|
+ * included in all copies or substantial portions of the Software.
|
|
+ *
|
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
+#include <dt-bindings/clock/sun8i-r40-ccu.h>
|
|
+#include <dt-bindings/reset/sun8i-r40-ccu.h>
|
|
+
|
|
+/ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ interrupt-parent = <&gic>;
|
|
+
|
|
+ clocks {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ osc24M: osc24M {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <24000000>;
|
|
+ clock-output-names = "osc24M";
|
|
+ };
|
|
+
|
|
+ osc32k: osc32k {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-clock";
|
|
+ clock-frequency = <32768>;
|
|
+ clock-output-names = "osc32k";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cpus {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu@0 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <0>;
|
|
+ };
|
|
+
|
|
+ cpu@1 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <1>;
|
|
+ };
|
|
+
|
|
+ cpu@2 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <2>;
|
|
+ };
|
|
+
|
|
+ cpu@3 {
|
|
+ compatible = "arm,cortex-a7";
|
|
+ device_type = "cpu";
|
|
+ reg = <3>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ soc {
|
|
+ compatible = "simple-bus";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+
|
|
+ nmi_intc: interrupt-controller@1c00030 {
|
|
+ compatible = "allwinner,sun7i-a20-sc-nmi";
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ reg = <0x01c00030 0x0c>;
|
|
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@1c0f000 {
|
|
+ compatible = "allwinner,sun8i-r40-mmc",
|
|
+ "allwinner,sun50i-a64-mmc";
|
|
+ reg = <0x01c0f000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC0>;
|
|
+ reset-names = "ahb";
|
|
+ pinctrl-0 = <&mmc0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc1: mmc@1c10000 {
|
|
+ compatible = "allwinner,sun8i-r40-mmc",
|
|
+ "allwinner,sun50i-a64-mmc";
|
|
+ reg = <0x01c10000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC1>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc2: mmc@1c11000 {
|
|
+ compatible = "allwinner,sun8i-r40-emmc",
|
|
+ "allwinner,sun50i-a64-emmc";
|
|
+ reg = <0x01c11000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC2>;
|
|
+ reset-names = "ahb";
|
|
+ pinctrl-0 = <&mmc2_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ mmc3: mmc@1c12000 {
|
|
+ compatible = "allwinner,sun8i-r40-mmc",
|
|
+ "allwinner,sun50i-a64-mmc";
|
|
+ reg = <0x01c12000 0x1000>;
|
|
+ clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
|
|
+ clock-names = "ahb", "mmc";
|
|
+ resets = <&ccu RST_BUS_MMC3>;
|
|
+ reset-names = "ahb";
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usbphy: phy@1c13400 {
|
|
+ compatible = "allwinner,sun8i-r40-usb-phy";
|
|
+ reg = <0x01c13400 0x14>,
|
|
+ <0x01c14800 0x4>,
|
|
+ <0x01c19800 0x4>,
|
|
+ <0x01c1c800 0x4>;
|
|
+ reg-names = "phy_ctrl",
|
|
+ "pmu0",
|
|
+ "pmu1",
|
|
+ "pmu2";
|
|
+ clocks = <&ccu CLK_USB_PHY0>,
|
|
+ <&ccu CLK_USB_PHY1>,
|
|
+ <&ccu CLK_USB_PHY2>;
|
|
+ clock-names = "usb0_phy",
|
|
+ "usb1_phy",
|
|
+ "usb2_phy";
|
|
+ resets = <&ccu RST_USB_PHY0>,
|
|
+ <&ccu RST_USB_PHY1>,
|
|
+ <&ccu RST_USB_PHY2>;
|
|
+ reset-names = "usb0_reset",
|
|
+ "usb1_reset",
|
|
+ "usb2_reset";
|
|
+ status = "disabled";
|
|
+ #phy-cells = <1>;
|
|
+ };
|
|
+
|
|
+ ehci1: usb@1c19000 {
|
|
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
|
|
+ reg = <0x01c19000 0x100>;
|
|
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_EHCI1>;
|
|
+ resets = <&ccu RST_BUS_EHCI1>;
|
|
+ phys = <&usbphy 1>;
|
|
+ phy-names = "usb";
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ ohci1: usb@1c19400 {
|
|
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
|
|
+ reg = <0x01c19400 0x100>;
|
|
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
|
+ <&ccu CLK_USB_OHCI1>;
|
|
+ resets = <&ccu RST_BUS_OHCI1>;
|
|
+ phys = <&usbphy 1>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ehci2: usb@1c1c000 {
|
|
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
|
|
+ reg = <0x01c1c000 0x100>;
|
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_EHCI2>;
|
|
+ resets = <&ccu RST_BUS_EHCI2>;
|
|
+ phys = <&usbphy 2>;
|
|
+ phy-names = "usb";
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ ohci2: usb@1c1c400 {
|
|
+ compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
|
|
+ reg = <0x01c1c400 0x100>;
|
|
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_OHCI2>,
|
|
+ <&ccu CLK_USB_OHCI2>;
|
|
+ resets = <&ccu RST_BUS_OHCI2>;
|
|
+ phys = <&usbphy 2>;
|
|
+ phy-names = "usb";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ahci: sata@1c18000 {
|
|
+ compatible = "allwinner,sun8i-r40-ahci", "allwinner,sun4i-a10-ahci";
|
|
+ reg = <0x01c18000 0x1000>;
|
|
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_SATA>, <&ccu CLK_BUS_SATA>;
|
|
+ resets = <&ccu RST_BUS_SATA>;
|
|
+ status = "enabled";
|
|
+ };
|
|
+
|
|
+ ccu: clock@1c20000 {
|
|
+ compatible = "allwinner,sun8i-r40-ccu";
|
|
+ reg = <0x01c20000 0x400>;
|
|
+ clocks = <&osc24M>, <&osc32k>;
|
|
+ clock-names = "hosc", "losc";
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ pio: pinctrl@1c20800 {
|
|
+ compatible = "allwinner,sun8i-r40-pinctrl";
|
|
+ reg = <0x01c20800 0x400>;
|
|
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
|
|
+ clock-names = "apb", "hosc", "losc";
|
|
+ gpio-controller;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+ #gpio-cells = <3>;
|
|
+
|
|
+ i2c0_pins: i2c0-pins {
|
|
+ pins = "PB0", "PB1";
|
|
+ function = "i2c0";
|
|
+ };
|
|
+
|
|
+ mmc0_pins: mmc0-pins {
|
|
+ pins = "PF0", "PF1", "PF2",
|
|
+ "PF3", "PF4", "PF5";
|
|
+ function = "mmc0";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ mmc1_pg_pins: mmc1-pg-pins {
|
|
+ pins = "PG0", "PG1", "PG2",
|
|
+ "PG3", "PG4", "PG5";
|
|
+ function = "mmc1";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ mmc2_pins: mmc2-pins {
|
|
+ pins = "PC5", "PC6", "PC7", "PC8", "PC9",
|
|
+ "PC10", "PC11", "PC12", "PC13", "PC14",
|
|
+ "PC15", "PC24";
|
|
+ function = "mmc2";
|
|
+ drive-strength = <30>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
+ uart0_pb_pins: uart0-pb-pins {
|
|
+ pins = "PB22", "PB23";
|
|
+ function = "uart0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ wdt: watchdog@1c20c90 {
|
|
+ compatible = "allwinner,sun4i-a10-wdt";
|
|
+ reg = <0x01c20c90 0x10>;
|
|
+ };
|
|
+
|
|
+ uart0: serial@1c28000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28000 0x400>;
|
|
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART0>;
|
|
+ resets = <&ccu RST_BUS_UART0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart1: serial@1c28400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28400 0x400>;
|
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART1>;
|
|
+ resets = <&ccu RST_BUS_UART1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@1c28800 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28800 0x400>;
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART2>;
|
|
+ resets = <&ccu RST_BUS_UART2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@1c28c00 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c28c00 0x400>;
|
|
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART3>;
|
|
+ resets = <&ccu RST_BUS_UART3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart4: serial@1c29000 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c29000 0x400>;
|
|
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART4>;
|
|
+ resets = <&ccu RST_BUS_UART4>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart5: serial@1c29400 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c29400 0x400>;
|
|
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART5>;
|
|
+ resets = <&ccu RST_BUS_UART5>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart6: serial@1c29800 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c29800 0x400>;
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART6>;
|
|
+ resets = <&ccu RST_BUS_UART6>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart7: serial@1c29c00 {
|
|
+ compatible = "snps,dw-apb-uart";
|
|
+ reg = <0x01c29c00 0x400>;
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ reg-shift = <2>;
|
|
+ reg-io-width = <4>;
|
|
+ clocks = <&ccu CLK_BUS_UART7>;
|
|
+ resets = <&ccu RST_BUS_UART7>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@1c2ac00 {
|
|
+ compatible = "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2ac00 0x400>;
|
|
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C0>;
|
|
+ resets = <&ccu RST_BUS_I2C0>;
|
|
+ pinctrl-0 = <&i2c0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@1c2b000 {
|
|
+ compatible = "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2b000 0x400>;
|
|
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C1>;
|
|
+ resets = <&ccu RST_BUS_I2C1>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@1c2b400 {
|
|
+ compatible = "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2b400 0x400>;
|
|
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C2>;
|
|
+ resets = <&ccu RST_BUS_I2C2>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@1c2b800 {
|
|
+ compatible = "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2b800 0x400>;
|
|
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C3>;
|
|
+ resets = <&ccu RST_BUS_I2C3>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ i2c4: i2c@1c2c000 {
|
|
+ compatible = "allwinner,sun6i-a31-i2c";
|
|
+ reg = <0x01c2c000 0x400>;
|
|
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&ccu CLK_BUS_I2C4>;
|
|
+ resets = <&ccu RST_BUS_I2C4>;
|
|
+ status = "disabled";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ gic: interrupt-controller@1c81000 {
|
|
+ compatible = "arm,gic-400";
|
|
+ reg = <0x01c81000 0x1000>,
|
|
+ <0x01c82000 0x1000>,
|
|
+ <0x01c84000 0x2000>,
|
|
+ <0x01c86000 0x2000>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <3>;
|
|
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv7-timer";
|
|
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
+ };
|
|
+};
|
|
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
|
|
index 1161e11..9df7a2c 100644
|
|
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
|
|
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
|
|
@@ -112,6 +112,7 @@ enum sun4i_usb_phy_type {
|
|
sun8i_a33_phy,
|
|
sun8i_a83t_phy,
|
|
sun8i_h3_phy,
|
|
+ sun8i_r40_phy,
|
|
sun8i_v3s_phy,
|
|
sun50i_a64_phy,
|
|
};
|
|
@@ -919,6 +920,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
|
|
.phy0_dual_route = true,
|
|
};
|
|
|
|
+static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
|
|
+ .num_phys = 3,
|
|
+ .type = sun8i_r40_phy,
|
|
+ .disc_thresh = 3,
|
|
+ .phyctl_offset = REG_PHYCTL_A33,
|
|
+ .dedicated_clocks = true,
|
|
+ .enable_pmu_unk1 = true,
|
|
+ .phy0_dual_route = true,
|
|
+};
|
|
+
|
|
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
|
|
.num_phys = 1,
|
|
.type = sun8i_v3s_phy,
|
|
@@ -947,6 +958,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
|
|
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
|
|
{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
|
|
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
|
|
+ { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
|
|
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
|
|
{ .compatible = "allwinner,sun50i-a64-usb-phy",
|
|
.data = &sun50i_a64_cfg},
|
|
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
|
|
index 7826fb3..1a7fef8 100644
|
|
--- a/sound/soc/sunxi/sun4i-i2s.c
|
|
+++ b/sound/soc/sunxi/sun4i-i2s.c
|
|
@@ -905,6 +905,23 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
|
|
.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
|
|
};
|
|
|
|
+static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
|
|
+ .has_reset = true,
|
|
+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
|
|
+ .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
|
|
+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
|
|
+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
|
|
+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
|
|
+ .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
|
|
+ .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
|
|
+ .has_slave_select_bit = true,
|
|
+ .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
|
|
+ .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
|
|
+ .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
|
|
+ .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
|
|
+ .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
|
|
+};
|
|
+
|
|
static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
|
|
.has_reset = true,
|
|
.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
|
|
@@ -1136,6 +1153,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
|
|
.data = &sun6i_a31_i2s_quirks,
|
|
},
|
|
{
|
|
+ .compatible = "allwinner,sun8i-a83t-i2s",
|
|
+ .data = &sun8i_a83t_i2s_quirks,
|
|
+ },
|
|
+ {
|
|
.compatible = "allwinner,sun8i-h3-i2s",
|
|
.data = &sun8i_h3_i2s_quirks,
|
|
},
|