mirror of
https://github.com/Fishwaldo/build.git
synced 2025-04-27 00:11:23 +00:00
ff4c1488da
* Wireguard: bump tag to most recent since it breaks building on 5.4.y * Move rockchip current to 5.4.y * Move sunxi current to 5.4.y * Move meson64 to 5.4.y * Move odroidxu4 to 5.4.y and enable "current" targets * Enable missing target
176 lines
4.3 KiB
Diff
176 lines
4.3 KiB
Diff
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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index dc785da9c..141fd186b 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
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@@ -113,6 +113,12 @@
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clock-latency-ns = <244144>; /* 8 32k periods */
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};
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+ opp@1640000000 {
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+ opp-hz = /bits/ 64 <1640000000>;
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+ opp-microvolt = <1160000 1160000 1160000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ };
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+
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opp@1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1160000 1160000 1160000>;
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@@ -374,6 +381,17 @@
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#dma-cells = <1>;
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};
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+ gic: interrupt-controller@3021000 {
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+ compatible = "arm,gic-400";
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+ reg = <0x03021000 0x1000>,
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+ <0x03022000 0x2000>,
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+ <0x03024000 0x2000>,
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+ <0x03026000 0x2000>;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ };
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+
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sid: efuse@3006000 {
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compatible = "allwinner,sun50i-h6-sid";
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reg = <0x03006000 0x400>;
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@@ -279,6 +305,7 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ /omit-if-no-ref/
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ext_rgmii_pins: rgmii-pins {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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@@ -309,6 +354,7 @@
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bias-pull-up;
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};
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+ /omit-if-no-ref/
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC4", "PC5", "PC6",
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"PC7", "PC8", "PC9", "PC10",
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@@ -318,6 +364,16 @@
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bias-pull-up;
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};
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+ spi0_pins: spi0-pins {
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+ pins = "PC2", "PC3", "PC0", "PC5";
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+ function = "spi0";
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+ };
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+
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+ spi1_pins: spi1-pins {
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+ pins = "PH5", "PH6", "PH4", "PH3";
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+ function = "spi1";
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+ };
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+
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uart0_ph_pins: uart0-ph-pins {
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pins = "PH0", "PH1";
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function = "uart0";
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@@ -511,17 +540,26 @@
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pins = "PG8", "PG9";
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function = "uart1";
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};
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- };
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- gic: interrupt-controller@3021000 {
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- compatible = "arm,gic-400";
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- reg = <0x03021000 0x1000>,
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- <0x03022000 0x2000>,
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- <0x03024000 0x2000>,
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- <0x03026000 0x2000>;
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- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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- interrupt-controller;
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- #interrupt-cells = <3>;
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+ uart2_pins: uart2-pins {
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+ pins = "PD19", "PD20";
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+ function = "uart2";
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+ };
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+
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+ uart2_rts_cts_pins: uart2-rts-cts-pins {
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+ pins = "PD21", "PD22";
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+ function = "uart2";
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+ };
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+
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+ uart3_pins: uart3-pins {
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+ pins = "PD23", "PD24";
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+ function = "uart3";
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+ };
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+
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+ uart3_rts_cts_pins: uart3-rts-cts-pins {
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+ pins = "PD25", "PD26";
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+ function = "uart3";
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+ };
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};
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mmc0: mmc@4020000 {
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@@ -391,6 +495,38 @@
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#size-cells = <0>;
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};
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+ spi0: spi@5010000 {
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+ compatible = "allwinner,sun8i-h3-spi";
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+ reg = <0x05010000 0x1000>;
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+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 22>, <&dma 22>;
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+ dma-names = "rx", "tx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_pins>;
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+ resets = <&ccu RST_BUS_SPI0>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@5011000 {
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+ compatible = "allwinner,sun8i-h3-spi";
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+ reg = <0x05011000 0x1000>;
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+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
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+ clock-names = "ahb", "mod";
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+ dmas = <&dma 23>, <&dma 23>;
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+ dma-names = "rx", "tx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ resets = <&ccu RST_BUS_SPI1>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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uart0: serial@5000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000000 0x400>;
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@@ -963,6 +1033,19 @@
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};
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};
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+ r_uart: serial@7080000 {
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+ compatible = "snps,dw-apb-uart";
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+ reg = <0x07080000 0x400>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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+ reg-shift = <2>;
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+ reg-io-width = <4>;
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+ clocks = <&r_ccu CLK_R_APB2_UART>;
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+ resets = <&r_ccu RST_R_APB2_UART>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&r_uart_pins>;
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+ status = "disabled";
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+ };
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+
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rtc: rtc@7000000 {
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compatible = "allwinner,sun50i-h6-rtc";
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reg = <0x07000000 0x400>;
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@@ -1021,6 +1104,11 @@
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pins = "PL9";
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function = "s_cir_rx";
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};
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+
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+ r_uart_pins: r-uart-pins {
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+ pins = "PL2", "PL3";
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+ function = "s_uart";
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+ };
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};
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r_ir: ir@7040000 {
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