Marek Vasut 1c45ba93d3 net: dsa: microchip: Adjust reset release timing to match reference reset circuit ... KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended circuit for interfacing with CPU/FPGA reset consisting of 10k pullup resistor and 10uF capacitor to ground. This circuit takes ~100 ms to rise enough to release the reset. For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is VDDIO - VIH t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s VDDIO so we need ~95 ms for the reset to really de-assert, and then the original 100us for the switch itself to come out of reset. Simply msleep() for 100 ms which fits the constraint with a bit of extra space. Fixes: 5b79798090 ("net: dsa: microchip: Implement recommended reset timing") Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Michael Grzeschik <m.grzeschik@pengutronix.de> Reviewed-by: Paul Barker <pbarker@konsulko.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210120030502.617185-1-marex@denx.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>		2021-01-20 20:52:28 -08:00
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dsa	net: dsa: microchip: Adjust reset release timing to match reference reset circuit	2021-01-20 20:52:28 -08:00
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