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KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
resistor and 10uF capacitor to ground. This circuit takes ~100 ms to
rise enough to release the reset.
For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
VDDIO - VIH
t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s
VDDIO
so we need ~95 ms for the reset to really de-assert, and then the
original 100us for the switch itself to come out of reset. Simply
msleep() for 100 ms which fits the constraint with a bit of extra
space.
Fixes:
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.. | ||
b53 | ||
hirschmann | ||
microchip | ||
mv88e6xxx | ||
ocelot | ||
qca | ||
sja1105 | ||
bcm_sf2.c | ||
bcm_sf2.h | ||
bcm_sf2_cfp.c | ||
bcm_sf2_regs.h | ||
dsa_loop.c | ||
dsa_loop.h | ||
dsa_loop_bdinfo.c | ||
Kconfig | ||
lan9303-core.c | ||
lan9303.h | ||
lan9303_i2c.c | ||
lan9303_mdio.c | ||
lantiq_gswip.c | ||
lantiq_pce.h | ||
Makefile | ||
mt7530.c | ||
mt7530.h | ||
mv88e6060.c | ||
mv88e6060.h | ||
qca8k.c | ||
qca8k.h | ||
realtek-smi-core.c | ||
realtek-smi-core.h | ||
rtl8366.c | ||
rtl8366rb.c | ||
vitesse-vsc73xx-core.c | ||
vitesse-vsc73xx-platform.c | ||
vitesse-vsc73xx-spi.c | ||
vitesse-vsc73xx.h |