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firmware: Add a barrier instruction for wait for boot hart
Multi-core communication via memory requires the addition of a barrier instructions to ensure cache coherency. Signed-off-by: Xiang Wang <wxjstz@126.com>
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@ -114,6 +114,7 @@ _fdt_reloc_done:
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/* Wait for boot hart */
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_wait_for_boot_hart:
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fence rw, rw
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la a4, _boot_hart_done
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REG_L a5, (a4)
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beqz a5, _wait_for_boot_hart
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