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platform: include: andes45: Add PMU related CSR defines
Add CSR definitions for Andes PMU extension. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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@ -12,6 +12,17 @@
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#define CSR_MDCM_CFG 0xfc1
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#define CSR_MMSC_CFG 0xfc2
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/* Machine Trap Related Registers */
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#define CSR_MSLIDELEG 0x7d5
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/* Counter Related Registers */
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#define CSR_MCOUNTERWEN 0x7ce
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#define CSR_MCOUNTERINTEN 0x7cf
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#define CSR_MCOUNTERMASK_M 0x7d1
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#define CSR_MCOUNTERMASK_S 0x7d2
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#define CSR_MCOUNTERMASK_U 0x7d3
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#define CSR_MCOUNTEROVF 0x7d4
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#define MICM_CFG_ISZ_OFFSET 6
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#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
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@ -26,4 +37,19 @@
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
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/* Performance monitor */
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#define MMSC_CFG_PMNDS_MASK (1 << 15)
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#define MIP_PMOVI (1 << 18)
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#ifndef __ASSEMBLER__
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#define has_andes_pmu() \
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({ \
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(((csr_read(CSR_MMSC_CFG) & \
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MMSC_CFG_PMNDS_MASK) \
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&& misa_extension('S')) ? true : false); \
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})
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#endif /* __ASSEMBLER__ */
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#endif /* _RISCV_ANDES45_H */
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