GitHub-Mirror/opensbi
2
0
Fork 0
mirror of https://github.com/Fishwaldo/opensbi.git synced 2025-03-16 03:41:24 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

lib: No need to set VSSTATUS.MXR bit in get_insn()

Browse source 
We don't need to set VSSTATUS.MXR bit in get_insn() for
unpriv instruction read because MSTATUS.MXR bit applies
to both "Stage1" and "Stage2" page tables.

This also allows us to remove the "virt" parameter of
get_insn() function.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Anup Patel 2019-11-16 16:38:53 +05:30 • committed by Anup Patel
parent 838657c052
commit b1d8c988bc
4 changed files with 6 additions and 27 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
include/sbi/riscv_unpriv.h
View file

@ -42,7 +42,7 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64)
DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64)
DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong)
ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
struct unpriv_trap *trap);
#endif

10
lib/sbi/riscv_unpriv.c
View file

@ -101,10 +101,10 @@ void store_u64(u64 *addr, u64 val,
}
#endif
ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
struct unpriv_trap *trap)
{
ulong __mstatus = 0, __vsstatus = 0, val = 0;
ulong __mstatus = 0, val = 0;
#ifdef __riscv_compressed
ulong rvc_mask = 3, tmp;
#endif
@ -113,9 +113,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
trap->tval = 0;
sbi_hart_set_trap_info(scratch, trap);
if (virt)
__vsstatus = csr_read_set(CSR_VSSTATUS, SSTATUS_MXR);
#ifndef __riscv_compressed
asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
".option push\n"
@ -149,9 +146,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
[rvc_mask] "r"(rvc_mask));
#endif
if (virt)
csr_write(CSR_VSSTATUS, __vsstatus);
sbi_hart_set_trap_info(scratch, NULL);
switch (trap->cause) {
case CAUSE_LOAD_ACCESS:

7
lib/sbi/sbi_illegal_insn.c
View file

@ -130,16 +130,11 @@ int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
struct sbi_scratch *scratch)
{
ulong insn = csr_read(CSR_MTVAL);
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
struct unpriv_trap uptrap;
if (unlikely((insn & 3) != 3)) {
if (insn == 0) {
insn = get_insn(regs->mepc, virt, scratch, &uptrap);
insn = get_insn(regs->mepc, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch,
regs->mepc, uptrap.cause, uptrap.tval);

14
lib/sbi/sbi_misaligned_ldst.c
View file

@ -29,12 +29,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
struct unpriv_trap uptrap;
ulong addr = csr_read(CSR_MTVAL);
int i, fp = 0, shift = 0, len = 0;
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
ulong insn = get_insn(regs->mepc, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch, regs->mepc,
@ -136,12 +131,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
struct unpriv_trap uptrap;
ulong addr = csr_read(CSR_MTVAL);
int i, len = 0;
#if __riscv_xlen == 32
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
ulong insn = get_insn(regs->mepc, scratch, &uptrap);
if (uptrap.cause)
return sbi_trap_redirect(regs, scratch, regs->mepc,