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lib: No need to set VSSTATUS.MXR bit in get_insn()
We don't need to set VSSTATUS.MXR bit in get_insn() for unpriv instruction read because MSTATUS.MXR bit applies to both "Stage1" and "Stage2" page tables. This also allows us to remove the "virt" parameter of get_insn() function. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
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838657c052
commit
b1d8c988bc
4 changed files with 6 additions and 27 deletions
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@ -42,7 +42,7 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64)
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DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64)
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DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong)
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ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
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ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
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struct unpriv_trap *trap);
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#endif
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@ -101,10 +101,10 @@ void store_u64(u64 *addr, u64 val,
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}
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#endif
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ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
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ulong get_insn(ulong mepc, struct sbi_scratch *scratch,
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struct unpriv_trap *trap)
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{
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ulong __mstatus = 0, __vsstatus = 0, val = 0;
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ulong __mstatus = 0, val = 0;
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#ifdef __riscv_compressed
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ulong rvc_mask = 3, tmp;
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#endif
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@ -113,9 +113,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
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trap->tval = 0;
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sbi_hart_set_trap_info(scratch, trap);
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if (virt)
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__vsstatus = csr_read_set(CSR_VSSTATUS, SSTATUS_MXR);
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#ifndef __riscv_compressed
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asm("csrrs %[mstatus], " STR(CSR_MSTATUS) ", %[mprv]\n"
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".option push\n"
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@ -149,9 +146,6 @@ ulong get_insn(ulong mepc, bool virt, struct sbi_scratch *scratch,
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[rvc_mask] "r"(rvc_mask));
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#endif
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if (virt)
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csr_write(CSR_VSSTATUS, __vsstatus);
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sbi_hart_set_trap_info(scratch, NULL);
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switch (trap->cause) {
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case CAUSE_LOAD_ACCESS:
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@ -130,16 +130,11 @@ int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
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struct sbi_scratch *scratch)
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{
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ulong insn = csr_read(CSR_MTVAL);
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#if __riscv_xlen == 32
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bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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#else
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bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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#endif
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struct unpriv_trap uptrap;
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if (unlikely((insn & 3) != 3)) {
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if (insn == 0) {
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insn = get_insn(regs->mepc, virt, scratch, &uptrap);
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insn = get_insn(regs->mepc, scratch, &uptrap);
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if (uptrap.cause)
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return sbi_trap_redirect(regs, scratch,
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regs->mepc, uptrap.cause, uptrap.tval);
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@ -29,12 +29,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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struct unpriv_trap uptrap;
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ulong addr = csr_read(CSR_MTVAL);
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int i, fp = 0, shift = 0, len = 0;
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#if __riscv_xlen == 32
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bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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#else
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bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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#endif
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ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
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ulong insn = get_insn(regs->mepc, scratch, &uptrap);
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if (uptrap.cause)
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return sbi_trap_redirect(regs, scratch, regs->mepc,
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@ -136,12 +131,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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struct unpriv_trap uptrap;
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ulong addr = csr_read(CSR_MTVAL);
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int i, len = 0;
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#if __riscv_xlen == 32
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bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
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#else
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bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
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#endif
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ulong insn = get_insn(regs->mepc, virt, scratch, &uptrap);
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ulong insn = get_insn(regs->mepc, scratch, &uptrap);
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if (uptrap.cause)
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return sbi_trap_redirect(regs, scratch, regs->mepc,
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