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lib: Add misaligned load/store trap handling
We generally don't get misaligned load/store traps from Linux/U-Boot compiled using GCC 8.2 or higher but this is not true with older GCC toolchains. To tackle this we add misaligned load/store trap handling adopted from BBL sources but much more simpler. (Note: BBL sources can be found at https://github.com/riscv/riscv-pk.git) Signed-off-by: Anup Patel <anup.patel@wdc.com>
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4 changed files with 166 additions and 1 deletions
26
include/sbi/sbi_misaligned_ldst.h
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26
include/sbi/sbi_misaligned_ldst.h
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2018 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#ifndef __SBI_MISALIGNED_LDST_H__
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#define __SBI_MISALIGNED_LDST_H__
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#include <sbi/sbi_types.h>
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struct sbi_trap_regs;
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struct sbi_scratch;
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int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch);
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int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch);
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#endif
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@ -18,6 +18,7 @@ lib-objs-y += sbi_hart.o
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lib-objs-y += sbi_illegal_insn.o
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lib-objs-y += sbi_init.o
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lib-objs-y += sbi_ipi.o
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lib-objs-y += sbi_misaligned_ldst.o
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lib-objs-y += sbi_system.o
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lib-objs-y += sbi_timer.o
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lib-objs-y += sbi_trap.o
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129
lib/sbi_misaligned_ldst.c
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129
lib/sbi_misaligned_ldst.c
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/*
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* Copyright (c) 2018 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_misaligned_ldst.h>
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#include <sbi/sbi_trap.h>
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#include <sbi/sbi_unpriv.h>
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union reg_data {
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u8 data_bytes[8];
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ulong data_ulong;
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u64 data_u64;
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};
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int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
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struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch)
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{
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union reg_data val;
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ulong mstatus = csr_read(mstatus);
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ulong insn = get_insn(regs->mepc, &mstatus);
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ulong addr = csr_read(mtval);
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int i, shift = 0, len = 0;
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if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
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len = 4;
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shift = 8 * (sizeof(ulong) - len);
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#if __riscv_xlen == 64
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} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
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len = 8;
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shift = 8 * (sizeof(ulong) - len);
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} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
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len = 4;
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#endif
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} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
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len = 2;
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shift = 8 * (sizeof(ulong) - len);
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} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
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len = 2;
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#ifdef __riscv_compressed
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# if __riscv_xlen >= 64
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} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
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len = 8;
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shift = 8 * (sizeof(ulong) - len);
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insn = RVC_RS2S(insn) << SH_RD;
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} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 8;
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shift = 8 * (sizeof(ulong) - len);
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# endif
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} else if ((insn & INSN_MASK_C_LW) ==INSN_MATCH_C_LW) {
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len = 4;
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shift = 8 * (sizeof(ulong) - len);
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insn = RVC_RS2S(insn) << SH_RD;
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} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 4;
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shift = 8 * (sizeof(ulong) - len);
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#endif
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} else
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return SBI_EILL;
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val.data_u64 = 0;
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for (i = 0; i < len; i++)
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val.data_bytes[i] = load_u8((void *)(addr + i), regs->mepc);
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SET_RD(insn, regs, val.data_ulong << shift >> shift);
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regs->mepc += INSN_LEN(insn);
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return 0;
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}
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int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
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struct sbi_trap_regs *regs,
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struct sbi_scratch *scratch)
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{
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union reg_data val;
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ulong mstatus = csr_read(mstatus);
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ulong insn = get_insn(regs->mepc, &mstatus);
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ulong addr = csr_read(mtval);
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int i, len = 0;
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val.data_ulong = GET_RS2(insn, regs);
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if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
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len = 4;
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#if __riscv_xlen == 64
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} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
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len = 8;
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#endif
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} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
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len = 2;
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#ifdef __riscv_compressed
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# if __riscv_xlen >= 64
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} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
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len = 8;
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val.data_ulong = GET_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 8;
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val.data_ulong = GET_RS2C(insn, regs);
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# endif
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} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
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len = 4;
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val.data_ulong = GET_RS2S(insn, regs);
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} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
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((insn >> SH_RD) & 0x1f)) {
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len = 4;
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val.data_ulong = GET_RS2C(insn, regs);
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#endif
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} else
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return SBI_EILL;
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for (i = 0; i < len; i++)
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store_u8((void *)(addr + i), val.data_bytes[i], regs->mepc);
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regs->mepc += INSN_LEN(insn);
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return 0;
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}
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@ -12,9 +12,10 @@
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_ecall.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_illegal_insn.h>
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#include <sbi/sbi_hart.h>
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#include <sbi/sbi_illegal_insn.h>
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#include <sbi/sbi_ipi.h>
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#include <sbi/sbi_misaligned_ldst.h>
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#include <sbi/sbi_timer.h>
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#include <sbi/sbi_trap.h>
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rc = sbi_illegal_insn_handler(hartid, mcause, regs, scratch);
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msg = "illegal instruction handler failed";
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break;
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case CAUSE_MISALIGNED_LOAD:
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rc = sbi_misaligned_load_handler(hartid, mcause, regs, scratch);
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msg = "misaligned load handler failed";
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break;
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case CAUSE_MISALIGNED_STORE:
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rc = sbi_misaligned_store_handler(hartid, mcause, regs, scratch);
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msg = "misaligned store handler failed";
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break;
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case CAUSE_SUPERVISOR_ECALL:
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case CAUSE_HYPERVISOR_ECALL:
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rc = sbi_ecall_handler(hartid, mcause, regs, scratch);
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